CVSROOT: /home/cvs
Module name: linux
Changes by: ralf@ftp.linux-mips.org 05/07/15 16:23:23
Modified files:
arch/mips/mm : c-r4k.c c-tx39.c pg-r4k.c tlbex.c
Log message:
Avoid SMP cacheflushes. This is a minor optimization of startup but
will also avoid smp_call_function from doing stupid things when called
from a CPU that is not yet marked online.
diff -urN linux/arch/mips/mm/c-r4k.c linux/arch/mips/mm/c-r4k.c
--- linux/arch/mips/mm/c-r4k.c 2005/07/14 15:57:17 1.113
+++ linux/arch/mips/mm/c-r4k.c 2005/07/15 15:23:23 1.114
@@ -1270,9 +1270,8 @@
_dma_cache_inv = r4k_dma_cache_inv;
#endif
- __flush_cache_all();
- coherency_setup();
-
build_clear_page();
build_copy_page();
+ local_r4k___flush_cache_all(NULL);
+ coherency_setup();
}
diff -urN linux/arch/mips/mm/c-tx39.c linux/arch/mips/mm/c-tx39.c
--- linux/arch/mips/mm/c-tx39.c 2005/06/27 08:39:23 1.30
+++ linux/arch/mips/mm/c-tx39.c 2005/07/15 15:23:23 1.31
@@ -492,4 +492,5 @@
build_clear_page();
build_copy_page();
+ tx39h_flush_icache_all();
}
diff -urN linux/arch/mips/mm/pg-r4k.c linux/arch/mips/mm/pg-r4k.c
--- linux/arch/mips/mm/pg-r4k.c 2005/01/15 01:31:05 1.16
+++ linux/arch/mips/mm/pg-r4k.c 2005/07/15 15:23:23 1.17
@@ -404,9 +404,6 @@
build_jr_ra();
- flush_icache_range((unsigned long)&clear_page_array,
- (unsigned long) epc);
-
BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array));
}
@@ -482,8 +479,5 @@
build_jr_ra();
- flush_icache_range((unsigned long)©_page_array,
- (unsigned long) epc);
-
BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array));
}
diff -urN linux/arch/mips/mm/tlbex.c linux/arch/mips/mm/tlbex.c
--- linux/arch/mips/mm/tlbex.c 2005/07/14 17:47:58 1.31
+++ linux/arch/mips/mm/tlbex.c 2005/07/15 15:23:23 1.32
@@ -743,7 +743,6 @@
#endif
memcpy((void *)CAC_BASE, tlb_handler, 0x80);
- flush_icache_range(CAC_BASE, CAC_BASE + 0x80);
}
/*
@@ -1258,7 +1257,6 @@
#endif
memcpy((void *)CAC_BASE, final_handler, 0x100);
- flush_icache_range(CAC_BASE, CAC_BASE + 0x100);
}
/*
@@ -1519,9 +1517,6 @@
printk("%08x\n", handle_tlbl[i]);
}
#endif
-
- flush_icache_range((unsigned long)handle_tlbl,
- (unsigned long)handle_tlbl + FASTPATH_SIZE *
sizeof(u32));
}
static void __init build_r3000_tlb_store_handler(void)
@@ -1559,9 +1554,6 @@
printk("%08x\n", handle_tlbs[i]);
}
#endif
-
- flush_icache_range((unsigned long)handle_tlbs,
- (unsigned long)handle_tlbs + FASTPATH_SIZE *
sizeof(u32));
}
static void __init build_r3000_tlb_modify_handler(void)
@@ -1599,9 +1591,6 @@
printk("%08x\n", handle_tlbm[i]);
}
#endif
-
- flush_icache_range((unsigned long)handle_tlbm,
- (unsigned long)handle_tlbm + FASTPATH_SIZE *
sizeof(u32));
}
/*
@@ -1691,9 +1680,6 @@
printk("%08x\n", handle_tlbl[i]);
}
#endif
-
- flush_icache_range((unsigned long)handle_tlbl,
- (unsigned long)handle_tlbl + FASTPATH_SIZE *
sizeof(u32));
}
static void __init build_r4000_tlb_store_handler(void)
@@ -1730,9 +1716,6 @@
printk("%08x\n", handle_tlbs[i]);
}
#endif
-
- flush_icache_range((unsigned long)handle_tlbs,
- (unsigned long)handle_tlbs + FASTPATH_SIZE *
sizeof(u32));
}
static void __init build_r4000_tlb_modify_handler(void)
@@ -1770,9 +1753,6 @@
printk("%08x\n", handle_tlbm[i]);
}
#endif
-
- flush_icache_range((unsigned long)handle_tlbm,
- (unsigned long)handle_tlbm + FASTPATH_SIZE *
sizeof(u32));
}
void __init build_tlb_refill_handler(void)
|