CVS Update@linux-mips.org: linux

[ralf@linux-mips.org]

CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 05/07/14 08:34:19

Modified files:
        arch/mips/kernel: cpu-probe.c 
        include/asm-mips: cpu-features.h cpu.h mipsregs.h 

Log message:
        Detect the MIPS R2 vectored interrupt, external interrupt controller
        options and the precense of the MT ASE.

diff -urN linux/arch/mips/kernel/cpu-probe.c linux/arch/mips/kernel/cpu-probe.c
--- linux/arch/mips/kernel/cpu-probe.c  2005/07/13 19:22:45     1.52
+++ linux/arch/mips/kernel/cpu-probe.c  2005/07/14 07:34:18     1.53
@@ -507,6 +507,12 @@
                c->ases |= MIPS_ASE_SMARTMIPS;
        if (config3 & MIPS_CONF3_DSP)
                c->ases |= MIPS_ASE_DSP;
+       if (config3 & MIPS_CONF3_VINT)
+               c->ases |= MIPS_CPU_VINT;
+       if (config3 & MIPS_CONF3_VEIC)
+               c->ases |= MIPS_CPU_VEIC;
+       if (config3 & MIPS_CONF3_MT)
+                c->ases |= MIPS_CPU_MIPSMT;
 
        return config3 & MIPS_CONF_M;
 }
diff -urN linux/include/asm-mips/cpu-features.h 
linux/include/asm-mips/cpu-features.h
--- linux/include/asm-mips/cpu-features.h       2005/06/15 13:00:12     1.13
+++ linux/include/asm-mips/cpu-features.h       2005/07/14 07:34:18     1.14
@@ -126,6 +126,9 @@
 # define cpu_has_64bit_addresses       0
 # endif
 #endif
+#ifndef cpu_has_mipsmt
+# define cpu_has_mipsmt                (cpu_data[0].ases & MIPS_CPU_MIPSMT)
+#endif
 
 #ifdef CONFIG_MIPS64
 # ifndef cpu_has_nofpuex
@@ -145,6 +148,22 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_MIPSR2
+# if CONFIG_CPU_MIPSR2_IRQ_VI && !defined(cpu_has_vint)
+#  define cpu_has_vint         (cpu_data[0].options & MIPS_CPU_VINT)
+# else
+#  define cpu_has_vint                 0
+# endif
+# if CONFIG_CPU_MIPSR2_IRQ_EI && !defined(cpu_has_veic)
+#  define cpu_has_veic         (cpu_data[0].options & MIPS_CPU_VEIC)
+# else
+#  define cpu_has_veic                 0
+# endif
+#else
+# define cpu_has_vint                  0
+# define cpu_has_veic                  0
+#endif
+
 #ifndef cpu_has_subset_pcaches
 #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
 #endif
diff -urN linux/include/asm-mips/cpu.h linux/include/asm-mips/cpu.h
--- linux/include/asm-mips/cpu.h        2005/07/12 16:12:05     1.57
+++ linux/include/asm-mips/cpu.h        2005/07/14 07:34:18     1.58
@@ -227,6 +227,9 @@
 #define MIPS_CPU_LLSC          0x00010000 /* CPU has ll/sc instructions */
 #define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */
 #define MIPS_CPU_PREFETCH      0x00040000 /* CPU has usable prefetch */
+#define MIPS_CPU_VINT          0x00080000 /* CPU supports MIPSR2 vectored 
interrupts */
+#define MIPS_CPU_VEIC          0x00100000 /* CPU supports MIPSR2 external 
interrupt controller mode */
+#define MIPS_CPU_MIPSMT                0x00400000 /* CPU supports MIPS MT */
 
 /*
  * CPU ASE encodings
diff -urN linux/include/asm-mips/mipsregs.h linux/include/asm-mips/mipsregs.h
--- linux/include/asm-mips/mipsregs.h   2005/07/14 07:30:27     1.78
+++ linux/include/asm-mips/mipsregs.h   2005/07/14 07:34:18     1.79
@@ -528,6 +528,7 @@
 
 #define MIPS_CONF3_TL          (_ULCAST_(1) <<  0)
 #define MIPS_CONF3_SM          (_ULCAST_(1) <<  1)
+#define MIPS_CONF3_MT          (_ULCAST_(1) <<  2)
 #define MIPS_CONF3_SP          (_ULCAST_(1) <<  4)
 #define MIPS_CONF3_VINT                (_ULCAST_(1) <<  5)
 #define MIPS_CONF3_VEIC                (_ULCAST_(1) <<  6)