linux-cvs-patches
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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: ralf@linux-mips.org
Date: Wed, 13 Jul 2005 12:50:40 +0100
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 05/07/13 12:50:30

Modified files:
        .              : MAINTAINERS Makefile 
        Documentation  : feature-removal-schedule.txt 
                         kernel-parameters.txt 
        Documentation/dvb: README.dvb-usb bt8xx.txt 
        Documentation/i2c: dev-interface writing-clients 
        Documentation/i2c/chips: max6875 
        Documentation/pcmcia: driver-changes.txt 
        Documentation/power: video.txt 
        Documentation/usb: sn9c102.txt usbmon.txt 
        Documentation/video4linux: CARDLIST.bttv CARDLIST.cx88 
                                   CARDLIST.saa7134 CARDLIST.tuner 
                                   not-in-cx2388x-datasheet.txt 
        Documentation/video4linux/bttv: Cards 
        arch/alpha     : Kconfig 
        arch/arm       : Kconfig Makefile 
        arch/arm/configs: enp2611_defconfig ixdp2400_defconfig 
                          ixdp2401_defconfig ixdp2800_defconfig 
                          ixdp2801_defconfig omap_h2_1610_defconfig 
        arch/arm/kernel: armksyms.c 
        arch/arm/mach-ixp2000: core.c enp2611.c ixdp2x00.c ixdp2x01.c 
        arch/arm/mach-ixp4xx: common-pci.c coyote-setup.c 
                              ixdp425-setup.c 
        arch/arm/mm    : Kconfig mm-armv.c proc-v6.S 
        arch/arm26     : Kconfig 
        arch/cris      : Kconfig 
        arch/frv       : Kconfig 
        arch/frv/mb93090-mb00: pci-irq.c 
        arch/h8300     : Kconfig 
        arch/i386      : Kconfig 
        arch/i386/kernel: smpboot.c syscall_table.S time.c vmlinux.lds.S 
        arch/i386/kernel/acpi: Makefile wakeup.S 
        arch/i386/kernel/cpu: common.c intel.c 
        arch/i386/kernel/cpu/cpufreq: speedstep-centrino.c 
        arch/i386/kernel/cpu/mtrr: generic.c main.c mtrr.h 
        arch/i386/kernel/timers: timer_hpet.c 
        arch/i386/mm   : ioremap.c 
        arch/i386/pci  : irq.c visws.c 
        arch/i386/power: cpu.c 
        arch/ia64      : Kconfig 
        arch/ia64/hp/sim: simeth.c simserial.c 
        arch/ia64/kernel: Makefile acpi.c entry.S iosapic.c irq_ia64.c 
                          mca.c perfmon.c process.c setup.c signal.c 
                          smpboot.c topology.c traps.c 
        arch/ia64/mm   : discontig.c init.c 
        arch/ia64/sn/include/xtalk: hubdev.h 
        arch/ia64/sn/kernel: io_init.c irq.c setup.c tiocx.c xpc_main.c 
        arch/ia64/sn/pci: pci_dma.c tioca_provider.c 
        arch/ia64/sn/pci/pcibr: pcibr_ate.c pcibr_dma.c pcibr_provider.c 
                                pcibr_reg.c 
        arch/m32r      : Kconfig 
        arch/m32r/kernel: setup_m32700ut.c setup_mappi.c setup_mappi2.c 
                          setup_mappi3.c setup_oaks32r.c setup_opsput.c 
        arch/m68k      : Kconfig 
        arch/m68knommu : Kconfig 
        arch/mips      : Kconfig defconfig 
        arch/mips/configs: atlas_defconfig capcella_defconfig 
                           cobalt_defconfig db1000_defconfig 
                           db1100_defconfig db1500_defconfig 
                           db1550_defconfig ddb5476_defconfig 
                           ddb5477_defconfig decstation_defconfig 
                           e55_defconfig ev64120_defconfig 
                           ev96100_defconfig ip22_defconfig 
                           ip27_defconfig ip32_defconfig 
                           it8172_defconfig ivr_defconfig 
                           jaguar-atx_defconfig jmr3927_defconfig 
                           lasat200_defconfig malta_defconfig 
                           mpc30x_defconfig ocelot_3_defconfig 
                           ocelot_c_defconfig ocelot_defconfig 
                           ocelot_g_defconfig pb1100_defconfig 
                           pb1500_defconfig pb1550_defconfig 
                           qemu_defconfig rm200_defconfig 
                           sb1250-swarm_defconfig sead_defconfig 
                           tb0226_defconfig tb0229_defconfig 
                           workpad_defconfig yosemite_defconfig 
        arch/mips/kernel: scall32-o32.S scall64-64.S scall64-n32.S 
                          scall64-o32.S setup.c time.c 
        arch/mips/mm   : c-r4k.c 
        arch/parisc    : Kconfig 
        arch/ppc       : Kconfig 
        arch/ppc/kernel: machine_kexec.c 
        arch/ppc/platforms: pmac_cpufreq.c 
        arch/ppc/syslib: of_device.c 
        arch/ppc64     : Kconfig 
        arch/ppc64/kernel: cputable.c head.S hvconsole.c iSeries_setup.c 
                           idle.c maple_setup.c misc.S of_device.c 
                           pSeries_setup.c pmac_setup.c setup.c 
                           sys_ppc32.c sysfs.c 
        arch/ppc64/kernel/vdso32: vdso32.lds.S 
        arch/s390      : Kconfig 
        arch/sh        : Kconfig 
        arch/sh64      : Kconfig 
        arch/sparc     : Kconfig 
        arch/sparc/kernel: systbls.S 
        arch/sparc64   : Kconfig 
        arch/sparc64/kernel: dtlb_backend.S entry.S irq.c power.c 
                             ptrace.c smp.c sparc64_ksyms.c sys32.S 
                             systbls.S time.c vmlinux.lds.S 
        arch/sparc64/mm: fault.c 
        arch/sparc64/solaris: entry64.S 
        arch/um        : Kconfig Kconfig_i386 Kconfig_x86_64 Makefile 
                         Makefile-i386 Makefile-x86_64 defconfig 
        arch/um/drivers: line.c 
        arch/um/include: mem.h registers.h time_user.h tlb.h 
        arch/um/include/sysdep-i386: ptrace_user.h 
        arch/um/include/sysdep-x86_64: ptrace_user.h 
        arch/um/kernel : dyn.lds.S physmem.c process.c time.c tlb.c 
                         uml.lds.S 
        arch/um/kernel/skas: Makefile exec_kern.c mem.c mem_user.c mmu.c 
                             process.c process_kern.c tlb.c 
        arch/um/kernel/skas/include: mmu-skas.h skas.h 
        arch/um/kernel/tt: tlb.c 
        arch/um/os-Linux/sys-i386: registers.c 
        arch/um/os-Linux/sys-x86_64: registers.c 
        arch/um/scripts: Makefile.rules 
        arch/um/sys-i386: Makefile 
        arch/um/sys-x86_64: Makefile 
        arch/v850      : Kconfig 
        arch/v850/lib  : checksum.c 
        arch/x86_64    : Kconfig Makefile 
        arch/x86_64/kernel: setup.c suspend.c vmlinux.lds.S 
        arch/xtensa    : Kconfig 
        arch/xtensa/kernel: asm-offsets.c syscalls.c syscalls.h traps.c 
                            vmlinux.lds.S 
        crypto         : Kconfig api.c cipher.c des.c hmac.c internal.h 
                         scatterwalk.c scatterwalk.h serpent.c 
        drivers        : Kconfig Makefile 
        drivers/acpi   : Kconfig Makefile asus_acpi.c bus.c button.c 
                         ec.c ibm_acpi.c osl.c pci_link.c 
                         processor_core.c processor_idle.c 
                         processor_perflib.c scan.c toshiba_acpi.c 
                         video.c 
        drivers/acpi/dispatcher: dsfield.c dsinit.c dsmethod.c 
                                 dsmthdat.c dsobject.c dsopcode.c 
                                 dsutils.c dswexec.c dswload.c 
                                 dswscope.c dswstate.c 
        drivers/acpi/events: evevent.c evgpe.c evgpeblk.c evmisc.c 
                             evregion.c evrgnini.c evsci.c evxface.c 
                             evxfevnt.c 
        drivers/acpi/executer: exconfig.c exconvrt.c excreate.c exdump.c 
                               exfield.c exfldio.c exmisc.c exmutex.c 
                               exnames.c exoparg1.c exoparg2.c 
                               exoparg3.c exoparg6.c exprep.c exregion.c 
                               exresnte.c exresolv.c exresop.c exstore.c 
                               exstoren.c exstorob.c exsystem.c 
                               exutils.c 
        drivers/acpi/hardware: hwacpi.c hwgpe.c hwregs.c hwsleep.c 
                               hwtimer.c 
        drivers/acpi/namespace: nsaccess.c nsalloc.c nsdump.c nsdumpdv.c 
                                nseval.c nsinit.c nsload.c nsnames.c 
                                nsobject.c nssearch.c nsutils.c nswalk.c 
                                nsxfeval.c nsxfname.c nsxfobj.c 
        drivers/acpi/parser: psargs.c psopcode.c psparse.c psscope.c 
                             pstree.c psutils.c pswalk.c psxface.c 
        drivers/acpi/resources: rsaddr.c rscalc.c rscreate.c rsdump.c 
                                rsio.c rsirq.c rslist.c rsmemory.c 
                                rsmisc.c rsutils.c rsxface.c 
        drivers/acpi/sleep: main.c poweroff.c proc.c 
        drivers/acpi/tables: tbconvrt.c tbget.c tbgetall.c tbinstal.c 
                             tbrsdt.c tbutils.c tbxface.c tbxfroot.c 
        drivers/acpi/utilities: utalloc.c utcopy.c utdebug.c utdelete.c 
                                uteval.c utglobal.c utinit.c utmath.c 
                                utmisc.c utobject.c utxface.c 
        drivers/base   : sys.c 
        drivers/bluetooth: bluecard_cs.c bt3c_cs.c btuart_cs.c dtl1_cs.c 
                           hci_vhci.c 
        drivers/char   : Makefile hvc_console.c hvsi.c n_tty.c random.c 
                         sysrq.c 
        drivers/char/drm: Kconfig Makefile ati_pcigart.c drm.h drmP.h 
                          drm_auth.c drm_bufs.c drm_context.c drm_drv.c 
                          drm_fops.c drm_irq.c drm_lock.c drm_memory.c 
                          drm_pciids.h drm_proc.c drm_stub.c drm_vm.c 
                          i810_dma.c i810_drv.h i830_dma.c i830_drv.c 
                          i830_drv.h i830_irq.c i915_dma.c i915_drv.c 
                          i915_drv.h i915_irq.c mga_drv.c mga_drv.h 
                          r128_drv.c r128_drv.h r128_state.c 
        drivers/char/pcmcia: synclink_cs.c 
        drivers/cpufreq: cpufreq.c 
        drivers/crypto : padlock-aes.c padlock.h 
        drivers/i2c    : i2c-core.c 
        drivers/i2c/algos: i2c-algo-ite.c 
        drivers/i2c/busses: i2c-i801.c i2c-keywest.c i2c-piix4.c 
                            i2c-sis5595.c 
        drivers/i2c/chips: Kconfig Makefile eeprom.c m41t00.c max6875.c 
                           tps65010.c 
        drivers/ide    : ide-cd.c 
        drivers/ide/legacy: ide-cs.c 
        drivers/ide/ppc: pmac.c 
        drivers/ieee1394: Kconfig csr.c csr1212.c dma.c eth1394.c 
                          ieee1394_core.c ieee1394_core.h iso.c iso.h 
                          nodemgr.c ohci1394.c pcilynx.c raw1394.c 
                          sbp2.c 
        drivers/infiniband: Kconfig 
        drivers/infiniband/core: Makefile verbs.c 
        drivers/infiniband/hw/mthca: mthca_cq.c mthca_dev.h mthca_main.c 
                                     mthca_memfree.c mthca_memfree.h 
                                     mthca_pd.c mthca_provider.c 
                                     mthca_provider.h mthca_qp.c 
        drivers/infiniband/include: ib_verbs.h 
        drivers/isdn/hardware/avm: avm_cs.c 
        drivers/isdn/hisax: avma1_cs.c elsa_cs.c isdnl1.c isdnl2.c 
                            isdnl3.c sedlbauer_cs.c teles_cs.c 
        drivers/isdn/i4l: isdn_tty.c 
        drivers/isdn/icn: icn.c 
        drivers/macintosh: Makefile macio_asic.c mediabay.c therm_pm72.c 
                           therm_windtunnel.c 
        drivers/md     : dm-mpath.c dm-raid1.c dm-snap.c dm-table.c dm.c 
        drivers/media/common: ir-common.c saa7146_core.c 
        drivers/media/dvb: Kconfig Makefile 
        drivers/media/dvb/b2c2: Kconfig Makefile flexcop-common.h 
                                flexcop-dma.c flexcop-hw-filter.c 
                                flexcop-misc.c flexcop-pci.c 
                                flexcop-reg.h flexcop-usb.c flexcop.c 
                                flexcop.h 
        drivers/media/dvb/bt8xx: dst.c dst_ca.c dst_common.h 
        drivers/media/dvb/cinergyT2: cinergyT2.c 
        drivers/media/dvb/dvb-core: dmxdev.c dvb_frontend.c 
                                    dvb_frontend.h 
        drivers/media/dvb/dvb-usb: Kconfig Makefile a800.c dibusb-mb.c 
                                   dibusb-mc.c digitv.c dtt200u-fe.c 
                                   dtt200u.c dtt200u.h dvb-usb-common.h 
                                   dvb-usb-dvb.c dvb-usb-ids.h 
                                   dvb-usb-init.c dvb-usb-remote.c 
                                   dvb-usb-urb.c dvb-usb.h nova-t-usb2.c 
                                   umt-010.c vp7045.c 
        drivers/media/dvb/frontends: Kconfig Makefile cx22702.c 
                                     cx22702.h dvb-pll.c dvb-pll.h 
                                     l64781.c stv0297.c tda1004x.c 
                                     tda1004x.h tda80xx.c 
        drivers/media/dvb/ttpci: Kconfig av7110.c av7110.h av7110_av.c 
                                 av7110_av.h av7110_hw.c av7110_hw.h 
                                 av7110_ipack.c budget-av.c budget-ci.c 
                                 budget.c 
        drivers/media/dvb/ttusb-budget: Kconfig dvb-ttusb-budget.c 
        drivers/media/dvb/ttusb-dec: ttusb_dec.c ttusbdecfe.c 
        drivers/media/video: Kconfig bt832.c bttv-cards.c bttv-driver.c 
                             bttv-i2c.c bttv-risc.c ir-kbd-i2c.c 
                             msp3400.c mt20xx.c mxb.c tda7432.c 
                             tda8290.c tda9875.c tda9887.c tea5767.c 
                             tuner-3036.c tuner-core.c tuner-simple.c 
                             tvaudio.c tveeprom.c 
        drivers/media/video/cx88: cx88-blackbird.c cx88-cards.c 
                                  cx88-core.c cx88-dvb.c cx88-i2c.c 
                                  cx88-input.c cx88-mpeg.c cx88-reg.h 
                                  cx88-tvaudio.c cx88-video.c cx88.h 
        drivers/media/video/saa7134: saa6752hs.c saa7134-cards.c 
                                     saa7134-core.c saa7134-dvb.c 
                                     saa7134-i2c.c saa7134-input.c 
                                     saa7134-oss.c saa7134-ts.c 
                                     saa7134-tvaudio.c saa7134-vbi.c 
                                     saa7134-video.c saa7134.h 
        drivers/message/fusion: mptbase.c mptscsih.h 
        drivers/message/i2o: config-osm.c 
        drivers/misc   : Kconfig 
        drivers/mtd    : cmdlinepart.c ftl.c mtdchar.c mtdcore.c 
                         mtdpart.c 
        drivers/mtd/chips: Kconfig amd_flash.c cfi_cmdset_0001.c 
                           cfi_cmdset_0002.c fwh_lock.h gen_probe.c 
                           jedec_probe.c 
        drivers/mtd/devices: block2mtd.c ms02-nv.c mtdram.c phram.c 
                             slram.c 
        drivers/mtd/maps: Kconfig Makefile amd76xrom.c bast-flash.c 
                          ichxrom.c ixp2000.c map_funcs.c pci.c 
                          pcmciamtd.c scb2_flash.c sharpsl-flash.c 
        drivers/mtd/nand: Kconfig Makefile diskonchip.c nand_base.c 
                          nand_bbt.c nand_ids.c nandsim.c rtc_from4.c 
                          s3c2410.c sharpsl.c 
        drivers/net    : Kconfig b44.c bmac.c mace.c myri_sbus.c 
                         ne2k-pci.c plip.c ppp_async.c ppp_generic.c 
                         ppp_synctty.c skge.c sungem.c sungem_phy.c 
                         sungem_phy.h tun.c typhoon.c 
        drivers/net/appletalk: Kconfig 
        drivers/net/hamradio: scc.c 
        drivers/net/pcmcia: 3c574_cs.c 3c589_cs.c axnet_cs.c 
                            com20020_cs.c fmvj18x_cs.c ibmtr_cs.c 
                            nmclan_cs.c pcnet_cs.c smc91c92_cs.c 
                            xirc2ps_cs.c 
        drivers/net/wan: farsync.c hdlc_cisco.c hdlc_ppp.c hdlc_raw.c 
        drivers/net/wireless: airo.c airo_cs.c airport.c atmel_cs.c 
                              netwave_cs.c orinoco_cs.c ray_cs.c 
                              wavelan_cs.c wavelan_cs.p.h wl3501_cs.c 
        drivers/parport: parport_cs.c 
        drivers/pci    : pci-acpi.c pci-driver.c pci.c pci.h search.c 
                         setup-bus.c 
        drivers/pci/hotplug: Kconfig Makefile 
        drivers/pci/pcie: portdrv_core.c 
        drivers/pcmcia : Kconfig au1000_generic.h au1000_pb1x00.c 
                         au1000_xxs1500.c cardbus.c cs.c cs_internal.h 
                         ds.c hd64465_ss.c i82365.c m32r_cfc.c 
                         m32r_pcc.c pcmcia_compat.c pcmcia_ioctl.c 
                         pcmcia_resource.c sa1100_generic.c soc_common.h 
                         socket_sysfs.c tcic.c ti113x.h yenta_socket.c 
        drivers/pnp    : resource.c 
        drivers/pnp/pnpacpi: rsparser.c 
        drivers/pnp/pnpbios: rsparser.c 
        drivers/s390/net: claw.c ctctty.c qeth_main.c 
        drivers/scsi   : mac53c94.c mesh.c 
        drivers/scsi/aacraid: commctrl.c 
        drivers/scsi/pcmcia: aha152x_stub.c fdomain_stub.c nsp_cs.c 
                             qlogic_stub.c sym53c500_cs.c 
        drivers/serial : pmac_zilog.c serial_cs.c 
        drivers/telephony: ixj_pcmcia.c 
        drivers/usb    : Makefile 
        drivers/usb/atm: cxacru.c speedtch.c 
        drivers/usb/class: cdc-acm.c 
        drivers/usb/core: buffer.c hcd-pci.c hcd.c hcd.h hub.c message.c 
                          sysfs.c urb.c usb.c 
        drivers/usb/gadget: dummy_hcd.c ether.c goku_udc.c lh7a40x_udc.c 
                            net2280.c omap_udc.c pxa2xx_udc.c zero.c 
        drivers/usb/host: ehci-hcd.c ehci-q.c ehci-sched.c hc_crisv10.c 
                          isp116x-hcd.c ohci-hcd.c ohci-hub.c ohci-mem.c 
                          ohci-omap.c sl811-hcd.c sl811_cs.c uhci-q.c 
        drivers/usb/input: Kconfig Makefile hid-core.c 
        drivers/usb/media: Makefile sn9c102.h sn9c102_core.c 
                           sn9c102_sensor.h sn9c102_tas5110c1b.c 
                           sn9c102_tas5130d1b.c 
        drivers/usb/misc: Kconfig Makefile 
        drivers/usb/mon: mon_text.c 
        drivers/usb/net: kaweth.c usbnet.c 
        drivers/usb/serial: ftdi_sio.c 
        drivers/usb/storage: unusual_devs.h 
        drivers/video  : fbsysfs.c platinumfb.c s1d13xxxfb.c 
        drivers/video/logo: Kconfig Makefile logo.c 
        drivers/video/savage: savagefb_driver.c 
        drivers/w1     : w1.c 
        fs             : Kconfig Makefile attr.c bio.c buffer.c 
                         char_dev.c compat.c dcookies.c exec.c 
                         file_table.c inode.c ioprio.c locks.c namei.c 
                         namespace.c open.c read_write.c super.c xattr.c 
        fs/autofs4     : waitq.c 
        fs/ext2        : ext2.h super.c 
        fs/ext3        : inode.c super.c 
        fs/hppfs       : hppfs_kern.c 
        fs/jffs2       : Makefile README.Locking background.c build.c 
                         compr_zlib.c dir.c erase.c file.c fs.c gc.c 
                         nodelist.c nodelist.h nodemgmt.c os-linux.h 
                         read.c readinode.c scan.c super.c symlink.c 
                         wbuf.c write.c 
        fs/nfsd        : nfs4proc.c nfs4recover.c nfs4state.c nfs4xdr.c 
                         vfs.c 
        fs/reiserfs    : bitmap.c dir.c do_balan.c file.c fix_node.c 
                         hashes.c ibalance.c inode.c ioctl.c item_ops.c 
                         journal.c lbalance.c namei.c objectid.c 
                         prints.c procfs.c resize.c stree.c super.c 
                         tail_conversion.c xattr.c xattr_acl.c 
                         xattr_security.c xattr_trusted.c xattr_user.c 
        fs/sysfs       : file.c 
        include/acpi   : acconfig.h acdebug.h acdisasm.h acdispat.h 
                         acevents.h acexcep.h acglobal.h achware.h 
                         acinterp.h aclocal.h acmacros.h acnamesp.h 
                         acobject.h acparser.h acpi.h acpi_bus.h 
                         acpi_drivers.h acpiosxf.h acpixf.h acresrc.h 
                         acstruct.h actables.h actbl.h actypes.h 
                         acutils.h amlcode.h processor.h 
        include/acpi/platform: acenv.h 
        include/asm-alpha: pci.h pgtable.h 
        include/asm-arm: pci.h 
        include/asm-arm/arch-ixp2000: platform.h 
        include/asm-arm/arch-ixp4xx: io.h 
        include/asm-arm/arch-omap: board-h2.h board-h3.h board-osk.h 
                                   board.h dma.h hardware.h irqs.h mux.h 
                                   omap16xx.h system.h 
        include/asm-h8300: pci.h 
        include/asm-i386: acpi.h apicdef.h mmzone.h pci.h processor.h 
                          unistd.h 
        include/asm-ia64: acpi.h hw_irq.h pci.h 
        include/asm-ia64/sn: arch.h intr.h pcidev.h sn_cpuid.h sn_sal.h 
                             xp.h 
        include/asm-m68k: pci.h 
        include/asm-mips: pci.h unistd.h 
        include/asm-ppc: kexec.h macio.h of_device.h pci.h unistd.h 
        include/asm-ppc64: cputable.h hvconsole.h machdep.h pci.h 
                           processor.h unistd.h 
        include/asm-sh : pci.h 
        include/asm-sh64: pci.h 
        include/asm-sparc: pci.h unistd.h 
        include/asm-sparc64: param.h parport.h pci.h thread_info.h 
                             unistd.h 
        include/asm-um : mmu_context.h 
        include/asm-v850: checksum.h mmu.h 
        include/asm-x86_64: acpi.h pci.h proto.h 
        include/asm-xtensa: unistd.h 
        include/linux  : acpi.h audit.h buffer_head.h cache.h cpufreq.h 
                         crypto.h device.h etherdevice.h ext3_fs.h 
                         fddidevice.h fs.h gfp.h hardirq.h hdlc.h igmp.h 
                         ioprio.h jffs2_fs_sb.h mod_devicetable.h 
                         mount.h namespace.h netlink.h pm.h 
                         reiserfs_acl.h reiserfs_fs.h reiserfs_fs_i.h 
                         reiserfs_fs_sb.h reiserfs_xattr.h sched.h 
                         skbuff.h slab.h string.h swap.h syscalls.h 
                         sysctl.h usb.h usb_cdc.h usb_gadget.h 
                         wanrouter.h 
        include/linux/mtd: cfi.h flashchip.h inftl.h map.h mtd.h nand.h 
                           xip.h 
        include/linux/nfsd: nfsd.h state.h 
        include/media  : audiochip.h saa6752hs.h tuner.h 
        include/mtd    : mtd-abi.h 
        include/net    : sock.h tcp.h x25device.h 
        include/net/irda: irda_device.h 
        include/net/sctp: sctp.h sm.h structs.h ulpevent.h ulpqueue.h 
        include/pcmcia : cs.h cs_types.h ds.h version.h 
        init           : Kconfig do_mounts.c do_mounts.h 
        ipc            : compat.c util.h 
        kernel         : fork.c profile.c sched.c sys_ni.c sysctl.c 
                         user.c 
        kernel/power   : disk.c main.c process.c swsusp.c 
        lib            : radix-tree.c 
        mm             : filemap_xip.c mempool.c oom_kill.c page_alloc.c 
                         slab.c 
        net            : Kconfig 
        net/802        : fddi.c 
        net/8021q      : vlan.c 
        net/atm        : br2684.c 
        net/bluetooth/cmtp: core.c 
        net/bluetooth/hidp: core.c 
        net/bluetooth/rfcomm: sock.c tty.c 
        net/core       : dev.c skbuff.c sock.c 
        net/decnet     : Kconfig af_decnet.c dn_nsp_out.c 
        net/ethernet   : eth.c 
        net/ipv4       : Kconfig icmp.c igmp.c ip_output.c ip_sockglue.c 
                         route.c tcp.c tcp_input.c tcp_output.c 
                         tcp_timer.c 
        net/ipv4/ipvs  : Kconfig ip_vs_conn.c ip_vs_ctl.c 
        net/ipv4/netfilter: ip_conntrack_standalone.c 
        net/ipv6       : Kconfig mcast.c 
        net/ipx        : Kconfig 
        net/irda       : irlap.c irlap_event.c irlap_frame.c irttp.c 
        net/llc        : llc_c_ev.c 
        net/netlink    : af_netlink.c 
        net/packet     : af_packet.c 
        net/sched      : Kconfig sch_red.c 
        net/sctp       : associola.c bind_addr.c chunk.c endpointola.c 
                         input.c inqueue.c output.c outqueue.c 
                         protocol.c sm_make_chunk.c sm_sideeffect.c 
                         socket.c ssnmap.c transport.c ulpevent.c 
                         ulpqueue.c 
        net/sunrpc     : xprt.c 
        net/unix       : af_unix.c 
        net/wanrouter  : wanmain.c 
        net/xfrm       : Kconfig 
        scripts/mod    : file2alias.c 
        security/keys  : keyring.c 
        sound/oss      : cs46xx.c 
        sound/pci      : bt87x.c 
        sound/pcmcia/pdaudiocf: pdaudiocf.c 
        sound/pcmcia/vx: vx_entry.c vxpocket.c 
Added files:
        Documentation  : acpi-hotkey.txt 
        Documentation/filesystems: inotify.txt 
        Documentation/hwmon: adm1021 adm1025 adm1026 adm1031 adm9240 
                             asb100 ds1621 fscher gl518sm it87 lm63 lm75 
                             lm77 lm78 lm80 lm83 lm85 lm87 lm90 lm92 
                             max1619 pc87360 sis5595 smsc47b397 smsc47m1 
                             sysfs-interface userspace-tools via686a 
                             w83627hf w83781d w83l785ts 
        Documentation/infiniband: user_verbs.txt 
        arch/arm/mach-omap1: Kconfig Makefile Makefile.boot 
                             board-generic.c board-h2.c board-h3.c 
                             board-innovator.c board-netstar.c 
                             board-osk.c board-perseus2.c 
                             board-voiceblue.c fpga.c id.c io.c irq.c 
                             leds-h2p2-debug.c leds-innovator.c 
                             leds-osk.c leds.c leds.h serial.c time.c 
        arch/arm/plat-omap: Kconfig Makefile clock.c clock.h common.c 
                            cpu-omap.c dma.c gpio.c mcbsp.c mux.c ocpi.c 
                            pm.c sleep.S usb.c 
        arch/frv       : defconfig 
        arch/i386/kernel/acpi: cstate.c 
        arch/ia64/kernel: numa.c 
        arch/um/include/sysdep-i386: stub.h 
        arch/um/include/sysdep-x86_64: stub.h 
        arch/um/kernel/skas: clone.c 
        arch/um/kernel/skas/include: mm_id.h stub-data.h 
        arch/um/sys-i386: stub.S stub_segv.c 
        arch/um/sys-x86_64: stub.S stub_segv.c 
        arch/x86_64/crypto: Makefile aes-x86_64-asm.S aes.c 
        drivers/acpi   : glue.c hotkey.c 
        drivers/char   : hvc_vio.c 
        drivers/char/drm: i915_ioc32.c mga_ioc32.c r128_ioc32.c 
                          via_3d_reg.h via_dma.c via_drm.h via_drv.c 
                          via_drv.h via_ds.c via_ds.h via_irq.c 
                          via_map.c via_mm.c via_mm.h via_verifier.c 
                          via_verifier.h via_video.c 
        drivers/hwmon  : Kconfig Makefile adm1021.c adm1025.c adm1026.c 
                         adm1031.c adm9240.c asb100.c atxp1.c ds1621.c 
                         fscher.c fscpos.c gl518sm.c gl520sm.c it87.c 
                         lm63.c lm75.c lm75.h lm77.c lm78.c lm80.c 
                         lm83.c lm85.c lm87.c lm90.c lm92.c max1619.c 
                         pc87360.c sis5595.c smsc47b397.c smsc47m1.c 
                         via686a.c w83627ehf.c w83627hf.c w83781d.c 
                         w83l785ts.c 
        drivers/infiniband/core: uverbs.h uverbs_cmd.c uverbs_main.c 
                                 uverbs_mem.c 
        drivers/infiniband/hw/mthca: mthca_user.h 
        drivers/infiniband/include: ib_user_verbs.h 
        drivers/macintosh: macio_sysfs.c 
        drivers/media/dvb/b2c2: flexcop_ibi_value_be.h 
                                flexcop_ibi_value_le.h 
        drivers/media/dvb/dvb-usb: cxusb.c cxusb.h 
        drivers/media/dvb/frontends: lgdt3302.c lgdt3302.h 
                                     lgdt3302_priv.h s5h1420.c s5h1420.h 
        drivers/media/dvb/pluto2: Kconfig Makefile pluto2.c 
        drivers/mtd/maps: mainstone-flash.c omap_nor.c plat-ram.c 
        drivers/pci/hotplug: sgi_hotplug.c 
        drivers/usb/input: keyspan_remote.c 
        drivers/usb/media: sn9c102_ov7630.c 
        drivers/usb/misc: ldusb.c 
        drivers/video/logo: logo_m32r_clut224.ppm 
        fs             : inotify.c 
        include/acpi   : acnames.h acopcode.h pdc_intel.h 
        include/asm-arm: mtd-xip.h 
        include/asm-arm/arch-omap: common.h 
        include/asm-arm/arch-pxa: mtd-xip.h 
        include/asm-arm/arch-sa1100: mtd-xip.h 
        include/asm-ia64/sn: pcibr_provider.h pic.h tiocp.h 
        include/asm-m32r: s1d13806.h 
        include/asm-sparc64: seccomp.h 
        include/linux  : fsnotify.h inotify.h 
        include/linux/mtd: plat-ram.h 
        net/8021q      : Kconfig 
        net/atm        : Kconfig 
        net/bridge     : Kconfig 
        net/econet     : Kconfig 
        net/lapb       : Kconfig 
        net/packet     : Kconfig 
        net/unix       : Kconfig 
        net/wanrouter  : Kconfig 
        net/x25        : Kconfig 
Removed files:
        Documentation/i2c: sysfs-interface userspace-tools 
        Documentation/i2c/chips: adm1021 adm1025 adm1026 adm1031 adm9240 
                                 asb100 ds1621 fscher gl518sm it87 lm63 
                                 lm75 lm77 lm78 lm80 lm83 lm85 lm87 lm90 
                                 lm92 max1619 pc87360 sis5595 smsc47b397 
                                 smsc47m1 via686a w83627hf w83781d 
                                 w83l785ts 
        arch/arm/mach-omap: Kconfig Makefile Makefile.boot 
                            board-generic.c board-h2.c board-h3.c 
                            board-innovator.c board-netstar.c 
                            board-osk.c board-perseus2.c 
                            board-voiceblue.c clock.c clock.h common.c 
                            common.h dma.c fpga.c gpio.c irq.c 
                            leds-h2p2-debug.c leds-innovator.c 
                            leds-osk.c leds.c leds.h mcbsp.c mux.c 
                            ocpi.c pm.c sleep.S time.c usb.c 
        arch/ia64/sn/include/pci: pcibr_provider.h pic.h tiocp.h 
        drivers/i2c/chips: adm1021.c adm1025.c adm1026.c adm1031.c 
                           adm9240.c asb100.c atxp1.c ds1621.c fscher.c 
                           fscpos.c gl518sm.c gl520sm.c it87.c lm63.c 
                           lm75.c lm75.h lm77.c lm78.c lm80.c lm83.c 
                           lm85.c lm87.c lm90.c lm92.c max1619.c 
                           pc87360.c sis5595.c smsc47b397.c smsc47m1.c 
                           via686a.c w83627ehf.c w83627hf.c w83781d.c 
                           w83l785ts.c 
        drivers/media/dvb/b2c2: skystar2.c 
        drivers/mtd/maps: elan-104nc.c 
        drivers/mtd/nand: tx4925ndfmc.c tx4938ndfmc.c 
        include/asm-xtensa: ipc.h 

Log message:
        Merge with Linux 2.6.13-rc3.

diff -urN linux/MAINTAINERS linux/MAINTAINERS
--- linux/MAINTAINERS   2005/07/11 20:45:51     1.183
+++ linux/MAINTAINERS   2005/07/13 11:48:45     1.184
@@ -370,6 +370,10 @@
 W:     http://atmelwlandriver.sourceforge.net/
 S:     Maintained
 
+AUDIT SUBSYSTEM
+L:     linux-audit@redhat.com (subscribers-only)
+S:     Maintained
+
 AX.25 NETWORK LAYER
 P:     Ralf Baechle
 M:     ralf@linux-mips.org
@@ -1236,7 +1240,7 @@
 
 IRDA SUBSYSTEM
 P:     Jean Tourrilhes
-L:     irda-users@lists.sourceforge.net
+L:     irda-users@lists.sourceforge.net (subscribers-only)
 W:     http://irda.sourceforge.net/
 S:     Maintained
 
@@ -1803,8 +1807,9 @@
 S:     Maintained
 
 PCMCIA SUBSYSTEM
+P:     Linux PCMCIA Team
 L:     http://lists.infradead.org/mailman/listinfo/linux-pcmcia
-S:     Unmaintained
+S:     Maintained
 
 PCNET32 NETWORK DRIVER
 P:     Thomas Bogendörfer
@@ -2161,7 +2166,7 @@
 P:     David S. Miller
 M:     davem@davemloft.net
 P:     Eddie C. Dost
-M:     ecd@skynet.be
+M:     ecd@brainaid.de
 P:     Jakub Jelinek
 M:     jj@sunsite.ms.mff.cuni.cz
 P:     Anton Blanchard
diff -urN linux/Makefile linux/Makefile
--- linux/Makefile      2005/07/12 09:18:53     1.256
+++ linux/Makefile      2005/07/13 11:48:45     1.257
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
 SUBLEVEL = 13
-EXTRAVERSION =-rc2
+EXTRAVERSION =-rc3
 NAME=Woozy Numbat
 
 # *DOCUMENTATION*
@@ -790,6 +790,9 @@
        $(Q)$(MAKE) $(build)=$(@D) $@
 %.o: %.c scripts FORCE
        $(Q)$(MAKE) $(build)=$(@D) $@
+%.ko: scripts FORCE
+       $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) $(build)=$(@D) 
$(@:.ko=.o)
+       $(Q)$(MAKE) -rR -f $(srctree)/scripts/Makefile.modpost
 %/:      scripts prepare FORCE
        $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) $(build)=$(@D)
 %.lst: %.c scripts FORCE
@@ -1031,6 +1034,7 @@
        @echo  '  modules_install - Install all modules'
        @echo  '  dir/            - Build all files in dir and below'
        @echo  '  dir/file.[ois]  - Build specified target only'
+       @echo  '  dir/file.ko     - Build module including final link'
        @echo  '  rpm             - Build a kernel as an RPM package'
        @echo  '  tags/TAGS       - Generate tags file for editors'
        @echo  '  cscope          - Generate cscope index'
@@ -1147,7 +1151,7 @@
 #(which is the most common case IMHO) to avoid unneeded clutter in the big 
tags file.
 #Adding $(srctree) adds about 20M on i386 to the size of the output file!
 
-ifeq ($(KBUILD_OUTPUT),)
+ifeq ($(src),$(obj))
 __srctree =
 else
 __srctree = $(srctree)/
diff -urN linux/Documentation/acpi-hotkey.txt 
linux/Documentation/acpi-hotkey.txt
--- linux/Documentation/acpi-hotkey.txt 1970/01/01 00:00:00
+++ linux/Documentation/acpi-hotkey.txt 2005-07-13 12:48:46.330682000 +0100     
1.1
@@ -0,0 +1,35 @@
+driver/acpi/hotkey.c implement:
+1. /proc/acpi/hotkey/event_config 
+(event based hotkey or event config interface):
+a. add a  event based hotkey(event) : 
+echo "0:bus::action:method:num:num" > event_config
+
+b. delete a event based hotkey(event): 
+echo "1:::::num:num" > event_config
+
+c.  modify a event based hotkey(event):    
+echo "2:bus::action:method:num:num" > event_config
+
+2. /proc/acpi/hotkey/poll_config 
+(polling based hotkey or event config interface):
+a.add a polling based hotkey(event) :  
+echo "0:bus:method:action:method:num" > poll_config
+this adding command will create a proc file 
+/proc/acpi/hotkey/method, which is used to get 
+result of polling.
+
+b.delete a polling based hotkey(event):        
+echo "1:::::num" > event_config
+
+c.modify a polling based hotkey(event):    
+echo "2:bus:method:action:method:num" > poll_config
+
+3./proc/acpi/hotkey/action 
+(interface to call aml method associated with a 
+specific hotkey(event))
+echo "event_num:event_type:event_argument" > 
+       /proc/acpi/hotkey/action.
+The result of the execution of this aml method is 
+attached to /proc/acpi/hotkey/poll_method, which is dnyamically
+created.  Please use command "cat /proc/acpi/hotkey/polling_method" 
+to retrieve it.
diff -urN linux/Documentation/feature-removal-schedule.txt 
linux/Documentation/feature-removal-schedule.txt
--- linux/Documentation/feature-removal-schedule.txt    2005/07/11 20:45:51     
1.8
+++ linux/Documentation/feature-removal-schedule.txt    2005/07/13 11:48:46     
1.9
@@ -119,3 +119,19 @@
        will be available until removal of old names.
 Who:   Grant Coady <gcoady@gmail.com>
 
+---------------------------
+
+What:  PCMCIA control ioctl (needed for pcmcia-cs [cardmgr, cardctl])
+When:  November 2005
+Files: drivers/pcmcia/: pcmcia_ioctl.c
+Why:   With the 16-bit PCMCIA subsystem now behaving (almost) like a
+       normal hotpluggable bus, and with it using the default kernel
+       infrastructure (hotplug, driver core, sysfs) keeping the PCMCIA
+       control ioctl needed by cardmgr and cardctl from pcmcia-cs is
+       unnecessary, and makes further cleanups and integration of the
+       PCMCIA subsystem into the Linux kernel device driver model more
+       difficult. The features provided by cardmgr and cardctl are either
+       handled by the kernel itself now or are available in the new
+       pcmciautils package available at
+       http://kernel.org/pub/linux/utils/kernel/pcmcia/
+Who:   Dominik Brodowski <linux@brodo.de>
diff -urN linux/Documentation/kernel-parameters.txt 
linux/Documentation/kernel-parameters.txt
--- linux/Documentation/kernel-parameters.txt   2005/07/12 09:18:54     1.61
+++ linux/Documentation/kernel-parameters.txt   2005/07/13 11:48:46     1.62
@@ -37,7 +37,7 @@
        IA-32   IA-32 aka i386 architecture is enabled.
        IA-64   IA-64 architecture is enabled.
        IOSCHED More than one I/O scheduler is enabled.
-       IP_PNP  IP DCHP, BOOTP, or RARP is enabled.
+       IP_PNP  IP DHCP, BOOTP, or RARP is enabled.
        ISAPNP  ISA PnP code is enabled.
        ISDN    Appropriate ISDN support is enabled.
        JOY     Appropriate joystick support is enabled.
@@ -758,6 +758,9 @@
        maxcpus=        [SMP] Maximum number of processors that an SMP kernel
                        should make use of
 
+       max_addr=[KMG]  [KNL,BOOT,ia64] All physical memory greater than or
+                       equal to this physical address is ignored.
+
        max_luns=       [SCSI] Maximum number of LUNs to probe
                        Should be between 1 and 2^32-1.
 
diff -urN linux/Documentation/dvb/README.dvb-usb 
linux/Documentation/dvb/README.dvb-usb
--- linux/Documentation/dvb/README.dvb-usb      2005/07/11 20:45:53     1.1
+++ linux/Documentation/dvb/README.dvb-usb      2005/07/13 11:48:46     1.2
@@ -13,14 +13,17 @@
 The framework provides generic functions (mostly kernel API calls), such as:
 
 - Transport Stream URB handling in conjunction with dvb-demux-feed-control
-  (bulk and isoc (TODO) are supported)
+  (bulk and isoc are supported)
 - registering the device for the DVB-API
 - registering an I2C-adapter if applicable
 - remote-control/input-device handling
 - firmware requesting and loading (currently just for the Cypress USB
-  controller)
+  controllers)
 - other functions/methods which can be shared by several drivers (such as
   functions for bulk-control-commands)
+- TODO: a I2C-chunker. It creates device-specific chunks of register-accesses
+  depending on length of a register and the number of values that can be
+  multi-written and multi-read.
 
 The source code of the particular DVB USB devices does just the communication
 with the device via the bus. The connection between the DVB-API-functionality
@@ -36,93 +39,18 @@
 TODO: dynamic enabling and disabling of the pid-filter in regard to number of
 feeds requested.
 
-Supported devices USB1.1
+Supported devices
 ========================
 
-Produced and reselled by Twinhan:
----------------------------------
-- TwinhanDTV USB-Ter DVB-T Device (VP7041)
-       http://www.twinhan.com/product_terrestrial_3.asp
+See the LinuxTV DVB Wiki at www.linuxtv.org for a complete list of
+cards/drivers/firmwares:
 
-- TwinhanDTV Magic Box (VP7041e)
-       http://www.twinhan.com/product_terrestrial_4.asp
-
-- HAMA DVB-T USB device
-       http://www.hama.de/portal/articleId*110620/action*2598
-
-- CTS Portable (Chinese Television System) (2)
-       http://www.2cts.tv/ctsportable/
-
-- Unknown USB DVB-T device with vendor ID Hyper-Paltek
-
-
-Produced and reselled by KWorld:
---------------------------------
-- KWorld V-Stream XPERT DTV DVB-T USB
-       http://www.kworld.com.tw/en/product/DVBT-USB/DVBT-USB.html
-
-- JetWay DTV DVB-T USB
-       http://www.jetway.com.tw/evisn/product/lcd-tv/DVT-USB/dtv-usb.htm
-
-- ADSTech Instant TV DVB-T USB
-       
http://www.adstech.com/products/PTV-333/intro/PTV-333_intro.asp?pid=PTV-333
-
-
-Others:
--------
-- Ultima Electronic/Artec T1 USB TVBOX (AN2135, AN2235, AN2235 with Panasonic 
Tuner)
-       http://82.161.246.249/products-tvbox.html
-
-- Compro Videomate DVB-U2000 - DVB-T USB (2)
-       http://www.comprousa.com/products/vmu2000.htm
-
-- Grandtec USB DVB-T
-       http://www.grand.com.tw/
-
-- AVerMedia AverTV DVBT USB
-       http://www.avermedia.com/
-
-- DiBcom USB DVB-T reference device (non-public)
-
-
-Supported devices USB2.0-only
-=============================
-- Twinhan MagicBox II
-       http://www.twinhan.com/product_terrestrial_7.asp
-
-- TwinhanDTV Alpha
-       http://www.twinhan.com/product_terrestrial_8.asp
-
-- DigitalNow TinyUSB 2 DVB-t Receiver
-       http://www.digitalnow.com.au/DigitalNow%20tinyUSB2%20Specifications.html
-
-- Hanftek UMT-010
-       
http://www.globalsources.com/si/6008819757082/ProductDetail/Digital-TV/product_id-100046529
-
-
-Supported devices USB2.0 and USB1.1
-=============================
-- Typhoon/Yakumo/HAMA/Yuan DVB-T mobile USB2.0
-       http://www.yakumo.de/produkte/index.php?pid=1&ag=DVB-T
-       http://www.yuan.com.tw/en/products/vdo_ub300.html
-       http://www.hama.de/portal/articleId*114663/action*2563
-       http://www.anubisline.com/english/articlec.asp?id=50502&catid=002
-
-- Artec T1 USB TVBOX (FX2) (2)
-
-- Hauppauge WinTV NOVA-T USB2
-       http://www.hauppauge.com/
-
-- KWorld/ADSTech Instant DVB-T USB2.0 (DiB3000M-B)
-
-- DiBcom USB2.0 DVB-T reference device (non-public)
-
-- AVerMedia AverTV A800 DVB-T USB2.0
-
-1) It is working almost - work-in-progress.
-2) No test reports received yet.
+http://www.linuxtv.org/wiki/index.php/DVB_USB
 
 0. History & News:
+  2005-06-30 - added support for WideView WT-220U (Thanks to Steve Chang)
+  2005-05-30 - added basic isochronous support to the dvb-usb-framework
+               added support for Conexant Hybrid reference design and Nebula 
DigiTV USB
   2005-04-17 - all dibusb devices ported to make use of the dvb-usb-framework
   2005-04-02 - re-enabled and improved remote control code.
   2005-03-31 - ported the Yakumo/Hama/Typhoon DVB-T USB2.0 device to dvb-usb.
@@ -137,7 +65,7 @@
   2005-01-31 - distorted streaming is gone for USB1.1 devices
   2005-01-13 - moved the mirrored pid_filter_table back to dvb-dibusb
              - first almost working version for HanfTek UMT-010
-             - found out, that Yakumo/HAMA/Typhoon are predessors of the 
HanfTek UMT-010
+             - found out, that Yakumo/HAMA/Typhoon are predecessors of the 
HanfTek UMT-010
   2005-01-10 - refactoring completed, now everything is very delightful
              - tuner quirks for some weird devices (Artec T1 AN2235 device has 
sometimes a
                Panasonic Tuner assembled). Tunerprobing implemented. Thanks a 
lot to Gunnar Wittich.
@@ -187,25 +115,13 @@
 1. How to use?
 1.1. Firmware
 
-Most of the USB drivers need to download a firmware to start working.
-
-for USB1.1 (AN2135) you need: dvb-usb-dibusb-5.0.0.11.fw
-for USB2.0 HanfTek: dvb-usb-umt-010-02.fw
-for USB2.0 DiBcom: dvb-usb-dibusb-6.0.0.8.fw
-for USB2.0 AVerMedia AverTV DVB-T USB2: dvb-usb-avertv-a800-01.fw
-for USB2.0 TwinhanDTV Alpha/MagicBox II: dvb-usb-vp7045-01.fw
-
-The files can be found on http://www.linuxtv.org/download/firmware/ .
+Most of the USB drivers need to download a firmware to the device before start
+working.
 
-We do not have the permission (yet) to publish the following firmware-files.
-You'll need to extract them from the windows drivers.
+Have a look at the Wikipage for the DVB-USB-drivers to find out, which firmware
+you need for your device:
 
-You should be able to use "get_dvb_firmware dvb-usb" to get the firmware:
-
-for USB1.1 (AN2235) (a few Artec T1 devices): dvb-usb-dibusb-an2235-01.fw
-for USB2.0 Hauppauge: dvb-usb-nova-t-usb2-01.fw
-for USB2.0 ADSTech/Kworld USB2.0: dvb-usb-adstech-usb2-01.fw
-for USB2.0 Yakumo/Typhoon/Hama: dvb-usb-dtt200u-01.fw
+http://www.linuxtv.org/wiki/index.php/DVB_USB
 
 1.2. Compiling
 
@@ -289,6 +205,9 @@
    Gunnar Wittich and Joachim von Caron for their trust for providing
     root-shells on their machines to implement support for new devices.
 
+   Allan Third and Michael Hutchinson for their help to write the Nebula
+    digitv-driver.
+
    Glen Harris for bringing up, that there is a new dibusb-device and Jiun-Kuei
     Jung from AVerMedia who kindly provided a special firmware to get the 
device
     up and running in Linux.
@@ -296,7 +215,12 @@
    Jennifer Chen, Jeff and Jack from Twinhan for kindly supporting by
        writing the vp7045-driver.
 
-   Some guys on the linux-dvb mailing list for encouraging me
+   Steve Chang from WideView for providing information for new devices and
+       firmware files.
+
+   Michael Paxton for submitting remote control keymaps.
+
+   Some guys on the linux-dvb mailing list for encouraging me.
 
    Peter Schildmann >peter.schildmann-nospam-at-web.de< for his
     user-level firmware loader, which saves a lot of time
@@ -305,4 +229,4 @@
    Ulf Hermenau for helping me out with traditional chinese.
 
    André Smoktun and Christian Frömmel for supporting me with
-    hardware and listening to my problems very patient.
+    hardware and listening to my problems very patiently.
diff -urN linux/Documentation/dvb/bt8xx.txt linux/Documentation/dvb/bt8xx.txt
--- linux/Documentation/dvb/bt8xx.txt   2005/07/11 20:45:53     1.3
+++ linux/Documentation/dvb/bt8xx.txt   2005/07/13 11:48:46     1.4
@@ -1,66 +1,55 @@
-How to get the Nebula, PCTV and Twinhan DST cards working
-=========================================================
+How to get the Nebula Electronics DigiTV, Pinnacle PCTV Sat, Twinhan DST + 
clones working
+=========================================================================================
 
-This class of cards has a bt878a as the PCI interface, and
-require the bttv driver.
+1) General information
+======================
 
-Please pay close attention to the warning about the bttv module
-options below for the DST card.
+This class of cards has a bt878a chip as the PCI interface.
+The different card drivers require the bttv driver to provide the means
+to access the i2c bus and the gpio pins of the bt8xx chipset.
 
-1) General informations
-=======================
+2) Compilation rules for Kernel >= 2.6.12
+=========================================
 
-These drivers require the bttv driver to provide the means to access
-the i2c bus and the gpio pins of the bt8xx chipset.
+Enable the following options:
 
-Because of this, you need to enable
 "Device drivers" => "Multimedia devices"
-  => "Video For Linux" => "BT848 Video For Linux"
-
-Furthermore you need to enable
+ => "Video For Linux" => "BT848 Video For Linux"
 "Device drivers" => "Multimedia devices" => "Digital Video Broadcasting 
Devices"
-  => "DVB for Linux" "DVB Core Support" "Nebula/Pinnacle PCTV/TwinHan PCI 
Cards"
+ => "DVB for Linux" "DVB Core Support" "Nebula/Pinnacle PCTV/TwinHan PCI Cards"
 
-2) Loading Modules
-==================
+3) Loading Modules, described by two approaches
+===============================================
 
 In general you need to load the bttv driver, which will handle the gpio and
-i2c communication for us, plus the common dvb-bt8xx device driver.
-The frontends for Nebula (nxt6000), Pinnacle PCTV (cx24110) and
-TwinHan (dst) are loaded automatically by the dvb-bt8xx device driver.
+i2c communication for us, plus the common dvb-bt8xx device driver,
+which is called the backend.
+The frontends for Nebula DigiTV (nxt6000), Pinnacle PCTV Sat (cx24110),
+TwinHan DST + clones (dst and dst-ca) are loaded automatically by the backend.
+For further details about TwinHan DST + clones see /Documentation/dvb/ci.txt.
+
+3a) The manual approach
+-----------------------
+
+Loading modules:
+modprobe bttv
+modprobe dvb-bt8xx
+
+Unloading modules:
+modprobe -r dvb-bt8xx
+modprobe -r bttv
 
-3a) Nebula / Pinnacle PCTV
+3b) The automatic approach
 --------------------------
 
-   $ modprobe bttv (normally bttv is being loaded automatically by kmod)
-   $ modprobe dvb-bt8xx (or just place dvb-bt8xx in /etc/modules for automatic 
loading)
-
+If not already done by installation, place a line either in
+/etc/modules.conf or in /etc/modprobe.conf containing this text:
+alias char-major-81    bttv
 
-3b) TwinHan and Clones
---------------------------
+Then place a line in /etc/modules containing this text:
+dvb-bt8xx
 
-   $ modprobe bttv i2c_hw=1 card=0x71
-   $ modprobe dvb-bt8xx
-   $ modprobe dst
-
-The value 0x71 will override the PCI type detection for dvb-bt8xx,
-which is necessary for TwinHan cards.
-
-If you're having an older card (blue color circuit) and card=0x71 locks
-your machine, try using 0x68, too. If that does not work, ask on the
-mailing list.
-
-The DST module takes a couple of useful parameters:
-
-a. verbose takes values 0 to 5. These values control the verbosity level.
-b. debug takes values 0 and 1. You can either disable or enable debugging.
-c. dst_addons takes values 0 and 0x20:
-- A value of 0 means it is a FTA card.
-- A value of 0x20 means it has a Conditional Access slot.
-
-The autodetected values are determined by the "response string"
-of the card, which you can see in your logs:
-e.g.: dst_get_device_id: Recognize [DSTMCI]
+Reboot your system and have fun!
 
 --
 Authors: Richard Walker, Jamie Honan, Michael Hunold, Manu Abraham, Uwe Bugla
diff -urN linux/Documentation/filesystems/inotify.txt 
linux/Documentation/filesystems/inotify.txt
--- linux/Documentation/filesystems/inotify.txt 1970/01/01 00:00:00
+++ linux/Documentation/filesystems/inotify.txt 2005-07-13 12:48:46.749684000 
+0100     1.1
@@ -0,0 +1,138 @@
+                                   inotify
+            a powerful yet simple file change notification system
+
+
+
+Document started 15 Mar 2005 by Robert Love <rml@novell.com>
+
+(i) User Interface
+
+Inotify is controlled by a set of three sys calls 
+
+First step in using inotify is to initialise an inotify instance
+
+       int fd = inotify_init ();
+
+Change events are managed by "watches".  A watch is an (object,mask) pair where
+the object is a file or directory and the mask is a bit mask of one or more
+inotify events that the application wishes to receive.  See <linux/inotify.h>
+for valid events.  A watch is referenced by a watch descriptor, or wd.
+
+Watches are added via a path to the file.
+
+Watches on a directory will return events on any files inside of the directory.
+
+Adding a watch is simple,
+
+       int wd = inotify_add_watch (fd, path, mask);
+
+You can add a large number of files via something like
+
+       for each file to watch {
+               int wd = inotify_add_watch (fd, file, mask);
+       }
+
+You can update an existing watch in the same manner, by passing in a new mask.
+
+An existing watch is removed via the INOTIFY_IGNORE ioctl, for example
+
+       inotify_rm_watch (fd, wd);
+
+Events are provided in the form of an inotify_event structure that is read(2)
+from a inotify instance fd.  The filename is of dynamic length and follows the 
+struct. It is of size len.  The filename is padded with null bytes to ensure 
+proper alignment.  This padding is reflected in len.
+
+You can slurp multiple events by passing a large buffer, for example
+
+       size_t len = read (fd, buf, BUF_LEN);
+
+Will return as many events as are available and fit in BUF_LEN.
+
+each inotify instance fd is also select()- and poll()-able.
+
+You can find the size of the current event queue via the FIONREAD ioctl.
+
+All watches are destroyed and cleaned up on close.
+
+
+(ii) Internal Kernel Implementation
+
+Each open inotify instance is associated with an inotify_device structure.
+
+Each watch is associated with an inotify_watch structure.  Watches are chained
+off of each associated device and each associated inode.
+
+See fs/inotify.c for the locking and lifetime rules.
+
+
+(iii) Rationale
+
+Q: What is the design decision behind not tying the watch to the open fd of
+   the watched object?
+
+A: Watches are associated with an open inotify device, not an open file.
+   This solves the primary problem with dnotify: keeping the file open pins
+   the file and thus, worse, pins the mount.  Dnotify is therefore infeasible
+   for use on a desktop system with removable media as the media cannot be
+   unmounted.
+
+Q: What is the design decision behind using an-fd-per-device as opposed to
+   an fd-per-watch?
+
+A: An fd-per-watch quickly consumes more file descriptors than are allowed,
+   more fd's than are feasible to manage, and more fd's than are optimally
+   select()-able.  Yes, root can bump the per-process fd limit and yes, users
+   can use epoll, but requiring both is a silly and extraneous requirement.
+   A watch consumes less memory than an open file, separating the number
+   spaces is thus sensible.  The current design is what user-space developers
+   want: Users initialize inotify, once, and add n watches, requiring but one 
fd
+   and no twiddling with fd limits.  Initializing an inotify instance two
+   thousand times is silly.  If we can implement user-space's preferences 
+   cleanly--and we can, the idr layer makes stuff like this trivial--then we 
+   should.
+
+   There are other good arguments.  With a single fd, there is a single
+   item to block on, which is mapped to a single queue of events.  The single
+   fd returns all watch events and also any potential out-of-band data.  If
+   every fd was a separate watch,
+
+   - There would be no way to get event ordering.  Events on file foo and
+     file bar would pop poll() on both fd's, but there would be no way to tell
+     which happened first.  A single queue trivially gives you ordering.  Such
+     ordering is crucial to existing applications such as Beagle.  Imagine
+     "mv a b ; mv b a" events without ordering.
+
+   - We'd have to maintain n fd's and n internal queues with state,
+     versus just one.  It is a lot messier in the kernel.  A single, linear
+     queue is the data structure that makes sense.
+
+   - User-space developers prefer the current API.  The Beagle guys, for
+     example, love it.  Trust me, I asked.  It is not a surprise: Who'd want
+     to manage and block on 1000 fd's via select?
+
+   - You'd have to manage the fd's, as an example: Call close() when you
+     received a delete event.
+
+   - No way to get out of band data.
+
+   - 1024 is still too low.  ;-)
+
+   When you talk about designing a file change notification system that
+   scales to 1000s of directories, juggling 1000s of fd's just does not seem
+   the right interface.  It is too heavy.
+
+Q: Why the system call approach?
+
+A: The poor user-space interface is the second biggest problem with dnotify.
+   Signals are a terrible, terrible interface for file notification.  Or for
+   anything, for that matter.  The ideal solution, from all perspectives, is a
+   file descriptor-based one that allows basic file I/O and poll/select.
+   Obtaining the fd and managing the watches could have been done either via a
+   device file or a family of new system calls.  We decided to implement a
+   family of system calls because that is the preffered approach for new kernel
+   features and it means our user interface requirements.
+
+   Additionally, it _is_ possible to  more than one instance  and
+   juggle more than one queue and thus more than one associated fd.
+
diff -urN linux/Documentation/hwmon/adm1021 linux/Documentation/hwmon/adm1021
--- linux/Documentation/hwmon/adm1021   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/adm1021   2005-07-13 12:48:46.946588000 +0100     
1.1
@@ -0,0 +1,111 @@
+Kernel driver adm1021
+=====================
+
+Supported chips:
+  * Analog Devices ADM1021
+    Prefix: 'adm1021'
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+    Datasheet: Publicly available at the Analog Devices website
+  * Analog Devices ADM1021A/ADM1023
+    Prefix: 'adm1023'
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+    Datasheet: Publicly available at the Analog Devices website
+  * Genesys Logic GL523SM
+    Prefix: 'gl523sm'
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+    Datasheet:
+  * Intel Xeon Processor
+    Prefix: - any other - may require 'force_adm1021' parameter
+    Addresses scanned: none
+    Datasheet: Publicly available at Intel website
+  * Maxim MAX1617
+    Prefix: 'max1617'
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+    Datasheet: Publicly available at the Maxim website
+  * Maxim MAX1617A
+    Prefix: 'max1617a'
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+    Datasheet: Publicly available at the Maxim website
+  * National Semiconductor LM84
+    Prefix: 'lm84'
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+    Datasheet: Publicly available at the National Semiconductor website
+  * Philips NE1617
+    Prefix: 'max1617' (probably detected as a max1617)
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+    Datasheet: Publicly available at the Philips website
+  * Philips NE1617A
+    Prefix: 'max1617' (probably detected as a max1617)
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+    Datasheet: Publicly available at the Philips website
+  * TI THMC10
+    Prefix: 'thmc10'
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+    Datasheet: Publicly available at the TI website
+  * Onsemi MC1066
+    Prefix: 'mc1066'
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+    Datasheet: Publicly available at the Onsemi website
+
+
+Authors:
+        Frodo Looijaard <frodol@dds.nl>,
+        Philip Edelbrock <phil@netroedge.com>
+
+Module Parameters
+-----------------
+
+* read_only: int
+  Don't set any values, read only mode
+
+
+Description
+-----------
+
+The chips supported by this driver are very similar. The Maxim MAX1617 is
+the oldest; it has the problem that it is not very well detectable. The
+MAX1617A solves that. The ADM1021 is a straight clone of the MAX1617A.
+Ditto for the THMC10. From here on, we will refer to all these chips as
+ADM1021-clones.
+
+The ADM1021 and MAX1617A reports a die code, which is a sort of revision
+code. This can help us pinpoint problems; it is not very useful
+otherwise.
+
+ADM1021-clones implement two temperature sensors. One of them is internal,
+and measures the temperature of the chip itself; the other is external and
+is realised in the form of a transistor-like device. A special alarm
+indicates whether the remote sensor is connected.
+
+Each sensor has its own low and high limits. When they are crossed, the
+corresponding alarm is set and remains on as long as the temperature stays
+out of range. Temperatures are measured in degrees Celsius. Measurements
+are possible between -65 and +127 degrees, with a resolution of one degree.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may already
+have disappeared!
+
+This driver only updates its values each 1.5 seconds; reading it more often
+will do no harm, but will return 'old' values. It is possible to make
+ADM1021-clones do faster measurements, but there is really no good reason
+for that.
+
+Xeon support
+------------
+
+Some Xeon processors have real max1617, adm1021, or compatible chips
+within them, with two temperature sensors.
+
+Other Xeons have chips with only one sensor.
+
+If you have a Xeon, and the adm1021 module loads, and both temperatures
+appear valid, then things are good.
+
+If the adm1021 module doesn't load, you should try this:
+       modprobe adm1021 force_adm1021=BUS,ADDRESS
+       ADDRESS can only be 0x18, 0x1a, 0x29, 0x2b, 0x4c, or 0x4e.
+
+If you have dual Xeons you may have appear to have two separate
+adm1021-compatible chips, or two single-temperature sensors, at distinct
+addresses.
diff -urN linux/Documentation/hwmon/adm1025 linux/Documentation/hwmon/adm1025
--- linux/Documentation/hwmon/adm1025   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/adm1025   2005-07-13 12:48:46.971100000 +0100     
1.1
@@ -0,0 +1,51 @@
+Kernel driver adm1025
+=====================
+
+Supported chips:
+  * Analog Devices ADM1025, ADM1025A
+    Prefix: 'adm1025'
+    Addresses scanned: I2C 0x2c - 0x2e
+    Datasheet: Publicly available at the Analog Devices website
+  * Philips NE1619
+    Prefix: 'ne1619'
+    Addresses scanned: I2C 0x2c - 0x2d
+    Datasheet: Publicly available at the Philips website
+
+The NE1619 presents some differences with the original ADM1025:
+  * Only two possible addresses (0x2c - 0x2d).
+  * No temperature offset register, but we don't use it anyway.
+  * No INT mode for pin 16. We don't play with it anyway.
+
+Authors:
+        Chen-Yuan Wu <gwu@esoft.com>,
+        Jean Delvare <khali@linux-fr.org>
+
+Description
+-----------
+
+(This is from Analog Devices.) The ADM1025 is a complete system hardware
+monitor for microprocessor-based systems, providing measurement and limit
+comparison of various system parameters. Five voltage measurement inputs
+are provided, for monitoring +2.5V, +3.3V, +5V and +12V power supplies and
+the processor core voltage. The ADM1025 can monitor a sixth power-supply
+voltage by measuring its own VCC. One input (two pins) is dedicated to a
+remote temperature-sensing diode and an on-chip temperature sensor allows
+ambient temperature to be monitored.
+
+One specificity of this chip is that the pin 11 can be hardwired in two
+different manners. It can act as the +12V power-supply voltage analog
+input, or as the a fifth digital entry for the VID reading (bit 4). It's
+kind of strange since both are useful, and the reason for designing the
+chip that way is obscure at least to me. The bit 5 of the configuration
+register can be used to define how the chip is hardwired. Please note that
+it is not a choice you have to make as the user. The choice was already
+made by your motherboard's maker. If the configuration bit isn't set
+properly, you'll have a wrong +12V reading or a wrong VID reading. The way
+the driver handles that is to preserve this bit through the initialization
+process, assuming that the BIOS set it up properly beforehand. If it turns
+out not to be true in some cases, we'll provide a module parameter to force
+modes.
+
+This driver also supports the ADM1025A, which differs from the ADM1025
+only in that it has "open-drain VID inputs while the ADM1025 has on-chip
+100k pull-ups on the VID inputs". It doesn't make any difference for us.
diff -urN linux/Documentation/hwmon/adm1026 linux/Documentation/hwmon/adm1026
--- linux/Documentation/hwmon/adm1026   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/adm1026   2005-07-13 12:48:46.990545000 +0100     
1.1
@@ -0,0 +1,93 @@
+Kernel driver adm1026
+=====================
+
+Supported chips:
+  * Analog Devices ADM1026
+    Prefix: 'adm1026'
+    Addresses scanned: I2C 0x2c, 0x2d, 0x2e
+    Datasheet: Publicly available at the Analog Devices website
+               http://www.analog.com/en/prod/0,,766_825_ADM1026,00.html
+
+Authors:
+        Philip Pokorny <ppokorny@penguincomputing.com> for Penguin Computing
+        Justin Thiessen <jthiessen@penguincomputing.com>
+
+Module Parameters
+-----------------
+
+* gpio_input: int array (min = 1, max = 17)
+  List of GPIO pins (0-16) to program as inputs
+* gpio_output: int array (min = 1, max = 17)
+  List of GPIO pins (0-16) to program as outputs
+* gpio_inverted: int array (min = 1, max = 17)
+  List of GPIO pins (0-16) to program as inverted
+* gpio_normal: int array (min = 1, max = 17)
+  List of GPIO pins (0-16) to program as normal/non-inverted
+* gpio_fan: int array (min = 1, max = 8)
+  List of GPIO pins (0-7) to program as fan tachs
+
+
+Description
+-----------
+
+This driver implements support for the Analog Devices ADM1026. Analog
+Devices calls it a "complete thermal system management controller."
+
+The ADM1026 implements three (3) temperature sensors, 17 voltage sensors,
+16 general purpose digital I/O lines, eight (8) fan speed sensors (8-bit),
+an analog output and a PWM output along with limit, alarm and mask bits for
+all of the above. There is even 8k bytes of EEPROM memory on chip.
+
+Temperatures are measured in degrees Celsius. There are two external
+sensor inputs and one internal sensor. Each sensor has a high and low
+limit. If the limit is exceeded, an interrupt (#SMBALERT) can be
+generated. The interrupts can be masked. In addition, there are over-temp
+limits for each sensor. If this limit is exceeded, the #THERM output will
+be asserted. The current temperature and limits have a resolution of 1
+degree.
+
+Fan rotation speeds are reported in RPM (rotations per minute) but measured
+in counts of a 22.5kHz internal clock. Each fan has a high limit which
+corresponds to a minimum fan speed. If the limit is exceeded, an interrupt
+can be generated. Each fan can be programmed to divide the reference clock
+by 1, 2, 4 or 8. Not all RPM values can accurately be represented, so some
+rounding is done. With a divider of 8, the slowest measurable speed of a
+two pulse per revolution fan is 661 RPM.
+
+There are 17 voltage sensors. An alarm is triggered if the voltage has
+crossed a programmable minimum or maximum limit. Note that minimum in this
+case always means 'closest to zero'; this is important for negative voltage
+measurements. Several inputs have integrated attenuators so they can measure
+higher voltages directly. 3.3V, 5V, 12V, -12V and battery voltage all have
+dedicated inputs. There are several inputs scaled to 0-3V full-scale range
+for SCSI terminator power. The remaining inputs are not scaled and have
+a 0-2.5V full-scale range. A 2.5V or 1.82V reference voltage is provided
+for negative voltage measurements.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may already
+have disappeared! Note that in the current implementation, all hardware
+registers are read whenever any data is read (unless it is less than 2.0
+seconds since the last update). This means that you can easily miss
+once-only alarms.
+
+The ADM1026 measures continuously. Analog inputs are measured about 4
+times a second. Fan speed measurement time depends on fan speed and
+divisor. It can take as long as 1.5 seconds to measure all fan speeds.
+
+The ADM1026 has the ability to automatically control fan speed based on the
+temperature sensor inputs. Both the PWM output and the DAC output can be
+used to control fan speed. Usually only one of these two outputs will be
+used. Write the minimum PWM or DAC value to the appropriate control
+register. Then set the low temperature limit in the tmin values for each
+temperature sensor. The range of control is fixed at 20 °C, and the
+largest difference between current and tmin of the temperature sensors sets
+the control output. See the datasheet for several example circuits for
+controlling fan speed with the PWM and DAC outputs. The fan speed sensors
+do not have PWM compensation, so it is probably best to control the fan
+voltage from the power lead rather than on the ground lead.
+
+The datasheet shows an example application with VID signals attached to
+GPIO lines. Unfortunately, the chip may not be connected to the VID lines
+in this way. The driver assumes that the chips *is* connected this way to
+get a VID voltage.
diff -urN linux/Documentation/hwmon/adm1031 linux/Documentation/hwmon/adm1031
--- linux/Documentation/hwmon/adm1031   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/adm1031   2005-07-13 12:48:47.014606000 +0100     
1.1
@@ -0,0 +1,35 @@
+Kernel driver adm1031
+=====================
+
+Supported chips:
+  * Analog Devices ADM1030
+    Prefix: 'adm1030'
+    Addresses scanned: I2C 0x2c to 0x2e
+    Datasheet: Publicly available at the Analog Devices website
+               http://products.analog.com/products/info.asp?product=ADM1030
+
+  * Analog Devices ADM1031
+    Prefix: 'adm1031'
+    Addresses scanned: I2C 0x2c to 0x2e
+    Datasheet: Publicly available at the Analog Devices website
+               http://products.analog.com/products/info.asp?product=ADM1031
+
+Authors:
+        Alexandre d'Alton <alex@alexdalton.org>
+        Jean Delvare <khali@linux-fr.org>
+
+Description
+-----------
+
+The ADM1030 and ADM1031 are digital temperature sensors and fan controllers.
+They sense their own temperature as well as the temperature of up to one
+(ADM1030) or two (ADM1031) external diodes.
+
+All temperature values are given in degrees Celsius. Resolution is 0.5
+degree for the local temperature, 0.125 degree for the remote temperatures.
+
+Each temperature channel has its own high and low limits, plus a critical
+limit.
+
+The ADM1030 monitors a single fan speed, while the ADM1031 monitors up to
+two. Each fan channel has its own low speed limit.
diff -urN linux/Documentation/hwmon/adm9240 linux/Documentation/hwmon/adm9240
--- linux/Documentation/hwmon/adm9240   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/adm9240   2005-07-13 12:48:47.041186000 +0100     
1.1
@@ -0,0 +1,177 @@
+Kernel driver adm9240
+=====================
+
+Supported chips:
+  * Analog Devices ADM9240
+    Prefix: 'adm9240'
+    Addresses scanned: I2C 0x2c - 0x2f
+    Datasheet: Publicly available at the Analog Devices website
+    http://www.analog.com/UploadedFiles/Data_Sheets/79857778ADM9240_0.pdf
+
+  * Dallas Semiconductor DS1780
+    Prefix: 'ds1780'
+    Addresses scanned: I2C 0x2c - 0x2f
+    Datasheet: Publicly available at the Dallas Semiconductor (Maxim) website
+    http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
+
+  * National Semiconductor LM81
+    Prefix: 'lm81'
+    Addresses scanned: I2C 0x2c - 0x2f
+    Datasheet: Publicly available at the National Semiconductor website
+    http://www.national.com/ds.cgi/LM/LM81.pdf
+
+Authors:
+    Frodo Looijaard <frodol@dds.nl>,
+    Philip Edelbrock <phil@netroedge.com>,
+    Michiel Rook <michiel@grendelproject.nl>,
+    Grant Coady <gcoady@gmail.com> with guidance
+        from Jean Delvare <khali@linux-fr.org>
+
+Interface
+---------
+The I2C addresses listed above assume BIOS has not changed the
+chip MSB 5-bit address. Each chip reports a unique manufacturer
+identification code as well as the chip revision/stepping level.
+
+Description
+-----------
+[From ADM9240] The ADM9240 is a complete system hardware monitor for
+microprocessor-based systems, providing measurement and limit comparison
+of up to four power supplies and two processor core voltages, plus
+temperature, two fan speeds and chassis intrusion. Measured values can
+be read out via an I2C-compatible serial System Management Bus, and values
+for limit comparisons can be programmed in over the same serial bus. The
+high speed successive approximation ADC allows frequent sampling of all
+analog channels to ensure a fast interrupt response to any out-of-limit
+measurement.
+
+The ADM9240, DS1780 and LM81 are register compatible, the following
+details are common to the three chips. Chip differences are described
+after this section.
+
+
+Measurements
+------------
+The measurement cycle
+
+The adm9240 driver will take a measurement reading no faster than once
+each two seconds. User-space may read sysfs interface faster than the
+measurement update rate and will receive cached data from the most
+recent measurement.
+
+ADM9240 has a very fast 320us temperature and voltage measurement cycle
+with independent fan speed measurement cycles counting alternating rising
+edges of the fan tacho inputs.
+
+DS1780 measurement cycle is about once per second including fan speed.
+
+LM81 measurement cycle is about once per 400ms including fan speed.
+The LM81 12-bit extended temperature measurement mode is not supported.
+
+Temperature
+-----------
+On chip temperature is reported as degrees Celsius as 9-bit signed data
+with resolution of 0.5 degrees Celsius. High and low temperature limits
+are 8-bit signed data with resolution of one degree Celsius.
+
+Temperature alarm is asserted once the temperature exceeds the high limit,
+and is cleared when the temperature falls below the temp1_max_hyst value.
+
+Fan Speed
+---------
+Two fan tacho inputs are provided, the ADM9240 gates an internal 22.5kHz
+clock via a divider to an 8-bit counter. Fan speed (rpm) is calculated by:
+
+rpm = (22500 * 60) / (count * divider)
+
+Automatic fan clock divider
+
+  * User sets 0 to fan_min limit
+    - low speed alarm is disabled
+    - fan clock divider not changed
+    - auto fan clock adjuster enabled for valid fan speed reading
+
+  * User sets fan_min limit too low
+    - low speed alarm is enabled
+    - fan clock divider set to max
+    - fan_min set to register value 254 which corresponds
+      to 664 rpm on adm9240
+    - low speed alarm will be asserted if fan speed is
+      less than minimum measurable speed
+    - auto fan clock adjuster disabled
+
+  * User sets reasonable fan speed
+    - low speed alarm is enabled
+    - fan clock divider set to suit fan_min
+    - auto fan clock adjuster enabled: adjusts fan_min
+
+  * User sets unreasonably high low fan speed limit
+    - resolution of the low speed limit may be reduced
+    - alarm will be asserted
+    - auto fan clock adjuster enabled: adjusts fan_min
+
+    * fan speed may be displayed as zero until the auto fan clock divider
+      adjuster brings fan speed clock divider back into chip measurement
+      range, this will occur within a few measurement cycles.
+
+Analog Output
+-------------
+An analog output provides a 0 to 1.25 volt signal intended for an external
+fan speed amplifier circuit. The analog output is set to maximum value on
+power up or reset. This doesn't do much on the test Intel SE440BX-2.
+
+Voltage Monitor
+
+Voltage (IN) measurement is internally scaled:
+
+    nr  label       nominal     maximum   resolution
+                      mV          mV         mV
+    0   +2.5V        2500        3320       13.0
+    1   Vccp1        2700        3600       14.1
+    2   +3.3V        3300        4380       17.2
+    3     +5V        5000        6640       26.0
+    4    +12V       12000       15940       62.5
+    5   Vccp2        2700        3600       14.1
+
+The reading is an unsigned 8-bit value, nominal voltage measurement is
+represented by a reading of 192, being 3/4 of the measurement range.
+
+An alarm is asserted for any voltage going below or above the set limits.
+
+The driver reports and accepts voltage limits scaled to the above table.
+
+VID Monitor
+-----------
+The chip has five inputs to read the 5-bit VID and reports the mV value
+based on detected CPU type.
+
+Chassis Intrusion
+-----------------
+An alarm is asserted when the CI pin goes active high. The ADM9240
+Datasheet has an example of an external temperature sensor driving
+this pin. On an Intel SE440BX-2 the Chassis Intrusion header is
+connected to a normally open switch.
+
+The ADM9240 provides an internal open drain on this line, and may output
+a 20 ms active low pulse to reset an external Chassis Intrusion latch.
+
+Clear the CI latch by writing value 1 to the sysfs chassis_clear file.
+
+Alarm flags reported as 16-bit word
+
+    bit     label               comment
+    ---     -------------       --------------------------
+     0      +2.5 V_Error        high or low limit exceeded
+     1      VCCP_Error          high or low limit exceeded
+     2      +3.3 V_Error        high or low limit exceeded
+     3      +5 V_Error          high or low limit exceeded
+     4      Temp_Error          temperature error
+     6      FAN1_Error          fan low limit exceeded
+     7      FAN2_Error          fan low limit exceeded
+     8      +12 V_Error         high or low limit exceeded
+     9      VCCP2_Error         high or low limit exceeded
+    12      Chassis_Error       CI pin went high
+
+Remaining bits are reserved and thus undefined. It is important to note
+that alarm bits may be cleared on read, user-space may latch alarms and
+provide the end-user with a method to clear alarm memory.
diff -urN linux/Documentation/hwmon/asb100 linux/Documentation/hwmon/asb100
--- linux/Documentation/hwmon/asb100    1970/01/01 00:00:00
+++ linux/Documentation/hwmon/asb100    2005-07-13 12:48:47.062759000 +0100     
1.1
@@ -0,0 +1,72 @@
+Kernel driver asb100
+====================
+
+Supported Chips:
+  * Asus ASB100 and ASB100-A "Bach"
+    Prefix: 'asb100'
+    Addresses scanned: I2C 0x2d
+    Datasheet: none released
+
+Author: Mark M. Hoffman <mhoffman@lightlink.com>
+
+Description
+-----------
+
+This driver implements support for the Asus ASB100 and ASB100-A "Bach".
+These are custom ASICs available only on Asus mainboards. Asus refuses to
+supply a datasheet for these chips. Thanks go to many people who helped
+investigate their hardware, including:
+
+Vitaly V. Bursov
+Alexander van Kaam (author of MBM for Windows)
+Bertrik Sikken
+
+The ASB100 implements seven voltage sensors, three fan rotation speed
+sensors, four temperature sensors, VID lines and alarms. In addition to
+these, the ASB100-A also implements a single PWM controller for fans 2 and
+3 (i.e. one setting controls both.) If you have a plain ASB100, the PWM
+controller will simply not work (or maybe it will for you... it doesn't for
+me).
+
+Temperatures are measured and reported in degrees Celsius.
+
+Fan speeds are reported in RPM (rotations per minute). An alarm is
+triggered if the rotation speed has dropped below a programmable limit.
+
+Voltage sensors (also known as IN sensors) report values in volts.
+
+The VID lines encode the core voltage value: the voltage level your
+processor should work with. This is hardcoded by the mainboard and/or
+processor itself. It is a value in volts.
+
+Alarms: (TODO question marks indicate may or may not work)
+
+0x0001 => in0 (?)
+0x0002 => in1 (?)
+0x0004 => in2
+0x0008 => in3
+0x0010 => temp1 (1)
+0x0020 => temp2
+0x0040 => fan1
+0x0080 => fan2
+0x0100 => in4
+0x0200 => in5 (?) (2)
+0x0400 => in6 (?) (2)
+0x0800 => fan3
+0x1000 => chassis switch
+0x2000 => temp3
+
+Alarm Notes:
+
+(1) This alarm will only trigger if the hysteresis value is 127C.
+I.e. it behaves the same as w83781d.
+
+(2) The min and max registers for these values appear to
+be read-only or otherwise stuck at 0x00.
+
+TODO:
+* Experiment with fan divisors > 8.
+* Experiment with temp. sensor types.
+* Are there really 13 voltage inputs? Probably not...
+* Cleanups, no doubt...
+
diff -urN linux/Documentation/hwmon/ds1621 linux/Documentation/hwmon/ds1621
--- linux/Documentation/hwmon/ds1621    1970/01/01 00:00:00
+++ linux/Documentation/hwmon/ds1621    2005-07-13 12:48:47.081685000 +0100     
1.1
@@ -0,0 +1,108 @@
+Kernel driver ds1621
+====================
+
+Supported chips:
+  * Dallas Semiconductor DS1621
+    Prefix: 'ds1621'
+    Addresses scanned: I2C 0x48 - 0x4f
+    Datasheet: Publicly available at the Dallas Semiconductor website
+               http://www.dalsemi.com/
+  * Dallas Semiconductor DS1625
+    Prefix: 'ds1621'
+    Addresses scanned: I2C 0x48 - 0x4f
+    Datasheet: Publicly available at the Dallas Semiconductor website
+               http://www.dalsemi.com/
+
+Authors:
+        Christian W. Zuckschwerdt <zany@triq.net>
+        valuable contributions by Jan M. Sendler <sendler@sendler.de>
+        ported to 2.6 by Aurelien Jarno <aurelien@aurel32.net>
+        with the help of Jean Delvare <khali@linux-fr.org>
+
+Module Parameters
+------------------
+
+* polarity int
+  Output's polarity: 0 = active high, 1 = active low
+
+Description
+-----------
+
+The DS1621 is a (one instance) digital thermometer and thermostat. It has
+both high and low temperature limits which can be user defined (i.e.
+programmed into non-volatile on-chip registers). Temperature range is -55
+degree Celsius to +125 in 0.5 increments. You may convert this into a
+Fahrenheit range of -67 to +257 degrees with 0.9 steps. If polarity
+parameter is not provided, original value is used.
+
+As for the thermostat, behavior can also be programmed using the polarity
+toggle. On the one hand ("heater"), the thermostat output of the chip,
+Tout, will trigger when the low limit temperature is met or underrun and
+stays high until the high limit is met or exceeded. On the other hand
+("cooler"), vice versa. That way "heater" equals "active low", whereas
+"conditioner" equals "active high". Please note that the DS1621 data sheet
+is somewhat misleading in this point since setting the polarity bit does
+not simply invert Tout.
+
+A second thing is that, during extensive testing, Tout showed a tolerance
+of up to +/- 0.5 degrees even when compared against precise temperature
+readings. Be sure to have a high vs. low temperature limit gap of al least
+1.0 degree Celsius to avoid Tout "bouncing", though!
+
+As for alarms, you can read the alarm status of the DS1621 via the 'alarms'
+/sys file interface. The result consists mainly of bit 6 and 5 of the
+configuration register of the chip; bit 6 (0x40 or 64) is the high alarm
+bit and bit 5 (0x20 or 32) the low one. These bits are set when the high or
+low limits are met or exceeded and are reset by the module as soon as the
+respective temperature ranges are left.
+
+The alarm registers are in no way suitable to find out about the actual
+status of Tout. They will only tell you about its history, whether or not
+any of the limits have ever been met or exceeded since last power-up or
+reset. Be aware: When testing, it showed that the status of Tout can change
+with neither of the alarms set.
+
+Temperature conversion of the DS1621 takes up to 1000ms; internal access to
+non-volatile registers may last for 10ms or below.
+
+High Accuracy Temperature Reading
+---------------------------------
+
+As said before, the temperature issued via the 9-bit i2c-bus data is
+somewhat arbitrary. Internally, the temperature conversion is of a
+different kind that is explained (not so...) well in the DS1621 data sheet.
+To cut the long story short: Inside the DS1621 there are two oscillators,
+both of them biassed by a temperature coefficient.
+
+Higher resolution of the temperature reading can be achieved using the
+internal projection, which means taking account of REG_COUNT and REG_SLOPE
+(the driver manages them):
+
+Taken from Dallas Semiconductors App Note 068: 'Increasing Temperature
+Resolution on the DS1620' and App Note 105: 'High Resolution Temperature
+Measurement with Dallas Direct-to-Digital Temperature Sensors'
+
+- Read the 9-bit temperature and strip the LSB (Truncate the .5 degs)
+- The resulting value is TEMP_READ.
+- Then, read REG_COUNT.
+- And then, REG_SLOPE.
+
+      TEMP = TEMP_READ - 0.25 + ((REG_SLOPE - REG_COUNT) / REG_SLOPE)
+
+Note that this is what the DONE bit in the DS1621 configuration register is
+good for: Internally, one temperature conversion takes up to 1000ms. Before
+that conversion is complete you will not be able to read valid things out
+of REG_COUNT and REG_SLOPE. The DONE bit, as you may have guessed by now,
+tells you whether the conversion is complete ("done", in plain English) and
+thus, whether the values you read are good or not.
+
+The DS1621 has two modes of operation: "Continuous" conversion, which can
+be understood as the default stand-alone mode where the chip gets the
+temperature and controls external devices via its Tout pin or tells other
+i2c's about it if they care. The other mode is called "1SHOT", that means
+that it only figures out about the temperature when it is explicitly told
+to do so; this can be seen as power saving mode.
+
+Now if you want to read REG_COUNT and REG_SLOPE, you have to either stop
+the continuous conversions until the contents of these registers are valid,
+or, in 1SHOT mode, you have to have one conversion made.
diff -urN linux/Documentation/hwmon/fscher linux/Documentation/hwmon/fscher
--- linux/Documentation/hwmon/fscher    1970/01/01 00:00:00
+++ linux/Documentation/hwmon/fscher    2005-07-13 12:48:47.105604000 +0100     
1.1
@@ -0,0 +1,169 @@
+Kernel driver fscher
+====================
+
+Supported chips:
+  * Fujitsu-Siemens Hermes chip
+    Prefix: 'fscher'
+    Addresses scanned: I2C 0x73
+
+Authors:
+        Reinhard Nissl <rnissl@gmx.de> based on work
+        from Hermann Jung <hej@odn.de>,
+        Frodo Looijaard <frodol@dds.nl>,
+        Philip Edelbrock <phil@netroedge.com>
+
+Description
+-----------
+
+This driver implements support for the Fujitsu-Siemens Hermes chip. It is
+described in the 'Register Set Specification BMC Hermes based Systemboard'
+from Fujitsu-Siemens.
+
+The Hermes chip implements a hardware-based system management, e.g. for
+controlling fan speed and core voltage. There is also a watchdog counter on
+the chip which can trigger an alarm and even shut the system down.
+
+The chip provides three temperature values (CPU, motherboard and
+auxiliary), three voltage values (+12V, +5V and battery) and three fans
+(power supply, CPU and auxiliary).
+
+Temperatures are measured in degrees Celsius. The resolution is 1 degree.
+
+Fan rotation speeds are reported in RPM (rotations per minute). The value
+can be divided by a programmable divider (1, 2 or 4) which is stored on
+the chip.
+
+Voltage sensors (also known as "in" sensors) report their values in volts.
+
+All values are reported as final values from the driver. There is no need
+for further calculations.
+
+
+Detailed description
+--------------------
+
+Below you'll find a single line description of all the bit values. With
+this information, you're able to decode e. g. alarms, wdog, etc. To make
+use of the watchdog, you'll need to set the watchdog time and enable the
+watchdog. After that it is necessary to restart the watchdog time within
+the specified period of time, or a system reset will occur.
+
+* revision
+  READING & 0xff = 0x??: HERMES revision identification
+
+* alarms
+  READING & 0x80 = 0x80: CPU throttling active
+  READING & 0x80 = 0x00: CPU running at full speed
+
+  READING & 0x10 = 0x10: software event (see control:1)
+  READING & 0x10 = 0x00: no software event
+
+  READING & 0x08 = 0x08: watchdog event (see wdog:2)
+  READING & 0x08 = 0x00: no watchdog event
+
+  READING & 0x02 = 0x02: thermal event (see temp*:1)
+  READING & 0x02 = 0x00: no thermal event
+
+  READING & 0x01 = 0x01: fan event (see fan*:1)
+  READING & 0x01 = 0x00: no fan event
+
+  READING & 0x13 ! 0x00: ALERT LED is flashing
+
+* control
+  READING & 0x01 = 0x01: software event
+  READING & 0x01 = 0x00: no software event
+
+  WRITING & 0x01 = 0x01: set software event
+  WRITING & 0x01 = 0x00: clear software event
+
+* watchdog_control
+  READING & 0x80 = 0x80: power off on watchdog event while thermal event
+  READING & 0x80 = 0x00: watchdog power off disabled (just system reset 
enabled)
+
+  READING & 0x40 = 0x40: watchdog timebase 60 seconds (see also wdog:1)
+  READING & 0x40 = 0x00: watchdog timebase  2 seconds
+
+  READING & 0x10 = 0x10: watchdog enabled
+  READING & 0x10 = 0x00: watchdog disabled
+
+  WRITING & 0x80 = 0x80: enable "power off on watchdog event while thermal 
event"
+  WRITING & 0x80 = 0x00: disable "power off on watchdog event while thermal 
event"
+
+  WRITING & 0x40 = 0x40: set watchdog timebase to 60 seconds
+  WRITING & 0x40 = 0x00: set watchdog timebase to  2 seconds
+
+  WRITING & 0x20 = 0x20: disable watchdog
+
+  WRITING & 0x10 = 0x10: enable watchdog / restart watchdog time
+
+* watchdog_state
+  READING & 0x02 = 0x02: watchdog system reset occurred
+  READING & 0x02 = 0x00: no watchdog system reset occurred
+
+  WRITING & 0x02 = 0x02: clear watchdog event
+
+* watchdog_preset
+  READING & 0xff = 0x??: configured watch dog time in units (see wdog:3 0x40)
+
+  WRITING & 0xff = 0x??: configure watch dog time in units
+
+* in*     (0: +5V, 1: +12V, 2: onboard 3V battery)
+  READING: actual voltage value
+
+* temp*_status   (1: CPU sensor, 2: onboard sensor, 3: auxiliary sensor)
+  READING & 0x02 = 0x02: thermal event (overtemperature)
+  READING & 0x02 = 0x00: no thermal event
+
+  READING & 0x01 = 0x01: sensor is working
+  READING & 0x01 = 0x00: sensor is faulty
+
+  WRITING & 0x02 = 0x02: clear thermal event
+
+* temp*_input   (1: CPU sensor, 2: onboard sensor, 3: auxiliary sensor)
+  READING: actual temperature value
+
+* fan*_status   (1: power supply fan, 2: CPU fan, 3: auxiliary fan)
+  READING & 0x04 = 0x04: fan event (fan fault)
+  READING & 0x04 = 0x00: no fan event
+
+  WRITING & 0x04 = 0x04: clear fan event
+
+* fan*_div (1: power supply fan, 2: CPU fan, 3: auxiliary fan)
+       Divisors 2,4 and 8 are supported, both for reading and writing
+
+* fan*_pwm   (1: power supply fan, 2: CPU fan, 3: auxiliary fan)
+  READING & 0xff = 0x00: fan may be switched off
+  READING & 0xff = 0x01: fan must run at least at minimum speed (supply: 6V)
+  READING & 0xff = 0xff: fan must run at maximum speed (supply: 12V)
+  READING & 0xff = 0x??: fan must run at least at given speed (supply: 6V..12V)
+
+  WRITING & 0xff = 0x00: fan may be switched off
+  WRITING & 0xff = 0x01: fan must run at least at minimum speed (supply: 6V)
+  WRITING & 0xff = 0xff: fan must run at maximum speed (supply: 12V)
+  WRITING & 0xff = 0x??: fan must run at least at given speed (supply: 6V..12V)
+
+* fan*_input   (1: power supply fan, 2: CPU fan, 3: auxiliary fan)
+  READING: actual RPM value
+
+
+Limitations
+-----------
+
+* Measuring fan speed
+It seems that the chip counts "ripples" (typical fans produce 2 ripples per
+rotation while VERAX fans produce 18) in a 9-bit register. This register is
+read out every second, then the ripple prescaler (2, 4 or 8) is applied and
+the result is stored in the 8 bit output register. Due to the limitation of
+the counting register to 9 bits, it is impossible to measure a VERAX fan
+properly (even with a prescaler of 8). At its maximum speed of 3500 RPM the
+fan produces 1080 ripples per second which causes the counting register to
+overflow twice, leading to only 186 RPM.
+
+* Measuring input voltages
+in2 ("battery") reports the voltage of the onboard lithium battery and not
++3.3V from the power supply.
+
+* Undocumented features
+Fujitsu-Siemens Computers has not documented all features of the chip so
+far. Their software, System Guard, shows that there are a still some
+features which cannot be controlled by this implementation.
diff -urN linux/Documentation/hwmon/gl518sm linux/Documentation/hwmon/gl518sm
--- linux/Documentation/hwmon/gl518sm   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/gl518sm   2005-07-13 12:48:47.133423000 +0100     
1.1
@@ -0,0 +1,74 @@
+Kernel driver gl518sm
+=====================
+
+Supported chips:
+  * Genesys Logic GL518SM release 0x00
+    Prefix: 'gl518sm'
+    Addresses scanned: I2C 0x2c and 0x2d
+    Datasheet: http://www.genesyslogic.com/pdf
+  * Genesys Logic GL518SM release 0x80
+    Prefix: 'gl518sm'
+    Addresses scanned: I2C 0x2c and 0x2d
+    Datasheet: http://www.genesyslogic.com/pdf
+
+Authors:
+        Frodo Looijaard <frodol@dds.nl>,
+        Kyösti Mälkki <kmalkki@cc.hut.fi>
+        Hong-Gunn Chew <hglinux@gunnet.org>
+        Jean Delvare <khali@linux-fr.org>
+
+Description
+-----------
+
+IMPORTANT:
+
+For the revision 0x00 chip, the in0, in1, and in2  values (+5V, +3V,
+and +12V) CANNOT be read. This is a limitation of the chip, not the driver.
+
+This driver supports the Genesys Logic GL518SM chip. There are at least
+two revision of this chip, which we call revision 0x00 and 0x80. Revision
+0x80 chips support the reading of all voltages and revision 0x00 only
+for VIN3.
+
+The GL518SM implements one temperature sensor, two fan rotation speed
+sensors, and four voltage sensors. It can report alarms through the
+computer speakers.
+
+Temperatures are measured in degrees Celsius. An alarm goes off while the
+temperature is above the over temperature limit, and has not yet dropped
+below the hysteresis limit. The alarm always reflects the current
+situation. Measurements are guaranteed between -10 degrees and +110
+degrees, with a accuracy of +/-3 degrees.
+
+Rotation speeds are reported in RPM (rotations per minute). An alarm is
+triggered if the rotation speed has dropped below a programmable limit. In
+case when you have selected to turn fan1 off, no fan1 alarm is triggered.
+
+Fan readings can be divided by a programmable divider (1, 2, 4 or 8) to
+give the readings more range or accuracy.  Not all RPM values can
+accurately be represented, so some rounding is done. With a divider
+of 2, the lowest representable value is around 1900 RPM.
+
+Voltage sensors (also known as VIN sensors) report their values in volts.
+An alarm is triggered if the voltage has crossed a programmable minimum or
+maximum limit. Note that minimum in this case always means 'closest to
+zero'; this is important for negative voltage measurements. The VDD input
+measures voltages between 0.000 and 5.865 volt, with a resolution of 0.023
+volt. The other inputs measure voltages between 0.000 and 4.845 volt, with
+a resolution of 0.019 volt. Note that revision 0x00 chips do not support
+reading the current voltage of any input except for VIN3; limit setting and
+alarms work fine, though.
+
+When an alarm is triggered, you can be warned by a beeping signal through your
+computer speaker. It is possible to enable all beeping globally, or only the
+beeping for some alarms.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once (except for temperature alarms). This means that the
+cause for the alarm may already have disappeared! Note that in the current
+implementation, all hardware registers are read whenever any data is read
+(unless it is less than 1.5 seconds since the last update). This means that
+you can easily miss once-only alarms.
+
+The GL518SM only updates its values each 1.5 seconds; reading it more often
+will do no harm, but will return 'old' values.
diff -urN linux/Documentation/hwmon/it87 linux/Documentation/hwmon/it87
--- linux/Documentation/hwmon/it87      1970/01/01 00:00:00
+++ linux/Documentation/hwmon/it87      2005-07-13 12:48:47.153575000 +0100     
1.1
@@ -0,0 +1,96 @@
+Kernel driver it87
+==================
+
+Supported chips:
+  * IT8705F
+    Prefix: 'it87'
+    Addresses scanned: from Super I/O config space, or default ISA 0x290 (8 
I/O ports)
+    Datasheet: Publicly available at the ITE website
+               http://www.ite.com.tw/
+  * IT8712F
+    Prefix: 'it8712'
+    Addresses scanned: I2C 0x28 - 0x2f
+                       from Super I/O config space, or default ISA 0x290 (8 
I/O ports)
+    Datasheet: Publicly available at the ITE website
+               http://www.ite.com.tw/
+  * SiS950   [clone of IT8705F]
+    Prefix: 'sis950'
+    Addresses scanned: from Super I/O config space, or default ISA 0x290 (8 
I/O ports)
+    Datasheet: No longer be available
+
+Author: Christophe Gauthron <chrisg@0-in.com>
+
+
+Module Parameters
+-----------------
+
+* update_vbat: int
+
+  0 if vbat should report power on value, 1 if vbat should be updated after
+  each read. Default is 0. On some boards the battery voltage is provided
+  by either the battery or the onboard power supply. Only the first reading
+  at power on will be the actual battery voltage (which the chip does
+  automatically). On other boards the battery voltage is always fed to
+  the chip so can be read at any time. Excessive reading may decrease
+  battery life but no information is given in the datasheet.
+
+* fix_pwm_polarity int
+
+  Force PWM polarity to active high (DANGEROUS). Some chips are
+  misconfigured by BIOS - PWM values would be inverted. This option tries
+  to fix this. Please contact your BIOS manufacturer and ask him for fix.
+
+Description
+-----------
+
+This driver implements support for the IT8705F, IT8712F and SiS950 chips.
+
+This driver also supports IT8712F, which adds SMBus access, and a VID
+input, used to report the Vcore voltage of the Pentium processor.
+The IT8712F additionally features VID inputs.
+
+These chips are 'Super I/O chips', supporting floppy disks, infrared ports,
+joysticks and other miscellaneous stuff. For hardware monitoring, they
+include an 'environment controller' with 3 temperature sensors, 3 fan
+rotation speed sensors, 8 voltage sensors, and associated alarms.
+
+Temperatures are measured in degrees Celsius. An alarm is triggered once
+when the Overtemperature Shutdown limit is crossed.
+
+Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
+triggered if the rotation speed has dropped below a programmable limit. Fan
+readings can be divided by a programmable divider (1, 2, 4 or 8) to give the
+readings more range or accuracy. Not all RPM values can accurately be
+represented, so some rounding is done. With a divider of 2, the lowest
+representable value is around 2600 RPM.
+
+Voltage sensors (also known as IN sensors) report their values in volts. An
+alarm is triggered if the voltage has crossed a programmable minimum or
+maximum limit. Note that minimum in this case always means 'closest to
+zero'; this is important for negative voltage measurements. All voltage
+inputs can measure voltages between 0 and 4.08 volts, with a resolution of
+0.016 volt. The battery voltage in8 does not have limit registers.
+
+The VID lines (IT8712F only) encode the core voltage value: the voltage
+level your processor should work with. This is hardcoded by the mainboard
+and/or processor itself. It is a value in volts.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may already
+have disappeared! Note that in the current implementation, all hardware
+registers are read whenever any data is read (unless it is less than 1.5
+seconds since the last update). This means that you can easily miss
+once-only alarms.
+
+The IT87xx only updates its values each 1.5 seconds; reading it more often
+will do no harm, but will return 'old' values.
+
+To change sensor N to a thermistor, 'echo 2 > tempN_type' where N is 1, 2,
+or 3. To change sensor N to a thermal diode, 'echo 3 > tempN_type'.
+Give 0 for unused sensor. Any other value is invalid. To configure this at
+startup, consult lm_sensors's /etc/sensors.conf. (2 = thermistor;
+3 = thermal diode)
+
+The fan speed control features are limited to manual PWM mode. Automatic
+"Smart Guardian" mode control handling is not implemented. However
+if you want to go for "manual mode" just write 1 to pwmN_enable.
diff -urN linux/Documentation/hwmon/lm63 linux/Documentation/hwmon/lm63
--- linux/Documentation/hwmon/lm63      1970/01/01 00:00:00
+++ linux/Documentation/hwmon/lm63      2005-07-13 12:48:47.177538000 +0100     
1.1
@@ -0,0 +1,57 @@
+Kernel driver lm63
+==================
+
+Supported chips:
+  * National Semiconductor LM63
+    Prefix: 'lm63'
+    Addresses scanned: I2C 0x4c
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/pf/LM/LM63.html
+
+Author: Jean Delvare <khali@linux-fr.org>
+
+Thanks go to Tyan and especially Alex Buckingham for setting up a remote
+access to their S4882 test platform for this driver.
+  http://www.tyan.com/
+
+Description
+-----------
+
+The LM63 is a digital temperature sensor with integrated fan monitoring
+and control.
+
+The LM63 is basically an LM86 with fan speed monitoring and control
+capabilities added. It misses some of the LM86 features though:
+ - No low limit for local temperature.
+ - No critical limit for local temperature.
+ - Critical limit for remote temperature can be changed only once. We
+   will consider that the critical limit is read-only.
+
+The datasheet isn't very clear about what the tachometer reading is.
+
+An explanation from National Semiconductor: The two lower bits of the read
+value have to be masked out. The value is still 16 bit in width.
+
+All temperature values are given in degrees Celsius. Resolution is 1.0
+degree for the local temperature, 0.125 degree for the remote temperature.
+
+The fan speed is measured using a tachometer. Contrary to most chips which
+store the value in an 8-bit register and have a selectable clock divider
+to make sure that the result will fit in the register, the LM63 uses 16-bit
+value for measuring the speed of the fan. It can measure fan speeds down to
+83 RPM, at least in theory.
+
+Note that the pin used for fan monitoring is shared with an alert out
+function. Depending on how the board designer wanted to use the chip, fan
+speed monitoring will or will not be possible. The proper chip configuration
+is left to the BIOS, and the driver will blindly trust it.
+
+A PWM output can be used to control the speed of the fan. The LM63 has two
+PWM modes: manual and automatic. Automatic mode is not fully implemented yet
+(you cannot define your custom PWM/temperature curve), and mode change isn't
+supported either.
+
+The lm63 driver will not update its values more frequently than every
+second; reading them more often will do no harm, but will return 'old'
+values.
+
diff -urN linux/Documentation/hwmon/lm75 linux/Documentation/hwmon/lm75
--- linux/Documentation/hwmon/lm75      1970/01/01 00:00:00
+++ linux/Documentation/hwmon/lm75      2005-07-13 12:48:47.204503000 +0100     
1.1
@@ -0,0 +1,65 @@
+Kernel driver lm75
+==================
+
+Supported chips:
+  * National Semiconductor LM75
+    Prefix: 'lm75'
+    Addresses scanned: I2C 0x48 - 0x4f
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/
+  * Dallas Semiconductor DS75
+    Prefix: 'lm75'
+    Addresses scanned: I2C 0x48 - 0x4f
+    Datasheet: Publicly available at the Dallas Semiconductor website
+               http://www.maxim-ic.com/
+  * Dallas Semiconductor DS1775
+    Prefix: 'lm75'
+    Addresses scanned: I2C 0x48 - 0x4f
+    Datasheet: Publicly available at the Dallas Semiconductor website
+               http://www.maxim-ic.com/
+  * Maxim MAX6625, MAX6626
+    Prefix: 'lm75'
+    Addresses scanned: I2C 0x48 - 0x4b
+    Datasheet: Publicly available at the Maxim website
+               http://www.maxim-ic.com/
+  * Microchip (TelCom) TCN75
+    Prefix: 'lm75'
+    Addresses scanned: I2C 0x48 - 0x4f
+    Datasheet: Publicly available at the Microchip website
+               http://www.microchip.com/
+
+Author: Frodo Looijaard <frodol@dds.nl>
+
+Description
+-----------
+
+The LM75 implements one temperature sensor. Limits can be set through the
+Overtemperature Shutdown register and Hysteresis register. Each value can be
+set and read to half-degree accuracy.
+An alarm is issued (usually to a connected LM78) when the temperature
+gets higher then the Overtemperature Shutdown value; it stays on until
+the temperature falls below the Hysteresis value.
+All temperatures are in degrees Celsius, and are guaranteed within a
+range of -55 to +125 degrees.
+
+The LM75 only updates its values each 1.5 seconds; reading it more often
+will do no harm, but will return 'old' values.
+
+The LM75 is usually used in combination with LM78-like chips, to measure
+the temperature of the processor(s).
+
+The DS75, DS1775, MAX6625, and MAX6626 are supported as well.
+They are not distinguished from an LM75. While most of these chips
+have three additional bits of accuracy (12 vs. 9 for the LM75),
+the additional bits are not supported. Not only that, but these chips will
+not be detected if not in 9-bit precision mode (use the force parameter if
+needed).
+
+The TCN75 is supported as well, and is not distinguished from an LM75.
+
+The LM75 is essentially an industry standard; there may be other
+LM75 clones not listed here, with or without various enhancements,
+that are supported.
+
+The LM77 is not supported, contrary to what we pretended for a long time.
+Both chips are simply not compatible, value encoding differs.
diff -urN linux/Documentation/hwmon/lm77 linux/Documentation/hwmon/lm77
--- linux/Documentation/hwmon/lm77      1970/01/01 00:00:00
+++ linux/Documentation/hwmon/lm77      2005-07-13 12:48:47.228564000 +0100     
1.1
@@ -0,0 +1,22 @@
+Kernel driver lm77
+==================
+
+Supported chips:
+  * National Semiconductor LM77
+    Prefix: 'lm77'
+    Addresses scanned: I2C 0x48 - 0x4b
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/
+
+Author: Andras BALI <drewie@freemail.hu>
+
+Description
+-----------
+
+The LM77 implements one temperature sensor. The temperature
+sensor incorporates a band-gap type temperature sensor,
+10-bit ADC, and a digital comparator with user-programmable upper
+and lower limit values.
+
+Limits can be set through the Overtemperature Shutdown register and
+Hysteresis register.
diff -urN linux/Documentation/hwmon/lm78 linux/Documentation/hwmon/lm78
--- linux/Documentation/hwmon/lm78      1970/01/01 00:00:00
+++ linux/Documentation/hwmon/lm78      2005-07-13 12:48:47.249978000 +0100     
1.1
@@ -0,0 +1,82 @@
+Kernel driver lm78
+==================
+
+Supported chips:
+  * National Semiconductor LM78
+    Prefix: 'lm78'
+    Addresses scanned: I2C 0x20 - 0x2f, ISA 0x290 (8 I/O ports)
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/
+  * National Semiconductor LM78-J
+    Prefix: 'lm78-j'
+    Addresses scanned: I2C 0x20 - 0x2f, ISA 0x290 (8 I/O ports)
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/
+  * National Semiconductor LM79
+    Prefix: 'lm79'
+    Addresses scanned: I2C 0x20 - 0x2f, ISA 0x290 (8 I/O ports)
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/
+
+Author: Frodo Looijaard <frodol@dds.nl>
+
+Description
+-----------
+
+This driver implements support for the National Semiconductor LM78, LM78-J
+and LM79. They are described as 'Microprocessor System Hardware Monitors'.
+
+There is almost no difference between the three supported chips. Functionally,
+the LM78 and LM78-J are exactly identical. The LM79 has one more VID line,
+which is used to report the lower voltages newer Pentium processors use.
+From here on, LM7* means either of these three types.
+
+The LM7* implements one temperature sensor, three fan rotation speed sensors,
+seven voltage sensors, VID lines, alarms, and some miscellaneous stuff.
+
+Temperatures are measured in degrees Celsius. An alarm is triggered once
+when the Overtemperature Shutdown limit is crossed; it is triggered again
+as soon as it drops below the Hysteresis value. A more useful behavior
+can be found by setting the Hysteresis value to +127 degrees Celsius; in
+this case, alarms are issued during all the time when the actual temperature
+is above the Overtemperature Shutdown value. Measurements are guaranteed
+between -55 and +125 degrees, with a resolution of 1 degree.
+
+Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
+triggered if the rotation speed has dropped below a programmable limit. Fan
+readings can be divided by a programmable divider (1, 2, 4 or 8) to give
+the readings more range or accuracy. Not all RPM values can accurately be
+represented, so some rounding is done. With a divider of 2, the lowest
+representable value is around 2600 RPM.
+
+Voltage sensors (also known as IN sensors) report their values in volts.
+An alarm is triggered if the voltage has crossed a programmable minimum
+or maximum limit. Note that minimum in this case always means 'closest to
+zero'; this is important for negative voltage measurements. All voltage
+inputs can measure voltages between 0 and 4.08 volts, with a resolution
+of 0.016 volt.
+
+The VID lines encode the core voltage value: the voltage level your processor
+should work with. This is hardcoded by the mainboard and/or processor itself.
+It is a value in volts. When it is unconnected, you will often find the
+value 3.50 V here.
+
+In addition to the alarms described above, there are a couple of additional
+ones. There is a BTI alarm, which gets triggered when an external chip has
+crossed its limits. Usually, this is connected to all LM75 chips; if at
+least one crosses its limits, this bit gets set. The CHAS alarm triggers
+if your computer case is open. The FIFO alarms should never trigger; it
+indicates an internal error. The SMI_IN alarm indicates some other chip
+has triggered an SMI interrupt. As we do not use SMI interrupts at all,
+this condition usually indicates there is a problem with some other
+device.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may
+already have disappeared! Note that in the current implementation, all
+hardware registers are read whenever any data is read (unless it is less
+than 1.5 seconds since the last update). This means that you can easily
+miss once-only alarms.
+
+The LM7* only updates its values each 1.5 seconds; reading it more often
+will do no harm, but will return 'old' values.
diff -urN linux/Documentation/hwmon/lm80 linux/Documentation/hwmon/lm80
--- linux/Documentation/hwmon/lm80      1970/01/01 00:00:00
+++ linux/Documentation/hwmon/lm80      2005-07-13 12:48:47.274914000 +0100     
1.1
@@ -0,0 +1,56 @@
+Kernel driver lm80
+==================
+
+Supported chips:
+  * National Semiconductor LM80
+    Prefix: 'lm80'
+    Addresses scanned: I2C 0x28 - 0x2f
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/
+
+Authors:
+        Frodo Looijaard <frodol@dds.nl>,
+        Philip Edelbrock <phil@netroedge.com>
+
+Description
+-----------
+
+This driver implements support for the National Semiconductor LM80.
+It is described as a 'Serial Interface ACPI-Compatible Microprocessor
+System Hardware Monitor'.
+
+The LM80 implements one temperature sensor, two fan rotation speed sensors,
+seven voltage sensors, alarms, and some miscellaneous stuff.
+
+Temperatures are measured in degrees Celsius. There are two sets of limits
+which operate independently. When the HOT Temperature Limit is crossed,
+this will cause an alarm that will be reasserted until the temperature
+drops below the HOT Hysteresis. The Overtemperature Shutdown (OS) limits
+should work in the same way (but this must be checked; the datasheet
+is unclear about this). Measurements are guaranteed between -55 and
++125 degrees. The current temperature measurement has a resolution of
+0.0625 degrees; the limits have a resolution of 1 degree.
+
+Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
+triggered if the rotation speed has dropped below a programmable limit. Fan
+readings can be divided by a programmable divider (1, 2, 4 or 8) to give
+the readings more range or accuracy. Not all RPM values can accurately be
+represented, so some rounding is done. With a divider of 2, the lowest
+representable value is around 2600 RPM.
+
+Voltage sensors (also known as IN sensors) report their values in volts.
+An alarm is triggered if the voltage has crossed a programmable minimum
+or maximum limit. Note that minimum in this case always means 'closest to
+zero'; this is important for negative voltage measurements. All voltage
+inputs can measure voltages between 0 and 2.55 volts, with a resolution
+of 0.01 volt.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may
+already have disappeared! Note that in the current implementation, all
+hardware registers are read whenever any data is read (unless it is less
+than 2.0 seconds since the last update). This means that you can easily
+miss once-only alarms.
+
+The LM80 only updates its values each 1.5 seconds; reading it more often
+will do no harm, but will return 'old' values.
diff -urN linux/Documentation/hwmon/lm83 linux/Documentation/hwmon/lm83
--- linux/Documentation/hwmon/lm83      1970/01/01 00:00:00
+++ linux/Documentation/hwmon/lm83      2005-07-13 12:48:47.298481000 +0100     
1.1
@@ -0,0 +1,76 @@
+Kernel driver lm83
+==================
+
+Supported chips:
+  * National Semiconductor LM83
+    Prefix: 'lm83'
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/pf/LM/LM83.html
+
+
+Author: Jean Delvare <khali@linux-fr.org>
+
+Description
+-----------
+
+The LM83 is a digital temperature sensor. It senses its own temperature as
+well as the temperature of up to three external diodes. It is compatible
+with many other devices such as the LM84 and all other ADM1021 clones.
+The main difference between the LM83 and the LM84 in that the later can
+only sense the temperature of one external diode.
+
+Using the adm1021 driver for a LM83 should work, but only two temperatures
+will be reported instead of four.
+
+The LM83 is only found on a handful of motherboards. Both a confirmed
+list and an unconfirmed list follow. If you can confirm or infirm the
+fact that any of these motherboards do actually have an LM83, please
+contact us. Note that the LM90 can easily be misdetected as a LM83.
+
+Confirmed motherboards:
+    SBS         P014
+
+Unconfirmed motherboards:
+    Gigabyte    GA-8IK1100
+    Iwill       MPX2
+    Soltek      SL-75DRV5
+
+The driver has been successfully tested by Magnus Forsström, who I'd
+like to thank here. More testers will be of course welcome.
+
+The fact that the LM83 is only scarcely used can be easily explained.
+Most motherboards come with more than just temperature sensors for
+health monitoring. They also have voltage and fan rotation speed
+sensors. This means that temperature-only chips are usually used as
+secondary chips coupled with another chip such as an IT8705F or similar
+chip, which provides more features. Since systems usually need three
+temperature sensors (motherboard, processor, power supply) and primary
+chips provide some temperature sensors, the secondary chip, if needed,
+won't have to handle more than two temperatures. Thus, ADM1021 clones
+are sufficient, and there is no need for a four temperatures sensor
+chip such as the LM83. The only case where using an LM83 would make
+sense is on SMP systems, such as the above-mentioned Iwill MPX2,
+because you want an additional temperature sensor for each additional
+CPU.
+
+On the SBS P014, this is different, since the LM83 is the only hardware
+monitoring chipset. One temperature sensor is used for the motherboard
+(actually measuring the LM83's own temperature), one is used for the
+CPU. The two other sensors must be used to measure the temperature of
+two other points of the motherboard. We suspect these points to be the
+north and south bridges, but this couldn't be confirmed.
+
+All temperature values are given in degrees Celsius. Local temperature
+is given within a range of 0 to +85 degrees. Remote temperatures are
+given within a range of 0 to +125 degrees. Resolution is 1.0 degree,
+accuracy is guaranteed to 3.0 degrees (see the datasheet for more
+details).
+
+Each sensor has its own high limit, but the critical limit is common to
+all four sensors. There is no hysteresis mechanism as found on most
+recent temperature sensors.
+
+The lm83 driver will not update its values more frequently than every
+other second; reading them more often will do no harm, but will return
+'old' values.
diff -urN linux/Documentation/hwmon/lm85 linux/Documentation/hwmon/lm85
--- linux/Documentation/hwmon/lm85      1970/01/01 00:00:00
+++ linux/Documentation/hwmon/lm85      2005-07-13 12:48:47.319982000 +0100     
1.1
@@ -0,0 +1,221 @@
+Kernel driver lm85
+==================
+
+Supported chips:
+  * National Semiconductor LM85 (B and C versions)
+    Prefix: 'lm85'
+    Addresses scanned: I2C 0x2c, 0x2d, 0x2e
+    Datasheet: http://www.national.com/pf/LM/LM85.html
+  * Analog Devices ADM1027
+    Prefix: 'adm1027'
+    Addresses scanned: I2C 0x2c, 0x2d, 0x2e
+    Datasheet: http://www.analog.com/en/prod/0,,766_825_ADM1027,00.html
+  * Analog Devices ADT7463
+    Prefix: 'adt7463'
+    Addresses scanned: I2C 0x2c, 0x2d, 0x2e
+    Datasheet: http://www.analog.com/en/prod/0,,766_825_ADT7463,00.html
+  * SMSC EMC6D100, SMSC EMC6D101
+    Prefix: 'emc6d100'
+    Addresses scanned: I2C 0x2c, 0x2d, 0x2e
+    Datasheet: http://www.smsc.com/main/tools/discontinued/6d100.pdf
+  * SMSC EMC6D102
+    Prefix: 'emc6d102'
+    Addresses scanned: I2C 0x2c, 0x2d, 0x2e
+    Datasheet: http://www.smsc.com/main/catalog/emc6d102.html
+
+Authors:
+        Philip Pokorny <ppokorny@penguincomputing.com>,
+        Frodo Looijaard <frodol@dds.nl>,
+        Richard Barrington <rich_b_nz@clear.net.nz>,
+        Margit Schubert-While <margitsw@t-online.de>,
+        Justin Thiessen <jthiessen@penguincomputing.com>
+
+Description
+-----------
+
+This driver implements support for the National Semiconductor LM85 and
+compatible chips including the Analog Devices ADM1027, ADT7463 and
+SMSC EMC6D10x chips family.
+
+The LM85 uses the 2-wire interface compatible with the SMBUS 2.0
+specification. Using an analog to digital converter it measures three (3)
+temperatures and five (5) voltages. It has four (4) 16-bit counters for
+measuring fan speed. Five (5) digital inputs are provided for sampling the
+VID signals from the processor to the VRM. Lastly, there are three (3) PWM
+outputs that can be used to control fan speed.
+
+The voltage inputs have internal scaling resistors so that the following
+voltage can be measured without external resistors:
+
+  2.5V, 3.3V, 5V, 12V, and CPU core voltage (2.25V)
+
+The temperatures measured are one internal diode, and two remote diodes.
+Remote 1 is generally the CPU temperature. These inputs are designed to
+measure a thermal diode like the one in a Pentium 4 processor in a socket
+423 or socket 478 package. They can also measure temperature using a
+transistor like the 2N3904.
+
+A sophisticated control system for the PWM outputs is designed into the
+LM85 that allows fan speed to be adjusted automatically based on any of the
+three temperature sensors. Each PWM output is individually adjustable and
+programmable. Once configured, the LM85 will adjust the PWM outputs in
+response to the measured temperatures without further host intervention.
+This feature can also be disabled for manual control of the PWM's.
+
+Each of the measured inputs (voltage, temperature, fan speed) has
+corresponding high/low limit values. The LM85 will signal an ALARM if any
+measured value exceeds either limit.
+
+The LM85 samples all inputs continuously. The lm85 driver will not read
+the registers more often than once a second. Further, configuration data is
+only read once each 5 minutes. There is twice as much config data as
+measurements, so this would seem to be a worthwhile optimization.
+
+Special Features
+----------------
+
+The LM85 has four fan speed monitoring modes. The ADM1027 has only two.
+Both have special circuitry to compensate for PWM interactions with the
+TACH signal from the fans. The ADM1027 can be configured to measure the
+speed of a two wire fan, but the input conditioning circuitry is different
+for 3-wire and 2-wire mode. For this reason, the 2-wire fan modes are not
+exposed to user control. The BIOS should initialize them to the correct
+mode. If you've designed your own ADM1027, you'll have to modify the
+init_client function and add an insmod parameter to set this up.
+
+To smooth the response of fans to changes in temperature, the LM85 has an
+optional filter for smoothing temperatures. The ADM1027 has the same
+config option but uses it to rate limit the changes to fan speed instead.
+
+The ADM1027 and ADT7463 have a 10-bit ADC and can therefore measure
+temperatures with 0.25 degC resolution. They also provide an offset to the
+temperature readings that is automatically applied during measurement.
+This offset can be used to zero out any errors due to traces and placement.
+The documentation says that the offset is in 0.25 degC steps, but in
+initial testing of the ADM1027 it was 1.00 degC steps. Analog Devices has
+confirmed this "bug". The ADT7463 is reported to work as described in the
+documentation. The current lm85 driver does not show the offset register.
+
+The ADT7463 has a THERM asserted counter. This counter has a 22.76ms
+resolution and a range of 5.8 seconds. The driver implements a 32-bit
+accumulator of the counter value to extend the range to over a year. The
+counter will stay at it's max value until read.
+
+See the vendor datasheets for more information. There is application note
+from National (AN-1260) with some additional information about the LM85.
+The Analog Devices datasheet is very detailed and describes a procedure for
+determining an optimal configuration for the automatic PWM control.
+
+The SMSC EMC6D100 & EMC6D101 monitor external voltages, temperatures, and
+fan speeds. They use this monitoring capability to alert the system to out
+of limit conditions and can automatically control the speeds of multiple
+fans in a PC or embedded system. The EMC6D101, available in a 24-pin SSOP
+package, and the EMC6D100, available in a 28-pin SSOP package, are designed
+to be register compatible. The EMC6D100 offers all the features of the
+EMC6D101 plus additional voltage monitoring and system control features.
+Unfortunately it is not possible to distinguish between the package
+versions on register level so these additional voltage inputs may read
+zero. The EMC6D102 features addtional ADC bits thus extending precision
+of voltage and temperature channels.
+
+
+Hardware Configurations
+-----------------------
+
+The LM85 can be jumpered for 3 different SMBus addresses. There are
+no other hardware configuration options for the LM85.
+
+The lm85 driver detects both LM85B and LM85C revisions of the chip. See the
+datasheet for a complete description of the differences. Other than
+identifying the chip, the driver behaves no differently with regard to
+these two chips. The LM85B is recommended for new designs.
+
+The ADM1027 and ADT7463 chips have an optional SMBALERT output that can be
+used to signal the chipset in case a limit is exceeded or the temperature
+sensors fail. Individual sensor interrupts can be masked so they won't
+trigger SMBALERT. The SMBALERT output if configured replaces one of the other
+functions (PWM2 or IN0). This functionality is not implemented in current
+driver.
+
+The ADT7463 also has an optional THERM output/input which can be connected
+to the processor PROC_HOT output. If available, the autofan control
+dynamic Tmin feature can be enabled to keep the system temperature within
+spec (just?!) with the least possible fan noise.
+
+Configuration Notes
+-------------------
+
+Besides standard interfaces driver adds following:
+
+* Temperatures and Zones
+
+Each temperature sensor is associated with a Zone. There are three
+sensors and therefore three zones (# 1, 2 and 3). Each zone has the following
+temperature configuration points:
+
+* temp#_auto_temp_off - temperature below which fans should be off or spinning 
very low.
+* temp#_auto_temp_min - temperature over which fans start to spin.
+* temp#_auto_temp_max - temperature when fans spin at full speed.
+* temp#_auto_temp_crit - temperature when all fans will run full speed.
+
+* PWM Control
+
+There are three PWM outputs. The LM85 datasheet suggests that the
+pwm3 output control both fan3 and fan4. Each PWM can be individually
+configured and assigned to a zone for it's control value. Each PWM can be
+configured individually according to the following options.
+
+* pwm#_auto_pwm_min - this specifies the PWM value for temp#_auto_temp_off
+                      temperature. (PWM value from 0 to 255)
+
+* pwm#_auto_pwm_freq - select base frequency of PWM output. You can select
+                       in range of 10.0 to 94.0 Hz in .1 Hz units.
+                      (Values 100 to 940).
+
+The pwm#_auto_pwm_freq can be set to one of the following 8 values. Setting the
+frequency to a value not on this list, will result in the next higher frequency
+being selected. The actual device frequency may vary slightly from this
+specification as designed by the manufacturer. Consult the datasheet for more
+details. (PWM Frequency values:  100, 150, 230, 300, 380, 470, 620, 940)
+
+* pwm#_auto_pwm_minctl - this flags selects for temp#_auto_temp_off temperature
+                         the bahaviour of fans. Write 1 to let fans spinning at
+                        pwm#_auto_pwm_min or write 0 to let them off.
+
+NOTE: It has been reported that there is a bug in the LM85 that causes the flag
+to be associated with the zones not the PWMs. This contradicts all the
+published documentation. Setting pwm#_min_ctl in this case actually affects all
+PWMs controlled by zone '#'.
+
+* PWM Controlling Zone selection
+
+* pwm#_auto_channels - controls zone that is associated with PWM
+
+Configuration choices:
+
+   Value     Meaning
+  ------  ------------------------------------------------
+      1    Controlled by Zone 1
+      2    Controlled by Zone 2
+      3    Controlled by Zone 3
+     23    Controlled by higher temp of Zone 2 or 3
+    123    Controlled by highest temp of Zone 1, 2 or 3
+      0    PWM always 0%  (off)
+     -1    PWM always 100%  (full on)
+     -2    Manual control (write to 'pwm#' to set)
+
+The National LM85's have two vendor specific configuration
+features. Tach. mode and Spinup Control. For more details on these,
+see the LM85 datasheet or Application Note AN-1260.
+
+The Analog Devices ADM1027 has several vendor specific enhancements.
+The number of pulses-per-rev of the fans can be set, Tach monitoring
+can be optimized for PWM operation, and an offset can be applied to
+the temperatures to compensate for systemic errors in the
+measurements.
+
+In addition to the ADM1027 features, the ADT7463 also has Tmin control
+and THERM asserted counts. Automatic Tmin control acts to adjust the
+Tmin value to maintain the measured temperature sensor at a specified
+temperature. There isn't much documentation on this feature in the
+ADT7463 data sheet. This is not supported by current driver.
diff -urN linux/Documentation/hwmon/lm87 linux/Documentation/hwmon/lm87
--- linux/Documentation/hwmon/lm87      1970/01/01 00:00:00
+++ linux/Documentation/hwmon/lm87      2005-07-13 12:48:47.346149000 +0100     
1.1
@@ -0,0 +1,73 @@
+Kernel driver lm87
+==================
+
+Supported chips:
+  * National Semiconductor LM87
+    Prefix: 'lm87'
+    Addresses scanned: I2C 0x2c - 0x2f
+    Datasheet: http://www.national.com/pf/LM/LM87.html
+
+Authors:
+        Frodo Looijaard <frodol@dds.nl>,
+        Philip Edelbrock <phil@netroedge.com>,
+        Mark Studebaker <mdsxyz123@yahoo.com>,
+        Stephen Rousset <stephen.rousset@rocketlogix.com>,
+        Dan Eaton <dan.eaton@rocketlogix.com>,
+        Jean Delvare <khali@linux-fr.org>,
+        Original 2.6 port Jeff Oliver
+
+Description
+-----------
+
+This driver implements support for the National Semiconductor LM87.
+
+The LM87 implements up to three temperature sensors, up to two fan
+rotation speed sensors, up to seven voltage sensors, alarms, and some
+miscellaneous stuff.
+
+Temperatures are measured in degrees Celsius. Each input has a high
+and low alarm settings. A high limit produces an alarm when the value
+goes above it, and an alarm is also produced when the value goes below
+the low limit.
+
+Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
+triggered if the rotation speed has dropped below a programmable limit. Fan
+readings can be divided by a programmable divider (1, 2, 4 or 8) to give
+the readings more range or accuracy. Not all RPM values can accurately be
+represented, so some rounding is done. With a divider of 2, the lowest
+representable value is around 2600 RPM.
+
+Voltage sensors (also known as IN sensors) report their values in
+volts. An alarm is triggered if the voltage has crossed a programmable
+minimum or maximum limit. Note that minimum in this case always means
+'closest to zero'; this is important for negative voltage measurements.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may
+already have disappeared! Note that in the current implementation, all
+hardware registers are read whenever any data is read (unless it is less
+than 1.0 seconds since the last update). This means that you can easily
+miss once-only alarms.
+
+The lm87 driver only updates its values each 1.0 seconds; reading it more
+often will do no harm, but will return 'old' values.
+
+
+Hardware Configurations
+-----------------------
+
+The LM87 has four pins which can serve one of two possible functions,
+depending on the hardware configuration.
+
+Some functions share pins, so not all functions are available at the same
+time. Which are depends on the hardware setup. This driver assumes that
+the BIOS configured the chip correctly. In that respect, it differs from
+the original driver (from lm_sensors for Linux 2.4), which would force the
+LM87 to an arbitrary, compile-time chosen mode, regardless of the actual
+chipset wiring.
+
+For reference, here is the list of exclusive functions:
+ - in0+in5 (default) or temp3
+ - fan1 (default) or in6
+ - fan2 (default) or in7
+ - VID lines (default) or IRQ lines (not handled by this driver)
diff -urN linux/Documentation/hwmon/lm90 linux/Documentation/hwmon/lm90
--- linux/Documentation/hwmon/lm90      1970/01/01 00:00:00
+++ linux/Documentation/hwmon/lm90      2005-07-13 12:48:47.367488000 +0100     
1.1
@@ -0,0 +1,121 @@
+Kernel driver lm90
+==================
+
+Supported chips:
+  * National Semiconductor LM90
+    Prefix: 'lm90'
+    Addresses scanned: I2C 0x4c
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/pf/LM/LM90.html
+  * National Semiconductor LM89
+    Prefix: 'lm99'
+    Addresses scanned: I2C 0x4c and 0x4d
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/pf/LM/LM89.html
+  * National Semiconductor LM99
+    Prefix: 'lm99'
+    Addresses scanned: I2C 0x4c and 0x4d
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/pf/LM/LM99.html
+  * National Semiconductor LM86
+    Prefix: 'lm86'
+    Addresses scanned: I2C 0x4c
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/pf/LM/LM86.html
+  * Analog Devices ADM1032
+    Prefix: 'adm1032'
+    Addresses scanned: I2C 0x4c
+    Datasheet: Publicly available at the Analog Devices website
+               http://products.analog.com/products/info.asp?product=ADM1032
+  * Analog Devices ADT7461
+    Prefix: 'adt7461'
+    Addresses scanned: I2C 0x4c
+    Datasheet: Publicly available at the Analog Devices website
+               http://products.analog.com/products/info.asp?product=ADT7461
+    Note: Only if in ADM1032 compatibility mode
+  * Maxim MAX6657
+    Prefix: 'max6657'
+    Addresses scanned: I2C 0x4c
+    Datasheet: Publicly available at the Maxim website
+               http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2578
+  * Maxim MAX6658
+    Prefix: 'max6657'
+    Addresses scanned: I2C 0x4c
+    Datasheet: Publicly available at the Maxim website
+               http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2578
+  * Maxim MAX6659
+    Prefix: 'max6657'
+    Addresses scanned: I2C 0x4c, 0x4d (unsupported 0x4e)
+    Datasheet: Publicly available at the Maxim website
+               http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2578
+
+
+Author: Jean Delvare <khali@linux-fr.org>
+
+
+Description
+-----------
+
+The LM90 is a digital temperature sensor. It senses its own temperature as
+well as the temperature of up to one external diode. It is compatible
+with many other devices such as the LM86, the LM89, the LM99, the ADM1032,
+the MAX6657, MAX6658 and the MAX6659 all of which are supported by this driver.
+Note that there is no easy way to differentiate between the last three
+variants. The extra address and features of the MAX6659 are not supported by
+this driver. Additionally, the ADT7461 is supported if found in ADM1032
+compatibility mode.
+
+The specificity of this family of chipsets over the ADM1021/LM84
+family is that it features critical limits with hysteresis, and an
+increased resolution of the remote temperature measurement.
+
+The different chipsets of the family are not strictly identical, although
+very similar. This driver doesn't handle any specific feature for now,
+but could if there ever was a need for it. For reference, here comes a
+non-exhaustive list of specific features:
+
+LM90:
+  * Filter and alert configuration register at 0xBF.
+  * ALERT is triggered by temperatures over critical limits.
+
+LM86 and LM89:
+  * Same as LM90
+  * Better external channel accuracy
+
+LM99:
+  * Same as LM89
+  * External temperature shifted by 16 degrees down
+
+ADM1032:
+  * Consecutive alert register at 0x22.
+  * Conversion averaging.
+  * Up to 64 conversions/s.
+  * ALERT is triggered by open remote sensor.
+
+ADT7461
+  * Extended temperature range (breaks compatibility)
+  * Lower resolution for remote temperature
+
+MAX6657 and MAX6658:
+  * Remote sensor type selection
+
+MAX6659
+  * Selectable address
+  * Second critical temperature limit
+  * Remote sensor type selection
+
+All temperature values are given in degrees Celsius. Resolution
+is 1.0 degree for the local temperature, 0.125 degree for the remote
+temperature.
+
+Each sensor has its own high and low limits, plus a critical limit.
+Additionally, there is a relative hysteresis value common to both critical
+values. To make life easier to user-space applications, two absolute values
+are exported, one for each channel, but these values are of course linked.
+Only the local hysteresis can be set from user-space, and the same delta
+applies to the remote hysteresis.
+
+The lm90 driver will not update its values more frequently than every
+other second; reading them more often will do no harm, but will return
+'old' values.
+
diff -urN linux/Documentation/hwmon/lm92 linux/Documentation/hwmon/lm92
--- linux/Documentation/hwmon/lm92      1970/01/01 00:00:00
+++ linux/Documentation/hwmon/lm92      2005-07-13 12:48:47.395629000 +0100     
1.1
@@ -0,0 +1,37 @@
+Kernel driver lm92
+==================
+
+Supported chips:
+  * National Semiconductor LM92
+    Prefix: 'lm92'
+    Addresses scanned: I2C 0x48 - 0x4b
+    Datasheet: http://www.national.com/pf/LM/LM92.html
+  * National Semiconductor LM76
+    Prefix: 'lm92'
+    Addresses scanned: none, force parameter needed
+    Datasheet: http://www.national.com/pf/LM/LM76.html
+  * Maxim MAX6633/MAX6634/MAX6635
+    Prefix: 'lm92'
+    Addresses scanned: I2C 0x48 - 0x4b
+    MAX6633 with address in 0x40 - 0x47, 0x4c - 0x4f needs force parameter
+    and MAX6634 with address in 0x4c - 0x4f needs force parameter
+    Datasheet: http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3074
+
+Authors:
+        Abraham van der Merwe <abraham@2d3d.co.za>
+        Jean Delvare <khali@linux-fr.org>
+
+
+Description
+-----------
+
+This driver implements support for the National Semiconductor LM92
+temperature sensor.
+
+Each LM92 temperature sensor supports a single temperature sensor. There are
+alarms for high, low, and critical thresholds. There's also an hysteresis to
+control the thresholds for resetting alarms.
+
+Support was added later for the LM76 and Maxim MAX6633/MAX6634/MAX6635,
+which are mostly compatible. They have not all been tested, so you
+may need to use the force parameter.
diff -urN linux/Documentation/hwmon/max1619 linux/Documentation/hwmon/max1619
--- linux/Documentation/hwmon/max1619   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/max1619   2005-07-13 12:48:47.414493000 +0100     
1.1
@@ -0,0 +1,29 @@
+Kernel driver max1619
+=====================
+
+Supported chips:
+  * Maxim MAX1619
+    Prefix: 'max1619'
+    Addresses scanned: I2C 0x18-0x1a, 0x29-0x2b, 0x4c-0x4e
+    Datasheet: Publicly available at the Maxim website
+               http://pdfserv.maxim-ic.com/en/ds/MAX1619.pdf
+
+Authors:
+        Alexey Fisher <fishor@mail.ru>,
+        Jean Delvare <khali@linux-fr.org>
+
+Description
+-----------
+
+The MAX1619 is a digital temperature sensor. It senses its own temperature as
+well as the temperature of up to one external diode.
+
+All temperature values are given in degrees Celsius. Resolution
+is 1.0 degree for the local temperature and for the remote temperature.
+
+Only the external sensor has high and low limits.
+
+The max1619 driver will not update its values more frequently than every
+other second; reading them more often will do no harm, but will return
+'old' values.
+
diff -urN linux/Documentation/hwmon/pc87360 linux/Documentation/hwmon/pc87360
--- linux/Documentation/hwmon/pc87360   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/pc87360   2005-07-13 12:48:47.438400000 +0100     
1.1
@@ -0,0 +1,189 @@
+Kernel driver pc87360
+=====================
+
+Supported chips:
+  * National Semiconductor PC87360, PC87363, PC87364, PC87365 and PC87366
+    Prefixes: 'pc87360', 'pc87363', 'pc87364', 'pc87365', 'pc87366'
+    Addresses scanned: none, address read from Super I/O config space
+    Datasheets:
+        http://www.national.com/pf/PC/PC87360.html
+        http://www.national.com/pf/PC/PC87363.html
+        http://www.national.com/pf/PC/PC87364.html
+        http://www.national.com/pf/PC/PC87365.html
+        http://www.national.com/pf/PC/PC87366.html
+
+Authors: Jean Delvare <khali@linux-fr.org>
+
+Thanks to Sandeep Mehta, Tonko de Rooy and Daniel Ceregatti for testing.
+Thanks to Rudolf Marek for helping me investigate conversion issues.
+
+
+Module Parameters
+-----------------
+
+* init int
+  Chip initialization level:
+   0: None
+  *1: Forcibly enable internal voltage and temperature channels, except in9
+   2: Forcibly enable all voltage and temperature channels, except in9
+   3: Forcibly enable all voltage and temperature channels, including in9
+
+Note that this parameter has no effect for the PC87360, PC87363 and PC87364
+chips.
+
+Also note that for the PC87366, initialization levels 2 and 3 don't enable
+all temperature channels, because some of them share pins with each other,
+so they can't be used at the same time.
+
+
+Description
+-----------
+
+The National Semiconductor PC87360 Super I/O chip contains monitoring and
+PWM control circuitry for two fans. The PC87363 chip is similar, and the
+PC87364 chip has monitoring and PWM control for a third fan.
+
+The National Semiconductor PC87365 and PC87366 Super I/O chips are complete
+hardware monitoring chipsets, not only controlling and monitoring three fans,
+but also monitoring eleven voltage inputs and two (PC87365) or up to four
+(PC87366) temperatures.
+
+  Chip        #vin    #fan    #pwm    #temp   devid
+
+  PC87360     -       2       2       -       0xE1
+  PC87363     -       2       2       -       0xE8
+  PC87364     -       3       3       -       0xE4
+  PC87365     11      3       3       2       0xE5
+  PC87366     11      3       3       3-4     0xE9
+
+The driver assumes that no more than one chip is present, and one of the
+standard Super I/O addresses is used (0x2E/0x2F or 0x4E/0x4F)
+
+Fan Monitoring
+--------------
+
+Fan rotation speeds are reported in RPM (revolutions per minute). An alarm
+is triggered if the rotation speed has dropped below a programmable limit.
+A different alarm is triggered if the fan speed is too low to be measured.
+
+Fan readings are affected by a programmable clock divider, giving the
+readings more range or accuracy. Usually, users have to learn how it works,
+but this driver implements dynamic clock divider selection, so you don't
+have to care no more.
+
+For reference, here are a few values about clock dividers:
+
+                slowest         accuracy        highest
+                measurable      around 3000     accurate
+    divider     speed (RPM)     RPM (RPM)       speed (RPM)
+         1        1882              18           6928
+         2         941              37           4898
+         4         470              74           3464
+         8         235             150           2449
+
+For the curious, here is how the values above were computed:
+ * slowest measurable speed: clock/(255*divider)
+ * accuracy around 3000 RPM: 3000^2/clock
+ * highest accurate speed: sqrt(clock*100)
+The clock speed for the PC87360 family is 480 kHz. I arbitrarily chose 100
+RPM as the lowest acceptable accuracy.
+
+As mentioned above, you don't have to care about this no more.
+
+Note that not all RPM values can be represented, even when the best clock
+divider is selected. This is not only true for the measured speeds, but
+also for the programmable low limits, so don't be surprised if you try to
+set, say, fan1_min to 2900 and it finally reads 2909.
+
+
+Fan Control
+-----------
+
+PWM (pulse width modulation) values range from 0 to 255, with 0 meaning
+that the fan is stopped, and 255 meaning that the fan goes at full speed.
+
+Be extremely careful when changing PWM values. Low PWM values, even
+non-zero, can stop the fan, which may cause irreversible damage to your
+hardware if temperature increases too much. When changing PWM values, go
+step by step and keep an eye on temperatures.
+
+One user reported problems with PWM. Changing PWM values would break fan
+speed readings. No explanation nor fix could be found.
+
+
+Temperature Monitoring
+----------------------
+
+Temperatures are reported in degrees Celsius. Each temperature measured has
+associated low, high and overtemperature limits, each of which triggers an
+alarm when crossed.
+
+The first two temperature channels are external. The third one (PC87366
+only) is internal.
+
+The PC87366 has three additional temperature channels, based on
+thermistors (as opposed to thermal diodes for the first three temperature
+channels). For technical reasons, these channels are held by the VLM
+(voltage level monitor) logical device, not the TMS (temperature
+measurement) one. As a consequence, these temperatures are exported as
+voltages, and converted into temperatures in user-space.
+
+Note that these three additional channels share their pins with the
+external thermal diode channels, so you (physically) can't use them all at
+the same time. Although it should be possible to mix the two sensor types,
+the documents from National Semiconductor suggest that motherboard
+manufacturers should choose one type and stick to it. So you will more
+likely have either channels 1 to 3 (thermal diodes) or 3 to 6 (internal
+thermal diode, and thermistors).
+
+
+Voltage Monitoring
+------------------
+
+Voltages are reported relatively to a reference voltage, either internal or
+external. Some of them (in7:Vsb, in8:Vdd and in10:AVdd) are divided by two
+internally, you will have to compensate in sensors.conf. Others (in0 to in6)
+are likely to be divided externally. The meaning of each of these inputs as
+well as the values of the resistors used for division is left to the
+motherboard manufacturers, so you will have to document yourself and edit
+sensors.conf accordingly. National Semiconductor has a document with
+recommended resistor values for some voltages, but this still leaves much
+room for per motherboard specificities, unfortunately. Even worse,
+motherboard manufacturers don't seem to care about National Semiconductor's
+recommendations.
+
+Each voltage measured has associated low and high limits, each of which
+triggers an alarm when crossed.
+
+When available, VID inputs are used to provide the nominal CPU Core voltage.
+The driver will default to VRM 9.0, but this can be changed from user-space.
+The chipsets can handle two sets of VID inputs (on dual-CPU systems), but
+the driver will only export one for now. This may change later if there is
+a need.
+
+
+General Remarks
+---------------
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may already
+have disappeared! Note that all hardware registers are read whenever any
+data is read (unless it is less than 2 seconds since the last update, in
+which case cached values are returned instead). As a consequence, when
+a once-only alarm triggers, it may take 2 seconds for it to show, and 2
+more seconds for it to disappear.
+
+Monitoring of in9 isn't enabled at lower init levels (<3) because that
+channel measures the battery voltage (Vbat). It is a known fact that
+repeatedly sampling the battery voltage reduces its lifetime. National
+Semiconductor smartly designed their chipset so that in9 is sampled only
+once every 1024 sampling cycles (that is every 34 minutes at the default
+sampling rate), so the effect is attenuated, but still present.
+
+
+Limitations
+-----------
+
+The datasheets suggests that some values (fan mins, fan dividers)
+shouldn't be changed once the monitoring has started, but we ignore that
+recommendation. We'll reconsider if it actually causes trouble.
diff -urN linux/Documentation/hwmon/sis5595 linux/Documentation/hwmon/sis5595
--- linux/Documentation/hwmon/sis5595   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/sis5595   2005-07-13 12:48:47.461698000 +0100     
1.1
@@ -0,0 +1,106 @@
+Kernel driver sis5595
+=====================
+
+Supported chips:
+  * Silicon Integrated Systems Corp. SiS5595 Southbridge Hardware Monitor
+    Prefix: 'sis5595'
+    Addresses scanned: ISA in PCI-space encoded address
+    Datasheet: Publicly available at the Silicon Integrated Systems Corp. site.
+
+Authors:
+        Kyösti Mälkki <kmalkki@cc.hut.fi>,
+        Mark D. Studebaker <mdsxyz123@yahoo.com>,
+        Aurelien Jarno <aurelien@aurel32.net> 2.6 port
+
+   SiS southbridge has a LM78-like chip integrated on the same IC.
+   This driver is a customized copy of lm78.c
+
+   Supports following revisions:
+       Version         PCI ID          PCI Revision
+       1               1039/0008       AF or less
+       2               1039/0008       B0 or greater
+
+   Note: these chips contain a 0008 device which is incompatible with the
+        5595. We recognize these by the presence of the listed
+        "blacklist" PCI ID and refuse to load.
+
+   NOT SUPPORTED       PCI ID          BLACKLIST PCI ID
+        540            0008            0540
+        550            0008            0550
+       5513            0008            5511
+       5581            0008            5597
+       5582            0008            5597
+       5597            0008            5597
+        630            0008            0630
+        645            0008            0645
+        730            0008            0730
+        735            0008            0735
+
+
+Module Parameters
+-----------------
+force_addr=0xaddr      Set the I/O base address. Useful for boards
+                       that don't set the address in the BIOS. Does not do a
+                       PCI force; the device must still be present in lspci.
+                       Don't use this unless the driver complains that the
+                       base address is not set.
+                       Example: 'modprobe sis5595 force_addr=0x290'
+
+
+Description
+-----------
+
+The SiS5595 southbridge has integrated hardware monitor functions. It also
+has an I2C bus, but this driver only supports the hardware monitor. For the
+I2C bus driver see i2c-sis5595.
+
+The SiS5595 implements zero or one temperature sensor, two fan speed
+sensors, four or five voltage sensors, and alarms.
+
+On the first version of the chip, there are four voltage sensors and one
+temperature sensor.
+
+On the second version of the chip, the temperature sensor (temp) and the
+fifth voltage sensor (in4) share a pin which is configurable, but not
+through the driver. Sorry. The driver senses the configuration of the pin,
+which was hopefully set by the BIOS.
+
+Temperatures are measured in degrees Celsius. An alarm is triggered once
+when the max is crossed; it is also triggered when it drops below the min
+value. Measurements are guaranteed between -55 and +125 degrees, with a
+resolution of 1 degree.
+
+Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
+triggered if the rotation speed has dropped below a programmable limit. Fan
+readings can be divided by a programmable divider (1, 2, 4 or 8) to give
+the readings more range or accuracy. Not all RPM values can accurately be
+represented, so some rounding is done. With a divider of 2, the lowest
+representable value is around 2600 RPM.
+
+Voltage sensors (also known as IN sensors) report their values in volts. An
+alarm is triggered if the voltage has crossed a programmable minimum or
+maximum limit. Note that minimum in this case always means 'closest to
+zero'; this is important for negative voltage measurements. All voltage
+inputs can measure voltages between 0 and 4.08 volts, with a resolution of
+0.016 volt.
+
+In addition to the alarms described above, there is a BTI alarm, which gets
+triggered when an external chip has crossed its limits. Usually, this is
+connected to some LM75-like chip; if at least one crosses its limits, this
+bit gets set.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may already
+have disappeared! Note that in the current implementation, all hardware
+registers are read whenever any data is read (unless it is less than 1.5
+seconds since the last update). This means that you can easily miss
+once-only alarms.
+
+The SiS5595 only updates its values each 1.5 seconds; reading it more often
+will do no harm, but will return 'old' values.
+
+Problems
+--------
+Some chips refuse to be enabled. We don't know why.
+The driver will recognize this and print a message in dmesg.
+
diff -urN linux/Documentation/hwmon/smsc47b397 
linux/Documentation/hwmon/smsc47b397
--- linux/Documentation/hwmon/smsc47b397        1970/01/01 00:00:00
+++ linux/Documentation/hwmon/smsc47b397        2005-07-13 12:48:47.484526000 
+0100     1.1
@@ -0,0 +1,158 @@
+Kernel driver smsc47b397
+========================
+
+Supported chips:
+  * SMSC LPC47B397-NC
+    Prefix: 'smsc47b397'
+    Addresses scanned: none, address read from Super I/O config space
+    Datasheet: In this file
+
+Authors: Mark M. Hoffman <mhoffman@lightlink.com>
+         Utilitek Systems, Inc.
+
+November 23, 2004
+
+The following specification describes the SMSC LPC47B397-NC sensor chip
+(for which there is no public datasheet available). This document was
+provided by Craig Kelly (In-Store Broadcast Network) and edited/corrected
+by Mark M. Hoffman <mhoffman@lightlink.com>.
+
+* * * * *
+
+Methods for detecting the HP SIO and reading the thermal data on a dc7100.
+
+The thermal information on the dc7100 is contained in the SIO Hardware Monitor
+(HWM). The information is accessed through an index/data pair. The index/data
+pair is located at the HWM Base Address + 0 and the HWM Base Address + 1. The
+HWM Base address can be obtained from Logical Device 8, registers 0x60 (MSB)
+and 0x61 (LSB). Currently we are using 0x480 for the HWM Base Address and
+0x480 and 0x481 for the index/data pair.
+
+Reading temperature information.
+The temperature information is located in the following registers:
+Temp1          0x25    (Currently, this reflects the CPU temp on all systems).
+Temp2          0x26
+Temp3          0x27
+Temp4          0x80
+
+Programming Example
+The following is an example of how to read the HWM temperature registers:
+MOV    DX,480H
+MOV    AX,25H
+OUT    DX,AL
+MOV    DX,481H
+IN     AL,DX
+
+AL contains the data in hex, the temperature in Celsius is the decimal
+equivalent.
+
+Ex: If AL contains 0x2A, the temperature is 42 degrees C.
+
+Reading tach information.
+The fan speed information is located in the following registers:
+               LSB     MSB
+Tach1          0x28    0x29    (Currently, this reflects the CPU
+                               fan speed on all systems).
+Tach2          0x2A    0x2B
+Tach3          0x2C    0x2D
+Tach4          0x2E    0x2F
+
+Important!!!
+Reading the tach LSB locks the tach MSB.
+The LSB Must be read first.
+
+How to convert the tach reading to RPM.
+The tach reading (TCount) is given by: (Tach MSB * 256) + (Tach LSB)
+The SIO counts the number of 90kHz (11.111us) pulses per revolution.
+RPM = 60/(TCount * 11.111us)
+
+Example:
+Reg 0x28 = 0x9B
+Reg 0x29 = 0x08
+
+TCount = 0x89B = 2203
+
+RPM = 60 / (2203 * 11.11111 E-6) = 2451 RPM
+
+Obtaining the SIO version.
+
+CONFIGURATION SEQUENCE
+To program the configuration registers, the following sequence must be 
followed:
+1. Enter Configuration Mode
+2. Configure the Configuration Registers
+3. Exit Configuration Mode.
+
+Enter Configuration Mode
+To place the chip into the Configuration State The config key (0x55) is written
+to the CONFIG PORT (0x2E).
+
+Configuration Mode
+In configuration mode, the INDEX PORT is located at the CONFIG PORT address and
+the DATA PORT is at INDEX PORT address + 1.
+
+The desired configuration registers are accessed in two steps:
+a.     Write the index of the Logical Device Number Configuration Register
+       (i.e., 0x07) to the INDEX PORT and then write the number of the
+       desired logical device to the DATA PORT.
+
+b.     Write the address of the desired configuration register within the
+       logical device to the INDEX PORT and then write or read the config-
+       uration register through the DATA PORT.
+
+Note: If accessing the Global Configuration Registers, step (a) is not 
required.
+
+Exit Configuration Mode
+To exit the Configuration State the write 0xAA to the CONFIG PORT (0x2E).
+The chip returns to the RUN State.  (This is important).
+
+Programming Example
+The following is an example of how to read the SIO Device ID located at 0x20
+
+; ENTER CONFIGURATION MODE
+MOV    DX,02EH
+MOV    AX,055H
+OUT    DX,AL
+; GLOBAL CONFIGURATION  REGISTER
+MOV    DX,02EH
+MOV    AL,20H
+OUT    DX,AL
+; READ THE DATA
+MOV    DX,02FH
+IN     AL,DX
+; EXIT CONFIGURATION MODE
+MOV    DX,02EH
+MOV    AX,0AAH
+OUT    DX,AL
+
+The registers of interest for identifying the SIO on the dc7100 are Device ID
+(0x20) and Device Rev  (0x21).
+
+The Device ID will read 0X6F
+The Device Rev currently reads 0x01
+
+Obtaining the HWM Base Address.
+The following is an example of how to read the HWM Base Address located in
+Logical Device 8.
+
+; ENTER CONFIGURATION MODE
+MOV    DX,02EH
+MOV    AX,055H
+OUT    DX,AL
+; CONFIGURE REGISTER CRE0,
+; LOGICAL DEVICE 8
+MOV    DX,02EH
+MOV    AL,07H
+OUT    DX,AL ;Point to LD# Config Reg
+MOV    DX,02FH
+MOV    AL, 08H
+OUT    DX,AL;Point to Logical Device 8
+;
+MOV    DX,02EH
+MOV    AL,60H
+OUT    DX,AL   ; Point to HWM Base Addr MSB
+MOV    DX,02FH
+IN     AL,DX   ; Get MSB of HWM Base Addr
+; EXIT CONFIGURATION MODE
+MOV    DX,02EH
+MOV    AX,0AAH
+OUT    DX,AL
diff -urN linux/Documentation/hwmon/smsc47m1 linux/Documentation/hwmon/smsc47m1
--- linux/Documentation/hwmon/smsc47m1  1970/01/01 00:00:00
+++ linux/Documentation/hwmon/smsc47m1  2005-07-13 12:48:47.509978000 +0100     
1.1
@@ -0,0 +1,52 @@
+Kernel driver smsc47m1
+======================
+
+Supported chips:
+  * SMSC LPC47B27x, LPC47M10x, LPC47M13x, LPC47M14x, LPC47M15x and LPC47M192
+    Addresses scanned: none, address read from Super I/O config space
+    Prefix: 'smsc47m1'
+    Datasheets:
+        http://www.smsc.com/main/datasheets/47b27x.pdf
+        http://www.smsc.com/main/datasheets/47m10x.pdf
+        http://www.smsc.com/main/tools/discontinued/47m13x.pdf
+        http://www.smsc.com/main/datasheets/47m14x.pdf
+        http://www.smsc.com/main/tools/discontinued/47m15x.pdf
+        http://www.smsc.com/main/datasheets/47m192.pdf
+
+Authors:
+        Mark D. Studebaker <mdsxyz123@yahoo.com>,
+        With assistance from Bruce Allen <ballen@uwm.edu>, and his
+        fan.c program: http://www.lsc-group.phys.uwm.edu/%7Eballen/driver/
+        Gabriele Gorla <gorlik@yahoo.com>,
+        Jean Delvare <khali@linux-fr.org>
+
+Description
+-----------
+
+The Standard Microsystems Corporation (SMSC) 47M1xx Super I/O chips
+contain monitoring and PWM control circuitry for two fans.
+
+The 47M15x and 47M192 chips contain a full 'hardware monitoring block'
+in addition to the fan monitoring and control. The hardware monitoring
+block is not supported by the driver.
+
+Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
+triggered if the rotation speed has dropped below a programmable limit. Fan
+readings can be divided by a programmable divider (1, 2, 4 or 8) to give
+the readings more range or accuracy. Not all RPM values can accurately be
+represented, so some rounding is done. With a divider of 2, the lowest
+representable value is around 2600 RPM.
+
+PWM values are from 0 to 255.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may
+already have disappeared! Note that in the current implementation, all
+hardware registers are read whenever any data is read (unless it is less
+than 1.5 seconds since the last update). This means that you can easily
+miss once-only alarms.
+
+
+**********************
+The lm_sensors project gratefully acknowledges the support of
+Intel in the development of this driver.
diff -urN linux/Documentation/hwmon/sysfs-interface 
linux/Documentation/hwmon/sysfs-interface
--- linux/Documentation/hwmon/sysfs-interface   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/sysfs-interface   2005-07-13 12:48:47.530864000 
+0100     1.1
@@ -0,0 +1,274 @@
+Naming and data format standards for sysfs files
+------------------------------------------------
+
+The libsensors library offers an interface to the raw sensors data
+through the sysfs interface. See libsensors documentation and source for
+more further information. As of writing this document, libsensors
+(from lm_sensors 2.8.3) is heavily chip-dependant. Adding or updating
+support for any given chip requires modifying the library's code.
+This is because libsensors was written for the procfs interface
+older kernel modules were using, which wasn't standardized enough.
+Recent versions of libsensors (from lm_sensors 2.8.2 and later) have
+support for the sysfs interface, though.
+
+The new sysfs interface was designed to be as chip-independant as
+possible.
+
+Note that motherboards vary widely in the connections to sensor chips.
+There is no standard that ensures, for example, that the second
+temperature sensor is connected to the CPU, or that the second fan is on
+the CPU. Also, some values reported by the chips need some computation
+before they make full sense. For example, most chips can only measure
+voltages between 0 and +4V. Other voltages are scaled back into that
+range using external resistors. Since the values of these resistors
+can change from motherboard to motherboard, the conversions cannot be
+hard coded into the driver and have to be done in user space.
+
+For this reason, even if we aim at a chip-independant libsensors, it will
+still require a configuration file (e.g. /etc/sensors.conf) for proper
+values conversion, labeling of inputs and hiding of unused inputs.
+
+An alternative method that some programs use is to access the sysfs
+files directly. This document briefly describes the standards that the
+drivers follow, so that an application program can scan for entries and
+access this data in a simple and consistent way. That said, such programs
+will have to implement conversion, labeling and hiding of inputs. For
+this reason, it is still not recommended to bypass the library.
+
+If you are developing a userspace application please send us feedback on
+this standard.
+
+Note that this standard isn't completely established yet, so it is subject
+to changes, even important ones. One more reason to use the library instead
+of accessing sysfs files directly.
+
+Each chip gets its own directory in the sysfs /sys/devices tree.  To
+find all sensor chips, it is easier to follow the symlinks from
+/sys/i2c/devices/
+
+All sysfs values are fixed point numbers.  To get the true value of some
+of the values, you should divide by the specified value.
+
+There is only one value per file, unlike the older /proc specification.
+The common scheme for files naming is: <type><number>_<item>. Usual
+types for sensor chips are "in" (voltage), "temp" (temperature) and
+"fan" (fan). Usual items are "input" (measured value), "max" (high
+threshold, "min" (low threshold). Numbering usually starts from 1,
+except for voltages which start from 0 (because most data sheets use
+this). A number is always used for elements that can be present more
+than once, even if there is a single element of the given type on the
+specific chip. Other files do not refer to a specific element, so
+they have a simple name, and no number.
+
+Alarms are direct indications read from the chips. The drivers do NOT
+make comparisons of readings to thresholds. This allows violations
+between readings to be caught and alarmed. The exact definition of an
+alarm (for example, whether a threshold must be met or must be exceeded
+to cause an alarm) is chip-dependent.
+
+
+-------------------------------------------------------------------------
+
+************
+* Voltages *
+************
+
+in[0-8]_min    Voltage min value.
+               Unit: millivolt
+               Read/Write
+               
+in[0-8]_max    Voltage max value.
+               Unit: millivolt
+               Read/Write
+               
+in[0-8]_input  Voltage input value.
+               Unit: millivolt
+               Read only
+               Actual voltage depends on the scaling resistors on the
+               motherboard, as recommended in the chip datasheet.
+               This varies by chip and by motherboard.
+               Because of this variation, values are generally NOT scaled
+               by the chip driver, and must be done by the application.
+               However, some drivers (notably lm87 and via686a)
+               do scale, with various degrees of success.
+               These drivers will output the actual voltage.
+
+               Typical usage:
+                       in0_*   CPU #1 voltage (not scaled)
+                       in1_*   CPU #2 voltage (not scaled)
+                       in2_*   3.3V nominal (not scaled)
+                       in3_*   5.0V nominal (scaled)
+                       in4_*   12.0V nominal (scaled)
+                       in5_*   -12.0V nominal (scaled)
+                       in6_*   -5.0V nominal (scaled)
+                       in7_*   varies
+                       in8_*   varies
+
+cpu[0-1]_vid   CPU core reference voltage.
+               Unit: millivolt
+               Read only.
+               Not always correct.
+
+vrm            Voltage Regulator Module version number. 
+               Read only.
+               Two digit number, first is major version, second is
+               minor version.
+               Affects the way the driver calculates the CPU core reference
+               voltage from the vid pins.
+
+
+********
+* Fans *
+********
+
+fan[1-3]_min   Fan minimum value
+               Unit: revolution/min (RPM)
+               Read/Write.
+
+fan[1-3]_input Fan input value.
+               Unit: revolution/min (RPM)
+               Read only.
+
+fan[1-3]_div   Fan divisor.
+               Integer value in powers of two (1, 2, 4, 8, 16, 32, 64, 128).
+               Some chips only support values 1, 2, 4 and 8.
+               Note that this is actually an internal clock divisor, which
+               affects the measurable speed range, not the read value.
+
+*******
+* PWM *
+*******
+
+pwm[1-3]       Pulse width modulation fan control.
+               Integer value in the range 0 to 255
+               Read/Write
+               255 is max or 100%.
+
+pwm[1-3]_enable
+               Switch PWM on and off.
+               Not always present even if fan*_pwm is.
+               0 to turn off
+               1 to turn on in manual mode
+               2 to turn on in automatic mode
+               Read/Write
+
+pwm[1-*]_auto_channels_temp
+               Select which temperature channels affect this PWM output in
+               auto mode. Bitfield, 1 is temp1, 2 is temp2, 4 is temp3 etc...
+               Which values are possible depend on the chip used.
+
+pwm[1-*]_auto_point[1-*]_pwm
+pwm[1-*]_auto_point[1-*]_temp
+pwm[1-*]_auto_point[1-*]_temp_hyst
+               Define the PWM vs temperature curve. Number of trip points is
+               chip-dependent. Use this for chips which associate trip points
+               to PWM output channels.
+
+OR
+
+temp[1-*]_auto_point[1-*]_pwm
+temp[1-*]_auto_point[1-*]_temp
+temp[1-*]_auto_point[1-*]_temp_hyst
+               Define the PWM vs temperature curve. Number of trip points is
+               chip-dependent. Use this for chips which associate trip points
+               to temperature channels.
+
+
+****************
+* Temperatures *
+****************
+
+temp[1-3]_type Sensor type selection.
+               Integers 1, 2, 3 or thermistor Beta value (3435)
+               Read/Write.
+               1: PII/Celeron Diode
+               2: 3904 transistor
+               3: thermal diode
+               Not all types are supported by all chips
+
+temp[1-4]_max  Temperature max value.
+               Unit: millidegree Celcius
+               Read/Write value.
+
+temp[1-3]_min  Temperature min value.
+               Unit: millidegree Celcius
+               Read/Write value.
+
+temp[1-3]_max_hyst
+               Temperature hysteresis value for max limit.
+               Unit: millidegree Celcius
+               Must be reported as an absolute temperature, NOT a delta
+               from the max value.
+               Read/Write value.
+
+temp[1-4]_input Temperature input value.
+               Unit: millidegree Celcius
+               Read only value.
+
+temp[1-4]_crit Temperature critical value, typically greater than
+               corresponding temp_max values.
+               Unit: millidegree Celcius
+               Read/Write value.
+
+temp[1-2]_crit_hyst
+               Temperature hysteresis value for critical limit.
+               Unit: millidegree Celcius
+               Must be reported as an absolute temperature, NOT a delta
+               from the critical value.
+               Read/Write value.
+
+               If there are multiple temperature sensors, temp1_* is
+               generally the sensor inside the chip itself,
+               reported as "motherboard temperature".  temp2_* to
+               temp4_* are generally sensors external to the chip
+               itself, for example the thermal diode inside the CPU or
+               a thermistor nearby.
+
+
+************
+* Currents *
+************
+
+Note that no known chip provides current measurements as of writing,
+so this part is theoretical, so to say.
+
+curr[1-n]_max  Current max value
+               Unit: milliampere
+               Read/Write.
+
+curr[1-n]_min  Current min value.
+               Unit: milliampere
+               Read/Write.
+
+curr[1-n]_input        Current input value
+               Unit: milliampere
+               Read only.
+
+
+*********
+* Other *
+*********
+
+alarms         Alarm bitmask.
+               Read only.
+               Integer representation of one to four bytes.
+               A '1' bit means an alarm.
+               Chips should be programmed for 'comparator' mode so that
+               the alarm will 'come back' after you read the register
+               if it is still valid.
+               Generally a direct representation of a chip's internal
+               alarm registers; there is no standard for the position
+               of individual bits.
+               Bits are defined in kernel/include/sensors.h.
+
+beep_enable    Beep/interrupt enable
+               0 to disable.
+               1 to enable.
+               Read/Write
+
+beep_mask      Bitmask for beep.
+               Same format as 'alarms' with the same bit locations.
+               Read/Write
+
+eeprom         Raw EEPROM data in binary form.
+               Read only.
diff -urN linux/Documentation/hwmon/userspace-tools 
linux/Documentation/hwmon/userspace-tools
--- linux/Documentation/hwmon/userspace-tools   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/userspace-tools   2005-07-13 12:48:47.552480000 
+0100     1.1
@@ -0,0 +1,39 @@
+Introduction
+------------
+
+Most mainboards have sensor chips to monitor system health (like temperatures,
+voltages, fans speed). They are often connected through an I2C bus, but some
+are also connected directly through the ISA bus.
+
+The kernel drivers make the data from the sensor chips available in the /sys
+virtual filesystem. Userspace tools are then used to display or set or the
+data in a more friendly manner.
+
+Lm-sensors
+----------
+
+Core set of utilites that will allow you to obtain health information,
+setup monitoring limits etc. You can get them on their homepage
+http://www.lm-sensors.nu/ or as a package from your Linux distribution.
+
+If from website:
+Get lmsensors from project web site. Please note, you need only userspace
+part, so compile with "make user_install" target.
+
+General hints to get things working:
+
+0) get lm-sensors userspace utils
+1) compile all drivers in I2C section as modules in your kernel
+2) run sensors-detect script, it will tell you what modules you need to load.
+3) load them and run "sensors" command, you should see some results.
+4) fix sensors.conf, labels, limits, fan divisors
+5) if any more problems consult FAQ, or documentation
+
+Other utilites
+--------------
+
+If you want some graphical indicators of system health look for applications
+like: gkrellm, ksensors, xsensors, wmtemp, wmsensors, wmgtemp, ksysguardd,
+hardware-monitor
+
+If you are server administrator you can try snmpd or mrtgutils.
diff -urN linux/Documentation/hwmon/via686a linux/Documentation/hwmon/via686a
--- linux/Documentation/hwmon/via686a   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/via686a   2005-07-13 12:48:47.567491000 +0100     
1.1
@@ -0,0 +1,65 @@
+Kernel driver via686a
+=====================
+
+Supported chips:
+  * Via VT82C686A, VT82C686B  Southbridge Integrated Hardware Monitor
+    Prefix: 'via686a'
+    Addresses scanned: ISA in PCI-space encoded address
+    Datasheet: On request through web form 
(http://www.via.com.tw/en/support/datasheets/)
+
+Authors:
+        Kyösti Mälkki <kmalkki@cc.hut.fi>,
+        Mark D. Studebaker <mdsxyz123@yahoo.com>
+        Bob Dougherty <bobd@stanford.edu>
+        (Some conversion-factor data were contributed by
+        Jonathan Teh Soon Yew <j.teh@iname.com>
+        and Alex van Kaam <darkside@chello.nl>.)
+
+Module Parameters
+-----------------
+
+force_addr=0xaddr       Set the I/O base address. Useful for Asus A7V boards
+                        that don't set the address in the BIOS. Does not do a
+                        PCI force; the via686a must still be present in lspci.
+                        Don't use this unless the driver complains that the
+                        base address is not set.
+                        Example: 'modprobe via686a force_addr=0x6000'
+
+Description
+-----------
+
+The driver does not distinguish between the chips and reports
+all as a 686A.
+
+The Via 686a southbridge has integrated hardware monitor functionality.
+It also has an I2C bus, but this driver only supports the hardware monitor.
+For the I2C bus driver, see <file:Documentation/i2c/busses/i2c-viapro>
+
+The Via 686a implements three temperature sensors, two fan rotation speed
+sensors, five voltage sensors and alarms.
+
+Temperatures are measured in degrees Celsius. An alarm is triggered once
+when the Overtemperature Shutdown limit is crossed; it is triggered again
+as soon as it drops below the hysteresis value.
+
+Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
+triggered if the rotation speed has dropped below a programmable limit. Fan
+readings can be divided by a programmable divider (1, 2, 4 or 8) to give
+the readings more range or accuracy. Not all RPM values can accurately be
+represented, so some rounding is done. With a divider of 2, the lowest
+representable value is around 2600 RPM.
+
+Voltage sensors (also known as IN sensors) report their values in volts.
+An alarm is triggered if the voltage has crossed a programmable minimum
+or maximum limit. Voltages are internally scalled, so each voltage channel
+has a different resolution and range.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may
+already have disappeared! Note that in the current implementation, all
+hardware registers are read whenever any data is read (unless it is less
+than 1.5 seconds since the last update). This means that you can easily
+miss once-only alarms.
+
+The driver only updates its values each 1.5 seconds; reading it more often
+will do no harm, but will return 'old' values.
diff -urN linux/Documentation/hwmon/w83627hf linux/Documentation/hwmon/w83627hf
--- linux/Documentation/hwmon/w83627hf  1970/01/01 00:00:00
+++ linux/Documentation/hwmon/w83627hf  2005-07-13 12:48:47.597068000 +0100     
1.1
@@ -0,0 +1,66 @@
+Kernel driver w83627hf
+======================
+
+Supported chips:
+  * Winbond W83627HF (ISA accesses ONLY)
+    Prefix: 'w83627hf'
+    Addresses scanned: ISA address retrieved from Super I/O registers
+    Datasheet: http://www.winbond.com/PDF/sheet/w83627hf.pdf
+  * Winbond W83627THF
+    Prefix: 'w83627thf'
+    Addresses scanned: ISA address retrieved from Super I/O registers
+    Datasheet: http://www.winbond.com/PDF/sheet/w83627thf.pdf
+  * Winbond W83697HF
+    Prefix: 'w83697hf'
+    Addresses scanned: ISA address retrieved from Super I/O registers
+    Datasheet: http://www.winbond.com/PDF/sheet/697hf.pdf
+  * Winbond W83637HF
+    Prefix: 'w83637hf'
+    Addresses scanned: ISA address retrieved from Super I/O registers
+    Datasheet: http://www.winbond.com/PDF/sheet/w83637hf.pdf
+
+Authors:
+        Frodo Looijaard <frodol@dds.nl>,
+        Philip Edelbrock <phil@netroedge.com>,
+        Mark Studebaker <mdsxyz123@yahoo.com>,
+        Bernhard C. Schrenk <clemy@clemy.org>
+
+Module Parameters
+-----------------
+
+* force_addr: int
+  Initialize the ISA address of the sensors
+* force_i2c: int
+  Initialize the I2C address of the sensors
+* init: int
+  (default is 1)
+  Use 'init=0' to bypass initializing the chip.
+  Try this if your computer crashes when you load the module.
+
+Description
+-----------
+
+This driver implements support for ISA accesses *only* for
+the Winbond W83627HF, W83627THF, W83697HF and W83637HF Super I/O chips.
+We will refer to them collectively as Winbond chips.
+
+This driver supports ISA accesses, which should be more reliable
+than i2c accesses. Also, for Tyan boards which contain both a
+Super I/O chip and a second i2c-only Winbond chip (often a W83782D),
+using this driver will avoid i2c address conflicts and complex
+initialization that were required in the w83781d driver.
+
+If you really want i2c accesses for these Super I/O chips,
+use the w83781d driver. However this is not the preferred method
+now that this ISA driver has been developed.
+
+Technically, the w83627thf does not support a VID reading. However, it's
+possible or even likely that your mainboard maker has routed these signals
+to a specific set of general purpose IO pins (the Asus P4C800-E is one such
+board). The w83627thf driver now interprets these as VID. If the VID on
+your board doesn't work, first see doc/vid in the lm_sensors package. If
+that still doesn't help, email us at lm-sensors@lm-sensors.org.
+
+For further information on this driver see the w83781d driver
+documentation.
+
diff -urN linux/Documentation/hwmon/w83781d linux/Documentation/hwmon/w83781d
--- linux/Documentation/hwmon/w83781d   1970/01/01 00:00:00
+++ linux/Documentation/hwmon/w83781d   2005-07-13 12:48:47.618636000 +0100     
1.1
@@ -0,0 +1,402 @@
+Kernel driver w83781d
+=====================
+
+Supported chips:
+  * Winbond W83781D
+    Prefix: 'w83781d'
+    Addresses scanned: I2C 0x20 - 0x2f, ISA 0x290 (8 I/O ports)
+    Datasheet: 
http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83781d.pdf
+  * Winbond W83782D
+    Prefix: 'w83782d'
+    Addresses scanned: I2C 0x20 - 0x2f, ISA 0x290 (8 I/O ports)
+    Datasheet: http://www.winbond.com/PDF/sheet/w83782d.pdf
+  * Winbond W83783S
+    Prefix: 'w83783s'
+    Addresses scanned: I2C 0x2d
+    Datasheet: 
http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83783s.pdf
+  * Winbond W83627HF
+    Prefix: 'w83627hf'
+    Addresses scanned: I2C 0x20 - 0x2f, ISA 0x290 (8 I/O ports)
+    Datasheet: http://www.winbond.com/PDF/sheet/w83627hf.pdf
+  * Asus AS99127F
+    Prefix: 'as99127f'
+    Addresses scanned: I2C 0x28 - 0x2f
+    Datasheet: Unavailable from Asus
+
+Authors:
+        Frodo Looijaard <frodol@dds.nl>,
+        Philip Edelbrock <phil@netroedge.com>,
+        Mark Studebaker <mdsxyz123@yahoo.com>
+
+Module parameters
+-----------------
+
+* init int
+  (default 1)
+  Use 'init=0' to bypass initializing the chip.
+  Try this if your computer crashes when you load the module.
+
+force_subclients=bus,caddr,saddr,saddr
+  This is used to force the i2c addresses for subclients of
+  a certain chip. Typical usage is `force_subclients=0,0x2d,0x4a,0x4b'
+  to force the subclients of chip 0x2d on bus 0 to i2c addresses
+  0x4a and 0x4b. This parameter is useful for certain Tyan boards.
+
+Description
+-----------
+
+This driver implements support for the Winbond W83781D, W83782D, W83783S,
+W83627HF chips, and the Asus AS99127F chips. We will refer to them
+collectively as W8378* chips.
+
+There is quite some difference between these chips, but they are similar
+enough that it was sensible to put them together in one driver.
+The W83627HF chip is assumed to be identical to the ISA W83782D.
+The Asus chips are similar to an I2C-only W83782D.
+
+Chip        #vin    #fanin  #pwm    #temp   wchipid vendid  i2c     ISA
+as99127f    7       3       0       3       0x31    0x12c3  yes     no
+as99127f rev.2 (type_name = as99127f)       0x31    0x5ca3  yes     no
+w83781d     7       3       0       3       0x10-1  0x5ca3  yes     yes
+w83627hf    9       3       2       3       0x21    0x5ca3  yes     yes(LPC)
+w83782d     9       3       2-4     3       0x30    0x5ca3  yes     yes
+w83783s     5-6     3       2       1-2     0x40    0x5ca3  yes     no
+
+Detection of these chips can sometimes be foiled because they can be in
+an internal state that allows no clean access. If you know the address
+of the chip, use a 'force' parameter; this will put them into a more
+well-behaved state first.
+
+The W8378* implements temperature sensors (three on the W83781D and W83782D,
+two on the W83783S), three fan rotation speed sensors, voltage sensors
+(seven on the W83781D, nine on the W83782D and six on the W83783S), VID
+lines, alarms with beep warnings, and some miscellaneous stuff.
+
+Temperatures are measured in degrees Celsius. There is always one main
+temperature sensor, and one (W83783S) or two (W83781D and W83782D) other
+sensors. An alarm is triggered for the main sensor once when the
+Overtemperature Shutdown limit is crossed; it is triggered again as soon as
+it drops below the Hysteresis value. A more useful behavior
+can be found by setting the Hysteresis value to +127 degrees Celsius; in
+this case, alarms are issued during all the time when the actual temperature
+is above the Overtemperature Shutdown value. The driver sets the
+hysteresis value for temp1 to 127 at initialization.
+
+For the other temperature sensor(s), an alarm is triggered when the
+temperature gets higher then the Overtemperature Shutdown value; it stays
+on until the temperature falls below the Hysteresis value. But on the
+W83781D, there is only one alarm that functions for both other sensors!
+Temperatures are guaranteed within a range of -55 to +125 degrees. The
+main temperature sensors has a resolution of 1 degree; the other sensor(s)
+of 0.5 degree.
+
+Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
+triggered if the rotation speed has dropped below a programmable limit. Fan
+readings can be divided by a programmable divider (1, 2, 4 or 8 for the
+W83781D; 1, 2, 4, 8, 16, 32, 64 or 128 for the others) to give
+the readings more range or accuracy. Not all RPM values can accurately
+be represented, so some rounding is done. With a divider of 2, the lowest
+representable value is around 2600 RPM.
+
+Voltage sensors (also known as IN sensors) report their values in volts.
+An alarm is triggered if the voltage has crossed a programmable minimum
+or maximum limit. Note that minimum in this case always means 'closest to
+zero'; this is important for negative voltage measurements. All voltage
+inputs can measure voltages between 0 and 4.08 volts, with a resolution
+of 0.016 volt.
+
+The VID lines encode the core voltage value: the voltage level your processor
+should work with. This is hardcoded by the mainboard and/or processor itself.
+It is a value in volts. When it is unconnected, you will often find the
+value 3.50 V here.
+
+The W83782D and W83783S temperature conversion machine understands about
+several kinds of temperature probes. You can program the so-called
+beta value in the sensor files. '1' is the PII/Celeron diode, '2' is the
+TN3904 transistor, and 3435 the default thermistor value. Other values
+are (not yet) supported.
+
+In addition to the alarms described above, there is a CHAS alarm on the
+chips which triggers if your computer case is open.
+
+When an alarm goes off, you can be warned by a beeping signal through
+your computer speaker. It is possible to enable all beeping globally,
+or only the beeping for some alarms.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may
+already have disappeared! Note that in the current implementation, all
+hardware registers are read whenever any data is read (unless it is less
+than 1.5 seconds since the last update). This means that you can easily
+miss once-only alarms.
+
+The chips only update values each 1.5 seconds; reading them more often
+will do no harm, but will return 'old' values.
+
+AS99127F PROBLEMS
+-----------------
+The as99127f support was developed without the benefit of a datasheet.
+In most cases it is treated as a w83781d (although revision 2 of the
+AS99127F looks more like a w83782d).
+This support will be BETA until a datasheet is released.
+One user has reported problems with fans stopping
+occasionally.
+
+Note that the individual beep bits are inverted from the other chips.
+The driver now takes care of this so that user-space applications
+don't have to know about it.
+
+Known problems:
+       - Problems with diode/thermistor settings (supported?)
+       - One user reports fans stopping under high server load.
+       - Revision 2 seems to have 2 PWM registers but we don't know
+         how to handle them. More details below.
+
+These will not be fixed unless we get a datasheet.
+If you have problems, please lobby Asus to release a datasheet.
+Unfortunately several others have without success.
+Please do not send mail to us asking for better as99127f support.
+We have done the best we can without a datasheet.
+Please do not send mail to the author or the sensors group asking for
+a datasheet or ideas on how to convince Asus. We can't help.
+
+
+NOTES:
+-----
+  783s has no in1 so that in[2-6] are compatible with the 781d/782d.
+
+  783s pin is programmable for -5V or temp1; defaults to -5V,
+       no control in driver so temp1 doesn't work.
+
+  782d and 783s datasheets differ on which is pwm1 and which is pwm2.
+       We chose to follow 782d.
+
+  782d and 783s pin is programmable for fan3 input or pwm2 output;
+       defaults to fan3 input.
+       If pwm2 is enabled (with echo 255 1 > pwm2), then
+       fan3 will report 0.
+
+  782d has pwm1-2 for ISA, pwm1-4 for i2c. (pwm3-4 share pins with
+       the ISA pins)
+
+Data sheet updates:
+------------------
+       - PWM clock registers:
+
+               000: master /  512
+               001: master / 1024
+               010: master / 2048
+               011: master / 4096
+               100: master / 8192
+
+
+Answers from Winbond tech support
+---------------------------------
+>
+> 1) In the W83781D data sheet section 7.2 last paragraph, it talks about
+>    reprogramming the R-T table if the Beta of the thermistor is not
+>    3435K. The R-T table is described briefly in section 8.20.
+>    What formulas do I use to program a new R-T table for a given Beta?
+>
+       We are sorry that the calculation for R-T table value is
+confidential. If you have another Beta value of thermistor, we can help
+to calculate the R-T table for you. But you should give us real R-T
+Table which can be gotten by thermistor vendor. Therefore we will calculate
+them and obtain 32-byte data, and you can fill the 32-byte data to the
+register in Bank0.CR51 of W83781D.
+
+
+> 2) In the W83782D data sheet, it mentions that pins 38, 39, and 40 are
+>    programmable to be either thermistor or Pentium II diode inputs.
+>    How do I program them for diode inputs? I can't find any register
+>    to program these to be diode inputs.
+ --> You may program Bank0 CR[5Dh] and CR[59h] registers.
+
+       CR[5Dh]                 bit 1(VTIN1)    bit 2(VTIN2)   bit 3(VTIN3)
+
+       thermistor                0              0              0
+       diode                     1              1              1
+
+
+(error) CR[59h]                bit 4(VTIN1)    bit 2(VTIN2)   bit 3(VTIN3)
+(right) CR[59h]                bit 4(VTIN1)    bit 5(VTIN2)   bit 6(VTIN3)
+
+       PII thermal diode         1              1              1
+       2N3904  diode             0              0              0
+
+
+Asus Clones
+-----------
+
+We have no datasheets for the Asus clones (AS99127F and ASB100 Bach).
+Here are some very useful information that were given to us by Alex Van
+Kaam about how to detect these chips, and how to read their values. He
+also gives advice for another Asus chipset, the Mozart-2 (which we
+don't support yet). Thanks Alex!
+I reworded some parts and added personal comments.
+
+# Detection:
+
+AS99127F rev.1, AS99127F rev.2 and ASB100:
+- I2C address range: 0x29 - 0x2F
+- If register 0x58 holds 0x31 then we have an Asus (either ASB100 or
+  AS99127F)
+- Which one depends on register 0x4F (manufacturer ID):
+  0x06 or 0x94: ASB100
+  0x12 or 0xC3: AS99127F rev.1
+  0x5C or 0xA3: AS99127F rev.2
+  Note that 0x5CA3 is Winbond's ID (WEC), which let us think Asus get their
+  AS99127F rev.2 direct from Winbond. The other codes mean ATT and DVC,
+  respectively. ATT could stand for Asustek something (although it would be
+  very badly chosen IMHO), I don't know what DVC could stand for. Maybe
+  these codes simply aren't meant to be decoded that way.
+
+Mozart-2:
+- I2C address: 0x77
+- If register 0x58 holds 0x56 or 0x10 then we have a Mozart-2
+- Of the Mozart there are 3 types:
+  0x58=0x56, 0x4E=0x94, 0x4F=0x36: Asus ASM58 Mozart-2
+  0x58=0x56, 0x4E=0x94, 0x4F=0x06: Asus AS2K129R Mozart-2
+  0x58=0x10, 0x4E=0x5C, 0x4F=0xA3: Asus ??? Mozart-2
+  You can handle all 3 the exact same way :)
+
+# Temperature sensors:
+
+ASB100:
+- sensor 1: register 0x27
+- sensor 2 & 3 are the 2 LM75's on the SMBus
+- sensor 4: register 0x17
+Remark: I noticed that on Intel boards sensor 2 is used for the CPU
+  and 4 is ignored/stuck, on AMD boards sensor 4 is the CPU and sensor 2 is
+  either ignored or a socket temperature.
+
+AS99127F (rev.1 and 2 alike):
+- sensor 1: register 0x27
+- sensor 2 & 3 are the 2 LM75's on the SMBus
+Remark: Register 0x5b is suspected to be temperature type selector. Bit 1
+  would control temp1, bit 3 temp2 and bit 5 temp3.
+
+Mozart-2:
+- sensor 1: register 0x27
+- sensor 2: register 0x13
+
+# Fan sensors:
+
+ASB100, AS99127F (rev.1 and 2 alike):
+- 3 fans, identical to the W83781D
+
+Mozart-2:
+- 2 fans only, 1350000/RPM/div
+- fan 1: register 0x28,  divisor on register 0xA1 (bits 4-5)
+- fan 2: register 0x29,  divisor on register 0xA1 (bits 6-7)
+
+# Voltages:
+
+This is where there is a difference between AS99127F rev.1 and 2.
+Remark: The difference is similar to the difference between
+  W83781D and W83782D.
+
+ASB100:
+in0=r(0x20)*0.016
+in1=r(0x21)*0.016
+in2=r(0x22)*0.016
+in3=r(0x23)*0.016*1.68
+in4=r(0x24)*0.016*3.8
+in5=r(0x25)*(-0.016)*3.97
+in6=r(0x26)*(-0.016)*1.666
+
+AS99127F rev.1:
+in0=r(0x20)*0.016
+in1=r(0x21)*0.016
+in2=r(0x22)*0.016
+in3=r(0x23)*0.016*1.68
+in4=r(0x24)*0.016*3.8
+in5=r(0x25)*(-0.016)*3.97
+in6=r(0x26)*(-0.016)*1.503
+
+AS99127F rev.2:
+in0=r(0x20)*0.016
+in1=r(0x21)*0.016
+in2=r(0x22)*0.016
+in3=r(0x23)*0.016*1.68
+in4=r(0x24)*0.016*3.8
+in5=(r(0x25)*0.016-3.6)*5.14+3.6
+in6=(r(0x26)*0.016-3.6)*3.14+3.6
+
+Mozart-2:
+in0=r(0x20)*0.016
+in1=255
+in2=r(0x22)*0.016
+in3=r(0x23)*0.016*1.68
+in4=r(0x24)*0.016*4
+in5=255
+in6=255
+
+
+# PWM
+
+Additional info about PWM on the AS99127F (may apply to other Asus
+chips as well) by Jean Delvare as of 2004-04-09:
+
+AS99127F revision 2 seems to have two PWM registers at 0x59 and 0x5A,
+and a temperature sensor type selector at 0x5B (which basically means
+that they swapped registers 0x59 and 0x5B when you compare with Winbond
+chips).
+Revision 1 of the chip also has the temperature sensor type selector at
+0x5B, but PWM registers have no effect.
+
+We don't know exactly how the temperature sensor type selection works.
+Looks like bits 1-0 are for temp1, bits 3-2 for temp2 and bits 5-4 for
+temp3, although it is possible that only the most significant bit matters
+each time. So far, values other than 0 always broke the readings.
+
+PWM registers seem to be split in two parts: bit 7 is a mode selector,
+while the other bits seem to define a value or threshold.
+
+When bit 7 is clear, bits 6-0 seem to hold a threshold value. If the value
+is below a given limit, the fan runs at low speed. If the value is above
+the limit, the fan runs at full speed. We have no clue as to what the limit
+represents. Note that there seem to be some inertia in this mode, speed
+changes may need some time to trigger. Also, an hysteresis mechanism is
+suspected since walking through all the values increasingly and then
+decreasingly led to slightly different limits.
+
+When bit 7 is set, bits 3-0 seem to hold a threshold value, while bits 6-4
+would not be significant. If the value is below a given limit, the fan runs
+at full speed, while if it is above the limit it runs at low speed (so this
+is the contrary of the other mode, in a way). Here again, we don't know
+what the limit is supposed to represent.
+
+One remarkable thing is that the fans would only have two or three
+different speeds (transitional states left apart), not a whole range as
+you usually get with PWM.
+
+As a conclusion, you can write 0x00 or 0x8F to the PWM registers to make
+fans run at low speed, and 0x7F or 0x80 to make them run at full speed.
+
+Please contact us if you can figure out how it is supposed to work. As
+long as we don't know more, the w83781d driver doesn't handle PWM on
+AS99127F chips at all.
+
+Additional info about PWM on the AS99127F rev.1 by Hector Martin:
+
+I've been fiddling around with the (in)famous 0x59 register and
+found out the following values do work as a form of coarse pwm:
+
+0x80 - seems to turn fans off after some time(1-2 minutes)... might be
+some form of auto-fan-control based on temp? hmm (Qfan? this mobo is an
+old ASUS, it isn't marketed as Qfan. Maybe some beta pre-attemp at Qfan
+that was dropped at the BIOS)
+0x81 - off
+0x82 - slightly "on-ner" than off, but my fans do not get to move. I can
+hear the high-pitched PWM sound that motors give off at too-low-pwm.
+0x83 - now they do move. Estimate about 70% speed or so.
+0x84-0x8f - full on
+
+Changing the high nibble doesn't seem to do much except the high bit
+(0x80) must be set for PWM to work, else the current pwm doesn't seem to
+change.
+
+My mobo is an ASUS A7V266-E. This behavior is similar to what I got
+with speedfan under Windows, where 0-15% would be off, 15-2x% (can't
+remember the exact value) would be 70% and higher would be full on.
diff -urN linux/Documentation/hwmon/w83l785ts 
linux/Documentation/hwmon/w83l785ts
--- linux/Documentation/hwmon/w83l785ts 1970/01/01 00:00:00
+++ linux/Documentation/hwmon/w83l785ts 2005-07-13 12:48:47.642409000 +0100     
1.1
@@ -0,0 +1,39 @@
+Kernel driver w83l785ts
+=======================
+
+Supported chips:
+  * Winbond W83L785TS-S
+    Prefix: 'w83l785ts'
+    Addresses scanned: I2C 0x2e
+    Datasheet: Publicly available at the Winbond USA website
+               
http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/W83L785TS-S.pdf
+
+Authors:
+        Jean Delvare <khali@linux-fr.org>
+
+Description
+-----------
+
+The W83L785TS-S is a digital temperature sensor. It senses the
+temperature of a single external diode. The high limit is
+theoretically defined as 85 or 100 degrees C through a combination
+of external resistors, so the user cannot change it. Values seen so
+far suggest that the two possible limits are actually 95 and 110
+degrees C. The datasheet is rather poor and obviously inaccurate
+on several points including this one.
+
+All temperature values are given in degrees Celsius. Resolution
+is 1.0 degree. See the datasheet for details.
+
+The w83l785ts driver will not update its values more frequently than
+every other second; reading them more often will do no harm, but will
+return 'old' values.
+
+Known Issues
+------------
+
+On some systems (Asus), the BIOS is known to interfere with the driver
+and cause read errors. The driver will retry a given number of times
+(5 by default) and then give up, returning the old value (or 0 if
+there is no old value). It seems to work well enough so that you should
+not notice anything. Thanks to James Bolt for helping test this feature.
diff -urN linux/Documentation/i2c/dev-interface 
linux/Documentation/i2c/dev-interface
--- linux/Documentation/i2c/dev-interface       2004/11/15 11:49:13     1.6
+++ linux/Documentation/i2c/dev-interface       2005/07/13 11:48:47     1.7
@@ -14,9 +14,12 @@
 =========
 
 So let's say you want to access an i2c adapter from a C program. The
-first thing to do is `#include <linux/i2c.h>" and "#include <linux/i2c-dev.h>. 
-Yes, I know, you should never include kernel header files, but until glibc 
-knows about i2c, there is not much choice.
+first thing to do is "#include <linux/i2c-dev.h>". Please note that
+there are two files named "i2c-dev.h" out there, one is distributed
+with the Linux kernel and is meant to be included from kernel
+driver code, the other one is distributed with lm_sensors and is
+meant to be included from user-space programs. You obviously want
+the second one here.
 
 Now, you have to decide which adapter you want to access. You should
 inspect /sys/class/i2c-dev/ to decide this. Adapter numbers are assigned
@@ -78,7 +81,7 @@
 ==========================
 
 The following IOCTLs are defined and fully supported 
-(see also i2c-dev.h and i2c.h):
+(see also i2c-dev.h):
 
 ioctl(file,I2C_SLAVE,long addr)
   Change slave address. The address is passed in the 7 lower bits of the
@@ -97,10 +100,10 @@
 ioctl(file,I2C_FUNCS,unsigned long *funcs)
   Gets the adapter functionality and puts it in *funcs.
 
-ioctl(file,I2C_RDWR,struct i2c_ioctl_rdwr_data *msgset)
+ioctl(file,I2C_RDWR,struct i2c_rdwr_ioctl_data *msgset)
 
   Do combined read/write transaction without stop in between.
-  The argument is a pointer to a struct i2c_ioctl_rdwr_data {
+  The argument is a pointer to a struct i2c_rdwr_ioctl_data {
 
       struct i2c_msg *msgs;  /* ptr to array of simple messages */
       int nmsgs;             /* number of messages to exchange */
diff -urN linux/Documentation/i2c/writing-clients 
linux/Documentation/i2c/writing-clients
--- linux/Documentation/i2c/writing-clients     2005/07/11 20:45:53     1.12
+++ linux/Documentation/i2c/writing-clients     2005/07/13 11:48:47     1.13
@@ -27,7 +27,6 @@
 static struct i2c_driver foo_driver = {
        .owner          = THIS_MODULE,
        .name           = "Foo version 2.3 driver",
-       .id             = I2C_DRIVERID_FOO, /* from i2c-id.h, optional */
        .flags          = I2C_DF_NOTIFY,
        .attach_adapter = &foo_attach_adapter,
        .detach_client  = &foo_detach_client,
@@ -37,12 +36,6 @@
 The name can be chosen freely, and may be upto 40 characters long. Please
 use something descriptive here.
 
-If used, the id should be a unique ID. The range 0xf000 to 0xffff is
-reserved for local use, and you can use one of those until you start
-distributing the driver, at which time you should contact the i2c authors
-to get your own ID(s). Note that most of the time you don't need an ID
-at all so you can just omit it.
-
 Don't worry about the flags field; just put I2C_DF_NOTIFY into it. This
 means that your driver will be notified when new adapters are found.
 This is almost always what you want.
diff -urN linux/Documentation/i2c/sysfs-interface 
linux/Documentation/i2c/sysfs-interface
--- linux/Documentation/i2c/Attic/sysfs-interface       2005-07-13 
12:48:47.878311000 +0100     1.7
+++ linux/Documentation/i2c/Attic/sysfs-interface       1970/01/01 00:00:00+0100
@@ -1,274 +0,0 @@
-Naming and data format standards for sysfs files
-------------------------------------------------
-
-The libsensors library offers an interface to the raw sensors data
-through the sysfs interface. See libsensors documentation and source for
-more further information. As of writing this document, libsensors
-(from lm_sensors 2.8.3) is heavily chip-dependant. Adding or updating
-support for any given chip requires modifying the library's code.
-This is because libsensors was written for the procfs interface
-older kernel modules were using, which wasn't standardized enough.
-Recent versions of libsensors (from lm_sensors 2.8.2 and later) have
-support for the sysfs interface, though.
-
-The new sysfs interface was designed to be as chip-independant as
-possible.
-
-Note that motherboards vary widely in the connections to sensor chips.
-There is no standard that ensures, for example, that the second
-temperature sensor is connected to the CPU, or that the second fan is on
-the CPU. Also, some values reported by the chips need some computation
-before they make full sense. For example, most chips can only measure
-voltages between 0 and +4V. Other voltages are scaled back into that
-range using external resistors. Since the values of these resistors
-can change from motherboard to motherboard, the conversions cannot be
-hard coded into the driver and have to be done in user space.
-
-For this reason, even if we aim at a chip-independant libsensors, it will
-still require a configuration file (e.g. /etc/sensors.conf) for proper
-values conversion, labeling of inputs and hiding of unused inputs.
-
-An alternative method that some programs use is to access the sysfs
-files directly. This document briefly describes the standards that the
-drivers follow, so that an application program can scan for entries and
-access this data in a simple and consistent way. That said, such programs
-will have to implement conversion, labeling and hiding of inputs. For
-this reason, it is still not recommended to bypass the library.
-
-If you are developing a userspace application please send us feedback on
-this standard.
-
-Note that this standard isn't completely established yet, so it is subject
-to changes, even important ones. One more reason to use the library instead
-of accessing sysfs files directly.
-
-Each chip gets its own directory in the sysfs /sys/devices tree.  To
-find all sensor chips, it is easier to follow the symlinks from
-/sys/i2c/devices/
-
-All sysfs values are fixed point numbers.  To get the true value of some
-of the values, you should divide by the specified value.
-
-There is only one value per file, unlike the older /proc specification.
-The common scheme for files naming is: <type><number>_<item>. Usual
-types for sensor chips are "in" (voltage), "temp" (temperature) and
-"fan" (fan). Usual items are "input" (measured value), "max" (high
-threshold, "min" (low threshold). Numbering usually starts from 1,
-except for voltages which start from 0 (because most data sheets use
-this). A number is always used for elements that can be present more
-than once, even if there is a single element of the given type on the
-specific chip. Other files do not refer to a specific element, so
-they have a simple name, and no number.
-
-Alarms are direct indications read from the chips. The drivers do NOT
-make comparisons of readings to thresholds. This allows violations
-between readings to be caught and alarmed. The exact definition of an
-alarm (for example, whether a threshold must be met or must be exceeded
-to cause an alarm) is chip-dependent.
-
-
--------------------------------------------------------------------------
-
-************
-* Voltages *
-************
-
-in[0-8]_min    Voltage min value.
-               Unit: millivolt
-               Read/Write
-               
-in[0-8]_max    Voltage max value.
-               Unit: millivolt
-               Read/Write
-               
-in[0-8]_input  Voltage input value.
-               Unit: millivolt
-               Read only
-               Actual voltage depends on the scaling resistors on the
-               motherboard, as recommended in the chip datasheet.
-               This varies by chip and by motherboard.
-               Because of this variation, values are generally NOT scaled
-               by the chip driver, and must be done by the application.
-               However, some drivers (notably lm87 and via686a)
-               do scale, with various degrees of success.
-               These drivers will output the actual voltage.
-
-               Typical usage:
-                       in0_*   CPU #1 voltage (not scaled)
-                       in1_*   CPU #2 voltage (not scaled)
-                       in2_*   3.3V nominal (not scaled)
-                       in3_*   5.0V nominal (scaled)
-                       in4_*   12.0V nominal (scaled)
-                       in5_*   -12.0V nominal (scaled)
-                       in6_*   -5.0V nominal (scaled)
-                       in7_*   varies
-                       in8_*   varies
-
-cpu[0-1]_vid   CPU core reference voltage.
-               Unit: millivolt
-               Read only.
-               Not always correct.
-
-vrm            Voltage Regulator Module version number. 
-               Read only.
-               Two digit number, first is major version, second is
-               minor version.
-               Affects the way the driver calculates the CPU core reference
-               voltage from the vid pins.
-
-
-********
-* Fans *
-********
-
-fan[1-3]_min   Fan minimum value
-               Unit: revolution/min (RPM)
-               Read/Write.
-
-fan[1-3]_input Fan input value.
-               Unit: revolution/min (RPM)
-               Read only.
-
-fan[1-3]_div   Fan divisor.
-               Integer value in powers of two (1, 2, 4, 8, 16, 32, 64, 128).
-               Some chips only support values 1, 2, 4 and 8.
-               Note that this is actually an internal clock divisor, which
-               affects the measurable speed range, not the read value.
-
-*******
-* PWM *
-*******
-
-pwm[1-3]       Pulse width modulation fan control.
-               Integer value in the range 0 to 255
-               Read/Write
-               255 is max or 100%.
-
-pwm[1-3]_enable
-               Switch PWM on and off.
-               Not always present even if fan*_pwm is.
-               0 to turn off
-               1 to turn on in manual mode
-               2 to turn on in automatic mode
-               Read/Write
-
-pwm[1-*]_auto_channels_temp
-               Select which temperature channels affect this PWM output in
-               auto mode. Bitfield, 1 is temp1, 2 is temp2, 4 is temp3 etc...
-               Which values are possible depend on the chip used.
-
-pwm[1-*]_auto_point[1-*]_pwm
-pwm[1-*]_auto_point[1-*]_temp
-pwm[1-*]_auto_point[1-*]_temp_hyst
-               Define the PWM vs temperature curve. Number of trip points is
-               chip-dependent. Use this for chips which associate trip points
-               to PWM output channels.
-
-OR
-
-temp[1-*]_auto_point[1-*]_pwm
-temp[1-*]_auto_point[1-*]_temp
-temp[1-*]_auto_point[1-*]_temp_hyst
-               Define the PWM vs temperature curve. Number of trip points is
-               chip-dependent. Use this for chips which associate trip points
-               to temperature channels.
-
-
-****************
-* Temperatures *
-****************
-
-temp[1-3]_type Sensor type selection.
-               Integers 1, 2, 3 or thermistor Beta value (3435)
-               Read/Write.
-               1: PII/Celeron Diode
-               2: 3904 transistor
-               3: thermal diode
-               Not all types are supported by all chips
-
-temp[1-4]_max  Temperature max value.
-               Unit: millidegree Celcius
-               Read/Write value.
-
-temp[1-3]_min  Temperature min value.
-               Unit: millidegree Celcius
-               Read/Write value.
-
-temp[1-3]_max_hyst
-               Temperature hysteresis value for max limit.
-               Unit: millidegree Celcius
-               Must be reported as an absolute temperature, NOT a delta
-               from the max value.
-               Read/Write value.
-
-temp[1-4]_input Temperature input value.
-               Unit: millidegree Celcius
-               Read only value.
-
-temp[1-4]_crit Temperature critical value, typically greater than
-               corresponding temp_max values.
-               Unit: millidegree Celcius
-               Read/Write value.
-
-temp[1-2]_crit_hyst
-               Temperature hysteresis value for critical limit.
-               Unit: millidegree Celcius
-               Must be reported as an absolute temperature, NOT a delta
-               from the critical value.
-               Read/Write value.
-
-               If there are multiple temperature sensors, temp1_* is
-               generally the sensor inside the chip itself,
-               reported as "motherboard temperature".  temp2_* to
-               temp4_* are generally sensors external to the chip
-               itself, for example the thermal diode inside the CPU or
-               a thermistor nearby.
-
-
-************
-* Currents *
-************
-
-Note that no known chip provides current measurements as of writing,
-so this part is theoretical, so to say.
-
-curr[1-n]_max  Current max value
-               Unit: milliampere
-               Read/Write.
-
-curr[1-n]_min  Current min value.
-               Unit: milliampere
-               Read/Write.
-
-curr[1-n]_input        Current input value
-               Unit: milliampere
-               Read only.
-
-
-*********
-* Other *
-*********
-
-alarms         Alarm bitmask.
-               Read only.
-               Integer representation of one to four bytes.
-               A '1' bit means an alarm.
-               Chips should be programmed for 'comparator' mode so that
-               the alarm will 'come back' after you read the register
-               if it is still valid.
-               Generally a direct representation of a chip's internal
-               alarm registers; there is no standard for the position
-               of individual bits.
-               Bits are defined in kernel/include/sensors.h.
-
-beep_enable    Beep/interrupt enable
-               0 to disable.
-               1 to enable.
-               Read/Write
-
-beep_mask      Bitmask for beep.
-               Same format as 'alarms' with the same bit locations.
-               Read/Write
-
-eeprom         Raw EEPROM data in binary form.
-               Read only.
diff -urN linux/Documentation/i2c/userspace-tools 
linux/Documentation/i2c/userspace-tools
--- linux/Documentation/i2c/Attic/userspace-tools       2005-07-13 
12:48:47.907697000 +0100     1.1
+++ linux/Documentation/i2c/Attic/userspace-tools       1970/01/01 00:00:00+0100
@@ -1,39 +0,0 @@
-Introduction
-------------
-
-Most mainboards have sensor chips to monitor system health (like temperatures,
-voltages, fans speed). They are often connected through an I2C bus, but some
-are also connected directly through the ISA bus.
-
-The kernel drivers make the data from the sensor chips available in the /sys
-virtual filesystem. Userspace tools are then used to display or set or the
-data in a more friendly manner.
-
-Lm-sensors
-----------
-
-Core set of utilites that will allow you to obtain health information,
-setup monitoring limits etc. You can get them on their homepage
-http://www.lm-sensors.nu/ or as a package from your Linux distribution.
-
-If from website:
-Get lmsensors from project web site. Please note, you need only userspace
-part, so compile with "make user_install" target.
-
-General hints to get things working:
-
-0) get lm-sensors userspace utils
-1) compile all drivers in I2C section as modules in your kernel
-2) run sensors-detect script, it will tell you what modules you need to load.
-3) load them and run "sensors" command, you should see some results.
-4) fix sensors.conf, labels, limits, fan divisors
-5) if any more problems consult FAQ, or documentation
-
-Other utilites
---------------
-
-If you want some graphical indicators of system health look for applications
-like: gkrellm, ksensors, xsensors, wmtemp, wmsensors, wmgtemp, ksysguardd,
-hardware-monitor
-
-If you are server administrator you can try snmpd or mrtgutils.
diff -urN linux/Documentation/i2c/chips/max6875 
linux/Documentation/i2c/chips/max6875
--- linux/Documentation/i2c/chips/max6875       2005/07/11 20:45:54     1.1
+++ linux/Documentation/i2c/chips/max6875       2005/07/13 11:48:47     1.2
@@ -2,10 +2,10 @@
 =====================
 
 Supported chips:
-  * Maxim max6874, max6875
-    Prefixes: 'max6875'
+  * Maxim MAX6874, MAX6875
+    Prefix: 'max6875'
     Addresses scanned: 0x50, 0x52
-    Datasheets:
+    Datasheet:
         http://pdfserv.maxim-ic.com/en/ds/MAX6874-MAX6875.pdf
 
 Author: Ben Gardner <bgardner@wabtec.com>
@@ -23,14 +23,26 @@
 Description
 -----------
 
-The MAXIM max6875 is a EEPROM-programmable power-supply sequencer/supervisor.
+The Maxim MAX6875 is an EEPROM-programmable power-supply sequencer/supervisor.
 It provides timed outputs that can be used as a watchdog, if properly wired.
 It also provides 512 bytes of user EEPROM.
 
-At reset, the max6875 reads the configuration eeprom into its configuration
+At reset, the MAX6875 reads the configuration EEPROM into its configuration
 registers.  The chip then begins to operate according to the values in the
 registers.
 
+The Maxim MAX6874 is a similar, mostly compatible device, with more intputs
+and outputs:
+
+             vin     gpi    vout
+MAX6874        6       4       8
+MAX6875        4       3       5
+
+MAX6874 chips can have four different addresses (as opposed to only two for
+the MAX6875). The additional addresses (0x54 and 0x56) are not probed by
+this driver by default, but the probe module parameter can be used if
+needed.
+
 See the datasheet for details on how to program the EEPROM.
 
 
diff -urN linux/Documentation/i2c/chips/adm1021 
linux/Documentation/i2c/chips/adm1021
--- linux/Documentation/i2c/chips/Attic/adm1021 2005-07-13 12:48:48.171279000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/adm1021 1970/01/01 00:00:00+0100
@@ -1,111 +0,0 @@
-Kernel driver adm1021
-=====================
-
-Supported chips:
-  * Analog Devices ADM1021
-    Prefix: 'adm1021'
-    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
-    Datasheet: Publicly available at the Analog Devices website
-  * Analog Devices ADM1021A/ADM1023
-    Prefix: 'adm1023'
-    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
-    Datasheet: Publicly available at the Analog Devices website
-  * Genesys Logic GL523SM
-    Prefix: 'gl523sm'
-    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
-    Datasheet:
-  * Intel Xeon Processor
-    Prefix: - any other - may require 'force_adm1021' parameter
-    Addresses scanned: none
-    Datasheet: Publicly available at Intel website
-  * Maxim MAX1617
-    Prefix: 'max1617'
-    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
-    Datasheet: Publicly available at the Maxim website
-  * Maxim MAX1617A
-    Prefix: 'max1617a'
-    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
-    Datasheet: Publicly available at the Maxim website
-  * National Semiconductor LM84
-    Prefix: 'lm84'
-    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
-    Datasheet: Publicly available at the National Semiconductor website
-  * Philips NE1617
-    Prefix: 'max1617' (probably detected as a max1617)
-    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
-    Datasheet: Publicly available at the Philips website
-  * Philips NE1617A
-    Prefix: 'max1617' (probably detected as a max1617)
-    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
-    Datasheet: Publicly available at the Philips website
-  * TI THMC10
-    Prefix: 'thmc10'
-    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
-    Datasheet: Publicly available at the TI website
-  * Onsemi MC1066
-    Prefix: 'mc1066'
-    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
-    Datasheet: Publicly available at the Onsemi website
-
-
-Authors:
-        Frodo Looijaard <frodol@dds.nl>,
-        Philip Edelbrock <phil@netroedge.com>
-
-Module Parameters
------------------
-
-* read_only: int
-  Don't set any values, read only mode
-
-
-Description
------------
-
-The chips supported by this driver are very similar. The Maxim MAX1617 is
-the oldest; it has the problem that it is not very well detectable. The
-MAX1617A solves that. The ADM1021 is a straight clone of the MAX1617A.
-Ditto for the THMC10. From here on, we will refer to all these chips as
-ADM1021-clones.
-
-The ADM1021 and MAX1617A reports a die code, which is a sort of revision
-code. This can help us pinpoint problems; it is not very useful
-otherwise.
-
-ADM1021-clones implement two temperature sensors. One of them is internal,
-and measures the temperature of the chip itself; the other is external and
-is realised in the form of a transistor-like device. A special alarm
-indicates whether the remote sensor is connected.
-
-Each sensor has its own low and high limits. When they are crossed, the
-corresponding alarm is set and remains on as long as the temperature stays
-out of range. Temperatures are measured in degrees Celsius. Measurements
-are possible between -65 and +127 degrees, with a resolution of one degree.
-
-If an alarm triggers, it will remain triggered until the hardware register
-is read at least once. This means that the cause for the alarm may already
-have disappeared!
-
-This driver only updates its values each 1.5 seconds; reading it more often
-will do no harm, but will return 'old' values. It is possible to make
-ADM1021-clones do faster measurements, but there is really no good reason
-for that.
-
-Xeon support
-------------
-
-Some Xeon processors have real max1617, adm1021, or compatible chips
-within them, with two temperature sensors.
-
-Other Xeons have chips with only one sensor.
-
-If you have a Xeon, and the adm1021 module loads, and both temperatures
-appear valid, then things are good.
-
-If the adm1021 module doesn't load, you should try this:
-       modprobe adm1021 force_adm1021=BUS,ADDRESS
-       ADDRESS can only be 0x18, 0x1a, 0x29, 0x2b, 0x4c, or 0x4e.
-
-If you have dual Xeons you may have appear to have two separate
-adm1021-compatible chips, or two single-temperature sensors, at distinct
-addresses.
diff -urN linux/Documentation/i2c/chips/adm1025 
linux/Documentation/i2c/chips/adm1025
--- linux/Documentation/i2c/chips/Attic/adm1025 2005-07-13 12:48:48.190301000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/adm1025 1970/01/01 00:00:00+0100
@@ -1,51 +0,0 @@
-Kernel driver adm1025
-=====================
-
-Supported chips:
-  * Analog Devices ADM1025, ADM1025A
-    Prefix: 'adm1025'
-    Addresses scanned: I2C 0x2c - 0x2e
-    Datasheet: Publicly available at the Analog Devices website
-  * Philips NE1619
-    Prefix: 'ne1619'
-    Addresses scanned: I2C 0x2c - 0x2d
-    Datasheet: Publicly available at the Philips website
-
-The NE1619 presents some differences with the original ADM1025:
-  * Only two possible addresses (0x2c - 0x2d).
-  * No temperature offset register, but we don't use it anyway.
-  * No INT mode for pin 16. We don't play with it anyway.
-
-Authors:
-        Chen-Yuan Wu <gwu@esoft.com>,
-        Jean Delvare <khali@linux-fr.org>
-
-Description
------------
-
-(This is from Analog Devices.) The ADM1025 is a complete system hardware
-monitor for microprocessor-based systems, providing measurement and limit
-comparison of various system parameters. Five voltage measurement inputs
-are provided, for monitoring +2.5V, +3.3V, +5V and +12V power supplies and
-the processor core voltage. The ADM1025 can monitor a sixth power-supply
-voltage by measuring its own VCC. One input (two pins) is dedicated to a
-remote temperature-sensing diode and an on-chip temperature sensor allows
-ambient temperature to be monitored.
-
-One specificity of this chip is that the pin 11 can be hardwired in two
-different manners. It can act as the +12V power-supply voltage analog
-input, or as the a fifth digital entry for the VID reading (bit 4). It's
-kind of strange since both are useful, and the reason for designing the
-chip that way is obscure at least to me. The bit 5 of the configuration
-register can be used to define how the chip is hardwired. Please note that
-it is not a choice you have to make as the user. The choice was already
-made by your motherboard's maker. If the configuration bit isn't set
-properly, you'll have a wrong +12V reading or a wrong VID reading. The way
-the driver handles that is to preserve this bit through the initialization
-process, assuming that the BIOS set it up properly beforehand. If it turns
-out not to be true in some cases, we'll provide a module parameter to force
-modes.
-
-This driver also supports the ADM1025A, which differs from the ADM1025
-only in that it has "open-drain VID inputs while the ADM1025 has on-chip
-100k pull-ups on the VID inputs". It doesn't make any difference for us.
diff -urN linux/Documentation/i2c/chips/adm1026 
linux/Documentation/i2c/chips/adm1026
--- linux/Documentation/i2c/chips/Attic/adm1026 2005-07-13 12:48:48.213124000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/adm1026 1970/01/01 00:00:00+0100
@@ -1,93 +0,0 @@
-Kernel driver adm1026
-=====================
-
-Supported chips:
-  * Analog Devices ADM1026
-    Prefix: 'adm1026'
-    Addresses scanned: I2C 0x2c, 0x2d, 0x2e
-    Datasheet: Publicly available at the Analog Devices website
-               http://www.analog.com/en/prod/0,,766_825_ADM1026,00.html
-
-Authors:
-        Philip Pokorny <ppokorny@penguincomputing.com> for Penguin Computing
-        Justin Thiessen <jthiessen@penguincomputing.com>
-
-Module Parameters
------------------
-
-* gpio_input: int array (min = 1, max = 17)
-  List of GPIO pins (0-16) to program as inputs
-* gpio_output: int array (min = 1, max = 17)
-  List of GPIO pins (0-16) to program as outputs
-* gpio_inverted: int array (min = 1, max = 17)
-  List of GPIO pins (0-16) to program as inverted
-* gpio_normal: int array (min = 1, max = 17)
-  List of GPIO pins (0-16) to program as normal/non-inverted
-* gpio_fan: int array (min = 1, max = 8)
-  List of GPIO pins (0-7) to program as fan tachs
-
-
-Description
------------
-
-This driver implements support for the Analog Devices ADM1026. Analog
-Devices calls it a "complete thermal system management controller."
-
-The ADM1026 implements three (3) temperature sensors, 17 voltage sensors,
-16 general purpose digital I/O lines, eight (8) fan speed sensors (8-bit),
-an analog output and a PWM output along with limit, alarm and mask bits for
-all of the above. There is even 8k bytes of EEPROM memory on chip.
-
-Temperatures are measured in degrees Celsius. There are two external
-sensor inputs and one internal sensor. Each sensor has a high and low
-limit. If the limit is exceeded, an interrupt (#SMBALERT) can be
-generated. The interrupts can be masked. In addition, there are over-temp
-limits for each sensor. If this limit is exceeded, the #THERM output will
-be asserted. The current temperature and limits have a resolution of 1
-degree.
-
-Fan rotation speeds are reported in RPM (rotations per minute) but measured
-in counts of a 22.5kHz internal clock. Each fan has a high limit which
-corresponds to a minimum fan speed. If the limit is exceeded, an interrupt
-can be generated. Each fan can be programmed to divide the reference clock
-by 1, 2, 4 or 8. Not all RPM values can accurately be represented, so some
-rounding is done. With a divider of 8, the slowest measurable speed of a
-two pulse per revolution fan is 661 RPM.
-
-There are 17 voltage sensors. An alarm is triggered if the voltage has
-crossed a programmable minimum or maximum limit. Note that minimum in this
-case always means 'closest to zero'; this is important for negative voltage
-measurements. Several inputs have integrated attenuators so they can measure
-higher voltages directly. 3.3V, 5V, 12V, -12V and battery voltage all have
-dedicated inputs. There are several inputs scaled to 0-3V full-scale range
-for SCSI terminator power. The remaining inputs are not scaled and have
-a 0-2.5V full-scale range. A 2.5V or 1.82V reference voltage is provided
-for negative voltage measurements.
-
-If an alarm triggers, it will remain triggered until the hardware register
-is read at least once. This means that the cause for the alarm may already
-have disappeared! Note that in the current implementation, all hardware
-registers are read whenever any data is read (unless it is less than 2.0
-seconds since the last update). This means that you can easily miss
-once-only alarms.
-
-The ADM1026 measures continuously. Analog inputs are measured about 4
-times a second. Fan speed measurement time depends on fan speed and
-divisor. It can take as long as 1.5 seconds to measure all fan speeds.
-
-The ADM1026 has the ability to automatically control fan speed based on the
-temperature sensor inputs. Both the PWM output and the DAC output can be
-used to control fan speed. Usually only one of these two outputs will be
-used. Write the minimum PWM or DAC value to the appropriate control
-register. Then set the low temperature limit in the tmin values for each
-temperature sensor. The range of control is fixed at 20 °C, and the
-largest difference between current and tmin of the temperature sensors sets
-the control output. See the datasheet for several example circuits for
-controlling fan speed with the PWM and DAC outputs. The fan speed sensors
-do not have PWM compensation, so it is probably best to control the fan
-voltage from the power lead rather than on the ground lead.
-
-The datasheet shows an example application with VID signals attached to
-GPIO lines. Unfortunately, the chip may not be connected to the VID lines
-in this way. The driver assumes that the chips *is* connected this way to
-get a VID voltage.
diff -urN linux/Documentation/i2c/chips/adm1031 
linux/Documentation/i2c/chips/adm1031
--- linux/Documentation/i2c/chips/Attic/adm1031 2005-07-13 12:48:48.238348000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/adm1031 1970/01/01 00:00:00+0100
@@ -1,35 +0,0 @@
-Kernel driver adm1031
-=====================
-
-Supported chips:
-  * Analog Devices ADM1030
-    Prefix: 'adm1030'
-    Addresses scanned: I2C 0x2c to 0x2e
-    Datasheet: Publicly available at the Analog Devices website
-               http://products.analog.com/products/info.asp?product=ADM1030
-
-  * Analog Devices ADM1031
-    Prefix: 'adm1031'
-    Addresses scanned: I2C 0x2c to 0x2e
-    Datasheet: Publicly available at the Analog Devices website
-               http://products.analog.com/products/info.asp?product=ADM1031
-
-Authors:
-        Alexandre d'Alton <alex@alexdalton.org>
-        Jean Delvare <khali@linux-fr.org>
-
-Description
------------
-
-The ADM1030 and ADM1031 are digital temperature sensors and fan controllers.
-They sense their own temperature as well as the temperature of up to one
-(ADM1030) or two (ADM1031) external diodes.
-
-All temperature values are given in degrees Celsius. Resolution is 0.5
-degree for the local temperature, 0.125 degree for the remote temperatures.
-
-Each temperature channel has its own high and low limits, plus a critical
-limit.
-
-The ADM1030 monitors a single fan speed, while the ADM1031 monitors up to
-two. Each fan channel has its own low speed limit.
diff -urN linux/Documentation/i2c/chips/adm9240 
linux/Documentation/i2c/chips/adm9240
--- linux/Documentation/i2c/chips/Attic/adm9240 2005-07-13 12:48:48.262512000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/adm9240 1970/01/01 00:00:00+0100
@@ -1,177 +0,0 @@
-Kernel driver adm9240
-=====================
-
-Supported chips:
-  * Analog Devices ADM9240
-    Prefix: 'adm9240'
-    Addresses scanned: I2C 0x2c - 0x2f
-    Datasheet: Publicly available at the Analog Devices website
-    http://www.analog.com/UploadedFiles/Data_Sheets/79857778ADM9240_0.pdf
-
-  * Dallas Semiconductor DS1780
-    Prefix: 'ds1780'
-    Addresses scanned: I2C 0x2c - 0x2f
-    Datasheet: Publicly available at the Dallas Semiconductor (Maxim) website
-    http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
-
-  * National Semiconductor LM81
-    Prefix: 'lm81'
-    Addresses scanned: I2C 0x2c - 0x2f
-    Datasheet: Publicly available at the National Semiconductor website
-    http://www.national.com/ds.cgi/LM/LM81.pdf
-
-Authors:
-    Frodo Looijaard <frodol@dds.nl>,
-    Philip Edelbrock <phil@netroedge.com>,
-    Michiel Rook <michiel@grendelproject.nl>,
-    Grant Coady <gcoady@gmail.com> with guidance
-        from Jean Delvare <khali@linux-fr.org>
-
-Interface
----------
-The I2C addresses listed above assume BIOS has not changed the
-chip MSB 5-bit address. Each chip reports a unique manufacturer
-identification code as well as the chip revision/stepping level.
-
-Description
------------
-[From ADM9240] The ADM9240 is a complete system hardware monitor for
-microprocessor-based systems, providing measurement and limit comparison
-of up to four power supplies and two processor core voltages, plus
-temperature, two fan speeds and chassis intrusion. Measured values can
-be read out via an I2C-compatible serial System Management Bus, and values
-for limit comparisons can be programmed in over the same serial bus. The
-high speed successive approximation ADC allows frequent sampling of all
-analog channels to ensure a fast interrupt response to any out-of-limit
-measurement.
-
-The ADM9240, DS1780 and LM81 are register compatible, the following
-details are common to the three chips. Chip differences are described
-after this section.
-
-
-Measurements
-------------
-The measurement cycle
-
-The adm9240 driver will take a measurement reading no faster than once
-each two seconds. User-space may read sysfs interface faster than the
-measurement update rate and will receive cached data from the most
-recent measurement.
-
-ADM9240 has a very fast 320us temperature and voltage measurement cycle
-with independent fan speed measurement cycles counting alternating rising
-edges of the fan tacho inputs.
-
-DS1780 measurement cycle is about once per second including fan speed.
-
-LM81 measurement cycle is about once per 400ms including fan speed.
-The LM81 12-bit extended temperature measurement mode is not supported.
-
-Temperature
------------
-On chip temperature is reported as degrees Celsius as 9-bit signed data
-with resolution of 0.5 degrees Celsius. High and low temperature limits
-are 8-bit signed data with resolution of one degree Celsius.
-
-Temperature alarm is asserted once the temperature exceeds the high limit,
-and is cleared when the temperature falls below the temp1_max_hyst value.
-
-Fan Speed
----------
-Two fan tacho inputs are provided, the ADM9240 gates an internal 22.5kHz
-clock via a divider to an 8-bit counter. Fan speed (rpm) is calculated by:
-
-rpm = (22500 * 60) / (count * divider)
-
-Automatic fan clock divider
-
-  * User sets 0 to fan_min limit
-    - low speed alarm is disabled
-    - fan clock divider not changed
-    - auto fan clock adjuster enabled for valid fan speed reading
-
-  * User sets fan_min limit too low
-    - low speed alarm is enabled
-    - fan clock divider set to max
-    - fan_min set to register value 254 which corresponds
-      to 664 rpm on adm9240
-    - low speed alarm will be asserted if fan speed is
-      less than minimum measurable speed
-    - auto fan clock adjuster disabled
-
-  * User sets reasonable fan speed
-    - low speed alarm is enabled
-    - fan clock divider set to suit fan_min
-    - auto fan clock adjuster enabled: adjusts fan_min
-
-  * User sets unreasonably high low fan speed limit
-    - resolution of the low speed limit may be reduced
-    - alarm will be asserted
-    - auto fan clock adjuster enabled: adjusts fan_min
-
-    * fan speed may be displayed as zero until the auto fan clock divider
-      adjuster brings fan speed clock divider back into chip measurement
-      range, this will occur within a few measurement cycles.
-
-Analog Output
--------------
-An analog output provides a 0 to 1.25 volt signal intended for an external
-fan speed amplifier circuit. The analog output is set to maximum value on
-power up or reset. This doesn't do much on the test Intel SE440BX-2.
-
-Voltage Monitor
-
-Voltage (IN) measurement is internally scaled:
-
-    nr  label       nominal     maximum   resolution
-                      mV          mV         mV
-    0   +2.5V        2500        3320       13.0
-    1   Vccp1        2700        3600       14.1
-    2   +3.3V        3300        4380       17.2
-    3     +5V        5000        6640       26.0
-    4    +12V       12000       15940       62.5
-    5   Vccp2        2700        3600       14.1
-
-The reading is an unsigned 8-bit value, nominal voltage measurement is
-represented by a reading of 192, being 3/4 of the measurement range.
-
-An alarm is asserted for any voltage going below or above the set limits.
-
-The driver reports and accepts voltage limits scaled to the above table.
-
-VID Monitor
------------
-The chip has five inputs to read the 5-bit VID and reports the mV value
-based on detected CPU type.
-
-Chassis Intrusion
------------------
-An alarm is asserted when the CI pin goes active high. The ADM9240
-Datasheet has an example of an external temperature sensor driving
-this pin. On an Intel SE440BX-2 the Chassis Intrusion header is
-connected to a normally open switch.
-
-The ADM9240 provides an internal open drain on this line, and may output
-a 20 ms active low pulse to reset an external Chassis Intrusion latch.
-
-Clear the CI latch by writing value 1 to the sysfs chassis_clear file.
-
-Alarm flags reported as 16-bit word
-
-    bit     label               comment
-    ---     -------------       --------------------------
-     0      +2.5 V_Error        high or low limit exceeded
-     1      VCCP_Error          high or low limit exceeded
-     2      +3.3 V_Error        high or low limit exceeded
-     3      +5 V_Error          high or low limit exceeded
-     4      Temp_Error          temperature error
-     6      FAN1_Error          fan low limit exceeded
-     7      FAN2_Error          fan low limit exceeded
-     8      +12 V_Error         high or low limit exceeded
-     9      VCCP2_Error         high or low limit exceeded
-    12      Chassis_Error       CI pin went high
-
-Remaining bits are reserved and thus undefined. It is important to note
-that alarm bits may be cleared on read, user-space may latch alarms and
-provide the end-user with a method to clear alarm memory.
diff -urN linux/Documentation/i2c/chips/asb100 
linux/Documentation/i2c/chips/asb100
--- linux/Documentation/i2c/chips/Attic/asb100  2005-07-13 12:48:48.286137000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/asb100  1970/01/01 00:00:00+0100
@@ -1,72 +0,0 @@
-Kernel driver asb100
-====================
-
-Supported Chips:
-  * Asus ASB100 and ASB100-A "Bach"
-    Prefix: 'asb100'
-    Addresses scanned: I2C 0x2d
-    Datasheet: none released
-
-Author: Mark M. Hoffman <mhoffman@lightlink.com>
-
-Description
------------
-
-This driver implements support for the Asus ASB100 and ASB100-A "Bach".
-These are custom ASICs available only on Asus mainboards. Asus refuses to
-supply a datasheet for these chips. Thanks go to many people who helped
-investigate their hardware, including:
-
-Vitaly V. Bursov
-Alexander van Kaam (author of MBM for Windows)
-Bertrik Sikken
-
-The ASB100 implements seven voltage sensors, three fan rotation speed
-sensors, four temperature sensors, VID lines and alarms. In addition to
-these, the ASB100-A also implements a single PWM controller for fans 2 and
-3 (i.e. one setting controls both.) If you have a plain ASB100, the PWM
-controller will simply not work (or maybe it will for you... it doesn't for
-me).
-
-Temperatures are measured and reported in degrees Celsius.
-
-Fan speeds are reported in RPM (rotations per minute). An alarm is
-triggered if the rotation speed has dropped below a programmable limit.
-
-Voltage sensors (also known as IN sensors) report values in volts.
-
-The VID lines encode the core voltage value: the voltage level your
-processor should work with. This is hardcoded by the mainboard and/or
-processor itself. It is a value in volts.
-
-Alarms: (TODO question marks indicate may or may not work)
-
-0x0001 => in0 (?)
-0x0002 => in1 (?)
-0x0004 => in2
-0x0008 => in3
-0x0010 => temp1 (1)
-0x0020 => temp2
-0x0040 => fan1
-0x0080 => fan2
-0x0100 => in4
-0x0200 => in5 (?) (2)
-0x0400 => in6 (?) (2)
-0x0800 => fan3
-0x1000 => chassis switch
-0x2000 => temp3
-
-Alarm Notes:
-
-(1) This alarm will only trigger if the hysteresis value is 127C.
-I.e. it behaves the same as w83781d.
-
-(2) The min and max registers for these values appear to
-be read-only or otherwise stuck at 0x00.
-
-TODO:
-* Experiment with fan divisors > 8.
-* Experiment with temp. sensor types.
-* Are there really 13 voltage inputs? Probably not...
-* Cleanups, no doubt...
-
diff -urN linux/Documentation/i2c/chips/ds1621 
linux/Documentation/i2c/chips/ds1621
--- linux/Documentation/i2c/chips/Attic/ds1621  2005-07-13 12:48:48.310523000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/ds1621  1970/01/01 00:00:00+0100
@@ -1,108 +0,0 @@
-Kernel driver ds1621
-====================
-
-Supported chips:
-  * Dallas Semiconductor DS1621
-    Prefix: 'ds1621'
-    Addresses scanned: I2C 0x48 - 0x4f
-    Datasheet: Publicly available at the Dallas Semiconductor website
-               http://www.dalsemi.com/
-  * Dallas Semiconductor DS1625
-    Prefix: 'ds1621'
-    Addresses scanned: I2C 0x48 - 0x4f
-    Datasheet: Publicly available at the Dallas Semiconductor website
-               http://www.dalsemi.com/
-
-Authors:
-        Christian W. Zuckschwerdt <zany@triq.net>
-        valuable contributions by Jan M. Sendler <sendler@sendler.de>
-        ported to 2.6 by Aurelien Jarno <aurelien@aurel32.net>
-        with the help of Jean Delvare <khali@linux-fr.org>
-
-Module Parameters
-------------------
-
-* polarity int
-  Output's polarity: 0 = active high, 1 = active low
-
-Description
------------
-
-The DS1621 is a (one instance) digital thermometer and thermostat. It has
-both high and low temperature limits which can be user defined (i.e.
-programmed into non-volatile on-chip registers). Temperature range is -55
-degree Celsius to +125 in 0.5 increments. You may convert this into a
-Fahrenheit range of -67 to +257 degrees with 0.9 steps. If polarity
-parameter is not provided, original value is used.
-
-As for the thermostat, behavior can also be programmed using the polarity
-toggle. On the one hand ("heater"), the thermostat output of the chip,
-Tout, will trigger when the low limit temperature is met or underrun and
-stays high until the high limit is met or exceeded. On the other hand
-("cooler"), vice versa. That way "heater" equals "active low", whereas
-"conditioner" equals "active high". Please note that the DS1621 data sheet
-is somewhat misleading in this point since setting the polarity bit does
-not simply invert Tout.
-
-A second thing is that, during extensive testing, Tout showed a tolerance
-of up to +/- 0.5 degrees even when compared against precise temperature
-readings. Be sure to have a high vs. low temperature limit gap of al least
-1.0 degree Celsius to avoid Tout "bouncing", though!
-
-As for alarms, you can read the alarm status of the DS1621 via the 'alarms'
-/sys file interface. The result consists mainly of bit 6 and 5 of the
-configuration register of the chip; bit 6 (0x40 or 64) is the high alarm
-bit and bit 5 (0x20 or 32) the low one. These bits are set when the high or
-low limits are met or exceeded and are reset by the module as soon as the
-respective temperature ranges are left.
-
-The alarm registers are in no way suitable to find out about the actual
-status of Tout. They will only tell you about its history, whether or not
-any of the limits have ever been met or exceeded since last power-up or
-reset. Be aware: When testing, it showed that the status of Tout can change
-with neither of the alarms set.
-
-Temperature conversion of the DS1621 takes up to 1000ms; internal access to
-non-volatile registers may last for 10ms or below.
-
-High Accuracy Temperature Reading
----------------------------------
-
-As said before, the temperature issued via the 9-bit i2c-bus data is
-somewhat arbitrary. Internally, the temperature conversion is of a
-different kind that is explained (not so...) well in the DS1621 data sheet.
-To cut the long story short: Inside the DS1621 there are two oscillators,
-both of them biassed by a temperature coefficient.
-
-Higher resolution of the temperature reading can be achieved using the
-internal projection, which means taking account of REG_COUNT and REG_SLOPE
-(the driver manages them):
-
-Taken from Dallas Semiconductors App Note 068: 'Increasing Temperature
-Resolution on the DS1620' and App Note 105: 'High Resolution Temperature
-Measurement with Dallas Direct-to-Digital Temperature Sensors'
-
-- Read the 9-bit temperature and strip the LSB (Truncate the .5 degs)
-- The resulting value is TEMP_READ.
-- Then, read REG_COUNT.
-- And then, REG_SLOPE.
-
-      TEMP = TEMP_READ - 0.25 + ((REG_SLOPE - REG_COUNT) / REG_SLOPE)
-
-Note that this is what the DONE bit in the DS1621 configuration register is
-good for: Internally, one temperature conversion takes up to 1000ms. Before
-that conversion is complete you will not be able to read valid things out
-of REG_COUNT and REG_SLOPE. The DONE bit, as you may have guessed by now,
-tells you whether the conversion is complete ("done", in plain English) and
-thus, whether the values you read are good or not.
-
-The DS1621 has two modes of operation: "Continuous" conversion, which can
-be understood as the default stand-alone mode where the chip gets the
-temperature and controls external devices via its Tout pin or tells other
-i2c's about it if they care. The other mode is called "1SHOT", that means
-that it only figures out about the temperature when it is explicitly told
-to do so; this can be seen as power saving mode.
-
-Now if you want to read REG_COUNT and REG_SLOPE, you have to either stop
-the continuous conversions until the contents of these registers are valid,
-or, in 1SHOT mode, you have to have one conversion made.
diff -urN linux/Documentation/i2c/chips/fscher 
linux/Documentation/i2c/chips/fscher
--- linux/Documentation/i2c/chips/Attic/fscher  2005-07-13 12:48:48.332778000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/fscher  1970/01/01 00:00:00+0100
@@ -1,169 +0,0 @@
-Kernel driver fscher
-====================
-
-Supported chips:
-  * Fujitsu-Siemens Hermes chip
-    Prefix: 'fscher'
-    Addresses scanned: I2C 0x73
-
-Authors:
-        Reinhard Nissl <rnissl@gmx.de> based on work
-        from Hermann Jung <hej@odn.de>,
-        Frodo Looijaard <frodol@dds.nl>,
-        Philip Edelbrock <phil@netroedge.com>
-
-Description
------------
-
-This driver implements support for the Fujitsu-Siemens Hermes chip. It is
-described in the 'Register Set Specification BMC Hermes based Systemboard'
-from Fujitsu-Siemens.
-
-The Hermes chip implements a hardware-based system management, e.g. for
-controlling fan speed and core voltage. There is also a watchdog counter on
-the chip which can trigger an alarm and even shut the system down.
-
-The chip provides three temperature values (CPU, motherboard and
-auxiliary), three voltage values (+12V, +5V and battery) and three fans
-(power supply, CPU and auxiliary).
-
-Temperatures are measured in degrees Celsius. The resolution is 1 degree.
-
-Fan rotation speeds are reported in RPM (rotations per minute). The value
-can be divided by a programmable divider (1, 2 or 4) which is stored on
-the chip.
-
-Voltage sensors (also known as "in" sensors) report their values in volts.
-
-All values are reported as final values from the driver. There is no need
-for further calculations.
-
-
-Detailed description
---------------------
-
-Below you'll find a single line description of all the bit values. With
-this information, you're able to decode e. g. alarms, wdog, etc. To make
-use of the watchdog, you'll need to set the watchdog time and enable the
-watchdog. After that it is necessary to restart the watchdog time within
-the specified period of time, or a system reset will occur.
-
-* revision
-  READING & 0xff = 0x??: HERMES revision identification
-
-* alarms
-  READING & 0x80 = 0x80: CPU throttling active
-  READING & 0x80 = 0x00: CPU running at full speed
-
-  READING & 0x10 = 0x10: software event (see control:1)
-  READING & 0x10 = 0x00: no software event
-
-  READING & 0x08 = 0x08: watchdog event (see wdog:2)
-  READING & 0x08 = 0x00: no watchdog event
-
-  READING & 0x02 = 0x02: thermal event (see temp*:1)
-  READING & 0x02 = 0x00: no thermal event
-
-  READING & 0x01 = 0x01: fan event (see fan*:1)
-  READING & 0x01 = 0x00: no fan event
-
-  READING & 0x13 ! 0x00: ALERT LED is flashing
-
-* control
-  READING & 0x01 = 0x01: software event
-  READING & 0x01 = 0x00: no software event
-
-  WRITING & 0x01 = 0x01: set software event
-  WRITING & 0x01 = 0x00: clear software event
-
-* watchdog_control
-  READING & 0x80 = 0x80: power off on watchdog event while thermal event
-  READING & 0x80 = 0x00: watchdog power off disabled (just system reset 
enabled)
-
-  READING & 0x40 = 0x40: watchdog timebase 60 seconds (see also wdog:1)
-  READING & 0x40 = 0x00: watchdog timebase  2 seconds
-
-  READING & 0x10 = 0x10: watchdog enabled
-  READING & 0x10 = 0x00: watchdog disabled
-
-  WRITING & 0x80 = 0x80: enable "power off on watchdog event while thermal 
event"
-  WRITING & 0x80 = 0x00: disable "power off on watchdog event while thermal 
event"
-
-  WRITING & 0x40 = 0x40: set watchdog timebase to 60 seconds
-  WRITING & 0x40 = 0x00: set watchdog timebase to  2 seconds
-
-  WRITING & 0x20 = 0x20: disable watchdog
-
-  WRITING & 0x10 = 0x10: enable watchdog / restart watchdog time
-
-* watchdog_state
-  READING & 0x02 = 0x02: watchdog system reset occurred
-  READING & 0x02 = 0x00: no watchdog system reset occurred
-
-  WRITING & 0x02 = 0x02: clear watchdog event
-
-* watchdog_preset
-  READING & 0xff = 0x??: configured watch dog time in units (see wdog:3 0x40)
-
-  WRITING & 0xff = 0x??: configure watch dog time in units
-
-* in*     (0: +5V, 1: +12V, 2: onboard 3V battery)
-  READING: actual voltage value
-
-* temp*_status   (1: CPU sensor, 2: onboard sensor, 3: auxiliary sensor)
-  READING & 0x02 = 0x02: thermal event (overtemperature)
-  READING & 0x02 = 0x00: no thermal event
-
-  READING & 0x01 = 0x01: sensor is working
-  READING & 0x01 = 0x00: sensor is faulty
-
-  WRITING & 0x02 = 0x02: clear thermal event
-
-* temp*_input   (1: CPU sensor, 2: onboard sensor, 3: auxiliary sensor)
-  READING: actual temperature value
-
-* fan*_status   (1: power supply fan, 2: CPU fan, 3: auxiliary fan)
-  READING & 0x04 = 0x04: fan event (fan fault)
-  READING & 0x04 = 0x00: no fan event
-
-  WRITING & 0x04 = 0x04: clear fan event
-
-* fan*_div (1: power supply fan, 2: CPU fan, 3: auxiliary fan)
-       Divisors 2,4 and 8 are supported, both for reading and writing
-
-* fan*_pwm   (1: power supply fan, 2: CPU fan, 3: auxiliary fan)
-  READING & 0xff = 0x00: fan may be switched off
-  READING & 0xff = 0x01: fan must run at least at minimum speed (supply: 6V)
-  READING & 0xff = 0xff: fan must run at maximum speed (supply: 12V)
-  READING & 0xff = 0x??: fan must run at least at given speed (supply: 6V..12V)
-
-  WRITING & 0xff = 0x00: fan may be switched off
-  WRITING & 0xff = 0x01: fan must run at least at minimum speed (supply: 6V)
-  WRITING & 0xff = 0xff: fan must run at maximum speed (supply: 12V)
-  WRITING & 0xff = 0x??: fan must run at least at given speed (supply: 6V..12V)
-
-* fan*_input   (1: power supply fan, 2: CPU fan, 3: auxiliary fan)
-  READING: actual RPM value
-
-
-Limitations
------------
-
-* Measuring fan speed
-It seems that the chip counts "ripples" (typical fans produce 2 ripples per
-rotation while VERAX fans produce 18) in a 9-bit register. This register is
-read out every second, then the ripple prescaler (2, 4 or 8) is applied and
-the result is stored in the 8 bit output register. Due to the limitation of
-the counting register to 9 bits, it is impossible to measure a VERAX fan
-properly (even with a prescaler of 8). At its maximum speed of 3500 RPM the
-fan produces 1080 ripples per second which causes the counting register to
-overflow twice, leading to only 186 RPM.
-
-* Measuring input voltages
-in2 ("battery") reports the voltage of the onboard lithium battery and not
-+3.3V from the power supply.
-
-* Undocumented features
-Fujitsu-Siemens Computers has not documented all features of the chip so
-far. Their software, System Guard, shows that there are a still some
-features which cannot be controlled by this implementation.
diff -urN linux/Documentation/i2c/chips/gl518sm 
linux/Documentation/i2c/chips/gl518sm
--- linux/Documentation/i2c/chips/Attic/gl518sm 2005-07-13 12:48:48.355234000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/gl518sm 1970/01/01 00:00:00+0100
@@ -1,74 +0,0 @@
-Kernel driver gl518sm
-=====================
-
-Supported chips:
-  * Genesys Logic GL518SM release 0x00
-    Prefix: 'gl518sm'
-    Addresses scanned: I2C 0x2c and 0x2d
-    Datasheet: http://www.genesyslogic.com/pdf
-  * Genesys Logic GL518SM release 0x80
-    Prefix: 'gl518sm'
-    Addresses scanned: I2C 0x2c and 0x2d
-    Datasheet: http://www.genesyslogic.com/pdf
-
-Authors:
-        Frodo Looijaard <frodol@dds.nl>,
-        Kyösti Mälkki <kmalkki@cc.hut.fi>
-        Hong-Gunn Chew <hglinux@gunnet.org>
-        Jean Delvare <khali@linux-fr.org>
-
-Description
------------
-
-IMPORTANT:
-
-For the revision 0x00 chip, the in0, in1, and in2  values (+5V, +3V,
-and +12V) CANNOT be read. This is a limitation of the chip, not the driver.
-
-This driver supports the Genesys Logic GL518SM chip. There are at least
-two revision of this chip, which we call revision 0x00 and 0x80. Revision
-0x80 chips support the reading of all voltages and revision 0x00 only
-for VIN3.
-
-The GL518SM implements one temperature sensor, two fan rotation speed
-sensors, and four voltage sensors. It can report alarms through the
-computer speakers.
-
-Temperatures are measured in degrees Celsius. An alarm goes off while the
-temperature is above the over temperature limit, and has not yet dropped
-below the hysteresis limit. The alarm always reflects the current
-situation. Measurements are guaranteed between -10 degrees and +110
-degrees, with a accuracy of +/-3 degrees.
-
-Rotation speeds are reported in RPM (rotations per minute). An alarm is
-triggered if the rotation speed has dropped below a programmable limit. In
-case when you have selected to turn fan1 off, no fan1 alarm is triggered.
-
-Fan readings can be divided by a programmable divider (1, 2, 4 or 8) to
-give the readings more range or accuracy.  Not all RPM values can
-accurately be represented, so some rounding is done. With a divider
-of 2, the lowest representable value is around 1900 RPM.
-
-Voltage sensors (also known as VIN sensors) report their values in volts.
-An alarm is triggered if the voltage has crossed a programmable minimum or
-maximum limit. Note that minimum in this case always means 'closest to
-zero'; this is important for negative voltage measurements. The VDD input
-measures voltages between 0.000 and 5.865 volt, with a resolution of 0.023
-volt. The other inputs measure voltages between 0.000 and 4.845 volt, with
-a resolution of 0.019 volt. Note that revision 0x00 chips do not support
-reading the current voltage of any input except for VIN3; limit setting and
-alarms work fine, though.
-
-When an alarm is triggered, you can be warned by a beeping signal through your
-computer speaker. It is possible to enable all beeping globally, or only the
-beeping for some alarms.
-
-If an alarm triggers, it will remain triggered until the hardware register
-is read at least once (except for temperature alarms). This means that the
-cause for the alarm may already have disappeared! Note that in the current
-implementation, all hardware registers are read whenever any data is read
-(unless it is less than 1.5 seconds since the last update). This means that
-you can easily miss once-only alarms.
-
-The GL518SM only updates its values each 1.5 seconds; reading it more often
-will do no harm, but will return 'old' values.
diff -urN linux/Documentation/i2c/chips/it87 linux/Documentation/i2c/chips/it87
--- linux/Documentation/i2c/chips/Attic/it87    2005-07-13 12:48:48.378834000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/it87    1970/01/01 00:00:00+0100
@@ -1,96 +0,0 @@
-Kernel driver it87
-==================
-
-Supported chips:
-  * IT8705F
-    Prefix: 'it87'
-    Addresses scanned: from Super I/O config space, or default ISA 0x290 (8 
I/O ports)
-    Datasheet: Publicly available at the ITE website
-               http://www.ite.com.tw/
-  * IT8712F
-    Prefix: 'it8712'
-    Addresses scanned: I2C 0x28 - 0x2f
-                       from Super I/O config space, or default ISA 0x290 (8 
I/O ports)
-    Datasheet: Publicly available at the ITE website
-               http://www.ite.com.tw/
-  * SiS950   [clone of IT8705F]
-    Prefix: 'sis950'
-    Addresses scanned: from Super I/O config space, or default ISA 0x290 (8 
I/O ports)
-    Datasheet: No longer be available
-
-Author: Christophe Gauthron <chrisg@0-in.com>
-
-
-Module Parameters
------------------
-
-* update_vbat: int
-
-  0 if vbat should report power on value, 1 if vbat should be updated after
-  each read. Default is 0. On some boards the battery voltage is provided
-  by either the battery or the onboard power supply. Only the first reading
-  at power on will be the actual battery voltage (which the chip does
-  automatically). On other boards the battery voltage is always fed to
-  the chip so can be read at any time. Excessive reading may decrease
-  battery life but no information is given in the datasheet.
-
-* fix_pwm_polarity int
-
-  Force PWM polarity to active high (DANGEROUS). Some chips are
-  misconfigured by BIOS - PWM values would be inverted. This option tries
-  to fix this. Please contact your BIOS manufacturer and ask him for fix.
-
-Description
------------
-
-This driver implements support for the IT8705F, IT8712F and SiS950 chips.
-
-This driver also supports IT8712F, which adds SMBus access, and a VID
-input, used to report the Vcore voltage of the Pentium processor.
-The IT8712F additionally features VID inputs.
-
-These chips are 'Super I/O chips', supporting floppy disks, infrared ports,
-joysticks and other miscellaneous stuff. For hardware monitoring, they
-include an 'environment controller' with 3 temperature sensors, 3 fan
-rotation speed sensors, 8 voltage sensors, and associated alarms.
-
-Temperatures are measured in degrees Celsius. An alarm is triggered once
-when the Overtemperature Shutdown limit is crossed.
-
-Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
-triggered if the rotation speed has dropped below a programmable limit. Fan
-readings can be divided by a programmable divider (1, 2, 4 or 8) to give the
-readings more range or accuracy. Not all RPM values can accurately be
-represented, so some rounding is done. With a divider of 2, the lowest
-representable value is around 2600 RPM.
-
-Voltage sensors (also known as IN sensors) report their values in volts. An
-alarm is triggered if the voltage has crossed a programmable minimum or
-maximum limit. Note that minimum in this case always means 'closest to
-zero'; this is important for negative voltage measurements. All voltage
-inputs can measure voltages between 0 and 4.08 volts, with a resolution of
-0.016 volt. The battery voltage in8 does not have limit registers.
-
-The VID lines (IT8712F only) encode the core voltage value: the voltage
-level your processor should work with. This is hardcoded by the mainboard
-and/or processor itself. It is a value in volts.
-
-If an alarm triggers, it will remain triggered until the hardware register
-is read at least once. This means that the cause for the alarm may already
-have disappeared! Note that in the current implementation, all hardware
-registers are read whenever any data is read (unless it is less than 1.5
-seconds since the last update). This means that you can easily miss
-once-only alarms.
-
-The IT87xx only updates its values each 1.5 seconds; reading it more often
-will do no harm, but will return 'old' values.
-
-To change sensor N to a thermistor, 'echo 2 > tempN_type' where N is 1, 2,
-or 3. To change sensor N to a thermal diode, 'echo 3 > tempN_type'.
-Give 0 for unused sensor. Any other value is invalid. To configure this at
-startup, consult lm_sensors's /etc/sensors.conf. (2 = thermistor;
-3 = thermal diode)
-
-The fan speed control features are limited to manual PWM mode. Automatic
-"Smart Guardian" mode control handling is not implemented. However
-if you want to go for "manual mode" just write 1 to pwmN_enable.
diff -urN linux/Documentation/i2c/chips/lm63 linux/Documentation/i2c/chips/lm63
--- linux/Documentation/i2c/chips/Attic/lm63    2005-07-13 12:48:48.402441000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/lm63    1970/01/01 00:00:00+0100
@@ -1,57 +0,0 @@
-Kernel driver lm63
-==================
-
-Supported chips:
-  * National Semiconductor LM63
-    Prefix: 'lm63'
-    Addresses scanned: I2C 0x4c
-    Datasheet: Publicly available at the National Semiconductor website
-               http://www.national.com/pf/LM/LM63.html
-
-Author: Jean Delvare <khali@linux-fr.org>
-
-Thanks go to Tyan and especially Alex Buckingham for setting up a remote
-access to their S4882 test platform for this driver.
-  http://www.tyan.com/
-
-Description
------------
-
-The LM63 is a digital temperature sensor with integrated fan monitoring
-and control.
-
-The LM63 is basically an LM86 with fan speed monitoring and control
-capabilities added. It misses some of the LM86 features though:
- - No low limit for local temperature.
- - No critical limit for local temperature.
- - Critical limit for remote temperature can be changed only once. We
-   will consider that the critical limit is read-only.
-
-The datasheet isn't very clear about what the tachometer reading is.
-
-An explanation from National Semiconductor: The two lower bits of the read
-value have to be masked out. The value is still 16 bit in width.
-
-All temperature values are given in degrees Celsius. Resolution is 1.0
-degree for the local temperature, 0.125 degree for the remote temperature.
-
-The fan speed is measured using a tachometer. Contrary to most chips which
-store the value in an 8-bit register and have a selectable clock divider
-to make sure that the result will fit in the register, the LM63 uses 16-bit
-value for measuring the speed of the fan. It can measure fan speeds down to
-83 RPM, at least in theory.
-
-Note that the pin used for fan monitoring is shared with an alert out
-function. Depending on how the board designer wanted to use the chip, fan
-speed monitoring will or will not be possible. The proper chip configuration
-is left to the BIOS, and the driver will blindly trust it.
-
-A PWM output can be used to control the speed of the fan. The LM63 has two
-PWM modes: manual and automatic. Automatic mode is not fully implemented yet
-(you cannot define your custom PWM/temperature curve), and mode change isn't
-supported either.
-
-The lm63 driver will not update its values more frequently than every
-second; reading them more often will do no harm, but will return 'old'
-values.
-
diff -urN linux/Documentation/i2c/chips/lm75 linux/Documentation/i2c/chips/lm75
--- linux/Documentation/i2c/chips/Attic/lm75    2005-07-13 12:48:48.424870000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/lm75    1970/01/01 00:00:00+0100
@@ -1,65 +0,0 @@
-Kernel driver lm75
-==================
-
-Supported chips:
-  * National Semiconductor LM75
-    Prefix: 'lm75'
-    Addresses scanned: I2C 0x48 - 0x4f
-    Datasheet: Publicly available at the National Semiconductor website
-               http://www.national.com/
-  * Dallas Semiconductor DS75
-    Prefix: 'lm75'
-    Addresses scanned: I2C 0x48 - 0x4f
-    Datasheet: Publicly available at the Dallas Semiconductor website
-               http://www.maxim-ic.com/
-  * Dallas Semiconductor DS1775
-    Prefix: 'lm75'
-    Addresses scanned: I2C 0x48 - 0x4f
-    Datasheet: Publicly available at the Dallas Semiconductor website
-               http://www.maxim-ic.com/
-  * Maxim MAX6625, MAX6626
-    Prefix: 'lm75'
-    Addresses scanned: I2C 0x48 - 0x4b
-    Datasheet: Publicly available at the Maxim website
-               http://www.maxim-ic.com/
-  * Microchip (TelCom) TCN75
-    Prefix: 'lm75'
-    Addresses scanned: I2C 0x48 - 0x4f
-    Datasheet: Publicly available at the Microchip website
-               http://www.microchip.com/
-
-Author: Frodo Looijaard <frodol@dds.nl>
-
-Description
------------
-
-The LM75 implements one temperature sensor. Limits can be set through the
-Overtemperature Shutdown register and Hysteresis register. Each value can be
-set and read to half-degree accuracy.
-An alarm is issued (usually to a connected LM78) when the temperature
-gets higher then the Overtemperature Shutdown value; it stays on until
-the temperature falls below the Hysteresis value.
-All temperatures are in degrees Celsius, and are guaranteed within a
-range of -55 to +125 degrees.
-
-The LM75 only updates its values each 1.5 seconds; reading it more often
-will do no harm, but will return 'old' values.
-
-The LM75 is usually used in combination with LM78-like chips, to measure
-the temperature of the processor(s).
-
-The DS75, DS1775, MAX6625, and MAX6626 are supported as well.
-They are not distinguished from an LM75. While most of these chips
-have three additional bits of accuracy (12 vs. 9 for the LM75),
-the additional bits are not supported. Not only that, but these chips will
-not be detected if not in 9-bit precision mode (use the force parameter if
-needed).
-
-The TCN75 is supported as well, and is not distinguished from an LM75.
-
-The LM75 is essentially an industry standard; there may be other
-LM75 clones not listed here, with or without various enhancements,
-that are supported.
-
-The LM77 is not supported, contrary to what we pretended for a long time.
-Both chips are simply not compatible, value encoding differs.
diff -urN linux/Documentation/i2c/chips/lm77 linux/Documentation/i2c/chips/lm77
--- linux/Documentation/i2c/chips/Attic/lm77    2005-07-13 12:48:48.445972000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/lm77    1970/01/01 00:00:00+0100
@@ -1,22 +0,0 @@
-Kernel driver lm77
-==================
-
-Supported chips:
-  * National Semiconductor LM77
-    Prefix: 'lm77'
-    Addresses scanned: I2C 0x48 - 0x4b
-    Datasheet: Publicly available at the National Semiconductor website
-               http://www.national.com/
-
-Author: Andras BALI <drewie@freemail.hu>
-
-Description
------------
-
-The LM77 implements one temperature sensor. The temperature
-sensor incorporates a band-gap type temperature sensor,
-10-bit ADC, and a digital comparator with user-programmable upper
-and lower limit values.
-
-Limits can be set through the Overtemperature Shutdown register and
-Hysteresis register.
diff -urN linux/Documentation/i2c/chips/lm78 linux/Documentation/i2c/chips/lm78
--- linux/Documentation/i2c/chips/Attic/lm78    2005-07-13 12:48:48.467803000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/lm78    1970/01/01 00:00:00+0100
@@ -1,82 +0,0 @@
-Kernel driver lm78
-==================
-
-Supported chips:
-  * National Semiconductor LM78
-    Prefix: 'lm78'
-    Addresses scanned: I2C 0x20 - 0x2f, ISA 0x290 (8 I/O ports)
-    Datasheet: Publicly available at the National Semiconductor website
-               http://www.national.com/
-  * National Semiconductor LM78-J
-    Prefix: 'lm78-j'
-    Addresses scanned: I2C 0x20 - 0x2f, ISA 0x290 (8 I/O ports)
-    Datasheet: Publicly available at the National Semiconductor website
-               http://www.national.com/
-  * National Semiconductor LM79
-    Prefix: 'lm79'
-    Addresses scanned: I2C 0x20 - 0x2f, ISA 0x290 (8 I/O ports)
-    Datasheet: Publicly available at the National Semiconductor website
-               http://www.national.com/
-
-Author: Frodo Looijaard <frodol@dds.nl>
-
-Description
------------
-
-This driver implements support for the National Semiconductor LM78, LM78-J
-and LM79. They are described as 'Microprocessor System Hardware Monitors'.
-
-There is almost no difference between the three supported chips. Functionally,
-the LM78 and LM78-J are exactly identical. The LM79 has one more VID line,
-which is used to report the lower voltages newer Pentium processors use.
-From here on, LM7* means either of these three types.
-
-The LM7* implements one temperature sensor, three fan rotation speed sensors,
-seven voltage sensors, VID lines, alarms, and some miscellaneous stuff.
-
-Temperatures are measured in degrees Celsius. An alarm is triggered once
-when the Overtemperature Shutdown limit is crossed; it is triggered again
-as soon as it drops below the Hysteresis value. A more useful behavior
-can be found by setting the Hysteresis value to +127 degrees Celsius; in
-this case, alarms are issued during all the time when the actual temperature
-is above the Overtemperature Shutdown value. Measurements are guaranteed
-between -55 and +125 degrees, with a resolution of 1 degree.
-
-Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
-triggered if the rotation speed has dropped below a programmable limit. Fan
-readings can be divided by a programmable divider (1, 2, 4 or 8) to give
-the readings more range or accuracy. Not all RPM values can accurately be
-represented, so some rounding is done. With a divider of 2, the lowest
-representable value is around 2600 RPM.
-
-Voltage sensors (also known as IN sensors) report their values in volts.
-An alarm is triggered if the voltage has crossed a programmable minimum
-or maximum limit. Note that minimum in this case always means 'closest to
-zero'; this is important for negative voltage measurements. All voltage
-inputs can measure voltages between 0 and 4.08 volts, with a resolution
-of 0.016 volt.
-
-The VID lines encode the core voltage value: the voltage level your processor
-should work with. This is hardcoded by the mainboard and/or processor itself.
-It is a value in volts. When it is unconnected, you will often find the
-value 3.50 V here.
-
-In addition to the alarms described above, there are a couple of additional
-ones. There is a BTI alarm, which gets triggered when an external chip has
-crossed its limits. Usually, this is connected to all LM75 chips; if at
-least one crosses its limits, this bit gets set. The CHAS alarm triggers
-if your computer case is open. The FIFO alarms should never trigger; it
-indicates an internal error. The SMI_IN alarm indicates some other chip
-has triggered an SMI interrupt. As we do not use SMI interrupts at all,
-this condition usually indicates there is a problem with some other
-device.
-
-If an alarm triggers, it will remain triggered until the hardware register
-is read at least once. This means that the cause for the alarm may
-already have disappeared! Note that in the current implementation, all
-hardware registers are read whenever any data is read (unless it is less
-than 1.5 seconds since the last update). This means that you can easily
-miss once-only alarms.
-
-The LM7* only updates its values each 1.5 seconds; reading it more often
-will do no harm, but will return 'old' values.
diff -urN linux/Documentation/i2c/chips/lm80 linux/Documentation/i2c/chips/lm80
--- linux/Documentation/i2c/chips/Attic/lm80    2005-07-13 12:48:48.492980000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/lm80    1970/01/01 00:00:00+0100
@@ -1,56 +0,0 @@
-Kernel driver lm80
-==================
-
-Supported chips:
-  * National Semiconductor LM80
-    Prefix: 'lm80'
-    Addresses scanned: I2C 0x28 - 0x2f
-    Datasheet: Publicly available at the National Semiconductor website
-               http://www.national.com/
-
-Authors:
-        Frodo Looijaard <frodol@dds.nl>,
-        Philip Edelbrock <phil@netroedge.com>
-
-Description
------------
-
-This driver implements support for the National Semiconductor LM80.
-It is described as a 'Serial Interface ACPI-Compatible Microprocessor
-System Hardware Monitor'.
-
-The LM80 implements one temperature sensor, two fan rotation speed sensors,
-seven voltage sensors, alarms, and some miscellaneous stuff.
-
-Temperatures are measured in degrees Celsius. There are two sets of limits
-which operate independently. When the HOT Temperature Limit is crossed,
-this will cause an alarm that will be reasserted until the temperature
-drops below the HOT Hysteresis. The Overtemperature Shutdown (OS) limits
-should work in the same way (but this must be checked; the datasheet
-is unclear about this). Measurements are guaranteed between -55 and
-+125 degrees. The current temperature measurement has a resolution of
-0.0625 degrees; the limits have a resolution of 1 degree.
-
-Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
-triggered if the rotation speed has dropped below a programmable limit. Fan
-readings can be divided by a programmable divider (1, 2, 4 or 8) to give
-the readings more range or accuracy. Not all RPM values can accurately be
-represented, so some rounding is done. With a divider of 2, the lowest
-representable value is around 2600 RPM.
-
-Voltage sensors (also known as IN sensors) report their values in volts.
-An alarm is triggered if the voltage has crossed a programmable minimum
-or maximum limit. Note that minimum in this case always means 'closest to
-zero'; this is important for negative voltage measurements. All voltage
-inputs can measure voltages between 0 and 2.55 volts, with a resolution
-of 0.01 volt.
-
-If an alarm triggers, it will remain triggered until the hardware register
-is read at least once. This means that the cause for the alarm may
-already have disappeared! Note that in the current implementation, all
-hardware registers are read whenever any data is read (unless it is less
-than 2.0 seconds since the last update). This means that you can easily
-miss once-only alarms.
-
-The LM80 only updates its values each 1.5 seconds; reading it more often
-will do no harm, but will return 'old' values.
diff -urN linux/Documentation/i2c/chips/lm83 linux/Documentation/i2c/chips/lm83
--- linux/Documentation/i2c/chips/Attic/lm83    2005-07-13 12:48:48.514159000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/lm83    1970/01/01 00:00:00+0100
@@ -1,76 +0,0 @@
-Kernel driver lm83
-==================
-
-Supported chips:
-  * National Semiconductor LM83
-    Prefix: 'lm83'
-    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
-    Datasheet: Publicly available at the National Semiconductor website
-               http://www.national.com/pf/LM/LM83.html
-
-
-Author: Jean Delvare <khali@linux-fr.org>
-
-Description
------------
-
-The LM83 is a digital temperature sensor. It senses its own temperature as
-well as the temperature of up to three external diodes. It is compatible
-with many other devices such as the LM84 and all other ADM1021 clones.
-The main difference between the LM83 and the LM84 in that the later can
-only sense the temperature of one external diode.
-
-Using the adm1021 driver for a LM83 should work, but only two temperatures
-will be reported instead of four.
-
-The LM83 is only found on a handful of motherboards. Both a confirmed
-list and an unconfirmed list follow. If you can confirm or infirm the
-fact that any of these motherboards do actually have an LM83, please
-contact us. Note that the LM90 can easily be misdetected as a LM83.
-
-Confirmed motherboards:
-    SBS         P014
-
-Unconfirmed motherboards:
-    Gigabyte    GA-8IK1100
-    Iwill       MPX2
-    Soltek      SL-75DRV5
-
-The driver has been successfully tested by Magnus Forsström, who I'd
-like to thank here. More testers will be of course welcome.
-
-The fact that the LM83 is only scarcely used can be easily explained.
-Most motherboards come with more than just temperature sensors for
-health monitoring. They also have voltage and fan rotation speed
-sensors. This means that temperature-only chips are usually used as
-secondary chips coupled with another chip such as an IT8705F or similar
-chip, which provides more features. Since systems usually need three
-temperature sensors (motherboard, processor, power supply) and primary
-chips provide some temperature sensors, the secondary chip, if needed,
-won't have to handle more than two temperatures. Thus, ADM1021 clones
-are sufficient, and there is no need for a four temperatures sensor
-chip such as the LM83. The only case where using an LM83 would make
-sense is on SMP systems, such as the above-mentioned Iwill MPX2,
-because you want an additional temperature sensor for each additional
-CPU.
-
-On the SBS P014, this is different, since the LM83 is the only hardware
-monitoring chipset. One temperature sensor is used for the motherboard
-(actually measuring the LM83's own temperature), one is used for the
-CPU. The two other sensors must be used to measure the temperature of
-two other points of the motherboard. We suspect these points to be the
-north and south bridges, but this couldn't be confirmed.
-
-All temperature values are given in degrees Celsius. Local temperature
-is given within a range of 0 to +85 degrees. Remote temperatures are
-given within a range of 0 to +125 degrees. Resolution is 1.0 degree,
-accuracy is guaranteed to 3.0 degrees (see the datasheet for more
-details).
-
-Each sensor has its own high limit, but the critical limit is common to
-all four sensors. There is no hysteresis mechanism as found on most
-recent temperature sensors.
-
-The lm83 driver will not update its values more frequently than every
-other second; reading them more often will do no harm, but will return
-'old' values.
diff -urN linux/Documentation/i2c/chips/lm85 linux/Documentation/i2c/chips/lm85
--- linux/Documentation/i2c/chips/Attic/lm85    2005-07-13 12:48:48.535115000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/lm85    1970/01/01 00:00:00+0100
@@ -1,221 +0,0 @@
-Kernel driver lm85
-==================
-
-Supported chips:
-  * National Semiconductor LM85 (B and C versions)
-    Prefix: 'lm85'
-    Addresses scanned: I2C 0x2c, 0x2d, 0x2e
-    Datasheet: http://www.national.com/pf/LM/LM85.html
-  * Analog Devices ADM1027
-    Prefix: 'adm1027'
-    Addresses scanned: I2C 0x2c, 0x2d, 0x2e
-    Datasheet: http://www.analog.com/en/prod/0,,766_825_ADM1027,00.html
-  * Analog Devices ADT7463
-    Prefix: 'adt7463'
-    Addresses scanned: I2C 0x2c, 0x2d, 0x2e
-    Datasheet: http://www.analog.com/en/prod/0,,766_825_ADT7463,00.html
-  * SMSC EMC6D100, SMSC EMC6D101
-    Prefix: 'emc6d100'
-    Addresses scanned: I2C 0x2c, 0x2d, 0x2e
-    Datasheet: http://www.smsc.com/main/tools/discontinued/6d100.pdf
-  * SMSC EMC6D102
-    Prefix: 'emc6d102'
-    Addresses scanned: I2C 0x2c, 0x2d, 0x2e
-    Datasheet: http://www.smsc.com/main/catalog/emc6d102.html
-
-Authors:
-        Philip Pokorny <ppokorny@penguincomputing.com>,
-        Frodo Looijaard <frodol@dds.nl>,
-        Richard Barrington <rich_b_nz@clear.net.nz>,
-        Margit Schubert-While <margitsw@t-online.de>,
-        Justin Thiessen <jthiessen@penguincomputing.com>
-
-Description
------------
-
-This driver implements support for the National Semiconductor LM85 and
-compatible chips including the Analog Devices ADM1027, ADT7463 and
-SMSC EMC6D10x chips family.
-
-The LM85 uses the 2-wire interface compatible with the SMBUS 2.0
-specification. Using an analog to digital converter it measures three (3)
-temperatures and five (5) voltages. It has four (4) 16-bit counters for
-measuring fan speed. Five (5) digital inputs are provided for sampling the
-VID signals from the processor to the VRM. Lastly, there are three (3) PWM
-outputs that can be used to control fan speed.
-
-The voltage inputs have internal scaling resistors so that the following
-voltage can be measured without external resistors:
-
-  2.5V, 3.3V, 5V, 12V, and CPU core voltage (2.25V)
-
-The temperatures measured are one internal diode, and two remote diodes.
-Remote 1 is generally the CPU temperature. These inputs are designed to
-measure a thermal diode like the one in a Pentium 4 processor in a socket
-423 or socket 478 package. They can also measure temperature using a
-transistor like the 2N3904.
-
-A sophisticated control system for the PWM outputs is designed into the
-LM85 that allows fan speed to be adjusted automatically based on any of the
-three temperature sensors. Each PWM output is individually adjustable and
-programmable. Once configured, the LM85 will adjust the PWM outputs in
-response to the measured temperatures without further host intervention.
-This feature can also be disabled for manual control of the PWM's.
-
-Each of the measured inputs (voltage, temperature, fan speed) has
-corresponding high/low limit values. The LM85 will signal an ALARM if any
-measured value exceeds either limit.
-
-The LM85 samples all inputs continuously. The lm85 driver will not read
-the registers more often than once a second. Further, configuration data is
-only read once each 5 minutes. There is twice as much config data as
-measurements, so this would seem to be a worthwhile optimization.
-
-Special Features
-----------------
-
-The LM85 has four fan speed monitoring modes. The ADM1027 has only two.
-Both have special circuitry to compensate for PWM interactions with the
-TACH signal from the fans. The ADM1027 can be configured to measure the
-speed of a two wire fan, but the input conditioning circuitry is different
-for 3-wire and 2-wire mode. For this reason, the 2-wire fan modes are not
-exposed to user control. The BIOS should initialize them to the correct
-mode. If you've designed your own ADM1027, you'll have to modify the
-init_client function and add an insmod parameter to set this up.
-
-To smooth the response of fans to changes in temperature, the LM85 has an
-optional filter for smoothing temperatures. The ADM1027 has the same
-config option but uses it to rate limit the changes to fan speed instead.
-
-The ADM1027 and ADT7463 have a 10-bit ADC and can therefore measure
-temperatures with 0.25 degC resolution. They also provide an offset to the
-temperature readings that is automatically applied during measurement.
-This offset can be used to zero out any errors due to traces and placement.
-The documentation says that the offset is in 0.25 degC steps, but in
-initial testing of the ADM1027 it was 1.00 degC steps. Analog Devices has
-confirmed this "bug". The ADT7463 is reported to work as described in the
-documentation. The current lm85 driver does not show the offset register.
-
-The ADT7463 has a THERM asserted counter. This counter has a 22.76ms
-resolution and a range of 5.8 seconds. The driver implements a 32-bit
-accumulator of the counter value to extend the range to over a year. The
-counter will stay at it's max value until read.
-
-See the vendor datasheets for more information. There is application note
-from National (AN-1260) with some additional information about the LM85.
-The Analog Devices datasheet is very detailed and describes a procedure for
-determining an optimal configuration for the automatic PWM control.
-
-The SMSC EMC6D100 & EMC6D101 monitor external voltages, temperatures, and
-fan speeds. They use this monitoring capability to alert the system to out
-of limit conditions and can automatically control the speeds of multiple
-fans in a PC or embedded system. The EMC6D101, available in a 24-pin SSOP
-package, and the EMC6D100, available in a 28-pin SSOP package, are designed
-to be register compatible. The EMC6D100 offers all the features of the
-EMC6D101 plus additional voltage monitoring and system control features.
-Unfortunately it is not possible to distinguish between the package
-versions on register level so these additional voltage inputs may read
-zero. The EMC6D102 features addtional ADC bits thus extending precision
-of voltage and temperature channels.
-
-
-Hardware Configurations
------------------------
-
-The LM85 can be jumpered for 3 different SMBus addresses. There are
-no other hardware configuration options for the LM85.
-
-The lm85 driver detects both LM85B and LM85C revisions of the chip. See the
-datasheet for a complete description of the differences. Other than
-identifying the chip, the driver behaves no differently with regard to
-these two chips. The LM85B is recommended for new designs.
-
-The ADM1027 and ADT7463 chips have an optional SMBALERT output that can be
-used to signal the chipset in case a limit is exceeded or the temperature
-sensors fail. Individual sensor interrupts can be masked so they won't
-trigger SMBALERT. The SMBALERT output if configured replaces one of the other
-functions (PWM2 or IN0). This functionality is not implemented in current
-driver.
-
-The ADT7463 also has an optional THERM output/input which can be connected
-to the processor PROC_HOT output. If available, the autofan control
-dynamic Tmin feature can be enabled to keep the system temperature within
-spec (just?!) with the least possible fan noise.
-
-Configuration Notes
--------------------
-
-Besides standard interfaces driver adds following:
-
-* Temperatures and Zones
-
-Each temperature sensor is associated with a Zone. There are three
-sensors and therefore three zones (# 1, 2 and 3). Each zone has the following
-temperature configuration points:
-
-* temp#_auto_temp_off - temperature below which fans should be off or spinning 
very low.
-* temp#_auto_temp_min - temperature over which fans start to spin.
-* temp#_auto_temp_max - temperature when fans spin at full speed.
-* temp#_auto_temp_crit - temperature when all fans will run full speed.
-
-* PWM Control
-
-There are three PWM outputs. The LM85 datasheet suggests that the
-pwm3 output control both fan3 and fan4. Each PWM can be individually
-configured and assigned to a zone for it's control value. Each PWM can be
-configured individually according to the following options.
-
-* pwm#_auto_pwm_min - this specifies the PWM value for temp#_auto_temp_off
-                      temperature. (PWM value from 0 to 255)
-
-* pwm#_auto_pwm_freq - select base frequency of PWM output. You can select
-                       in range of 10.0 to 94.0 Hz in .1 Hz units.
-                      (Values 100 to 940).
-
-The pwm#_auto_pwm_freq can be set to one of the following 8 values. Setting the
-frequency to a value not on this list, will result in the next higher frequency
-being selected. The actual device frequency may vary slightly from this
-specification as designed by the manufacturer. Consult the datasheet for more
-details. (PWM Frequency values:  100, 150, 230, 300, 380, 470, 620, 940)
-
-* pwm#_auto_pwm_minctl - this flags selects for temp#_auto_temp_off temperature
-                         the bahaviour of fans. Write 1 to let fans spinning at
-                        pwm#_auto_pwm_min or write 0 to let them off.
-
-NOTE: It has been reported that there is a bug in the LM85 that causes the flag
-to be associated with the zones not the PWMs. This contradicts all the
-published documentation. Setting pwm#_min_ctl in this case actually affects all
-PWMs controlled by zone '#'.
-
-* PWM Controlling Zone selection
-
-* pwm#_auto_channels - controls zone that is associated with PWM
-
-Configuration choices:
-
-   Value     Meaning
-  ------  ------------------------------------------------
-      1    Controlled by Zone 1
-      2    Controlled by Zone 2
-      3    Controlled by Zone 3
-     23    Controlled by higher temp of Zone 2 or 3
-    123    Controlled by highest temp of Zone 1, 2 or 3
-      0    PWM always 0%  (off)
-     -1    PWM always 100%  (full on)
-     -2    Manual control (write to 'pwm#' to set)
-
-The National LM85's have two vendor specific configuration
-features. Tach. mode and Spinup Control. For more details on these,
-see the LM85 datasheet or Application Note AN-1260.
-
-The Analog Devices ADM1027 has several vendor specific enhancements.
-The number of pulses-per-rev of the fans can be set, Tach monitoring
-can be optimized for PWM operation, and an offset can be applied to
-the temperatures to compensate for systemic errors in the
-measurements.
-
-In addition to the ADM1027 features, the ADT7463 also has Tmin control
-and THERM asserted counts. Automatic Tmin control acts to adjust the
-Tmin value to maintain the measured temperature sensor at a specified
-temperature. There isn't much documentation on this feature in the
-ADT7463 data sheet. This is not supported by current driver.
diff -urN linux/Documentation/i2c/chips/lm87 linux/Documentation/i2c/chips/lm87
--- linux/Documentation/i2c/chips/Attic/lm87    2005-07-13 12:48:48.561639000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/lm87    1970/01/01 00:00:00+0100
@@ -1,73 +0,0 @@
-Kernel driver lm87
-==================
-
-Supported chips:
-  * National Semiconductor LM87
-    Prefix: 'lm87'
-    Addresses scanned: I2C 0x2c - 0x2f
-    Datasheet: http://www.national.com/pf/LM/LM87.html
-
-Authors:
-        Frodo Looijaard <frodol@dds.nl>,
-        Philip Edelbrock <phil@netroedge.com>,
-        Mark Studebaker <mdsxyz123@yahoo.com>,
-        Stephen Rousset <stephen.rousset@rocketlogix.com>,
-        Dan Eaton <dan.eaton@rocketlogix.com>,
-        Jean Delvare <khali@linux-fr.org>,
-        Original 2.6 port Jeff Oliver
-
-Description
------------
-
-This driver implements support for the National Semiconductor LM87.
-
-The LM87 implements up to three temperature sensors, up to two fan
-rotation speed sensors, up to seven voltage sensors, alarms, and some
-miscellaneous stuff.
-
-Temperatures are measured in degrees Celsius. Each input has a high
-and low alarm settings. A high limit produces an alarm when the value
-goes above it, and an alarm is also produced when the value goes below
-the low limit.
-
-Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
-triggered if the rotation speed has dropped below a programmable limit. Fan
-readings can be divided by a programmable divider (1, 2, 4 or 8) to give
-the readings more range or accuracy. Not all RPM values can accurately be
-represented, so some rounding is done. With a divider of 2, the lowest
-representable value is around 2600 RPM.
-
-Voltage sensors (also known as IN sensors) report their values in
-volts. An alarm is triggered if the voltage has crossed a programmable
-minimum or maximum limit. Note that minimum in this case always means
-'closest to zero'; this is important for negative voltage measurements.
-
-If an alarm triggers, it will remain triggered until the hardware register
-is read at least once. This means that the cause for the alarm may
-already have disappeared! Note that in the current implementation, all
-hardware registers are read whenever any data is read (unless it is less
-than 1.0 seconds since the last update). This means that you can easily
-miss once-only alarms.
-
-The lm87 driver only updates its values each 1.0 seconds; reading it more
-often will do no harm, but will return 'old' values.
-
-
-Hardware Configurations
------------------------
-
-The LM87 has four pins which can serve one of two possible functions,
-depending on the hardware configuration.
-
-Some functions share pins, so not all functions are available at the same
-time. Which are depends on the hardware setup. This driver assumes that
-the BIOS configured the chip correctly. In that respect, it differs from
-the original driver (from lm_sensors for Linux 2.4), which would force the
-LM87 to an arbitrary, compile-time chosen mode, regardless of the actual
-chipset wiring.
-
-For reference, here is the list of exclusive functions:
- - in0+in5 (default) or temp3
- - fan1 (default) or in6
- - fan2 (default) or in7
- - VID lines (default) or IRQ lines (not handled by this driver)
diff -urN linux/Documentation/i2c/chips/lm90 linux/Documentation/i2c/chips/lm90
--- linux/Documentation/i2c/chips/Attic/lm90    2005-07-13 12:48:48.582197000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/lm90    1970/01/01 00:00:00+0100
@@ -1,121 +0,0 @@
-Kernel driver lm90
-==================
-
-Supported chips:
-  * National Semiconductor LM90
-    Prefix: 'lm90'
-    Addresses scanned: I2C 0x4c
-    Datasheet: Publicly available at the National Semiconductor website
-               http://www.national.com/pf/LM/LM90.html
-  * National Semiconductor LM89
-    Prefix: 'lm99'
-    Addresses scanned: I2C 0x4c and 0x4d
-    Datasheet: Publicly available at the National Semiconductor website
-               http://www.national.com/pf/LM/LM89.html
-  * National Semiconductor LM99
-    Prefix: 'lm99'
-    Addresses scanned: I2C 0x4c and 0x4d
-    Datasheet: Publicly available at the National Semiconductor website
-               http://www.national.com/pf/LM/LM99.html
-  * National Semiconductor LM86
-    Prefix: 'lm86'
-    Addresses scanned: I2C 0x4c
-    Datasheet: Publicly available at the National Semiconductor website
-               http://www.national.com/pf/LM/LM86.html
-  * Analog Devices ADM1032
-    Prefix: 'adm1032'
-    Addresses scanned: I2C 0x4c
-    Datasheet: Publicly available at the Analog Devices website
-               http://products.analog.com/products/info.asp?product=ADM1032
-  * Analog Devices ADT7461
-    Prefix: 'adt7461'
-    Addresses scanned: I2C 0x4c
-    Datasheet: Publicly available at the Analog Devices website
-               http://products.analog.com/products/info.asp?product=ADT7461
-    Note: Only if in ADM1032 compatibility mode
-  * Maxim MAX6657
-    Prefix: 'max6657'
-    Addresses scanned: I2C 0x4c
-    Datasheet: Publicly available at the Maxim website
-               http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2578
-  * Maxim MAX6658
-    Prefix: 'max6657'
-    Addresses scanned: I2C 0x4c
-    Datasheet: Publicly available at the Maxim website
-               http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2578
-  * Maxim MAX6659
-    Prefix: 'max6657'
-    Addresses scanned: I2C 0x4c, 0x4d (unsupported 0x4e)
-    Datasheet: Publicly available at the Maxim website
-               http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2578
-
-
-Author: Jean Delvare <khali@linux-fr.org>
-
-
-Description
------------
-
-The LM90 is a digital temperature sensor. It senses its own temperature as
-well as the temperature of up to one external diode. It is compatible
-with many other devices such as the LM86, the LM89, the LM99, the ADM1032,
-the MAX6657, MAX6658 and the MAX6659 all of which are supported by this driver.
-Note that there is no easy way to differentiate between the last three
-variants. The extra address and features of the MAX6659 are not supported by
-this driver. Additionally, the ADT7461 is supported if found in ADM1032
-compatibility mode.
-
-The specificity of this family of chipsets over the ADM1021/LM84
-family is that it features critical limits with hysteresis, and an
-increased resolution of the remote temperature measurement.
-
-The different chipsets of the family are not strictly identical, although
-very similar. This driver doesn't handle any specific feature for now,
-but could if there ever was a need for it. For reference, here comes a
-non-exhaustive list of specific features:
-
-LM90:
-  * Filter and alert configuration register at 0xBF.
-  * ALERT is triggered by temperatures over critical limits.
-
-LM86 and LM89:
-  * Same as LM90
-  * Better external channel accuracy
-
-LM99:
-  * Same as LM89
-  * External temperature shifted by 16 degrees down
-
-ADM1032:
-  * Consecutive alert register at 0x22.
-  * Conversion averaging.
-  * Up to 64 conversions/s.
-  * ALERT is triggered by open remote sensor.
-
-ADT7461
-  * Extended temperature range (breaks compatibility)
-  * Lower resolution for remote temperature
-
-MAX6657 and MAX6658:
-  * Remote sensor type selection
-
-MAX6659
-  * Selectable address
-  * Second critical temperature limit
-  * Remote sensor type selection
-
-All temperature values are given in degrees Celsius. Resolution
-is 1.0 degree for the local temperature, 0.125 degree for the remote
-temperature.
-
-Each sensor has its own high and low limits, plus a critical limit.
-Additionally, there is a relative hysteresis value common to both critical
-values. To make life easier to user-space applications, two absolute values
-are exported, one for each channel, but these values are of course linked.
-Only the local hysteresis can be set from user-space, and the same delta
-applies to the remote hysteresis.
-
-The lm90 driver will not update its values more frequently than every
-other second; reading them more often will do no harm, but will return
-'old' values.
-
diff -urN linux/Documentation/i2c/chips/lm92 linux/Documentation/i2c/chips/lm92
--- linux/Documentation/i2c/chips/Attic/lm92    2005-07-13 12:48:48.608067000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/lm92    1970/01/01 00:00:00+0100
@@ -1,37 +0,0 @@
-Kernel driver lm92
-==================
-
-Supported chips:
-  * National Semiconductor LM92
-    Prefix: 'lm92'
-    Addresses scanned: I2C 0x48 - 0x4b
-    Datasheet: http://www.national.com/pf/LM/LM92.html
-  * National Semiconductor LM76
-    Prefix: 'lm92'
-    Addresses scanned: none, force parameter needed
-    Datasheet: http://www.national.com/pf/LM/LM76.html
-  * Maxim MAX6633/MAX6634/MAX6635
-    Prefix: 'lm92'
-    Addresses scanned: I2C 0x48 - 0x4b
-    MAX6633 with address in 0x40 - 0x47, 0x4c - 0x4f needs force parameter
-    and MAX6634 with address in 0x4c - 0x4f needs force parameter
-    Datasheet: http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3074
-
-Authors:
-        Abraham van der Merwe <abraham@2d3d.co.za>
-        Jean Delvare <khali@linux-fr.org>
-
-
-Description
------------
-
-This driver implements support for the National Semiconductor LM92
-temperature sensor.
-
-Each LM92 temperature sensor supports a single temperature sensor. There are
-alarms for high, low, and critical thresholds. There's also an hysteresis to
-control the thresholds for resetting alarms.
-
-Support was added later for the LM76 and Maxim MAX6633/MAX6634/MAX6635,
-which are mostly compatible. They have not all been tested, so you
-may need to use the force parameter.
diff -urN linux/Documentation/i2c/chips/max1619 
linux/Documentation/i2c/chips/max1619
--- linux/Documentation/i2c/chips/Attic/max1619 2005-07-13 12:48:48.631600000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/max1619 1970/01/01 00:00:00+0100
@@ -1,29 +0,0 @@
-Kernel driver max1619
-=====================
-
-Supported chips:
-  * Maxim MAX1619
-    Prefix: 'max1619'
-    Addresses scanned: I2C 0x18-0x1a, 0x29-0x2b, 0x4c-0x4e
-    Datasheet: Publicly available at the Maxim website
-               http://pdfserv.maxim-ic.com/en/ds/MAX1619.pdf
-
-Authors:
-        Alexey Fisher <fishor@mail.ru>,
-        Jean Delvare <khali@linux-fr.org>
-
-Description
------------
-
-The MAX1619 is a digital temperature sensor. It senses its own temperature as
-well as the temperature of up to one external diode.
-
-All temperature values are given in degrees Celsius. Resolution
-is 1.0 degree for the local temperature and for the remote temperature.
-
-Only the external sensor has high and low limits.
-
-The max1619 driver will not update its values more frequently than every
-other second; reading them more often will do no harm, but will return
-'old' values.
-
diff -urN linux/Documentation/i2c/chips/pc87360 
linux/Documentation/i2c/chips/pc87360
--- linux/Documentation/i2c/chips/Attic/pc87360 2005-07-13 12:48:48.653378000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/pc87360 1970/01/01 00:00:00+0100
@@ -1,189 +0,0 @@
-Kernel driver pc87360
-=====================
-
-Supported chips:
-  * National Semiconductor PC87360, PC87363, PC87364, PC87365 and PC87366
-    Prefixes: 'pc87360', 'pc87363', 'pc87364', 'pc87365', 'pc87366'
-    Addresses scanned: none, address read from Super I/O config space
-    Datasheets:
-        http://www.national.com/pf/PC/PC87360.html
-        http://www.national.com/pf/PC/PC87363.html
-        http://www.national.com/pf/PC/PC87364.html
-        http://www.national.com/pf/PC/PC87365.html
-        http://www.national.com/pf/PC/PC87366.html
-
-Authors: Jean Delvare <khali@linux-fr.org>
-
-Thanks to Sandeep Mehta, Tonko de Rooy and Daniel Ceregatti for testing.
-Thanks to Rudolf Marek for helping me investigate conversion issues.
-
-
-Module Parameters
------------------
-
-* init int
-  Chip initialization level:
-   0: None
-  *1: Forcibly enable internal voltage and temperature channels, except in9
-   2: Forcibly enable all voltage and temperature channels, except in9
-   3: Forcibly enable all voltage and temperature channels, including in9
-
-Note that this parameter has no effect for the PC87360, PC87363 and PC87364
-chips.
-
-Also note that for the PC87366, initialization levels 2 and 3 don't enable
-all temperature channels, because some of them share pins with each other,
-so they can't be used at the same time.
-
-
-Description
------------
-
-The National Semiconductor PC87360 Super I/O chip contains monitoring and
-PWM control circuitry for two fans. The PC87363 chip is similar, and the
-PC87364 chip has monitoring and PWM control for a third fan.
-
-The National Semiconductor PC87365 and PC87366 Super I/O chips are complete
-hardware monitoring chipsets, not only controlling and monitoring three fans,
-but also monitoring eleven voltage inputs and two (PC87365) or up to four
-(PC87366) temperatures.
-
-  Chip        #vin    #fan    #pwm    #temp   devid
-
-  PC87360     -       2       2       -       0xE1
-  PC87363     -       2       2       -       0xE8
-  PC87364     -       3       3       -       0xE4
-  PC87365     11      3       3       2       0xE5
-  PC87366     11      3       3       3-4     0xE9
-
-The driver assumes that no more than one chip is present, and one of the
-standard Super I/O addresses is used (0x2E/0x2F or 0x4E/0x4F)
-
-Fan Monitoring
---------------
-
-Fan rotation speeds are reported in RPM (revolutions per minute). An alarm
-is triggered if the rotation speed has dropped below a programmable limit.
-A different alarm is triggered if the fan speed is too low to be measured.
-
-Fan readings are affected by a programmable clock divider, giving the
-readings more range or accuracy. Usually, users have to learn how it works,
-but this driver implements dynamic clock divider selection, so you don't
-have to care no more.
-
-For reference, here are a few values about clock dividers:
-
-                slowest         accuracy        highest
-                measurable      around 3000     accurate
-    divider     speed (RPM)     RPM (RPM)       speed (RPM)
-         1        1882              18           6928
-         2         941              37           4898
-         4         470              74           3464
-         8         235             150           2449
-
-For the curious, here is how the values above were computed:
- * slowest measurable speed: clock/(255*divider)
- * accuracy around 3000 RPM: 3000^2/clock
- * highest accurate speed: sqrt(clock*100)
-The clock speed for the PC87360 family is 480 kHz. I arbitrarily chose 100
-RPM as the lowest acceptable accuracy.
-
-As mentioned above, you don't have to care about this no more.
-
-Note that not all RPM values can be represented, even when the best clock
-divider is selected. This is not only true for the measured speeds, but
-also for the programmable low limits, so don't be surprised if you try to
-set, say, fan1_min to 2900 and it finally reads 2909.
-
-
-Fan Control
------------
-
-PWM (pulse width modulation) values range from 0 to 255, with 0 meaning
-that the fan is stopped, and 255 meaning that the fan goes at full speed.
-
-Be extremely careful when changing PWM values. Low PWM values, even
-non-zero, can stop the fan, which may cause irreversible damage to your
-hardware if temperature increases too much. When changing PWM values, go
-step by step and keep an eye on temperatures.
-
-One user reported problems with PWM. Changing PWM values would break fan
-speed readings. No explanation nor fix could be found.
-
-
-Temperature Monitoring
-----------------------
-
-Temperatures are reported in degrees Celsius. Each temperature measured has
-associated low, high and overtemperature limits, each of which triggers an
-alarm when crossed.
-
-The first two temperature channels are external. The third one (PC87366
-only) is internal.
-
-The PC87366 has three additional temperature channels, based on
-thermistors (as opposed to thermal diodes for the first three temperature
-channels). For technical reasons, these channels are held by the VLM
-(voltage level monitor) logical device, not the TMS (temperature
-measurement) one. As a consequence, these temperatures are exported as
-voltages, and converted into temperatures in user-space.
-
-Note that these three additional channels share their pins with the
-external thermal diode channels, so you (physically) can't use them all at
-the same time. Although it should be possible to mix the two sensor types,
-the documents from National Semiconductor suggest that motherboard
-manufacturers should choose one type and stick to it. So you will more
-likely have either channels 1 to 3 (thermal diodes) or 3 to 6 (internal
-thermal diode, and thermistors).
-
-
-Voltage Monitoring
-------------------
-
-Voltages are reported relatively to a reference voltage, either internal or
-external. Some of them (in7:Vsb, in8:Vdd and in10:AVdd) are divided by two
-internally, you will have to compensate in sensors.conf. Others (in0 to in6)
-are likely to be divided externally. The meaning of each of these inputs as
-well as the values of the resistors used for division is left to the
-motherboard manufacturers, so you will have to document yourself and edit
-sensors.conf accordingly. National Semiconductor has a document with
-recommended resistor values for some voltages, but this still leaves much
-room for per motherboard specificities, unfortunately. Even worse,
-motherboard manufacturers don't seem to care about National Semiconductor's
-recommendations.
-
-Each voltage measured has associated low and high limits, each of which
-triggers an alarm when crossed.
-
-When available, VID inputs are used to provide the nominal CPU Core voltage.
-The driver will default to VRM 9.0, but this can be changed from user-space.
-The chipsets can handle two sets of VID inputs (on dual-CPU systems), but
-the driver will only export one for now. This may change later if there is
-a need.
-
-
-General Remarks
----------------
-
-If an alarm triggers, it will remain triggered until the hardware register
-is read at least once. This means that the cause for the alarm may already
-have disappeared! Note that all hardware registers are read whenever any
-data is read (unless it is less than 2 seconds since the last update, in
-which case cached values are returned instead). As a consequence, when
-a once-only alarm triggers, it may take 2 seconds for it to show, and 2
-more seconds for it to disappear.
-
-Monitoring of in9 isn't enabled at lower init levels (<3) because that
-channel measures the battery voltage (Vbat). It is a known fact that
-repeatedly sampling the battery voltage reduces its lifetime. National
-Semiconductor smartly designed their chipset so that in9 is sampled only
-once every 1024 sampling cycles (that is every 34 minutes at the default
-sampling rate), so the effect is attenuated, but still present.
-
-
-Limitations
------------
-
-The datasheets suggests that some values (fan mins, fan dividers)
-shouldn't be changed once the monitoring has started, but we ignore that
-recommendation. We'll reconsider if it actually causes trouble.
diff -urN linux/Documentation/i2c/chips/sis5595 
linux/Documentation/i2c/chips/sis5595
--- linux/Documentation/i2c/chips/Attic/sis5595 2005-07-13 12:48:48.675718000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/sis5595 1970/01/01 00:00:00+0100
@@ -1,106 +0,0 @@
-Kernel driver sis5595
-=====================
-
-Supported chips:
-  * Silicon Integrated Systems Corp. SiS5595 Southbridge Hardware Monitor
-    Prefix: 'sis5595'
-    Addresses scanned: ISA in PCI-space encoded address
-    Datasheet: Publicly available at the Silicon Integrated Systems Corp. site.
-
-Authors:
-        Kyösti Mälkki <kmalkki@cc.hut.fi>,
-        Mark D. Studebaker <mdsxyz123@yahoo.com>,
-        Aurelien Jarno <aurelien@aurel32.net> 2.6 port
-
-   SiS southbridge has a LM78-like chip integrated on the same IC.
-   This driver is a customized copy of lm78.c
-
-   Supports following revisions:
-       Version         PCI ID          PCI Revision
-       1               1039/0008       AF or less
-       2               1039/0008       B0 or greater
-
-   Note: these chips contain a 0008 device which is incompatible with the
-        5595. We recognize these by the presence of the listed
-        "blacklist" PCI ID and refuse to load.
-
-   NOT SUPPORTED       PCI ID          BLACKLIST PCI ID
-        540            0008            0540
-        550            0008            0550
-       5513            0008            5511
-       5581            0008            5597
-       5582            0008            5597
-       5597            0008            5597
-        630            0008            0630
-        645            0008            0645
-        730            0008            0730
-        735            0008            0735
-
-
-Module Parameters
------------------
-force_addr=0xaddr      Set the I/O base address. Useful for boards
-                       that don't set the address in the BIOS. Does not do a
-                       PCI force; the device must still be present in lspci.
-                       Don't use this unless the driver complains that the
-                       base address is not set.
-                       Example: 'modprobe sis5595 force_addr=0x290'
-
-
-Description
------------
-
-The SiS5595 southbridge has integrated hardware monitor functions. It also
-has an I2C bus, but this driver only supports the hardware monitor. For the
-I2C bus driver see i2c-sis5595.
-
-The SiS5595 implements zero or one temperature sensor, two fan speed
-sensors, four or five voltage sensors, and alarms.
-
-On the first version of the chip, there are four voltage sensors and one
-temperature sensor.
-
-On the second version of the chip, the temperature sensor (temp) and the
-fifth voltage sensor (in4) share a pin which is configurable, but not
-through the driver. Sorry. The driver senses the configuration of the pin,
-which was hopefully set by the BIOS.
-
-Temperatures are measured in degrees Celsius. An alarm is triggered once
-when the max is crossed; it is also triggered when it drops below the min
-value. Measurements are guaranteed between -55 and +125 degrees, with a
-resolution of 1 degree.
-
-Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
-triggered if the rotation speed has dropped below a programmable limit. Fan
-readings can be divided by a programmable divider (1, 2, 4 or 8) to give
-the readings more range or accuracy. Not all RPM values can accurately be
-represented, so some rounding is done. With a divider of 2, the lowest
-representable value is around 2600 RPM.
-
-Voltage sensors (also known as IN sensors) report their values in volts. An
-alarm is triggered if the voltage has crossed a programmable minimum or
-maximum limit. Note that minimum in this case always means 'closest to
-zero'; this is important for negative voltage measurements. All voltage
-inputs can measure voltages between 0 and 4.08 volts, with a resolution of
-0.016 volt.
-
-In addition to the alarms described above, there is a BTI alarm, which gets
-triggered when an external chip has crossed its limits. Usually, this is
-connected to some LM75-like chip; if at least one crosses its limits, this
-bit gets set.
-
-If an alarm triggers, it will remain triggered until the hardware register
-is read at least once. This means that the cause for the alarm may already
-have disappeared! Note that in the current implementation, all hardware
-registers are read whenever any data is read (unless it is less than 1.5
-seconds since the last update). This means that you can easily miss
-once-only alarms.
-
-The SiS5595 only updates its values each 1.5 seconds; reading it more often
-will do no harm, but will return 'old' values.
-
-Problems
---------
-Some chips refuse to be enabled. We don't know why.
-The driver will recognize this and print a message in dmesg.
-
diff -urN linux/Documentation/i2c/chips/smsc47b397 
linux/Documentation/i2c/chips/smsc47b397
--- linux/Documentation/i2c/chips/Attic/smsc47b397      2005-07-13 
12:48:48.696155000 +0100     1.1
+++ linux/Documentation/i2c/chips/Attic/smsc47b397      1970/01/01 00:00:00+0100
@@ -1,158 +0,0 @@
-Kernel driver smsc47b397
-========================
-
-Supported chips:
-  * SMSC LPC47B397-NC
-    Prefix: 'smsc47b397'
-    Addresses scanned: none, address read from Super I/O config space
-    Datasheet: In this file
-
-Authors: Mark M. Hoffman <mhoffman@lightlink.com>
-         Utilitek Systems, Inc.
-
-November 23, 2004
-
-The following specification describes the SMSC LPC47B397-NC sensor chip
-(for which there is no public datasheet available). This document was
-provided by Craig Kelly (In-Store Broadcast Network) and edited/corrected
-by Mark M. Hoffman <mhoffman@lightlink.com>.
-
-* * * * *
-
-Methods for detecting the HP SIO and reading the thermal data on a dc7100.
-
-The thermal information on the dc7100 is contained in the SIO Hardware Monitor
-(HWM). The information is accessed through an index/data pair. The index/data
-pair is located at the HWM Base Address + 0 and the HWM Base Address + 1. The
-HWM Base address can be obtained from Logical Device 8, registers 0x60 (MSB)
-and 0x61 (LSB). Currently we are using 0x480 for the HWM Base Address and
-0x480 and 0x481 for the index/data pair.
-
-Reading temperature information.
-The temperature information is located in the following registers:
-Temp1          0x25    (Currently, this reflects the CPU temp on all systems).
-Temp2          0x26
-Temp3          0x27
-Temp4          0x80
-
-Programming Example
-The following is an example of how to read the HWM temperature registers:
-MOV    DX,480H
-MOV    AX,25H
-OUT    DX,AL
-MOV    DX,481H
-IN     AL,DX
-
-AL contains the data in hex, the temperature in Celsius is the decimal
-equivalent.
-
-Ex: If AL contains 0x2A, the temperature is 42 degrees C.
-
-Reading tach information.
-The fan speed information is located in the following registers:
-               LSB     MSB
-Tach1          0x28    0x29    (Currently, this reflects the CPU
-                               fan speed on all systems).
-Tach2          0x2A    0x2B
-Tach3          0x2C    0x2D
-Tach4          0x2E    0x2F
-
-Important!!!
-Reading the tach LSB locks the tach MSB.
-The LSB Must be read first.
-
-How to convert the tach reading to RPM.
-The tach reading (TCount) is given by: (Tach MSB * 256) + (Tach LSB)
-The SIO counts the number of 90kHz (11.111us) pulses per revolution.
-RPM = 60/(TCount * 11.111us)
-
-Example:
-Reg 0x28 = 0x9B
-Reg 0x29 = 0x08
-
-TCount = 0x89B = 2203
-
-RPM = 60 / (2203 * 11.11111 E-6) = 2451 RPM
-
-Obtaining the SIO version.
-
-CONFIGURATION SEQUENCE
-To program the configuration registers, the following sequence must be 
followed:
-1. Enter Configuration Mode
-2. Configure the Configuration Registers
-3. Exit Configuration Mode.
-
-Enter Configuration Mode
-To place the chip into the Configuration State The config key (0x55) is written
-to the CONFIG PORT (0x2E).
-
-Configuration Mode
-In configuration mode, the INDEX PORT is located at the CONFIG PORT address and
-the DATA PORT is at INDEX PORT address + 1.
-
-The desired configuration registers are accessed in two steps:
-a.     Write the index of the Logical Device Number Configuration Register
-       (i.e., 0x07) to the INDEX PORT and then write the number of the
-       desired logical device to the DATA PORT.
-
-b.     Write the address of the desired configuration register within the
-       logical device to the INDEX PORT and then write or read the config-
-       uration register through the DATA PORT.
-
-Note: If accessing the Global Configuration Registers, step (a) is not 
required.
-
-Exit Configuration Mode
-To exit the Configuration State the write 0xAA to the CONFIG PORT (0x2E).
-The chip returns to the RUN State.  (This is important).
-
-Programming Example
-The following is an example of how to read the SIO Device ID located at 0x20
-
-; ENTER CONFIGURATION MODE
-MOV    DX,02EH
-MOV    AX,055H
-OUT    DX,AL
-; GLOBAL CONFIGURATION  REGISTER
-MOV    DX,02EH
-MOV    AL,20H
-OUT    DX,AL
-; READ THE DATA
-MOV    DX,02FH
-IN     AL,DX
-; EXIT CONFIGURATION MODE
-MOV    DX,02EH
-MOV    AX,0AAH
-OUT    DX,AL
-
-The registers of interest for identifying the SIO on the dc7100 are Device ID
-(0x20) and Device Rev  (0x21).
-
-The Device ID will read 0X6F
-The Device Rev currently reads 0x01
-
-Obtaining the HWM Base Address.
-The following is an example of how to read the HWM Base Address located in
-Logical Device 8.
-
-; ENTER CONFIGURATION MODE
-MOV    DX,02EH
-MOV    AX,055H
-OUT    DX,AL
-; CONFIGURE REGISTER CRE0,
-; LOGICAL DEVICE 8
-MOV    DX,02EH
-MOV    AL,07H
-OUT    DX,AL ;Point to LD# Config Reg
-MOV    DX,02FH
-MOV    AL, 08H
-OUT    DX,AL;Point to Logical Device 8
-;
-MOV    DX,02EH
-MOV    AL,60H
-OUT    DX,AL   ; Point to HWM Base Addr MSB
-MOV    DX,02FH
-IN     AL,DX   ; Get MSB of HWM Base Addr
-; EXIT CONFIGURATION MODE
-MOV    DX,02EH
-MOV    AX,0AAH
-OUT    DX,AL
diff -urN linux/Documentation/i2c/chips/smsc47m1 
linux/Documentation/i2c/chips/smsc47m1
--- linux/Documentation/i2c/chips/Attic/smsc47m1        2005-07-13 
12:48:48.725822000 +0100     1.1
+++ linux/Documentation/i2c/chips/Attic/smsc47m1        1970/01/01 00:00:00+0100
@@ -1,52 +0,0 @@
-Kernel driver smsc47m1
-======================
-
-Supported chips:
-  * SMSC LPC47B27x, LPC47M10x, LPC47M13x, LPC47M14x, LPC47M15x and LPC47M192
-    Addresses scanned: none, address read from Super I/O config space
-    Prefix: 'smsc47m1'
-    Datasheets:
-        http://www.smsc.com/main/datasheets/47b27x.pdf
-        http://www.smsc.com/main/datasheets/47m10x.pdf
-        http://www.smsc.com/main/tools/discontinued/47m13x.pdf
-        http://www.smsc.com/main/datasheets/47m14x.pdf
-        http://www.smsc.com/main/tools/discontinued/47m15x.pdf
-        http://www.smsc.com/main/datasheets/47m192.pdf
-
-Authors:
-        Mark D. Studebaker <mdsxyz123@yahoo.com>,
-        With assistance from Bruce Allen <ballen@uwm.edu>, and his
-        fan.c program: http://www.lsc-group.phys.uwm.edu/%7Eballen/driver/
-        Gabriele Gorla <gorlik@yahoo.com>,
-        Jean Delvare <khali@linux-fr.org>
-
-Description
------------
-
-The Standard Microsystems Corporation (SMSC) 47M1xx Super I/O chips
-contain monitoring and PWM control circuitry for two fans.
-
-The 47M15x and 47M192 chips contain a full 'hardware monitoring block'
-in addition to the fan monitoring and control. The hardware monitoring
-block is not supported by the driver.
-
-Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
-triggered if the rotation speed has dropped below a programmable limit. Fan
-readings can be divided by a programmable divider (1, 2, 4 or 8) to give
-the readings more range or accuracy. Not all RPM values can accurately be
-represented, so some rounding is done. With a divider of 2, the lowest
-representable value is around 2600 RPM.
-
-PWM values are from 0 to 255.
-
-If an alarm triggers, it will remain triggered until the hardware register
-is read at least once. This means that the cause for the alarm may
-already have disappeared! Note that in the current implementation, all
-hardware registers are read whenever any data is read (unless it is less
-than 1.5 seconds since the last update). This means that you can easily
-miss once-only alarms.
-
-
-**********************
-The lm_sensors project gratefully acknowledges the support of
-Intel in the development of this driver.
diff -urN linux/Documentation/i2c/chips/via686a 
linux/Documentation/i2c/chips/via686a
--- linux/Documentation/i2c/chips/Attic/via686a 2005-07-13 12:48:48.749840000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/via686a 1970/01/01 00:00:00+0100
@@ -1,65 +0,0 @@
-Kernel driver via686a
-=====================
-
-Supported chips:
-  * Via VT82C686A, VT82C686B  Southbridge Integrated Hardware Monitor
-    Prefix: 'via686a'
-    Addresses scanned: ISA in PCI-space encoded address
-    Datasheet: On request through web form 
(http://www.via.com.tw/en/support/datasheets/)
-
-Authors:
-        Kyösti Mälkki <kmalkki@cc.hut.fi>,
-        Mark D. Studebaker <mdsxyz123@yahoo.com>
-        Bob Dougherty <bobd@stanford.edu>
-        (Some conversion-factor data were contributed by
-        Jonathan Teh Soon Yew <j.teh@iname.com>
-        and Alex van Kaam <darkside@chello.nl>.)
-
-Module Parameters
------------------
-
-force_addr=0xaddr       Set the I/O base address. Useful for Asus A7V boards
-                        that don't set the address in the BIOS. Does not do a
-                        PCI force; the via686a must still be present in lspci.
-                        Don't use this unless the driver complains that the
-                        base address is not set.
-                        Example: 'modprobe via686a force_addr=0x6000'
-
-Description
------------
-
-The driver does not distinguish between the chips and reports
-all as a 686A.
-
-The Via 686a southbridge has integrated hardware monitor functionality.
-It also has an I2C bus, but this driver only supports the hardware monitor.
-For the I2C bus driver, see <file:Documentation/i2c/busses/i2c-viapro>
-
-The Via 686a implements three temperature sensors, two fan rotation speed
-sensors, five voltage sensors and alarms.
-
-Temperatures are measured in degrees Celsius. An alarm is triggered once
-when the Overtemperature Shutdown limit is crossed; it is triggered again
-as soon as it drops below the hysteresis value.
-
-Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
-triggered if the rotation speed has dropped below a programmable limit. Fan
-readings can be divided by a programmable divider (1, 2, 4 or 8) to give
-the readings more range or accuracy. Not all RPM values can accurately be
-represented, so some rounding is done. With a divider of 2, the lowest
-representable value is around 2600 RPM.
-
-Voltage sensors (also known as IN sensors) report their values in volts.
-An alarm is triggered if the voltage has crossed a programmable minimum
-or maximum limit. Voltages are internally scalled, so each voltage channel
-has a different resolution and range.
-
-If an alarm triggers, it will remain triggered until the hardware register
-is read at least once. This means that the cause for the alarm may
-already have disappeared! Note that in the current implementation, all
-hardware registers are read whenever any data is read (unless it is less
-than 1.5 seconds since the last update). This means that you can easily
-miss once-only alarms.
-
-The driver only updates its values each 1.5 seconds; reading it more often
-will do no harm, but will return 'old' values.
diff -urN linux/Documentation/i2c/chips/w83627hf 
linux/Documentation/i2c/chips/w83627hf
--- linux/Documentation/i2c/chips/Attic/w83627hf        2005-07-13 
12:48:48.775340000 +0100     1.1
+++ linux/Documentation/i2c/chips/Attic/w83627hf        1970/01/01 00:00:00+0100
@@ -1,66 +0,0 @@
-Kernel driver w83627hf
-======================
-
-Supported chips:
-  * Winbond W83627HF (ISA accesses ONLY)
-    Prefix: 'w83627hf'
-    Addresses scanned: ISA address retrieved from Super I/O registers
-    Datasheet: http://www.winbond.com/PDF/sheet/w83627hf.pdf
-  * Winbond W83627THF
-    Prefix: 'w83627thf'
-    Addresses scanned: ISA address retrieved from Super I/O registers
-    Datasheet: http://www.winbond.com/PDF/sheet/w83627thf.pdf
-  * Winbond W83697HF
-    Prefix: 'w83697hf'
-    Addresses scanned: ISA address retrieved from Super I/O registers
-    Datasheet: http://www.winbond.com/PDF/sheet/697hf.pdf
-  * Winbond W83637HF
-    Prefix: 'w83637hf'
-    Addresses scanned: ISA address retrieved from Super I/O registers
-    Datasheet: http://www.winbond.com/PDF/sheet/w83637hf.pdf
-
-Authors:
-        Frodo Looijaard <frodol@dds.nl>,
-        Philip Edelbrock <phil@netroedge.com>,
-        Mark Studebaker <mdsxyz123@yahoo.com>,
-        Bernhard C. Schrenk <clemy@clemy.org>
-
-Module Parameters
------------------
-
-* force_addr: int
-  Initialize the ISA address of the sensors
-* force_i2c: int
-  Initialize the I2C address of the sensors
-* init: int
-  (default is 1)
-  Use 'init=0' to bypass initializing the chip.
-  Try this if your computer crashes when you load the module.
-
-Description
------------
-
-This driver implements support for ISA accesses *only* for
-the Winbond W83627HF, W83627THF, W83697HF and W83637HF Super I/O chips.
-We will refer to them collectively as Winbond chips.
-
-This driver supports ISA accesses, which should be more reliable
-than i2c accesses. Also, for Tyan boards which contain both a
-Super I/O chip and a second i2c-only Winbond chip (often a W83782D),
-using this driver will avoid i2c address conflicts and complex
-initialization that were required in the w83781d driver.
-
-If you really want i2c accesses for these Super I/O chips,
-use the w83781d driver. However this is not the preferred method
-now that this ISA driver has been developed.
-
-Technically, the w83627thf does not support a VID reading. However, it's
-possible or even likely that your mainboard maker has routed these signals
-to a specific set of general purpose IO pins (the Asus P4C800-E is one such
-board). The w83627thf driver now interprets these as VID. If the VID on
-your board doesn't work, first see doc/vid in the lm_sensors package. If
-that still doesn't help, email us at lm-sensors@lm-sensors.org.
-
-For further information on this driver see the w83781d driver
-documentation.
-
diff -urN linux/Documentation/i2c/chips/w83781d 
linux/Documentation/i2c/chips/w83781d
--- linux/Documentation/i2c/chips/Attic/w83781d 2005-07-13 12:48:48.796842000 
+0100     1.1
+++ linux/Documentation/i2c/chips/Attic/w83781d 1970/01/01 00:00:00+0100
@@ -1,402 +0,0 @@
-Kernel driver w83781d
-=====================
-
-Supported chips:
-  * Winbond W83781D
-    Prefix: 'w83781d'
-    Addresses scanned: I2C 0x20 - 0x2f, ISA 0x290 (8 I/O ports)
-    Datasheet: 
http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83781d.pdf
-  * Winbond W83782D
-    Prefix: 'w83782d'
-    Addresses scanned: I2C 0x20 - 0x2f, ISA 0x290 (8 I/O ports)
-    Datasheet: http://www.winbond.com/PDF/sheet/w83782d.pdf
-  * Winbond W83783S
-    Prefix: 'w83783s'
-    Addresses scanned: I2C 0x2d
-    Datasheet: 
http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83783s.pdf
-  * Winbond W83627HF
-    Prefix: 'w83627hf'
-    Addresses scanned: I2C 0x20 - 0x2f, ISA 0x290 (8 I/O ports)
-    Datasheet: http://www.winbond.com/PDF/sheet/w83627hf.pdf
-  * Asus AS99127F
-    Prefix: 'as99127f'
-    Addresses scanned: I2C 0x28 - 0x2f
-    Datasheet: Unavailable from Asus
-
-Authors:
-        Frodo Looijaard <frodol@dds.nl>,
-        Philip Edelbrock <phil@netroedge.com>,
-        Mark Studebaker <mdsxyz123@yahoo.com>
-
-Module parameters
------------------
-
-* init int
-  (default 1)
-  Use 'init=0' to bypass initializing the chip.
-  Try this if your computer crashes when you load the module.
-
-force_subclients=bus,caddr,saddr,saddr
-  This is used to force the i2c addresses for subclients of
-  a certain chip. Typical usage is `force_subclients=0,0x2d,0x4a,0x4b'
-  to force the subclients of chip 0x2d on bus 0 to i2c addresses
-  0x4a and 0x4b. This parameter is useful for certain Tyan boards.
-
-Description
------------
-
-This driver implements support for the Winbond W83781D, W83782D, W83783S,
-W83627HF chips, and the Asus AS99127F chips. We will refer to them
-collectively as W8378* chips.
-
-There is quite some difference between these chips, but they are similar
-enough that it was sensible to put them together in one driver.
-The W83627HF chip is assumed to be identical to the ISA W83782D.
-The Asus chips are similar to an I2C-only W83782D.
-
-Chip        #vin    #fanin  #pwm    #temp   wchipid vendid  i2c     ISA
-as99127f    7       3       0       3       0x31    0x12c3  yes     no
-as99127f rev.2 (type_name = as99127f)       0x31    0x5ca3  yes     no
-w83781d     7       3       0       3       0x10-1  0x5ca3  yes     yes
-w83627hf    9       3       2       3       0x21    0x5ca3  yes     yes(LPC)
-w83782d     9       3       2-4     3       0x30    0x5ca3  yes     yes
-w83783s     5-6     3       2       1-2     0x40    0x5ca3  yes     no
-
-Detection of these chips can sometimes be foiled because they can be in
-an internal state that allows no clean access. If you know the address
-of the chip, use a 'force' parameter; this will put them into a more
-well-behaved state first.
-
-The W8378* implements temperature sensors (three on the W83781D and W83782D,
-two on the W83783S), three fan rotation speed sensors, voltage sensors
-(seven on the W83781D, nine on the W83782D and six on the W83783S), VID
-lines, alarms with beep warnings, and some miscellaneous stuff.
-
-Temperatures are measured in degrees Celsius. There is always one main
-temperature sensor, and one (W83783S) or two (W83781D and W83782D) other
-sensors. An alarm is triggered for the main sensor once when the
-Overtemperature Shutdown limit is crossed; it is triggered again as soon as
-it drops below the Hysteresis value. A more useful behavior
-can be found by setting the Hysteresis value to +127 degrees Celsius; in
-this case, alarms are issued during all the time when the actual temperature
-is above the Overtemperature Shutdown value. The driver sets the
-hysteresis value for temp1 to 127 at initialization.
-
-For the other temperature sensor(s), an alarm is triggered when the
-temperature gets higher then the Overtemperature Shutdown value; it stays
-on until the temperature falls below the Hysteresis value. But on the
-W83781D, there is only one alarm that functions for both other sensors!
-Temperatures are guaranteed within a range of -55 to +125 degrees. The
-main temperature sensors has a resolution of 1 degree; the other sensor(s)
-of 0.5 degree.
-
-Fan rotation speeds are reported in RPM (rotations per minute). An alarm is
-triggered if the rotation speed has dropped below a programmable limit. Fan
-readings can be divided by a programmable divider (1, 2, 4 or 8 for the
-W83781D; 1, 2, 4, 8, 16, 32, 64 or 128 for the others) to give
-the readings more range or accuracy. Not all RPM values can accurately
-be represented, so some rounding is done. With a divider of 2, the lowest
-representable value is around 2600 RPM.
-
-Voltage sensors (also known as IN sensors) report their values in volts.
-An alarm is triggered if the voltage has crossed a programmable minimum
-or maximum limit. Note that minimum in this case always means 'closest to
-zero'; this is important for negative voltage measurements. All voltage
-inputs can measure voltages between 0 and 4.08 volts, with a resolution
-of 0.016 volt.
-
-The VID lines encode the core voltage value: the voltage level your processor
-should work with. This is hardcoded by the mainboard and/or processor itself.
-It is a value in volts. When it is unconnected, you will often find the
-value 3.50 V here.
-
-The W83782D and W83783S temperature conversion machine understands about
-several kinds of temperature probes. You can program the so-called
-beta value in the sensor files. '1' is the PII/Celeron diode, '2' is the
-TN3904 transistor, and 3435 the default thermistor value. Other values
-are (not yet) supported.
-
-In addition to the alarms described above, there is a CHAS alarm on the
-chips which triggers if your computer case is open.
-
-When an alarm goes off, you can be warned by a beeping signal through
-your computer speaker. It is possible to enable all beeping globally,
-or only the beeping for some alarms.
-
-If an alarm triggers, it will remain triggered until the hardware register
-is read at least once. This means that the cause for the alarm may
-already have disappeared! Note that in the current implementation, all
-hardware registers are read whenever any data is read (unless it is less
-than 1.5 seconds since the last update). This means that you can easily
-miss once-only alarms.
-
-The chips only update values each 1.5 seconds; reading them more often
-will do no harm, but will return 'old' values.
-
-AS99127F PROBLEMS
------------------
-The as99127f support was developed without the benefit of a datasheet.
-In most cases it is treated as a w83781d (although revision 2 of the
-AS99127F looks more like a w83782d).
-This support will be BETA until a datasheet is released.
-One user has reported problems with fans stopping
-occasionally.
-
-Note that the individual beep bits are inverted from the other chips.
-The driver now takes care of this so that user-space applications
-don't have to know about it.
-
-Known problems:
-       - Problems with diode/thermistor settings (supported?)
-       - One user reports fans stopping under high server load.
-       - Revision 2 seems to have 2 PWM registers but we don't know
-         how to handle them. More details below.
-
-These will not be fixed unless we get a datasheet.
-If you have problems, please lobby Asus to release a datasheet.
-Unfortunately several others have without success.
-Please do not send mail to us asking for better as99127f support.
-We have done the best we can without a datasheet.
-Please do not send mail to the author or the sensors group asking for
-a datasheet or ideas on how to convince Asus. We can't help.
-
-
-NOTES:
------
-  783s has no in1 so that in[2-6] are compatible with the 781d/782d.
-
-  783s pin is programmable for -5V or temp1; defaults to -5V,
-       no control in driver so temp1 doesn't work.
-
-  782d and 783s datasheets differ on which is pwm1 and which is pwm2.
-       We chose to follow 782d.
-
-  782d and 783s pin is programmable for fan3 input or pwm2 output;
-       defaults to fan3 input.
-       If pwm2 is enabled (with echo 255 1 > pwm2), then
-       fan3 will report 0.
-
-  782d has pwm1-2 for ISA, pwm1-4 for i2c. (pwm3-4 share pins with
-       the ISA pins)
-
-Data sheet updates:
-------------------
-       - PWM clock registers:
-
-               000: master /  512
-               001: master / 1024
-               010: master / 2048
-               011: master / 4096
-               100: master / 8192
-
-
-Answers from Winbond tech support
----------------------------------
->
-> 1) In the W83781D data sheet section 7.2 last paragraph, it talks about
->    reprogramming the R-T table if the Beta of the thermistor is not
->    3435K. The R-T table is described briefly in section 8.20.
->    What formulas do I use to program a new R-T table for a given Beta?
->
-       We are sorry that the calculation for R-T table value is
-confidential. If you have another Beta value of thermistor, we can help
-to calculate the R-T table for you. But you should give us real R-T
-Table which can be gotten by thermistor vendor. Therefore we will calculate
-them and obtain 32-byte data, and you can fill the 32-byte data to the
-register in Bank0.CR51 of W83781D.
-
-
-> 2) In the W83782D data sheet, it mentions that pins 38, 39, and 40 are
->    programmable to be either thermistor or Pentium II diode inputs.
->    How do I program them for diode inputs? I can't find any register
->    to program these to be diode inputs.
- --> You may program Bank0 CR[5Dh] and CR[59h] registers.
-
-       CR[5Dh]                 bit 1(VTIN1)    bit 2(VTIN2)   bit 3(VTIN3)
-
-       thermistor                0              0              0
-       diode                     1              1              1
-
-
-(error) CR[59h]                bit 4(VTIN1)    bit 2(VTIN2)   bit 3(VTIN3)
-(right) CR[59h]                bit 4(VTIN1)    bit 5(VTIN2)   bit 6(VTIN3)
-
-       PII thermal diode         1              1              1
-       2N3904  diode             0              0              0
-
-
-Asus Clones
------------
-
-We have no datasheets for the Asus clones (AS99127F and ASB100 Bach).
-Here are some very useful information that were given to us by Alex Van
-Kaam about how to detect these chips, and how to read their values. He
-also gives advice for another Asus chipset, the Mozart-2 (which we
-don't support yet). Thanks Alex!
-I reworded some parts and added personal comments.
-
-# Detection:
-
-AS99127F rev.1, AS99127F rev.2 and ASB100:
-- I2C address range: 0x29 - 0x2F
-- If register 0x58 holds 0x31 then we have an Asus (either ASB100 or
-  AS99127F)
-- Which one depends on register 0x4F (manufacturer ID):
-  0x06 or 0x94: ASB100
-  0x12 or 0xC3: AS99127F rev.1
-  0x5C or 0xA3: AS99127F rev.2
-  Note that 0x5CA3 is Winbond's ID (WEC), which let us think Asus get their
-  AS99127F rev.2 direct from Winbond. The other codes mean ATT and DVC,
-  respectively. ATT could stand for Asustek something (although it would be
-  very badly chosen IMHO), I don't know what DVC could stand for. Maybe
-  these codes simply aren't meant to be decoded that way.
-
-Mozart-2:
-- I2C address: 0x77
-- If register 0x58 holds 0x56 or 0x10 then we have a Mozart-2
-- Of the Mozart there are 3 types:
-  0x58=0x56, 0x4E=0x94, 0x4F=0x36: Asus ASM58 Mozart-2
-  0x58=0x56, 0x4E=0x94, 0x4F=0x06: Asus AS2K129R Mozart-2
-  0x58=0x10, 0x4E=0x5C, 0x4F=0xA3: Asus ??? Mozart-2
-  You can handle all 3 the exact same way :)
-
-# Temperature sensors:
-
-ASB100:
-- sensor 1: register 0x27
-- sensor 2 & 3 are the 2 LM75's on the SMBus
-- sensor 4: register 0x17
-Remark: I noticed that on Intel boards sensor 2 is used for the CPU
-  and 4 is ignored/stuck, on AMD boards sensor 4 is the CPU and sensor 2 is
-  either ignored or a socket temperature.
-
-AS99127F (rev.1 and 2 alike):
-- sensor 1: register 0x27
-- sensor 2 & 3 are the 2 LM75's on the SMBus
-Remark: Register 0x5b is suspected to be temperature type selector. Bit 1
-  would control temp1, bit 3 temp2 and bit 5 temp3.
-
-Mozart-2:
-- sensor 1: register 0x27
-- sensor 2: register 0x13
-
-# Fan sensors:
-
-ASB100, AS99127F (rev.1 and 2 alike):
-- 3 fans, identical to the W83781D
-
-Mozart-2:
-- 2 fans only, 1350000/RPM/div
-- fan 1: register 0x28,  divisor on register 0xA1 (bits 4-5)
-- fan 2: register 0x29,  divisor on register 0xA1 (bits 6-7)
-
-# Voltages:
-
-This is where there is a difference between AS99127F rev.1 and 2.
-Remark: The difference is similar to the difference between
-  W83781D and W83782D.
-
-ASB100:
-in0=r(0x20)*0.016
-in1=r(0x21)*0.016
-in2=r(0x22)*0.016
-in3=r(0x23)*0.016*1.68
-in4=r(0x24)*0.016*3.8
-in5=r(0x25)*(-0.016)*3.97
-in6=r(0x26)*(-0.016)*1.666
-
-AS99127F rev.1:
-in0=r(0x20)*0.016
-in1=r(0x21)*0.016
-in2=r(0x22)*0.016
-in3=r(0x23)*0.016*1.68
-in4=r(0x24)*0.016*3.8
-in5=r(0x25)*(-0.016)*3.97
-in6=r(0x26)*(-0.016)*1.503
-
-AS99127F rev.2:
-in0=r(0x20)*0.016
-in1=r(0x21)*0.016
-in2=r(0x22)*0.016
-in3=r(0x23)*0.016*1.68
-in4=r(0x24)*0.016*3.8
-in5=(r(0x25)*0.016-3.6)*5.14+3.6
-in6=(r(0x26)*0.016-3.6)*3.14+3.6
-
-Mozart-2:
-in0=r(0x20)*0.016
-in1=255
-in2=r(0x22)*0.016
-in3=r(0x23)*0.016*1.68
-in4=r(0x24)*0.016*4
-in5=255
-in6=255
-
-
-# PWM
-
-Additional info about PWM on the AS99127F (may apply to other Asus
-chips as well) by Jean Delvare as of 2004-04-09:
-
-AS99127F revision 2 seems to have two PWM registers at 0x59 and 0x5A,
-and a temperature sensor type selector at 0x5B (which basically means
-that they swapped registers 0x59 and 0x5B when you compare with Winbond
-chips).
-Revision 1 of the chip also has the temperature sensor type selector at
-0x5B, but PWM registers have no effect.
-
-We don't know exactly how the temperature sensor type selection works.
-Looks like bits 1-0 are for temp1, bits 3-2 for temp2 and bits 5-4 for
-temp3, although it is possible that only the most significant bit matters
-each time. So far, values other than 0 always broke the readings.
-
-PWM registers seem to be split in two parts: bit 7 is a mode selector,
-while the other bits seem to define a value or threshold.
-
-When bit 7 is clear, bits 6-0 seem to hold a threshold value. If the value
-is below a given limit, the fan runs at low speed. If the value is above
-the limit, the fan runs at full speed. We have no clue as to what the limit
-represents. Note that there seem to be some inertia in this mode, speed
-changes may need some time to trigger. Also, an hysteresis mechanism is
-suspected since walking through all the values increasingly and then
-decreasingly led to slightly different limits.
-
-When bit 7 is set, bits 3-0 seem to hold a threshold value, while bits 6-4
-would not be significant. If the value is below a given limit, the fan runs
-at full speed, while if it is above the limit it runs at low speed (so this
-is the contrary of the other mode, in a way). Here again, we don't know
-what the limit is supposed to represent.
-
-One remarkable thing is that the fans would only have two or three
-different speeds (transitional states left apart), not a whole range as
-you usually get with PWM.
-
-As a conclusion, you can write 0x00 or 0x8F to the PWM registers to make
-fans run at low speed, and 0x7F or 0x80 to make them run at full speed.
-
-Please contact us if you can figure out how it is supposed to work. As
-long as we don't know more, the w83781d driver doesn't handle PWM on
-AS99127F chips at all.
-
-Additional info about PWM on the AS99127F rev.1 by Hector Martin:
-
-I've been fiddling around with the (in)famous 0x59 register and
-found out the following values do work as a form of coarse pwm:
-
-0x80 - seems to turn fans off after some time(1-2 minutes)... might be
-some form of auto-fan-control based on temp? hmm (Qfan? this mobo is an
-old ASUS, it isn't marketed as Qfan. Maybe some beta pre-attemp at Qfan
-that was dropped at the BIOS)
-0x81 - off
-0x82 - slightly "on-ner" than off, but my fans do not get to move. I can
-hear the high-pitched PWM sound that motors give off at too-low-pwm.
-0x83 - now they do move. Estimate about 70% speed or so.
-0x84-0x8f - full on
-
-Changing the high nibble doesn't seem to do much except the high bit
-(0x80) must be set for PWM to work, else the current pwm doesn't seem to
-change.
-
-My mobo is an ASUS A7V266-E. This behavior is similar to what I got
-with speedfan under Windows, where 0-15% would be off, 15-2x% (can't
-remember the exact value) would be 70% and higher would be full on.
diff -urN linux/Documentation/i2c/chips/w83l785ts 
linux/Documentation/i2c/chips/w83l785ts
--- linux/Documentation/i2c/chips/Attic/w83l785ts       2005-07-13 
12:48:48.820115000 +0100     1.1
+++ linux/Documentation/i2c/chips/Attic/w83l785ts       1970/01/01 00:00:00+0100
@@ -1,39 +0,0 @@
-Kernel driver w83l785ts
-=======================
-
-Supported chips:
-  * Winbond W83L785TS-S
-    Prefix: 'w83l785ts'
-    Addresses scanned: I2C 0x2e
-    Datasheet: Publicly available at the Winbond USA website
-               
http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/W83L785TS-S.pdf
-
-Authors:
-        Jean Delvare <khali@linux-fr.org>
-
-Description
------------
-
-The W83L785TS-S is a digital temperature sensor. It senses the
-temperature of a single external diode. The high limit is
-theoretically defined as 85 or 100 degrees C through a combination
-of external resistors, so the user cannot change it. Values seen so
-far suggest that the two possible limits are actually 95 and 110
-degrees C. The datasheet is rather poor and obviously inaccurate
-on several points including this one.
-
-All temperature values are given in degrees Celsius. Resolution
-is 1.0 degree. See the datasheet for details.
-
-The w83l785ts driver will not update its values more frequently than
-every other second; reading them more often will do no harm, but will
-return 'old' values.
-
-Known Issues
-------------
-
-On some systems (Asus), the BIOS is known to interfere with the driver
-and cause read errors. The driver will retry a given number of times
-(5 by default) and then give up, returning the old value (or 0 if
-there is no old value). It seems to work well enough so that you should
-not notice anything. Thanks to James Bolt for helping test this feature.
diff -urN linux/Documentation/infiniband/user_verbs.txt 
linux/Documentation/infiniband/user_verbs.txt
--- linux/Documentation/infiniband/user_verbs.txt       1970/01/01 00:00:00
+++ linux/Documentation/infiniband/user_verbs.txt       2005-07-13 
12:48:48.956155000 +0100     1.1
@@ -0,0 +1,69 @@
+USERSPACE VERBS ACCESS
+
+  The ib_uverbs module, built by enabling CONFIG_INFINIBAND_USER_VERBS,
+  enables direct userspace access to IB hardware via "verbs," as
+  described in chapter 11 of the InfiniBand Architecture Specification.
+
+  To use the verbs, the libibverbs library, available from
+  <http://openib.org/>, is required.  libibverbs contains a
+  device-independent API for using the ib_uverbs interface.
+  libibverbs also requires appropriate device-dependent kernel and
+  userspace driver for your InfiniBand hardware.  For example, to use
+  a Mellanox HCA, you will need the ib_mthca kernel module and the
+  libmthca userspace driver be installed.
+
+User-kernel communication
+
+  Userspace communicates with the kernel for slow path, resource
+  management operations via the /dev/infiniband/uverbsN character
+  devices.  Fast path operations are typically performed by writing
+  directly to hardware registers mmap()ed into userspace, with no
+  system call or context switch into the kernel.
+
+  Commands are sent to the kernel via write()s on these device files.
+  The ABI is defined in drivers/infiniband/include/ib_user_verbs.h.
+  The structs for commands that require a response from the kernel
+  contain a 64-bit field used to pass a pointer to an output buffer.
+  Status is returned to userspace as the return value of the write()
+  system call.
+
+Resource management
+
+  Since creation and destruction of all IB resources is done by
+  commands passed through a file descriptor, the kernel can keep track
+  of which resources are attached to a given userspace context.  The
+  ib_uverbs module maintains idr tables that are used to translate
+  between kernel pointers and opaque userspace handles, so that kernel
+  pointers are never exposed to userspace and userspace cannot trick
+  the kernel into following a bogus pointer.
+
+  This also allows the kernel to clean up when a process exits and
+  prevent one process from touching another process's resources.
+
+Memory pinning
+
+  Direct userspace I/O requires that memory regions that are potential
+  I/O targets be kept resident at the same physical address.  The
+  ib_uverbs module manages pinning and unpinning memory regions via
+  get_user_pages() and put_page() calls.  It also accounts for the
+  amount of memory pinned in the process's locked_vm, and checks that
+  unprivileged processes do not exceed their RLIMIT_MEMLOCK limit.
+
+  Pages that are pinned multiple times are counted each time they are
+  pinned, so the value of locked_vm may be an overestimate of the
+  number of pages pinned by a process.
+
+/dev files
+
+  To create the appropriate character device files automatically with
+  udev, a rule like
+
+    KERNEL="uverbs*", NAME="infiniband/%k"
+
+  can be used.  This will create device nodes named
+
+    /dev/infiniband/uverbs0
+
+  and so on.  Since the InfiniBand userspace verbs should be safe for
+  use by non-privileged processes, it may be useful to add an
+  appropriate MODE or GROUP to the udev rule.
diff -urN linux/Documentation/pcmcia/driver-changes.txt 
linux/Documentation/pcmcia/driver-changes.txt
--- linux/Documentation/pcmcia/driver-changes.txt       2005/07/11 20:45:56     
1.1
+++ linux/Documentation/pcmcia/driver-changes.txt       2005/07/13 11:48:48     
1.2
@@ -1,6 +1,13 @@
 This file details changes in 2.6 which affect PCMCIA card driver authors:
 
-* in-kernel device<->driver matching
+* event handler initialization in struct pcmcia_driver (as of 2.6.13)
+   The event handler is notified of all events, and must be initialized
+   as the event() callback in the driver's struct pcmcia_driver.
+
+* pcmcia/version.h should not be used (as of 2.6.13)
+   This file will be removed eventually.
+
+* in-kernel device<->driver matching (as of 2.6.13)
    PCMCIA devices and their correct drivers can now be matched in
    kernelspace. See 'devicetable.txt' for details.
 
diff -urN linux/Documentation/power/video.txt 
linux/Documentation/power/video.txt
--- linux/Documentation/power/video.txt 2005/07/11 20:45:56     1.9
+++ linux/Documentation/power/video.txt 2005/07/13 11:48:49     1.10
@@ -117,6 +117,7 @@
 Medion MD4220                  ??? (*)
 Samsung P35                    vbetool needed (6)
 Sharp PC-AR10 (ATI rage)       none (1)
+Sony Vaio PCG-C1VRX/K          s3_bios (2)
 Sony Vaio PCG-F403             ??? (*)
 Sony Vaio PCG-N505SN           ??? (*)
 Sony Vaio vgn-s260             X or boot-radeon can init it (5)
diff -urN linux/Documentation/usb/sn9c102.txt 
linux/Documentation/usb/sn9c102.txt
--- linux/Documentation/usb/sn9c102.txt 2005/03/18 17:36:45     1.8
+++ linux/Documentation/usb/sn9c102.txt 2005/07/13 11:48:49     1.9
@@ -297,6 +297,7 @@
 0x0c45     0x602a
 0x0c45     0x602b
 0x0c45     0x602c
+0x0c45     0x602d
 0x0c45     0x6030
 0x0c45     0x6080
 0x0c45     0x6082
@@ -333,6 +334,7 @@
 -----       ------------
 HV7131D     Hynix Semiconductor, Inc.
 MI-0343     Micron Technology, Inc.
+OV7630      OmniVision Technologies, Inc.
 PAS106B     PixArt Imaging, Inc.
 PAS202BCB   PixArt Imaging, Inc.
 TAS5110C1B  Taiwan Advanced Sensor Corporation
@@ -470,9 +472,11 @@
 - Luca Capello for the donation of a webcam;
 - Joao Rodrigo Fuzaro, Joao Limirio, Claudio Filho and Caio Begotti for the
   donation of a webcam;
+- Jon Hollstrom for the donation of a webcam;
 - Carlos Eduardo Medaglia Dyonisio, who added the support for the PAS202BCB
   image sensor;
 - Stefano Mozzi, who donated 45 EU;
+- Andrew Pearce for the donation of a webcam;
 - Bertrik Sikken, who reverse-engineered and documented the Huffman compression
   algorithm used in the SN9C10x controllers and implemented the first decoder;
 - Mizuno Takafumi for the donation of a webcam;
diff -urN linux/Documentation/usb/usbmon.txt linux/Documentation/usb/usbmon.txt
--- linux/Documentation/usb/usbmon.txt  2005/04/08 18:57:47     1.1
+++ linux/Documentation/usb/usbmon.txt  2005/07/13 11:48:49     1.2
@@ -101,6 +101,13 @@
   or 3 and 2 positions, correspondingly.
 - URB Status. This field makes no sense for submissions, but is present
   to help scripts with parsing. In error case, it contains the error code.
+  In case of a setup packet, it contains a Setup Tag. If scripts read a number
+  in this field, the proceed to read Data Length. Otherwise, they read
+  the setup packet before reading the Data Length.
+- Setup packet, if present, consists of 5 words: one of each for bmRequestType,
+  bRequest, wValue, wIndex, wLength, as specified by the USB Specification 2.0.
+  These words are safe to decode if Setup Tag was 's'. Otherwise, the setup
+  packet was present, but not captured, and the fields contain filler.
 - Data Length. This is the actual length in the URB.
 - Data tag. The usbmon may not always capture data, even if length is nonzero.
   Only if tag is '=', the data words are present.
@@ -125,25 +132,31 @@
                        String data_str = st.nextToken();
                        int len = data_str.length() / 2;
                        int i;
+                       int b;  // byte is signed, apparently?! XXX
                        for (i = 0; i < len; i++) {
-                               data[data_len] = Byte.parseByte(
-                                   data_str.substring(i*2, i*2 + 2),
-                                   16);
+                               // data[data_len] = Byte.parseByte(
+                               //     data_str.substring(i*2, i*2 + 2),
+                               //     16);
+                               b = Integer.parseInt(
+                                    data_str.substring(i*2, i*2 + 2),
+                                    16);
+                               if (b >= 128)
+                                       b *= -1;
+                               data[data_len] = (byte) b;
                                data_len++;
                        }
                }
        }
 }
 
-This format is obviously deficient. For example, the setup packet for control
-transfers is not delivered. This will change in the future.
+This format may be changed in the future.
 
 Examples:
 
-An input control transfer to get a port status:
+An input control transfer to get a port status.
 
-d74ff9a0 2640288196 S Ci:001:00 -115 4 <
-d74ff9a0 2640288202 C Ci:001:00 0 4 = 01010100
+d5ea89a0 3575914555 S Ci:001:00 s a3 00 0000 0003 0004 4 <
+d5ea89a0 3575914560 C Ci:001:00 0 4 = 01050000
 
 An output bulk transfer to send a SCSI command 0x5E in a 31-byte Bulk wrapper
 to a storage device at address 5:
diff -urN linux/Documentation/video4linux/CARDLIST.bttv 
linux/Documentation/video4linux/CARDLIST.bttv
--- linux/Documentation/video4linux/CARDLIST.bttv       2005/07/11 20:45:57     
1.3
+++ linux/Documentation/video4linux/CARDLIST.bttv       2005/07/13 11:48:49     
1.4
@@ -1,4 +1,4 @@
-card=0 -  *** UNKNOWN/GENERIC *** 
+card=0 -  *** UNKNOWN/GENERIC ***
 card=1 - MIRO PCTV
 card=2 - Hauppauge (bt848)
 card=3 - STB, Gateway P/N 6000699 (bt848)
diff -urN linux/Documentation/video4linux/CARDLIST.cx88 
linux/Documentation/video4linux/CARDLIST.cx88
--- linux/Documentation/video4linux/CARDLIST.cx88       2005/07/11 20:45:57     
1.1
+++ linux/Documentation/video4linux/CARDLIST.cx88       2005/07/13 11:48:49     
1.2
@@ -27,3 +27,5 @@
 card=26 - IODATA GV/BCTV7E
 card=27 - PixelView PlayTV Ultra Pro (Stereo)
 card=28 - DViCO FusionHDTV 3 Gold-T
+card=29 - ADS Tech Instant TV DVB-T PCI
+card=30 - TerraTec Cinergy 1400 DVB-T
diff -urN linux/Documentation/video4linux/CARDLIST.saa7134 
linux/Documentation/video4linux/CARDLIST.saa7134
--- linux/Documentation/video4linux/CARDLIST.saa7134    2005/07/11 20:45:57     
1.4
+++ linux/Documentation/video4linux/CARDLIST.saa7134    2005/07/13 11:48:49     
1.5
@@ -1,10 +1,10 @@
-  0 -> UNKNOWN/GENERIC                         
+  0 -> UNKNOWN/GENERIC
   1 -> Proteus Pro [philips reference design]   [1131:2001,1131:2001]
   2 -> LifeView FlyVIDEO3000                    [5168:0138,4e42:0138]
   3 -> LifeView FlyVIDEO2000                    [5168:0138]
   4 -> EMPRESS                                  [1131:6752]
   5 -> SKNet Monster TV                         [1131:4e85]
-  6 -> Tevion MD 9717                          
+  6 -> Tevion MD 9717
   7 -> KNC One TV-Station RDS / Typhoon TV Tuner RDS [1131:fe01,1894:fe01]
   8 -> Terratec Cinergy 400 TV                  [153B:1142]
   9 -> Medion 5044
@@ -34,6 +34,7 @@
  33 -> AVerMedia DVD EZMaker                    [1461:10ff]
  34 -> Noval Prime TV 7133
  35 -> AverMedia AverTV Studio 305              [1461:2115]
+ 36 -> UPMOST PURPLE TV                         [12ab:0800]
  37 -> Items MuchTV Plus / IT-005
  38 -> Terratec Cinergy 200 TV                  [153B:1152]
  39 -> LifeView FlyTV Platinum Mini             [5168:0212]
@@ -43,20 +44,21 @@
  43 -> :Zolid Xpert TV7134
  44 -> Empire PCI TV-Radio LE
  45 -> Avermedia AVerTV Studio 307              [1461:9715]
- 46 -> AVerMedia Cardbus TV/Radio               [1461:d6ee]
+ 46 -> AVerMedia Cardbus TV/Radio (E500)        [1461:d6ee]
  47 -> Terratec Cinergy 400 mobile              [153b:1162]
  48 -> Terratec Cinergy 600 TV MK3              [153B:1158]
  49 -> Compro VideoMate Gold+ Pal               [185b:c200]
  50 -> Pinnacle PCTV 300i DVB-T + PAL           [11bd:002d]
  51 -> ProVideo PV952                           [1540:9524]
  52 -> AverMedia AverTV/305                     [1461:2108]
+ 53 -> ASUS TV-FM 7135                          [1043:4845]
  54 -> LifeView FlyTV Platinum FM               [5168:0214,1489:0214]
- 55 -> LifeView FlyDVB-T DUO                    [5168:0306]
+ 55 -> LifeView FlyDVB-T DUO                    [5168:0502,5168:0306]
  56 -> Avermedia AVerTV 307                     [1461:a70a]
  57 -> Avermedia AVerTV GO 007 FM               [1461:f31f]
  58 -> ADS Tech Instant TV (saa7135)            [1421:0350,1421:0370]
  59 -> Kworld/Tevion V-Stream Xpert TV PVR7134
- 60 -> Typhoon DVB-T Duo Digital/Analog Cardbus
- 61 -> Philips TOUGH DVB-T reference design
+ 60 -> Typhoon DVB-T Duo Digital/Analog Cardbus [4e42:0502]
+ 61 -> Philips TOUGH DVB-T reference design     [1131:2004]
  62 -> Compro VideoMate TV Gold+II
  63 -> Kworld Xpert TV PVR7134
diff -urN linux/Documentation/video4linux/CARDLIST.tuner 
linux/Documentation/video4linux/CARDLIST.tuner
--- linux/Documentation/video4linux/CARDLIST.tuner      2005/07/11 20:45:57     
1.3
+++ linux/Documentation/video4linux/CARDLIST.tuner      2005/07/13 11:48:49     
1.4
@@ -56,9 +56,9 @@
 tuner=55 - LG PAL (TAPE series)
 tuner=56 - Philips PAL/SECAM multi (FQ1216AME MK4)
 tuner=57 - Philips FQ1236A MK4
-tuner=58 - Ymec TVision TVF-8531MF
+tuner=58 - Ymec TVision TVF-8531MF/8831MF/8731MF
 tuner=59 - Ymec TVision TVF-5533MF
 tuner=60 - Thomson DDT 7611 (ATSC/NTSC)
-tuner=61 - Tena TNF9533-D/IF
+tuner=61 - Tena TNF9533-D/IF/TNF9533-B/DF
 tuner=62 - Philips TEA5767HN FM Radio
 tuner=63 - Philips FMD1216ME MK3 Hybrid Tuner
diff -urN linux/Documentation/video4linux/not-in-cx2388x-datasheet.txt 
linux/Documentation/video4linux/not-in-cx2388x-datasheet.txt
--- linux/Documentation/video4linux/not-in-cx2388x-datasheet.txt        
2005/07/11 20:45:57     1.1
+++ linux/Documentation/video4linux/not-in-cx2388x-datasheet.txt        
2005/07/13 11:48:49     1.2
@@ -34,4 +34,8 @@
   2: HACTEXT
   1: HSFMT
 
+0x47 is the sync byte for MPEG-2 transport stream packets.
+Datasheet incorrectly states to use 47 decimal. 188 is the length.
+All DVB compliant frontends output packets with this start code.
+
 
=================================================================================
diff -urN linux/Documentation/video4linux/bttv/Cards 
linux/Documentation/video4linux/bttv/Cards
--- linux/Documentation/video4linux/bttv/Cards  2005/03/18 17:36:45     1.8
+++ linux/Documentation/video4linux/bttv/Cards  2005/07/13 11:48:49     1.9
@@ -20,7 +20,7 @@
 decoders, EEPROMs, teletext decoders ...
 
 
-Unsupported Cards: 
+Unsupported Cards:
 ------------------
 
 Cards with Zoran (ZR) or Philips (SAA) or ISA are not supported by
@@ -50,11 +50,11 @@
 Miro/Pinnacle PCTV
 ------------------
 
-- Bt848 
-  some (all??) come with 2 crystals for PAL/SECAM and NTSC 
+- Bt848
+  some (all??) come with 2 crystals for PAL/SECAM and NTSC
 - PAL, SECAM or NTSC TV tuner (Philips or TEMIC)
 - MSP34xx sound decoder on add on board
-  decoder is supported but AFAIK does not yet work 
+  decoder is supported but AFAIK does not yet work
   (other sound MUX setting in GPIO port needed??? somebody who fixed this???)
 - 1 tuner, 1 composite and 1 S-VHS input
 - tuner type is autodetected
@@ -70,7 +70,7 @@
 Hauppauge Win/TV pci
 --------------------
 
-There are many different versions of the Hauppauge cards with different 
+There are many different versions of the Hauppauge cards with different
 tuners (TV+Radio ...), teletext decoders.
 Note that even cards with same model numbers have (depending on the revision)
 different chips on it.
@@ -80,22 +80,22 @@
 - PAL, SECAM, NTSC or tuner with or without Radio support
 
 e.g.:
-  PAL: 
+  PAL:
   TDA5737: VHF, hyperband and UHF mixer/oscillator for TV and VCR 3-band tuners
   TSA5522: 1.4 GHz I2C-bus controlled synthesizer, I2C 0xc2-0xc3
-  
+
   NTSC:
   TDA5731: VHF, hyperband and UHF mixer/oscillator for TV and VCR 3-band tuners
   TSA5518: no datasheet available on Philips site
-- Philips SAA5246 or SAA5284 ( or no) Teletext decoder chip    
+- Philips SAA5246 or SAA5284 ( or no) Teletext decoder chip
   with buffer RAM (e.g. Winbond W24257AS-35: 32Kx8 CMOS static RAM)
   SAA5246 (I2C 0x22) is supported
-- 256 bytes EEPROM: Microchip 24LC02B or Philips 8582E2Y 
+- 256 bytes EEPROM: Microchip 24LC02B or Philips 8582E2Y
   with configuration information
   I2C address 0xa0 (24LC02B also responds to 0xa2-0xaf)
 - 1 tuner, 1 composite and (depending on model) 1 S-VHS input
 - 14052B: mux for selection of sound source
-- sound decoder: TDA9800, MSP34xx (stereo cards) 
+- sound decoder: TDA9800, MSP34xx (stereo cards)
 
 
 Askey CPH-Series
@@ -108,17 +108,17 @@
     CPH05x: BT878 with FM
     CPH06x: BT878 (w/o FM)
     CPH07x: BT878 capture only
- 
+
   TV standards:
      CPH0x0: NTSC-M/M
      CPH0x1: PAL-B/G
      CPH0x2: PAL-I/I
      CPH0x3: PAL-D/K
-     CPH0x4: SECAM-L/L 
-     CPH0x5: SECAM-B/G 
-     CPH0x6: SECAM-D/K 
-     CPH0x7: PAL-N/N 
-     CPH0x8: PAL-B/H 
+     CPH0x4: SECAM-L/L
+     CPH0x5: SECAM-B/G
+     CPH0x6: SECAM-D/K
+     CPH0x7: PAL-N/N
+     CPH0x8: PAL-B/H
      CPH0x9: PAL-M/M
 
   CPH03x was often sold as "TV capturer".
@@ -174,7 +174,7 @@
       "The FlyVideo2000 and FlyVideo2000s product name have renamed to 
FlyVideo98."
       Their Bt8x8 cards are listed as discontinued.
       Flyvideo 2000S was probably sold as Flyvideo 3000 in some 
contries(Europe?).
-      The new Flyvideo 2000/3000 are SAA7130/SAA7134 based. 
+      The new Flyvideo 2000/3000 are SAA7130/SAA7134 based.
 
   "Flyvideo II" had been the name for the 848 cards, nowadays (in Germany)
   this name is re-used for LR50 Rev.W.
@@ -235,12 +235,12 @@
    Multimedia TV packages (card + software pack):
    PixelView Play TV Theater - (Model: PV-M4200) =  PixelView Play TV pro + 
Software
    PixelView Play TV PAK -     (Model: PV-BT878P+ REV 4E)
-   PixelView Play TV/VCR -     (Model: PV-M3200 REV 4C / 8D / 10A ) 
+   PixelView Play TV/VCR -     (Model: PV-M3200 REV 4C / 8D / 10A )
    PixelView Studio PAK -      (Model:    M2200 REV 4C / 8D / 10A )
    PixelView PowerStudio PAK - (Model: PV-M3600 REV 4E)
    PixelView DigitalVCR PAK -  (Model: PV-M2400 REV 4C / 8D / 10A )
 
-   PixelView PlayTV PAK II (TV/FM card + usb camera)  PV-M3800 
+   PixelView PlayTV PAK II (TV/FM card + usb camera)  PV-M3800
    PixelView PlayTV XP PV-M4700,PV-M4700(w/FM)
    PixelView PlayTV DVR PV-M4600  package contents:PixelView PlayTV pro, 
windvr & videoMail s/w
 
@@ -254,7 +254,7 @@
 
    DTV3000 PV-DTV3000P+ DVB-S CI = Twinhan VP-1030
    DTV2000 DVB-S = Twinhan VP-1020
-   
+
    Video Conferencing:
    PixelView Meeting PAK - (Model: PV-BT878P)
    PixelView Meeting PAK Lite - (Model: PV-BT878P)
@@ -308,7 +308,7 @@
 
    newer Cards have saa7134, but model name stayed the same?
 
-Provideo 
+Provideo
 --------
   PV951 or PV-951 (also are sold as:
    Boeder TV-FM Video Capture Card
@@ -353,7 +353,7 @@
    AVerTV
    AVerTV Stereo
    AVerTV Studio (w/FM)
-   AVerMedia TV98 with Remote 
+   AVerMedia TV98 with Remote
    AVerMedia TV/FM98 Stereo
    AVerMedia TVCAM98
    TVCapture (Bt848)
@@ -373,7 +373,7 @@
    (1) Daughterboard MB68-A with TDA9820T and TDA9840T
    (2) Sony NE41S soldered (stereo sound?)
    (3) Daughterboard M118-A w/ pic 16c54 and 4 MHz quartz
- 
+
    US site has different drivers for (as of 09/2002):
    EZ Capture/InterCam PCI (BT-848 chip)
    EZ Capture/InterCam PCI (BT-878 chip)
@@ -437,7 +437,7 @@
    Terra TValueRadio,             "LR102 Rev.C" printed on the PCB
    Terra TV/Radio+ Version 1.0,   "80-CP2830100-0" TTTV3 printed on the PCB,
                                     "CPH010-E83" on the back, SAA6588T, 
TDA9873H
-   Terra TValue Version BT878,    "80-CP2830110-0 TTTV4" printed on the PCB, 
+   Terra TValue Version BT878,    "80-CP2830110-0 TTTV4" printed on the PCB,
                                     "CPH011-D83" on back
    Terra TValue Version 1.0       "ceb105.PCB" (really identical to Terra TV+ 
Version 1.0)
    Terra TValue New Revision     "LR102 Rec.C"
@@ -528,7 +528,7 @@
    KW-606RSF
    KW-607A (capture only)
    KW-608 (Zoran capture only)
- 
+
 IODATA (jp)
 ------
    GV-BCTV/PCI
@@ -542,15 +542,15 @@
 -------
    WinDVR      = Kworld "KW-TVL878RF"
 
-www.sigmacom.co.kr 
+www.sigmacom.co.kr
 ------------------
-   Sigma Cyber TV II 
+   Sigma Cyber TV II
 
 www.sasem.co.kr
 ---------------
    Litte OnAir TV
 
-hama 
+hama
 ----
    TV/Radio-Tuner Card, PCI (Model 44677) = CPH051
 
@@ -638,7 +638,7 @@
 
 Jetway (www.jetway.com.tw)
 --------------------------
-   JW-TV 878M 
+   JW-TV 878M
    JW-TV 878  = KWorld KW-TV878RF
 
 Galaxis
@@ -715,7 +715,7 @@
   809 MyVideo
   872 MyTV2Go FM
 
- 
+
   546 WinTV Nova-S CI
   543 WinTV Nova
   907 Nova-S USB
@@ -739,7 +739,7 @@
   832 MyTV2Go
   869 MyTV2Go-FM
   805 MyVideo (USB)
-  
+
 
 Matrix-Vision
 -------------
@@ -764,7 +764,7 @@
    Intervision IV-550 (bt8x8)
    Intervision IV-100 (zoran)
    Intervision IV-1000 (bt8x8)
-   
+
 Asonic (www.asonic.com.cn) (website down)
 -----------------------------------------
    SkyEye tv 878
@@ -804,11 +804,11 @@
 
 JTT/ Justy Corp.http://www.justy.co.jp/ (www.jtt.com.jp website down)
 ---------------------------------------------------------------------
-   JTT-02 (JTT TV) "TV watchmate pro" (bt848) 
+   JTT-02 (JTT TV) "TV watchmate pro" (bt848)
 
 ADS www.adstech.com
 -------------------
-   Channel Surfer TV ( CHX-950 ) 
+   Channel Surfer TV ( CHX-950 )
    Channel Surfer TV+FM ( CHX-960FM )
 
 AVEC www.prochips.com
@@ -874,7 +874,7 @@
 ------------------
    Falcon Series (capture only)
  In USA: http://www.theimagingsource.com/
-   DFG/LC1     
+   DFG/LC1
 
 www.sknet-web.co.jp
 -------------------
@@ -890,7 +890,7 @@
    CyberMail Xtreme
   These are Flyvideo
 
-VCR (http://www.vcrinc.com/) 
+VCR (http://www.vcrinc.com/)
 ---
   Video Catcher 16
 
@@ -920,7 +920,7 @@
     SDI Silk 200 SDI Input Card
 
 www.euresys.com
-    PICOLO series 
+    PICOLO series
 
 PMC/Pace
 www.pacecom.co.uk website closed
diff -urN linux/arch/alpha/Kconfig linux/arch/alpha/Kconfig
--- linux/arch/alpha/Kconfig    2005/07/11 20:45:58     1.32
+++ linux/arch/alpha/Kconfig    2005/07/13 11:48:49     1.33
@@ -596,6 +596,8 @@
 
 endmenu
 
+source "net/Kconfig"
+
 source "drivers/Kconfig"
 
 source "fs/Kconfig"
diff -urN linux/arch/arm/Kconfig linux/arch/arm/Kconfig
--- linux/arch/arm/Kconfig      2005/07/11 20:45:58     1.49
+++ linux/arch/arm/Kconfig      2005/07/13 11:48:49     1.50
@@ -223,7 +223,9 @@
 
 source "arch/arm/mach-sa1100/Kconfig"
 
-source "arch/arm/mach-omap/Kconfig"
+source "arch/arm/plat-omap/Kconfig"
+
+source "arch/arm/mach-omap1/Kconfig"
 
 source "arch/arm/mach-s3c2410/Kconfig"
 
@@ -514,7 +516,7 @@
 
 endmenu
 
-if (ARCH_SA1100 || ARCH_INTEGRATOR)
+if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP1)
 
 menu "CPU Frequency scaling"
 
@@ -698,6 +700,8 @@
 
 endmenu
 
+source "net/Kconfig"
+
 menu "Device Drivers"
 
 source "drivers/base/Kconfig"
@@ -730,7 +734,7 @@
 
 source "drivers/message/i2o/Kconfig"
 
-source "net/Kconfig"
+source "drivers/net/Kconfig"
 
 source "drivers/isdn/Kconfig"
 
@@ -742,6 +746,8 @@
 
 source "drivers/i2c/Kconfig"
 
+source "drivers/hwmon/Kconfig"
+
 #source "drivers/l3/Kconfig"
 
 source "drivers/misc/Kconfig"
diff -urN linux/arch/arm/Makefile linux/arch/arm/Makefile
--- linux/arch/arm/Makefile     2005/07/12 09:18:54     1.77
+++ linux/arch/arm/Makefile     2005/07/13 11:48:49     1.78
@@ -91,7 +91,8 @@
  machine-$(CONFIG_ARCH_IOP3XX)    := iop3xx
  machine-$(CONFIG_ARCH_IXP4XX)    := ixp4xx
  machine-$(CONFIG_ARCH_IXP2000)    := ixp2000
- machine-$(CONFIG_ARCH_OMAP)      := omap
+ machine-$(CONFIG_ARCH_OMAP1)     := omap1
+  incdir-$(CONFIG_ARCH_OMAP)      := omap
  machine-$(CONFIG_ARCH_S3C2410)           := s3c2410
  machine-$(CONFIG_ARCH_LH7A40X)           := lh7a40x
  machine-$(CONFIG_ARCH_VERSATILE)  := versatile
@@ -142,6 +143,9 @@
 core-$(CONFIG_FPE_FASTFPE)     += $(FASTFPE_OBJ)
 core-$(CONFIG_VFP)             += arch/arm/vfp/
 
+# If we have a common platform directory, then include it in the build.
+core-$(CONFIG_ARCH_OMAP)       += arch/arm/plat-omap/
+
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
 drivers-$(CONFIG_ARCH_CLPS7500)        += drivers/acorn/char/
 drivers-$(CONFIG_ARCH_L7200)   += drivers/acorn/char/
diff -urN linux/arch/arm/configs/enp2611_defconfig 
linux/arch/arm/configs/enp2611_defconfig
--- linux/arch/arm/configs/enp2611_defconfig    2005/07/11 20:45:59     1.3
+++ linux/arch/arm/configs/enp2611_defconfig    2005/07/13 11:48:50     1.4
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-git6
-# Sat Jun 25 00:57:29 2005
+# Linux kernel version: 2.6.13-rc2
+# Thu Jul  7 16:41:21 2005
 #
 CONFIG_ARM=y
 CONFIG_MMU=y
@@ -137,6 +137,7 @@
 #
 # CONFIG_SMP is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
@@ -345,10 +346,9 @@
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_FIB_TRIE is not set
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -363,17 +363,8 @@
 # CONFIG_INET_TUNNEL is not set
 # CONFIG_IP_TCPDIAG is not set
 # CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# TCP congestion control
-#
+# CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_BIC=y
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-# CONFIG_TCP_CONG_HSTCP is not set
-# CONFIG_TCP_CONG_HYBLA is not set
-# CONFIG_TCP_CONG_VEGAS is not set
-# CONFIG_TCP_CONG_SCALABLE is not set
 # CONFIG_IPV6 is not set
 # CONFIG_NETFILTER is not set
 
@@ -931,4 +922,3 @@
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
-# CONFIG_TEXTSEARCH is not set
diff -urN linux/arch/arm/configs/ixdp2400_defconfig 
linux/arch/arm/configs/ixdp2400_defconfig
--- linux/arch/arm/configs/ixdp2400_defconfig   2005/07/11 20:45:59     1.3
+++ linux/arch/arm/configs/ixdp2400_defconfig   2005/07/13 11:48:50     1.4
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-git6
-# Sat Jun 25 00:58:38 2005
+# Linux kernel version: 2.6.13-rc2
+# Thu Jul  7 16:49:01 2005
 #
 CONFIG_ARM=y
 CONFIG_MMU=y
@@ -138,6 +138,7 @@
 #
 # CONFIG_SMP is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
@@ -346,10 +347,9 @@
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_FIB_TRIE is not set
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -364,17 +364,8 @@
 # CONFIG_INET_TUNNEL is not set
 # CONFIG_IP_TCPDIAG is not set
 # CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# TCP congestion control
-#
+# CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_BIC=y
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-# CONFIG_TCP_CONG_HSTCP is not set
-# CONFIG_TCP_CONG_HYBLA is not set
-# CONFIG_TCP_CONG_VEGAS is not set
-# CONFIG_TCP_CONG_SCALABLE is not set
 # CONFIG_IPV6 is not set
 # CONFIG_NETFILTER is not set
 
@@ -932,4 +923,3 @@
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
-# CONFIG_TEXTSEARCH is not set
diff -urN linux/arch/arm/configs/ixdp2401_defconfig 
linux/arch/arm/configs/ixdp2401_defconfig
--- linux/arch/arm/configs/ixdp2401_defconfig   2005/07/11 20:45:59     1.3
+++ linux/arch/arm/configs/ixdp2401_defconfig   2005/07/13 11:48:50     1.4
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-git6
-# Sat Jun 25 00:59:35 2005
+# Linux kernel version: 2.6.13-rc2
+# Thu Jul  7 16:49:08 2005
 #
 CONFIG_ARM=y
 CONFIG_MMU=y
@@ -138,6 +138,7 @@
 #
 # CONFIG_SMP is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
@@ -346,10 +347,9 @@
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_FIB_TRIE is not set
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -364,17 +364,8 @@
 # CONFIG_INET_TUNNEL is not set
 CONFIG_IP_TCPDIAG=y
 # CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# TCP congestion control
-#
+# CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_BIC=y
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-# CONFIG_TCP_CONG_HSTCP is not set
-# CONFIG_TCP_CONG_HYBLA is not set
-# CONFIG_TCP_CONG_VEGAS is not set
-# CONFIG_TCP_CONG_SCALABLE is not set
 # CONFIG_IPV6 is not set
 # CONFIG_NETFILTER is not set
 
@@ -933,4 +924,3 @@
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
-# CONFIG_TEXTSEARCH is not set
diff -urN linux/arch/arm/configs/ixdp2800_defconfig 
linux/arch/arm/configs/ixdp2800_defconfig
--- linux/arch/arm/configs/ixdp2800_defconfig   2005/07/11 20:45:59     1.4
+++ linux/arch/arm/configs/ixdp2800_defconfig   2005/07/13 11:48:50     1.5
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-git6
-# Sat Jun 25 01:00:27 2005
+# Linux kernel version: 2.6.13-rc2
+# Thu Jul  7 16:49:20 2005
 #
 CONFIG_ARM=y
 CONFIG_MMU=y
@@ -138,6 +138,7 @@
 #
 # CONFIG_SMP is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
@@ -346,10 +347,9 @@
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_FIB_TRIE is not set
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -364,17 +364,8 @@
 # CONFIG_INET_TUNNEL is not set
 # CONFIG_IP_TCPDIAG is not set
 # CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# TCP congestion control
-#
+# CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_BIC=y
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-# CONFIG_TCP_CONG_HSTCP is not set
-# CONFIG_TCP_CONG_HYBLA is not set
-# CONFIG_TCP_CONG_VEGAS is not set
-# CONFIG_TCP_CONG_SCALABLE is not set
 # CONFIG_IPV6 is not set
 # CONFIG_NETFILTER is not set
 
@@ -932,4 +923,3 @@
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
-# CONFIG_TEXTSEARCH is not set
diff -urN linux/arch/arm/configs/ixdp2801_defconfig 
linux/arch/arm/configs/ixdp2801_defconfig
--- linux/arch/arm/configs/ixdp2801_defconfig   2005/07/11 20:45:59     1.3
+++ linux/arch/arm/configs/ixdp2801_defconfig   2005/07/13 11:48:50     1.4
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-git6
-# Sat Jun 25 01:01:18 2005
+# Linux kernel version: 2.6.13-rc2
+# Thu Jul  7 16:49:13 2005
 #
 CONFIG_ARM=y
 CONFIG_MMU=y
@@ -138,6 +138,7 @@
 #
 # CONFIG_SMP is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
@@ -346,10 +347,9 @@
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_FIB_TRIE is not set
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -364,17 +364,8 @@
 # CONFIG_INET_TUNNEL is not set
 # CONFIG_IP_TCPDIAG is not set
 # CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# TCP congestion control
-#
+# CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_BIC=y
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-# CONFIG_TCP_CONG_HSTCP is not set
-# CONFIG_TCP_CONG_HYBLA is not set
-# CONFIG_TCP_CONG_VEGAS is not set
-# CONFIG_TCP_CONG_SCALABLE is not set
 # CONFIG_IPV6 is not set
 # CONFIG_NETFILTER is not set
 
@@ -933,4 +924,3 @@
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
-# CONFIG_TEXTSEARCH is not set
diff -urN linux/arch/arm/configs/omap_h2_1610_defconfig 
linux/arch/arm/configs/omap_h2_1610_defconfig
--- linux/arch/arm/configs/omap_h2_1610_defconfig       2005/04/08 18:57:49     
1.2
+++ linux/arch/arm/configs/omap_h2_1610_defconfig       2005/07/13 11:48:50     
1.3
@@ -1,14 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc1-bk2
-# Sun Mar 27 17:52:41 2005
+# Linux kernel version: 2.6.13-rc2
+# Fri Jul  8 04:49:34 2005
 #
 CONFIG_ARM=y
 CONFIG_MMU=y
 CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_IOMAP=y
 
 #
 # Code maturity level options
@@ -17,6 +16,7 @@
 CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
 
 #
 # General setup
@@ -33,8 +33,9 @@
 # CONFIG_IKCONFIG is not set
 # CONFIG_EMBEDDED is not set
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
@@ -82,10 +83,28 @@
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_IMX is not set
 # CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_AAEC2000 is not set
 
 #
 # TI OMAP Implementations
 #
+CONFIG_ARCH_OMAP_OTG=y
+CONFIG_ARCH_OMAP1=y
+# CONFIG_ARCH_OMAP2 is not set
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_MUX=y
+# CONFIG_OMAP_MUX_DEBUG is not set
+CONFIG_OMAP_MUX_WARNINGS=y
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
 
 #
 # OMAP Core Type
@@ -93,7 +112,6 @@
 # CONFIG_ARCH_OMAP730 is not set
 # CONFIG_ARCH_OMAP1510 is not set
 CONFIG_ARCH_OMAP16XX=y
-CONFIG_ARCH_OMAP_OTG=y
 
 #
 # OMAP Board Type
@@ -101,21 +119,14 @@
 # CONFIG_MACH_OMAP_INNOVATOR is not set
 CONFIG_MACH_OMAP_H2=y
 # CONFIG_MACH_OMAP_H3 is not set
-# CONFIG_MACH_OMAP_H4 is not set
 # CONFIG_MACH_OMAP_OSK is not set
 # CONFIG_MACH_OMAP_GENERIC is not set
 
 #
-# OMAP Feature Selections
+# OMAP CPU Speed
 #
-CONFIG_OMAP_MUX=y
-# CONFIG_OMAP_MUX_DEBUG is not set
-CONFIG_OMAP_MUX_WARNINGS=y
-CONFIG_OMAP_MPU_TIMER=y
-# CONFIG_OMAP_32K_TIMER is not set
-CONFIG_OMAP_LL_DEBUG_UART1=y
-# CONFIG_OMAP_LL_DEBUG_UART2 is not set
-# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set
+# CONFIG_OMAP_ARM_216MHZ is not set
 CONFIG_OMAP_ARM_192MHZ=y
 # CONFIG_OMAP_ARM_168MHZ is not set
 # CONFIG_OMAP_ARM_120MHZ is not set
@@ -145,6 +156,7 @@
 #
 # Bus support
 #
+CONFIG_ISA_DMA_API=y
 
 #
 # PCCARD (PCMCIA/CardBus) support
@@ -154,7 +166,16 @@
 #
 # Kernel Features
 #
+# CONFIG_SMP is not set
 CONFIG_PREEMPT=y
+CONFIG_NO_IDLE_HZ=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -167,6 +188,22 @@
 # CONFIG_XIP_KERNEL is not set
 
 #
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+
+#
 # Floating point emulation
 #
 
@@ -202,7 +239,6 @@
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
-CONFIG_DEBUG_DRIVER=y
 
 #
 # Memory Technology Devices (MTD)
@@ -292,7 +328,6 @@
 #
 # Block devices
 #
-# CONFIG_BLK_DEV_FD is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -327,6 +362,7 @@
 # CONFIG_CHR_DEV_OSST is not set
 # CONFIG_BLK_DEV_SR is not set
 # CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
 
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -356,6 +392,7 @@
 #
 # Fusion MPT device support
 #
+# CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
@@ -375,12 +412,12 @@
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -395,6 +432,8 @@
 # CONFIG_INET_TUNNEL is not set
 CONFIG_IP_TCPDIAG=y
 # CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
 # CONFIG_IPV6 is not set
 # CONFIG_NETFILTER is not set
 
@@ -442,6 +481,7 @@
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
 
 #
 # Ethernet (1000 Mbit)
@@ -518,7 +558,6 @@
 CONFIG_SERIO_SERPORT=y
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
@@ -567,13 +606,11 @@
 #
 # Ftape, the floppy tape device driver
 #
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
 
 #
 # TPM devices
 #
-# CONFIG_TCG_TPM is not set
 
 #
 # I2C support
@@ -604,7 +641,9 @@
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
 # CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
 # CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_FSCHER is not set
 # CONFIG_SENSORS_FSCPOS is not set
@@ -620,6 +659,7 @@
 # CONFIG_SENSORS_LM85 is not set
 # CONFIG_SENSORS_LM87 is not set
 # CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
@@ -627,15 +667,21 @@
 # CONFIG_SENSORS_W83781D is not set
 # CONFIG_SENSORS_W83L785TS is not set
 # CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
 
 #
 # Other I2C Chip support
 #
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_RTC8564 is not set
 CONFIG_ISP1301_OMAP=y
+CONFIG_TPS65010=y
+# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -663,8 +709,10 @@
 # CONFIG_FB_CFB_COPYAREA is not set
 # CONFIG_FB_CFB_IMAGEBLIT is not set
 # CONFIG_FB_SOFT_CURSOR is not set
+# CONFIG_FB_MACMODES is not set
 CONFIG_FB_MODE_HELPERS=y
 # CONFIG_FB_TILEBLITTING is not set
+# CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
 
 #
@@ -677,11 +725,13 @@
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
 # CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
 # CONFIG_FONT_PEARL_8x8 is not set
 # CONFIG_FONT_ACORN_8x8 is not set
 # CONFIG_FONT_MINI_4x6 is not set
 # CONFIG_FONT_SUN8x16 is not set
 # CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
 
 #
 # Logo configuration
@@ -729,14 +779,14 @@
 #
 CONFIG_USB_GADGET=y
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_PXA2XX is not set
 # CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_SA1100 is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_OMAP=y
 CONFIG_USB_OMAP=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
 # CONFIG_USB_GADGET_DUALSPEED is not set
 # CONFIG_USB_ZERO is not set
 CONFIG_USB_ETH=y
@@ -755,6 +805,7 @@
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_REISERFS_FS is not set
@@ -791,7 +842,6 @@
 #
 CONFIG_PROC_FS=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
 # CONFIG_DEVPTS_FS_XATTR is not set
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
@@ -828,12 +878,14 @@
 #
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
 CONFIG_RPCSEC_GSS_KRB5=y
@@ -903,24 +955,11 @@
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_KERNEL is not set
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-CONFIG_DEBUG_PREEMPT=y
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_FS is not set
 CONFIG_FRAME_POINTER=y
-CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_WAITQ is not set
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_USER is not set
 
 #
 # Security options
diff -urN linux/arch/arm/kernel/armksyms.c linux/arch/arm/kernel/armksyms.c
--- linux/arch/arm/kernel/armksyms.c    2005/07/12 09:18:55     1.45
+++ linux/arch/arm/kernel/armksyms.c    2005/07/13 11:48:50     1.46
@@ -41,7 +41,10 @@
  * This has a special calling convention; it doesn't
  * modify any of the usual registers, except for LR.
  */
+#define EXPORT_CRC_ALIAS(sym) __CRC_SYMBOL(sym, "")
+
 #define EXPORT_SYMBOL_ALIAS(sym,orig)          \
+ EXPORT_CRC_ALIAS(sym)                         \
  const struct kernel_symbol __ksymtab_##sym    \
   __attribute__((section("__ksymtab"))) =      \
     { (unsigned long)&orig, #sym };
diff -urN linux/arch/arm/mach-ixp2000/core.c linux/arch/arm/mach-ixp2000/core.c
--- linux/arch/arm/mach-ixp2000/core.c  2005/07/11 20:46:02     1.10
+++ linux/arch/arm/mach-ixp2000/core.c  2005/07/13 11:48:50     1.11
@@ -23,7 +23,7 @@
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/bitops.h>
-#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <linux/mm.h>
 
 #include <asm/types.h>
@@ -125,19 +125,6 @@
        }
 };
 
-static struct uart_port ixp2000_serial_port = {
-       .membase        = (char *)(IXP2000_UART_VIRT_BASE + 3),
-       .mapbase        = IXP2000_UART_PHYS_BASE + 3,
-       .irq            = IRQ_IXP2000_UART,
-       .flags          = UPF_SKIP_TEST,
-       .iotype         = UPIO_MEM,
-       .regshift       = 2,
-       .uartclk        = 50000000,
-       .line           = 0,
-       .type           = PORT_XSCALE,
-       .fifosize       = 16
-};
-
 void __init ixp2000_map_io(void)
 {
        extern unsigned int processor_id;
@@ -157,12 +144,50 @@
        }
 
        iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
-       early_serial_setup(&ixp2000_serial_port);
 
        /* Set slowport to 8-bit mode.  */
        ixp2000_reg_write(IXP2000_SLOWPORT_FRM, 1);
 }
 
+
+/*************************************************************************
+ * Serial port support for IXP2000
+ *************************************************************************/
+static struct plat_serial8250_port ixp2000_serial_port[] = {
+       {
+               .mapbase        = IXP2000_UART_PHYS_BASE,
+               .membase        = (char *)(IXP2000_UART_VIRT_BASE + 3),
+               .irq            = IRQ_IXP2000_UART,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = 50000000,
+       },
+       { },
+};
+
+static struct resource ixp2000_uart_resource = {
+       .start          = IXP2000_UART_PHYS_BASE,
+       .end            = IXP2000_UART_PHYS_BASE + 0xffff,
+       .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device ixp2000_serial_device = {
+       .name           = "serial8250",
+       .id             = 0,
+       .dev            = {
+               .platform_data          = ixp2000_serial_port,
+       },
+       .num_resources  = 1,
+       .resource       = &ixp2000_uart_resource,
+};
+
+void __init ixp2000_uart_init(void)
+{
+       platform_device_register(&ixp2000_serial_device);
+}
+
+
 /*************************************************************************
  * Timer-tick functions for IXP2000
  *************************************************************************/
diff -urN linux/arch/arm/mach-ixp2000/enp2611.c 
linux/arch/arm/mach-ixp2000/enp2611.c
--- linux/arch/arm/mach-ixp2000/enp2611.c       2005/07/12 09:18:57     1.9
+++ linux/arch/arm/mach-ixp2000/enp2611.c       2005/07/13 11:48:50     1.10
@@ -219,6 +219,7 @@
 static void __init enp2611_init_machine(void)
 {
        platform_add_devices(enp2611_devices, ARRAY_SIZE(enp2611_devices));
+       ixp2000_uart_init();
 }
 
 
diff -urN linux/arch/arm/mach-ixp2000/ixdp2x00.c 
linux/arch/arm/mach-ixp2000/ixdp2x00.c
--- linux/arch/arm/mach-ixp2000/ixdp2x00.c      2005/07/11 20:46:02     1.5
+++ linux/arch/arm/mach-ixp2000/ixdp2x00.c      2005/07/13 11:48:50     1.6
@@ -303,5 +303,6 @@
        gpio_line_config(IXDP2X00_GPIO_I2C_ENABLE, GPIO_OUT);
 
        platform_add_devices(ixdp2x00_devices, ARRAY_SIZE(ixdp2x00_devices));
+       ixp2000_uart_init();
 }
 
diff -urN linux/arch/arm/mach-ixp2000/ixdp2x01.c 
linux/arch/arm/mach-ixp2000/ixdp2x01.c
--- linux/arch/arm/mach-ixp2000/ixdp2x01.c      2005/07/12 09:18:57     1.6
+++ linux/arch/arm/mach-ixp2000/ixdp2x01.c      2005/07/13 11:48:50     1.7
@@ -370,6 +370,7 @@
                ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 
1);
 
        platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
+       ixp2000_uart_init();
 }
 
 
diff -urN linux/arch/arm/mach-ixp4xx/common-pci.c 
linux/arch/arm/mach-ixp4xx/common-pci.c
--- linux/arch/arm/mach-ixp4xx/common-pci.c     2005/05/19 12:08:07     1.8
+++ linux/arch/arm/mach-ixp4xx/common-pci.c     2005/07/13 11:48:50     1.9
@@ -453,8 +453,8 @@
        local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | 
PCI_COMMAND_MEMORY);
 
        res[0].name = "PCI I/O Space";
-       res[0].start = 0x00001000;
-       res[0].end = 0xffff0000;
+       res[0].start = 0x00000000;
+       res[0].end = 0x0000ffff;
        res[0].flags = IORESOURCE_IO;
 
        res[1].name = "PCI Memory Space";
diff -urN linux/arch/arm/mach-ixp4xx/coyote-setup.c 
linux/arch/arm/mach-ixp4xx/coyote-setup.c
--- linux/arch/arm/mach-ixp4xx/coyote-setup.c   2005/07/12 09:18:57     1.9
+++ linux/arch/arm/mach-ixp4xx/coyote-setup.c   2005/07/13 11:48:50     1.10
@@ -56,21 +56,24 @@
        .flags  = IORESOURCE_MEM,
 };
 
-static struct plat_serial8250_port coyote_uart_data = {
-       .mapbase        = IXP4XX_UART2_BASE_PHYS,
-       .membase        = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
-       .irq            = IRQ_IXP4XX_UART2,
-       .flags          = UPF_BOOT_AUTOCONF,
-       .iotype         = UPIO_MEM,
-       .regshift       = 2,
-       .uartclk        = IXP4XX_UART_XTAL,
+static struct plat_serial8250_port coyote_uart_data[] = {
+       {
+               .mapbase        = IXP4XX_UART2_BASE_PHYS,
+               .membase        = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+               .irq            = IRQ_IXP4XX_UART2,
+               .flags          = UPF_BOOT_AUTOCONF,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = IXP4XX_UART_XTAL,
+       },
+       { },
 };
 
 static struct platform_device coyote_uart = {
        .name           = "serial8250",
        .id             = 0,
        .dev                    = {
-               .platform_data  = &coyote_uart_data,
+               .platform_data  = coyote_uart_data,
        },
        .num_resources  = 1,
        .resource       = &coyote_uart_resource,
@@ -87,10 +90,10 @@
        *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
 
        if (machine_is_ixdpg425()) {
-               coyote_uart_data.membase =
+               coyote_uart_data[0].membase =
                        (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET);
-               coyote_uart_data.mapbase = IXP4XX_UART1_BASE_PHYS;
-               coyote_uart_data.irq = IRQ_IXP4XX_UART1;
+               coyote_uart_data[0].mapbase = IXP4XX_UART1_BASE_PHYS;
+               coyote_uart_data[0].irq = IRQ_IXP4XX_UART1;
        }
 
 
diff -urN linux/arch/arm/mach-ixp4xx/ixdp425-setup.c 
linux/arch/arm/mach-ixp4xx/ixdp425-setup.c
--- linux/arch/arm/mach-ixp4xx/ixdp425-setup.c  2005/07/12 09:18:57     1.8
+++ linux/arch/arm/mach-ixp4xx/ixdp425-setup.c  2005/07/13 11:48:50     1.9
@@ -95,7 +95,8 @@
                .iotype         = UPIO_MEM,
                .regshift       = 2,
                .uartclk        = IXP4XX_UART_XTAL,
-       }
+       },
+       { },
 };
 
 static struct platform_device ixdp425_uart = {
diff -urN linux/arch/arm/mach-omap/Kconfig linux/arch/arm/mach-omap/Kconfig
--- linux/arch/arm/mach-omap/Attic/Kconfig      2005-07-13 12:48:51.535511000 
+0100     1.6
+++ linux/arch/arm/mach-omap/Attic/Kconfig      1970/01/01 00:00:00+0100
@@ -1,221 +0,0 @@
-if ARCH_OMAP
-
-menu "TI OMAP Implementations"
-
-comment "OMAP Core Type"
-
-config ARCH_OMAP730
-       depends on ARCH_OMAP
-       bool "OMAP730 Based System"
-       select ARCH_OMAP_OTG
-
-config ARCH_OMAP1510
-       depends on ARCH_OMAP
-       default y
-       bool "OMAP1510 Based System"
-
-config ARCH_OMAP16XX
-       depends on ARCH_OMAP
-       bool "OMAP16XX Based System"
-       select ARCH_OMAP_OTG
-
-config ARCH_OMAP_OTG
-       bool
-
-comment "OMAP Board Type"
-
-config MACH_OMAP_INNOVATOR
-       bool "TI Innovator"
-       depends on ARCH_OMAP1510 || ARCH_OMAP16XX
-       help
-          TI OMAP 1510 or 1610 Innovator board support. Say Y here if you
-          have such a board.
-
-config MACH_OMAP_H2
-       bool "TI H2 Support"
-       depends on ARCH_OMAP16XX
-       help
-         TI OMAP 1610/1611B H2 board support. Say Y here if you have such
-         a board.
-
-config MACH_OMAP_H3
-       bool "TI H3 Support"
-       depends on ARCH_OMAP16XX
-       help
-         TI OMAP 1710 H3 board support. Say Y here if you have such
-         a board.
-
-config MACH_OMAP_H4
-       bool "TI H4 Support"
-       depends on ARCH_OMAP16XX
-       help
-         TI OMAP 1610 H4 board support. Say Y here if you have such
-         a board.
-
-config MACH_OMAP_OSK
-       bool "TI OSK Support"
-       depends on ARCH_OMAP16XX
-       help
-         TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here
-          if you have such a board.
-
-config MACH_OMAP_PERSEUS2
-       bool "TI Perseus2"
-       depends on ARCH_OMAP730
-       help
-         Support for TI OMAP 730 Perseus2 board. Say Y here if you have such
-         a board.
-
-config MACH_VOICEBLUE
-       bool "Voiceblue"
-       depends on ARCH_OMAP1510
-       help
-         Support for Voiceblue GSM/VoIP gateway. Say Y here if you have such
-         board.
-
-config MACH_NETSTAR
-       bool "NetStar"
-       depends on ARCH_OMAP1510
-       help
-         Support for NetStar PBX. Say Y here if you have such a board.
-
-config MACH_OMAP_GENERIC
-       bool "Generic OMAP board"
-       depends on ARCH_OMAP1510 || ARCH_OMAP16XX
-       help
-          Support for generic OMAP-1510, 1610 or 1710 board with
-          no FPGA. Can be used as template for porting Linux to
-          custom OMAP boards. Say Y here if you have a custom
-          board.
-
-comment "OMAP Feature Selections"
-
-#config OMAP_BOOT_TAG
-#      bool "OMAP bootloader information passing"
-#        depends on ARCH_OMAP
-#        default n
-#        help
-#          Say Y, if you have a bootloader which passes information
-#          about your board and its peripheral configuration.
-
-config OMAP_MUX
-       bool "OMAP multiplexing support"
-        depends on ARCH_OMAP
-       default y
-        help
-          Pin multiplexing support for OMAP boards. If your bootloader
-          sets the multiplexing correctly, say N. Otherwise, or if unsure,
-          say Y.
-
-config OMAP_MUX_DEBUG
-       bool "Multiplexing debug output"
-        depends on OMAP_MUX
-        default n
-        help
-          Makes the multiplexing functions print out a lot of debug info.
-          This is useful if you want to find out the correct values of the
-          multiplexing registers.
-
-config OMAP_MUX_WARNINGS
-       bool "Warn about pins the bootloader didn't set up"
-        depends on OMAP_MUX
-        default y
-        help
-         Choose Y here to warn whenever driver initialization logic needs
-         to change the pin multiplexing setup.  When there are no warnings
-         printed, it's safe to deselect OMAP_MUX for your product.
-
-choice
-        prompt "System timer"
-       default OMAP_MPU_TIMER
-
-config OMAP_MPU_TIMER
-       bool "Use mpu timer"
-       help
-         Select this option if you want to use the OMAP mpu timer. This
-         timer provides more intra-tick resolution than the 32KHz timer,
-         but consumes more power.
-
-config OMAP_32K_TIMER
-       bool "Use 32KHz timer"
-       depends on ARCH_OMAP16XX
-       help
-         Select this option if you want to enable the OMAP 32KHz timer.
-         This timer saves power compared to the OMAP_MPU_TIMER, and has
-         support for no tick during idle. The 32KHz timer provides less
-         intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
-         currently only available for OMAP-16xx.
-
-endchoice
-
-config OMAP_32K_TIMER_HZ
-       int "Kernel internal timer frequency for 32KHz timer"
-       range 32 1024
-       depends on OMAP_32K_TIMER
-       default "128"
-       help
-         Kernel internal timer frequency should be a divisor of 32768,
-         such as 64 or 128.
-
-choice
-       prompt "Low-level debug console UART"
-       depends on ARCH_OMAP
-       default OMAP_LL_DEBUG_UART1
-
-config OMAP_LL_DEBUG_UART1
-       bool "UART1"
-
-config OMAP_LL_DEBUG_UART2
-       bool "UART2"
-
-config OMAP_LL_DEBUG_UART3
-       bool "UART3"
-
-endchoice
-
-config OMAP_ARM_195MHZ
-       bool "OMAP ARM 195 MHz CPU"
-       depends on ARCH_OMAP730
-       help
-          Enable 195MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_192MHZ
-       bool "OMAP ARM 192 MHz CPU"
-       depends on ARCH_OMAP16XX
-       help
-          Enable 192MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_182MHZ
-       bool "OMAP ARM 182 MHz CPU"
-       depends on ARCH_OMAP730
-       help
-          Enable 182MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_168MHZ
-       bool "OMAP ARM 168 MHz CPU"
-       depends on ARCH_OMAP1510 || ARCH_OMAP16XX || ARCH_OMAP730
-       help
-          Enable 168MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_120MHZ
-       bool "OMAP ARM 120 MHz CPU"
-       depends on ARCH_OMAP1510 || ARCH_OMAP16XX || ARCH_OMAP730
-       help
-          Enable 120MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_60MHZ
-       bool "OMAP ARM 60 MHz CPU"
-       depends on ARCH_OMAP1510 || ARCH_OMAP16XX || ARCH_OMAP730
-        default y
-       help
-          Enable 60MHz clock for OMAP CPU. If unsure, say Y.
-
-config OMAP_ARM_30MHZ
-       bool "OMAP ARM 30 MHz CPU"
-       depends on ARCH_OMAP1510 || ARCH_OMAP16XX || ARCH_OMAP730
-       help
-          Enable 30MHz clock for OMAP CPU. If unsure, say N.
-
-endmenu
-
-endif
diff -urN linux/arch/arm/mach-omap/Makefile linux/arch/arm/mach-omap/Makefile
--- linux/arch/arm/mach-omap/Attic/Makefile     2005-07-13 12:48:51.580514000 
+0100     1.6
+++ linux/arch/arm/mach-omap/Attic/Makefile     1970/01/01 00:00:00+0100
@@ -1,40 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Common support
-obj-y := common.o time.o irq.o dma.o clock.o mux.o gpio.o mcbsp.o usb.o
-obj-m :=
-obj-n :=
-obj-  :=
-led-y := leds.o
-
-# Specific board support
-obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o
-obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o
-obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
-obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o
-obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o
-obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o
-obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o
-obj-$(CONFIG_MACH_NETSTAR) += board-netstar.o
-
-# OCPI interconnect support for 1710, 1610 and 5912
-obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
-
-# LEDs support
-led-$(CONFIG_MACH_OMAP_H2) += leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_INNOVATOR) += leds-innovator.o
-led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-h2p2-debug.o
-obj-$(CONFIG_LEDS) += $(led-y)
-
-# Power Management
-obj-$(CONFIG_PM) += pm.o sleep.o
-
-ifeq ($(CONFIG_ARCH_OMAP1510),y)
-# Innovator-1510 FPGA
-obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o
-endif
-
-# kgdb support
-obj-$(CONFIG_KGDB_SERIAL)      += kgdb-serial.o
diff -urN linux/arch/arm/mach-omap/Makefile.boot 
linux/arch/arm/mach-omap/Makefile.boot
--- linux/arch/arm/mach-omap/Attic/Makefile.boot        2005-07-13 
12:48:51.620473000 +0100     1.1
+++ linux/arch/arm/mach-omap/Attic/Makefile.boot        1970/01/01 00:00:00+0100
@@ -1,4 +0,0 @@
-   zreladdr-y          := 0x10008000
-params_phys-y          := 0x10000100
-initrd_phys-y          := 0x10800000
-
diff -urN linux/arch/arm/mach-omap/board-generic.c 
linux/arch/arm/mach-omap/board-generic.c
--- linux/arch/arm/mach-omap/Attic/board-generic.c      2005-07-13 
12:48:51.651914000 +0100     1.9
+++ linux/arch/arm/mach-omap/Attic/board-generic.c      1970/01/01 00:00:00+0100
@@ -1,100 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/board-generic.c
- *
- * Modified from board-innovator1510.c
- *
- * Code for generic OMAP board. Should work on many OMAP systems where
- * the device drivers take care of all the necessary hardware initialization.
- * Do not put any board specific code to this file; create a new machine
- * type if you need custom low-level initializations.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-
-#include <asm/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/board.h>
-
-#include "common.h"
-
-static int __initdata generic_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
-
-static void __init omap_generic_init_irq(void)
-{
-       omap_init_irq();
-}
-
-/* assume no Mini-AB port */
-
-#ifdef CONFIG_ARCH_OMAP1510
-static struct omap_usb_config generic1510_usb_config __initdata = {
-       .register_host  = 1,
-       .register_dev   = 1,
-       .hmc_mode       = 16,
-       .pins[0]        = 3,
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-static struct omap_usb_config generic1610_usb_config __initdata = {
-       .register_host  = 1,
-       .register_dev   = 1,
-       .hmc_mode       = 16,
-       .pins[0]        = 6,
-};
-#endif
-
-static struct omap_board_config_kernel generic_config[] = {
-       { OMAP_TAG_USB,           NULL },
-};
-
-static void __init omap_generic_init(void)
-{
-       /*
-        * Make sure the serial ports are muxed on at this point.
-        * You have to mux them off in device drivers later on
-        * if not needed.
-        */
-#ifdef CONFIG_ARCH_OMAP1510
-       if (cpu_is_omap1510()) {
-               generic_config[0].data = &generic1510_usb_config;
-       }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-       if (!cpu_is_omap1510()) {
-               generic_config[0].data = &generic1610_usb_config;
-       }
-#endif
-       omap_board_config = generic_config;
-       omap_board_config_size = ARRAY_SIZE(generic_config);
-       omap_serial_init(generic_serial_ports);
-}
-
-static void __init omap_generic_map_io(void)
-{
-       omap_map_io();
-}
-
-MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
-       /* Maintainer: Tony Lindgren <tony@atomide.com> */
-       .phys_ram       = 0x10000000,
-       .phys_io        = 0xfff00000,
-       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
-       .boot_params    = 0x10000100,
-       .map_io         = omap_generic_map_io,
-       .init_irq       = omap_generic_init_irq,
-       .init_machine   = omap_generic_init,
-       .timer          = &omap_timer,
-MACHINE_END
diff -urN linux/arch/arm/mach-omap/board-h2.c 
linux/arch/arm/mach-omap/board-h2.c
--- linux/arch/arm/mach-omap/Attic/board-h2.c   2005-07-13 12:48:51.703129000 
+0100     1.6
+++ linux/arch/arm/mach-omap/Attic/board-h2.c   1970/01/01 00:00:00+0100
@@ -1,189 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/board-h2.c
- *
- * Board specific inits for OMAP-1610 H2
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Copyright (C) 2002 MontaVista Software, Inc.
- *
- * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
- * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
- *
- * H2 specific changes and cleanup
- * Copyright (C) 2004 Nokia Corporation by Imre Deak <imre.deak@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/map.h>
-
-#include <asm/arch/gpio.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/usb.h>
-
-#include "common.h"
-
-extern int omap_gpio_init(void);
-
-static int __initdata h2_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
-
-static struct mtd_partition h2_partitions[] = {
-       /* bootloader (U-Boot, etc) in first sector */
-       {
-             .name             = "bootloader",
-             .offset           = 0,
-             .size             = SZ_128K,
-             .mask_flags       = MTD_WRITEABLE, /* force read-only */
-       },
-       /* bootloader params in the next sector */
-       {
-             .name             = "params",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = SZ_128K,
-             .mask_flags       = 0,
-       },
-       /* kernel */
-       {
-             .name             = "kernel",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = SZ_2M,
-             .mask_flags       = 0
-       },
-       /* file system */
-       {
-             .name             = "filesystem",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = MTDPART_SIZ_FULL,
-             .mask_flags       = 0
-       }
-};
-
-static struct flash_platform_data h2_flash_data = {
-       .map_name       = "cfi_probe",
-       .width          = 2,
-       .parts          = h2_partitions,
-       .nr_parts       = ARRAY_SIZE(h2_partitions),
-};
-
-static struct resource h2_flash_resource = {
-       .start          = OMAP_CS2B_PHYS,
-       .end            = OMAP_CS2B_PHYS + OMAP_CS2B_SIZE - 1,
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device h2_flash_device = {
-       .name           = "omapflash",
-       .id             = 0,
-       .dev            = {
-               .platform_data  = &h2_flash_data,
-       },
-       .num_resources  = 1,
-       .resource       = &h2_flash_resource,
-};
-
-static struct resource h2_smc91x_resources[] = {
-       [0] = {
-               .start  = OMAP1610_ETHR_START,          /* Physical */
-               .end    = OMAP1610_ETHR_START + 0xf,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = OMAP_GPIO_IRQ(0),
-               .end    = OMAP_GPIO_IRQ(0),
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device h2_smc91x_device = {
-       .name           = "smc91x",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(h2_smc91x_resources),
-       .resource       = h2_smc91x_resources,
-};
-
-static struct platform_device *h2_devices[] __initdata = {
-       &h2_flash_device,
-       &h2_smc91x_device,
-};
-
-static void __init h2_init_smc91x(void)
-{
-       if ((omap_request_gpio(0)) < 0) {
-               printk("Error requesting gpio 0 for smc91x irq\n");
-               return;
-       }
-       omap_set_gpio_edge_ctrl(0, OMAP_GPIO_FALLING_EDGE);
-}
-
-void h2_init_irq(void)
-{
-       omap_init_irq();
-       omap_gpio_init();
-       h2_init_smc91x();
-}
-
-static struct omap_usb_config h2_usb_config __initdata = {
-       /* usb1 has a Mini-AB port and external isp1301 transceiver */
-       .otg            = 2,
-
-#ifdef CONFIG_USB_GADGET_OMAP
-       .hmc_mode       = 19,   // 0:host(off) 1:dev|otg 2:disabled
-       // .hmc_mode    = 21,   // 0:host(off) 1:dev(loopback) 2:host(loopback)
-#elif  defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-       /* needs OTG cable, or NONSTANDARD (B-to-MiniB) */
-       .hmc_mode       = 20,   // 1:dev|otg(off) 1:host 2:disabled
-#endif
-
-       .pins[1]        = 3,
-};
-
-static struct omap_mmc_config h2_mmc_config __initdata = {
-       .mmc_blocks             = 1,
-       .mmc1_power_pin         = -1,   /* tps65010 gpio3 */
-       .mmc1_switch_pin        = OMAP_MPUIO(1),
-};
-
-static struct omap_board_config_kernel h2_config[] = {
-       { OMAP_TAG_USB,           &h2_usb_config },
-       { OMAP_TAG_MMC,           &h2_mmc_config },
-};
-
-static void __init h2_init(void)
-{
-       platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
-       omap_board_config = h2_config;
-       omap_board_config_size = ARRAY_SIZE(h2_config);
-}
-
-static void __init h2_map_io(void)
-{
-       omap_map_io();
-       omap_serial_init(h2_serial_ports);
-}
-
-MACHINE_START(OMAP_H2, "TI-H2")
-       /* Maintainer: Imre Deak <imre.deak@nokia.com> */
-       .phys_ram       = 0x10000000,
-       .phys_io        = 0xfff00000,
-       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
-       .boot_params    = 0x10000100,
-       .map_io         = h2_map_io,
-       .init_irq       = h2_init_irq,
-       .init_machine   = h2_init,
-       .timer          = &omap_timer,
-MACHINE_END
diff -urN linux/arch/arm/mach-omap/board-h3.c 
linux/arch/arm/mach-omap/board-h3.c
--- linux/arch/arm/mach-omap/Attic/board-h3.c   2005-07-13 12:48:51.750075000 
+0100     1.6
+++ linux/arch/arm/mach-omap/Attic/board-h3.c   1970/01/01 00:00:00+0100
@@ -1,207 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/board-h3.c
- *
- * This file contains OMAP1710 H3 specific code.
- *
- * Copyright (C) 2004 Texas Instruments, Inc.
- * Copyright (C) 2002 MontaVista Software, Inc.
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: RidgeRun, Inc.
- *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/config.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/major.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/map.h>
-
-#include <asm/arch/gpio.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/usb.h>
-
-#include "common.h"
-
-extern int omap_gpio_init(void);
-
-static int __initdata h3_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
-
-static struct mtd_partition h3_partitions[] = {
-       /* bootloader (U-Boot, etc) in first sector */
-       {
-             .name             = "bootloader",
-             .offset           = 0,
-             .size             = SZ_128K,
-             .mask_flags       = MTD_WRITEABLE, /* force read-only */
-       },
-       /* bootloader params in the next sector */
-       {
-             .name             = "params",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = SZ_128K,
-             .mask_flags       = 0,
-       },
-       /* kernel */
-       {
-             .name             = "kernel",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = SZ_2M,
-             .mask_flags       = 0
-       },
-       /* file system */
-       {
-             .name             = "filesystem",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = MTDPART_SIZ_FULL,
-             .mask_flags       = 0
-       }
-};
-
-static struct flash_platform_data h3_flash_data = {
-       .map_name       = "cfi_probe",
-       .width          = 2,
-       .parts          = h3_partitions,
-       .nr_parts       = ARRAY_SIZE(h3_partitions),
-};
-
-static struct resource h3_flash_resource = {
-       .start          = OMAP_CS2B_PHYS,
-       .end            = OMAP_CS2B_PHYS + OMAP_CS2B_SIZE - 1,
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device flash_device = {
-       .name           = "omapflash",
-       .id             = 0,
-       .dev            = {
-               .platform_data  = &h3_flash_data,
-       },
-       .num_resources  = 1,
-       .resource       = &h3_flash_resource,
-};
-
-static struct resource smc91x_resources[] = {
-       [0] = {
-               .start  = OMAP1710_ETHR_START,          /* Physical */
-               .end    = OMAP1710_ETHR_START + 0xf,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = OMAP_GPIO_IRQ(40),
-               .end    = OMAP_GPIO_IRQ(40),
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device smc91x_device = {
-       .name           = "smc91x",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(smc91x_resources),
-       .resource       = smc91x_resources,
-};
-
-#define GPTIMER_BASE           0xFFFB1400
-#define GPTIMER_REGS(x)        (0xFFFB1400 + (x * 0x800))
-#define GPTIMER_REGS_SIZE      0x46
-
-static struct resource intlat_resources[] = {
-       [0] = {
-               .start  = GPTIMER_REGS(0),            /* Physical */
-               .end    = GPTIMER_REGS(0) + GPTIMER_REGS_SIZE,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = INT_1610_GPTIMER1,
-               .end    = INT_1610_GPTIMER1,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device intlat_device = {
-       .name      = "omap_intlat",
-       .id          = 0,
-       .num_resources  = ARRAY_SIZE(intlat_resources),
-       .resource       = intlat_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-       &flash_device,
-        &smc91x_device,
-       &intlat_device,
-};
-
-static struct omap_usb_config h3_usb_config __initdata = {
-       /* usb1 has a Mini-AB port and external isp1301 transceiver */
-       .otg        = 2,
-
-#ifdef CONFIG_USB_GADGET_OMAP
-       .hmc_mode       = 19,   /* 0:host(off) 1:dev|otg 2:disabled */
-#elif  defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-       /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
-       .hmc_mode       = 20,   /* 1:dev|otg(off) 1:host 2:disabled */
-#endif
-
-       .pins[1]        = 3,
-};
-
-static struct omap_board_config_kernel h3_config[] = {
-       { OMAP_TAG_USB,  &h3_usb_config },
-};
-
-static void __init h3_init(void)
-{
-       (void) platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init h3_init_smc91x(void)
-{
-       omap_cfg_reg(W15_1710_GPIO40);
-       if (omap_request_gpio(40) < 0) {
-               printk("Error requesting gpio 40 for smc91x irq\n");
-               return;
-       }
-       omap_set_gpio_edge_ctrl(40, OMAP_GPIO_FALLING_EDGE);
-}
-
-void h3_init_irq(void)
-{
-       omap_init_irq();
-       omap_gpio_init();
-       h3_init_smc91x();
-}
-
-static void __init h3_map_io(void)
-{
-       omap_map_io();
-       omap_serial_init(h3_serial_ports);
-}
-
-MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
-       /* Maintainer: Texas Instruments, Inc. */
-       .phys_ram       = 0x10000000,
-       .phys_io        = 0xfff00000,
-       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
-       .boot_params    = 0x10000100,
-       .map_io         = h3_map_io,
-       .init_irq       = h3_init_irq,
-       .init_machine   = h3_init,
-       .timer          = &omap_timer,
-MACHINE_END
diff -urN linux/arch/arm/mach-omap/board-innovator.c 
linux/arch/arm/mach-omap/board-innovator.c
--- linux/arch/arm/mach-omap/Attic/board-innovator.c    2005-07-13 
12:48:51.775369000 +0100     1.10
+++ linux/arch/arm/mach-omap/Attic/board-innovator.c    1970/01/01 00:00:00+0100
@@ -1,282 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/board-innovator.c
- *
- * Board specific inits for OMAP-1510 and OMAP-1610 Innovator
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Copyright (C) 2002 MontaVista Software, Inc.
- *
- * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
- * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/map.h>
-
-#include <asm/arch/fpga.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/usb.h>
-
-#include "common.h"
-
-static int __initdata innovator_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
-
-static struct mtd_partition innovator_partitions[] = {
-       /* bootloader (U-Boot, etc) in first sector */
-       {
-             .name             = "bootloader",
-             .offset           = 0,
-             .size             = SZ_128K,
-             .mask_flags       = MTD_WRITEABLE, /* force read-only */
-       },
-       /* bootloader params in the next sector */
-       {
-             .name             = "params",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = SZ_128K,
-             .mask_flags       = 0,
-       },
-       /* kernel */
-       {
-             .name             = "kernel",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = SZ_2M,
-             .mask_flags       = 0
-       },
-       /* rest of flash1 is a file system */
-       {
-             .name             = "rootfs",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = SZ_16M - SZ_2M - 2 * SZ_128K,
-             .mask_flags       = 0
-       },
-       /* file system */
-       {
-             .name             = "filesystem",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = MTDPART_SIZ_FULL,
-             .mask_flags       = 0
-       }
-};
-
-static struct flash_platform_data innovator_flash_data = {
-       .map_name       = "cfi_probe",
-       .width          = 2,
-       .parts          = innovator_partitions,
-       .nr_parts       = ARRAY_SIZE(innovator_partitions),
-};
-
-static struct resource innovator_flash_resource = {
-       .start          = OMAP_CS0_PHYS,
-       .end            = OMAP_CS0_PHYS + SZ_32M - 1,
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device innovator_flash_device = {
-       .name           = "omapflash",
-       .id             = 0,
-       .dev            = {
-               .platform_data  = &innovator_flash_data,
-       },
-       .num_resources  = 1,
-       .resource       = &innovator_flash_resource,
-};
-
-#ifdef CONFIG_ARCH_OMAP1510
-
-/* Only FPGA needs to be mapped here. All others are done with ioremap */
-static struct map_desc innovator1510_io_desc[] __initdata = {
-{ OMAP1510_FPGA_BASE, OMAP1510_FPGA_START, OMAP1510_FPGA_SIZE,
-       MT_DEVICE },
-};
-
-static struct resource innovator1510_smc91x_resources[] = {
-       [0] = {
-               .start  = OMAP1510_FPGA_ETHR_START,     /* Physical */
-               .end    = OMAP1510_FPGA_ETHR_START + 0xf,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = OMAP1510_INT_ETHER,
-               .end    = OMAP1510_INT_ETHER,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device innovator1510_smc91x_device = {
-       .name           = "smc91x",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(innovator1510_smc91x_resources),
-       .resource       = innovator1510_smc91x_resources,
-};
-
-static struct platform_device *innovator1510_devices[] __initdata = {
-       &innovator_flash_device,
-       &innovator1510_smc91x_device,
-};
-
-#endif /* CONFIG_ARCH_OMAP1510 */
-
-#ifdef CONFIG_ARCH_OMAP16XX
-
-static struct resource innovator1610_smc91x_resources[] = {
-       [0] = {
-               .start  = INNOVATOR1610_ETHR_START,             /* Physical */
-               .end    = INNOVATOR1610_ETHR_START + 0xf,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = OMAP_GPIO_IRQ(0),
-               .end    = OMAP_GPIO_IRQ(0),
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device innovator1610_smc91x_device = {
-       .name           = "smc91x",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(innovator1610_smc91x_resources),
-       .resource       = innovator1610_smc91x_resources,
-};
-
-static struct platform_device *innovator1610_devices[] __initdata = {
-       &innovator_flash_device,
-       &innovator1610_smc91x_device,
-};
-
-#endif /* CONFIG_ARCH_OMAP16XX */
-
-static void __init innovator_init_smc91x(void)
-{
-       if (cpu_is_omap1510()) {
-               fpga_write(fpga_read(OMAP1510_FPGA_RST) & ~1,
-                          OMAP1510_FPGA_RST);
-               udelay(750);
-       } else {
-               if ((omap_request_gpio(0)) < 0) {
-                       printk("Error requesting gpio 0 for smc91x irq\n");
-                       return;
-               }
-               omap_set_gpio_edge_ctrl(0, OMAP_GPIO_RISING_EDGE);
-       }
-}
-
-void innovator_init_irq(void)
-{
-       omap_init_irq();
-       omap_gpio_init();
-#ifdef CONFIG_ARCH_OMAP1510
-       if (cpu_is_omap1510()) {
-               omap1510_fpga_init_irq();
-       }
-#endif
-       innovator_init_smc91x();
-}
-
-#ifdef CONFIG_ARCH_OMAP1510
-static struct omap_usb_config innovator1510_usb_config __initdata = {
-       /* for bundled non-standard host and peripheral cables */
-       .hmc_mode       = 4,
-
-       .register_host  = 1,
-       .pins[1]        = 6,
-       .pins[2]        = 6,            /* Conflicts with UART2 */
-
-       .register_dev   = 1,
-       .pins[0]        = 2,
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP16XX
-static struct omap_usb_config h2_usb_config __initdata = {
-       /* usb1 has a Mini-AB port and external isp1301 transceiver */
-       .otg            = 2,
-
-#ifdef CONFIG_USB_GADGET_OMAP
-       .hmc_mode       = 19,   // 0:host(off) 1:dev|otg 2:disabled
-       // .hmc_mode    = 21,   // 0:host(off) 1:dev(loopback) 2:host(loopback)
-#elif  defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-       /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
-       .hmc_mode       = 20,   // 1:dev|otg(off) 1:host 2:disabled
-#endif
-
-       .pins[1]        = 3,
-};
-#endif
-
-static struct omap_board_config_kernel innovator_config[] = {
-       { OMAP_TAG_USB,         NULL },
-};
-
-static void __init innovator_init(void)
-{
-#ifdef CONFIG_ARCH_OMAP1510
-       if (cpu_is_omap1510()) {
-               platform_add_devices(innovator1510_devices, 
ARRAY_SIZE(innovator1510_devices));
-       }
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-       if (!cpu_is_omap1510()) {
-               platform_add_devices(innovator1610_devices, 
ARRAY_SIZE(innovator1610_devices));
-       }
-#endif
-
-#ifdef CONFIG_ARCH_OMAP1510
-       if (cpu_is_omap1510())
-               innovator_config[0].data = &innovator1510_usb_config;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-       if (cpu_is_omap1610())
-               innovator_config[0].data = &h2_usb_config;
-#endif
-       omap_board_config = innovator_config;
-       omap_board_config_size = ARRAY_SIZE(innovator_config);
-}
-
-static void __init innovator_map_io(void)
-{
-       omap_map_io();
-
-#ifdef CONFIG_ARCH_OMAP1510
-       if (cpu_is_omap1510()) {
-               iotable_init(innovator1510_io_desc, 
ARRAY_SIZE(innovator1510_io_desc));
-               udelay(10);     /* Delay needed for FPGA */
-
-               /* Dump the Innovator FPGA rev early - useful info for support. 
*/
-               printk("Innovator FPGA Rev %d.%d Board Rev %d\n",
-                      fpga_read(OMAP1510_FPGA_REV_HIGH),
-                      fpga_read(OMAP1510_FPGA_REV_LOW),
-                      fpga_read(OMAP1510_FPGA_BOARD_REV));
-       }
-#endif
-       omap_serial_init(innovator_serial_ports);
-}
-
-MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
-       /* Maintainer: MontaVista Software, Inc. */
-       .phys_ram       = 0x10000000,
-       .phys_io        = 0xfff00000,
-       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
-       .boot_params    = 0x10000100,
-       .map_io         = innovator_map_io,
-       .init_irq       = innovator_init_irq,
-       .init_machine   = innovator_init,
-       .timer          = &omap_timer,
-MACHINE_END
diff -urN linux/arch/arm/mach-omap/board-netstar.c 
linux/arch/arm/mach-omap/board-netstar.c
--- linux/arch/arm/mach-omap/Attic/board-netstar.c      2005-07-13 
12:48:51.799639000 +0100     1.2
+++ linux/arch/arm/mach-omap/Attic/board-netstar.c      1970/01/01 00:00:00+0100
@@ -1,153 +0,0 @@
-/*
- * Modified from board-generic.c
- *
- * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
- *
- * Code for Netstar OMAP board.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/notifier.h>
-#include <linux/reboot.h>
-
-#include <asm/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-
-#include "common.h"
-
-extern void __init omap_init_time(void);
-extern int omap_gpio_init(void);
-
-static struct resource netstar_smc91x_resources[] = {
-       [0] = {
-               .start  = OMAP_CS1_PHYS + 0x300,
-               .end    = OMAP_CS1_PHYS + 0x300 + 16,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = OMAP_GPIO_IRQ(8),
-               .end    = OMAP_GPIO_IRQ(8),
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device netstar_smc91x_device = {
-       .name           = "smc91x",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(netstar_smc91x_resources),
-       .resource       = netstar_smc91x_resources,
-};
-
-static struct platform_device *netstar_devices[] __initdata = {
-       &netstar_smc91x_device,
-};
-
-static void __init netstar_init_irq(void)
-{
-       omap_init_irq();
-       omap_gpio_init();
-}
-
-static void __init netstar_init(void)
-{
-       /* green LED */
-       omap_request_gpio(4);
-       omap_set_gpio_direction(4, 0);
-       /* smc91x reset */
-       omap_request_gpio(7);
-       omap_set_gpio_direction(7, 0);
-       omap_set_gpio_dataout(7, 1);
-       udelay(2);      /* wait at least 100ns */
-       omap_set_gpio_dataout(7, 0);
-       mdelay(50);     /* 50ms until PHY ready */
-       /* smc91x interrupt pin */
-       omap_request_gpio(8);
-       omap_set_gpio_edge_ctrl(8, OMAP_GPIO_RISING_EDGE);
-
-       omap_request_gpio(12);
-       omap_request_gpio(13);
-       omap_request_gpio(14);
-       omap_request_gpio(15);
-       omap_set_gpio_edge_ctrl(12, OMAP_GPIO_FALLING_EDGE);
-       omap_set_gpio_edge_ctrl(13, OMAP_GPIO_FALLING_EDGE);
-       omap_set_gpio_edge_ctrl(14, OMAP_GPIO_FALLING_EDGE);
-       omap_set_gpio_edge_ctrl(15, OMAP_GPIO_FALLING_EDGE);
-
-       platform_add_devices(netstar_devices, ARRAY_SIZE(netstar_devices));
-
-       /* Switch on green LED */
-       omap_set_gpio_dataout(4, 0);
-       /* Switch off red LED */
-       omap_writeb(0x00, OMAP_LPG1_PMR);       /* Disable clock */
-       omap_writeb(0x80, OMAP_LPG1_LCR);
-}
-
-static int __initdata omap_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
-
-static void __init netstar_map_io(void)
-{
-       omap_map_io();
-       omap_serial_init(omap_serial_ports);
-}
-
-#define MACHINE_PANICED                1
-#define MACHINE_REBOOTING      2
-#define MACHINE_REBOOT         4
-static unsigned long machine_state;
-
-static int panic_event(struct notifier_block *this, unsigned long event,
-        void *ptr)
-{
-       if (test_and_set_bit(MACHINE_PANICED, &machine_state))
-               return NOTIFY_DONE;
-
-       /* Switch off green LED */
-       omap_set_gpio_dataout(4, 1);
-       /* Flash red LED */
-       omap_writeb(0x78, OMAP_LPG1_LCR);
-       omap_writeb(0x01, OMAP_LPG1_PMR);       /* Enable clock */
-
-       return NOTIFY_DONE;
-}
-
-static struct notifier_block panic_block = {
-       .notifier_call  = panic_event,
-};
-
-static int __init netstar_late_init(void)
-{
-       /* TODO: Setup front panel switch here */
-
-       /* Setup panic notifier */
-       notifier_chain_register(&panic_notifier_list, &panic_block);
-
-       return 0;
-}
-
-postcore_initcall(netstar_late_init);
-
-MACHINE_START(NETSTAR, "NetStar OMAP5910")
-       /* Maintainer: Ladislav Michl <michl@2n.cz> */
-       .phys_ram       = 0x10000000,
-       .phys_io        = 0xfff00000,
-       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
-       .boot_params    = 0x10000100,
-       .map_io         = netstar_map_io,
-       .init_irq       = netstar_init_irq,
-       .init_machine   = netstar_init,
-       .timer          = &omap_timer,
-MACHINE_END
diff -urN linux/arch/arm/mach-omap/board-osk.c 
linux/arch/arm/mach-omap/board-osk.c
--- linux/arch/arm/mach-omap/Attic/board-osk.c  2005-07-13 12:48:51.820385000 
+0100     1.10
+++ linux/arch/arm/mach-omap/Attic/board-osk.c  1970/01/01 00:00:00+0100
@@ -1,171 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/board-osk.c
- *
- * Board specific init for OMAP5912 OSK
- *
- * Written by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-
-#include <asm/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <asm/arch/gpio.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/tc.h>
-
-#include "common.h"
-
-static struct map_desc osk5912_io_desc[] __initdata = {
-{ OMAP_OSK_NOR_FLASH_BASE, OMAP_OSK_NOR_FLASH_START, OMAP_OSK_NOR_FLASH_SIZE,
-       MT_DEVICE },
-};
-
-static int __initdata osk_serial_ports[OMAP_MAX_NR_PORTS] = {1, 0, 0};
-
-static struct resource osk5912_smc91x_resources[] = {
-       [0] = {
-               .start  = OMAP_OSK_ETHR_START,          /* Physical */
-               .end    = OMAP_OSK_ETHR_START + 0xf,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = OMAP_GPIO_IRQ(0),
-               .end    = OMAP_GPIO_IRQ(0),
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device osk5912_smc91x_device = {
-       .name           = "smc91x",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(osk5912_smc91x_resources),
-       .resource       = osk5912_smc91x_resources,
-};
-
-static struct resource osk5912_cf_resources[] = {
-       [0] = {
-               .start  = OMAP_GPIO_IRQ(62),
-               .end    = OMAP_GPIO_IRQ(62),
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device osk5912_cf_device = {
-       .name           = "omap_cf",
-       .id             = -1,
-       .dev = {
-               .platform_data  = (void *) 2 /* CS2 */,
-       },
-       .num_resources  = ARRAY_SIZE(osk5912_cf_resources),
-       .resource       = osk5912_cf_resources,
-};
-
-static struct platform_device *osk5912_devices[] __initdata = {
-       &osk5912_smc91x_device,
-       &osk5912_cf_device,
-};
-
-static void __init osk_init_smc91x(void)
-{
-       if ((omap_request_gpio(0)) < 0) {
-               printk("Error requesting gpio 0 for smc91x irq\n");
-               return;
-       }
-       omap_set_gpio_edge_ctrl(0, OMAP_GPIO_RISING_EDGE);
-
-       /* Check EMIFS wait states to fix errors with SMC_GET_PKT_HDR */
-       EMIFS_CCS(1) |= 0x2;
-}
-
-static void __init osk_init_cf(void)
-{
-       omap_cfg_reg(M7_1610_GPIO62);
-       if ((omap_request_gpio(62)) < 0) {
-               printk("Error requesting gpio 62 for CF irq\n");
-               return;
-       }
-       /* it's really active-low */
-       omap_set_gpio_edge_ctrl(62, OMAP_GPIO_FALLING_EDGE);
-}
-
-void osk_init_irq(void)
-{
-       omap_init_irq();
-       omap_gpio_init();
-       osk_init_smc91x();
-       osk_init_cf();
-}
-
-static struct omap_usb_config osk_usb_config __initdata = {
-       /* has usb host connector (A) ... for development it can also
-        * be used, with a NONSTANDARD gender-bending cable/dongle, as
-        * a peripheral.
-        */
-#ifdef CONFIG_USB_GADGET_OMAP
-       .register_dev   = 1,
-       .hmc_mode       = 0,
-#else
-       .register_host  = 1,
-       .hmc_mode       = 16,
-       .rwc            = 1,
-#endif
-       .pins[0]        = 2,
-};
-
-static struct omap_board_config_kernel osk_config[] = {
-       { OMAP_TAG_USB,           &osk_usb_config },
-};
-
-static void __init osk_init(void)
-{
-       platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
-       omap_board_config = osk_config;
-       omap_board_config_size = ARRAY_SIZE(osk_config);
-       USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
-}
-
-static void __init osk_map_io(void)
-{
-       omap_map_io();
-       iotable_init(osk5912_io_desc, ARRAY_SIZE(osk5912_io_desc));
-       omap_serial_init(osk_serial_ports);
-}
-
-MACHINE_START(OMAP_OSK, "TI-OSK")
-       /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
-       .phys_ram       = 0x10000000,
-       .phys_io        = 0xfff00000,
-       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
-       .boot_params    = 0x10000100,
-       .map_io         = osk_map_io,
-       .init_irq       = osk_init_irq,
-       .init_machine   = osk_init,
-       .timer          = &omap_timer,
-MACHINE_END
diff -urN linux/arch/arm/mach-omap/board-perseus2.c 
linux/arch/arm/mach-omap/board-perseus2.c
--- linux/arch/arm/mach-omap/Attic/board-perseus2.c     2005-07-13 
12:48:51.847809000 +0100     1.10
+++ linux/arch/arm/mach-omap/Attic/board-perseus2.c     1970/01/01 00:00:00+0100
@@ -1,191 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/board-perseus2.c
- *
- * Modified from board-generic.c
- *
- * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
- * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/map.h>
-
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/fpga.h>
-
-#include "common.h"
-
-static struct resource smc91x_resources[] = {
-       [0] = {
-               .start  = H2P2_DBG_FPGA_ETHR_START,     /* Physical */
-               .end    = H2P2_DBG_FPGA_ETHR_START + 0xf,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = INT_730_MPU_EXT_NIRQ,
-               .end    = 0,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static int __initdata p2_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 0};
-
-static struct mtd_partition p2_partitions[] = {
-       /* bootloader (U-Boot, etc) in first sector */
-       {
-             .name             = "bootloader",
-             .offset           = 0,
-             .size             = SZ_128K,
-             .mask_flags       = MTD_WRITEABLE, /* force read-only */
-       },
-       /* bootloader params in the next sector */
-       {
-             .name             = "params",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = SZ_128K,
-             .mask_flags       = 0,
-       },
-       /* kernel */
-       {
-             .name             = "kernel",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = SZ_2M,
-             .mask_flags       = 0
-       },
-       /* rest of flash is a file system */
-       {
-             .name             = "rootfs",
-             .offset           = MTDPART_OFS_APPEND,
-             .size             = MTDPART_SIZ_FULL,
-             .mask_flags       = 0
-       },
-};
-
-static struct flash_platform_data p2_flash_data = {
-       .map_name       = "cfi_probe",
-       .width          = 2,
-       .parts          = p2_partitions,
-       .nr_parts       = ARRAY_SIZE(p2_partitions),
-};
-
-static struct resource p2_flash_resource = {
-       .start          = OMAP_FLASH_0_START,
-       .end            = OMAP_FLASH_0_START + OMAP_FLASH_0_SIZE - 1,
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device p2_flash_device = {
-       .name           = "omapflash",
-       .id             = 0,
-       .dev            = {
-               .platform_data  = &p2_flash_data,
-       },
-       .num_resources  = 1,
-       .resource       = &p2_flash_resource,
-};
-
-static struct platform_device smc91x_device = {
-       .name           = "smc91x",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(smc91x_resources),
-       .resource       = smc91x_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-       &p2_flash_device,
-       &smc91x_device,
-};
-
-static void __init omap_perseus2_init(void)
-{
-       (void) platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init perseus2_init_smc91x(void)
-{
-       fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
-       mdelay(50);
-       fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
-                  H2P2_DBG_FPGA_LAN_RESET);
-       mdelay(50);
-}
-
-void omap_perseus2_init_irq(void)
-{
-       omap_init_irq();
-       omap_gpio_init();
-       perseus2_init_smc91x();
-}
-
-/* Only FPGA needs to be mapped here. All others are done with ioremap */
-static struct map_desc omap_perseus2_io_desc[] __initdata = {
-       {H2P2_DBG_FPGA_BASE, H2P2_DBG_FPGA_START, H2P2_DBG_FPGA_SIZE,
-        MT_DEVICE},
-};
-
-static void __init omap_perseus2_map_io(void)
-{
-       omap_map_io();
-       iotable_init(omap_perseus2_io_desc,
-                    ARRAY_SIZE(omap_perseus2_io_desc));
-
-       /* Early, board-dependent init */
-
-       /*
-        * Hold GSM Reset until needed
-        */
-       omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
-
-       /*
-        * UARTs -> done automagically by 8250 driver
-        */
-
-       /*
-        * CSx timings, GPIO Mux ... setup
-        */
-
-       /* Flash: CS0 timings setup */
-       omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
-       omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
-
-       /*
-        * Ethernet support trough the debug board
-        * CS1 timings setup
-        */
-       omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
-       omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
-
-       /*
-        * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
-        * It is used as the Ethernet controller interrupt
-        */
-       omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, 
OMAP730_IO_CONF_9);
-       omap_serial_init(p2_serial_ports);
-}
-
-MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
-       /* Maintainer: Kevin Hilman <kjh@hilman.org> */
-       .phys_ram       = 0x10000000,
-       .phys_io        = 0xfff00000,
-       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
-       .boot_params    = 0x10000100,
-       .map_io         = omap_perseus2_map_io,
-       .init_irq       = omap_perseus2_init_irq,
-       .init_machine   = omap_perseus2_init,
-       .timer          = &omap_timer,
-MACHINE_END
diff -urN linux/arch/arm/mach-omap/board-voiceblue.c 
linux/arch/arm/mach-omap/board-voiceblue.c
--- linux/arch/arm/mach-omap/Attic/board-voiceblue.c    2005-07-13 
12:48:51.869372000 +0100     1.2
+++ linux/arch/arm/mach-omap/Attic/board-voiceblue.c    1970/01/01 00:00:00+0100
@@ -1,258 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/board-voiceblue.c
- *
- * Modified from board-generic.c
- *
- * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
- *
- * Code for OMAP5910 based VoiceBlue board (VoIP to GSM gateway).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/notifier.h>
-#include <linux/reboot.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_reg.h>
-
-#include <asm/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <asm/arch/gpio.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-
-#include "common.h"
-
-extern void omap_init_time(void);
-extern int omap_gpio_init(void);
-
-static struct plat_serial8250_port voiceblue_ports[] = {
-       {
-               .mapbase        = (unsigned long)(OMAP_CS1_PHYS + 0x40000),
-               .irq            = OMAP_GPIO_IRQ(12),
-               .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
-               .iotype         = UPIO_MEM,
-               .regshift       = 1,
-               .uartclk        = 3686400,
-       },
-       {
-               .mapbase        = (unsigned long)(OMAP_CS1_PHYS + 0x50000),
-               .irq            = OMAP_GPIO_IRQ(13),
-               .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
-               .iotype         = UPIO_MEM,
-               .regshift       = 1,
-               .uartclk        = 3686400,
-       },
-       {
-               .mapbase        = (unsigned long)(OMAP_CS1_PHYS + 0x60000),
-               .irq            = OMAP_GPIO_IRQ(14),
-               .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
-               .iotype         = UPIO_MEM,
-               .regshift       = 1,
-               .uartclk        = 3686400,
-       },
-       {
-               .mapbase        = (unsigned long)(OMAP_CS1_PHYS + 0x70000),
-               .irq            = OMAP_GPIO_IRQ(15),
-               .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
-               .iotype         = UPIO_MEM,
-               .regshift       = 1,
-               .uartclk        = 3686400,
-       },
-       { },
-};
-
-static struct platform_device serial_device = {
-       .name                   = "serial8250",
-       .id                     = 1,
-       .dev                    = {
-               .platform_data  = voiceblue_ports,
-       },
-};
-
-static int __init ext_uart_init(void)
-{
-       return platform_device_register(&serial_device);
-}
-arch_initcall(ext_uart_init);
-
-static struct resource voiceblue_smc91x_resources[] = {
-       [0] = {
-               .start  = OMAP_CS2_PHYS + 0x300,
-               .end    = OMAP_CS2_PHYS + 0x300 + 16,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = OMAP_GPIO_IRQ(8),
-               .end    = OMAP_GPIO_IRQ(8),
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device voiceblue_smc91x_device = {
-       .name           = "smc91x",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(voiceblue_smc91x_resources),
-       .resource       = voiceblue_smc91x_resources,
-};
-
-static struct platform_device *voiceblue_devices[] __initdata = {
-       &voiceblue_smc91x_device,
-};
-
-static struct omap_usb_config voiceblue_usb_config __initdata = {
-       .hmc_mode       = 3,
-       .register_host  = 1,
-       .register_dev   = 1,
-       .pins[0]        = 2,
-       .pins[1]        = 6,
-       .pins[2]        = 6,
-};
-
-static struct omap_board_config_kernel voiceblue_config[] = {
-       { OMAP_TAG_USB, &voiceblue_usb_config },
-};
-
-static void __init voiceblue_init_irq(void)
-{
-       omap_init_irq();
-       omap_gpio_init();
-}
-
-static void __init voiceblue_init(void)
-{
-       /* There is a good chance board is going up, so enable Power LED
-        * (it is connected through invertor) */
-       omap_writeb(0x00, OMAP_LPG1_LCR);
-       /* Watchdog */
-       omap_request_gpio(0);
-       /* smc91x reset */
-       omap_request_gpio(7);
-       omap_set_gpio_direction(7, 0);
-       omap_set_gpio_dataout(7, 1);
-       udelay(2);      /* wait at least 100ns */
-       omap_set_gpio_dataout(7, 0);
-       mdelay(50);     /* 50ms until PHY ready */
-       /* smc91x interrupt pin */
-       omap_request_gpio(8);
-       omap_set_gpio_edge_ctrl(8, OMAP_GPIO_RISING_EDGE);
-       /* 16C554 reset*/
-       omap_request_gpio(6);
-       omap_set_gpio_direction(6, 0);
-       omap_set_gpio_dataout(6, 0);
-       /* 16C554 interrupt pins */
-       omap_request_gpio(12);
-       omap_request_gpio(13);
-       omap_request_gpio(14);
-       omap_request_gpio(15);
-       omap_set_gpio_edge_ctrl(12, OMAP_GPIO_RISING_EDGE);
-       omap_set_gpio_edge_ctrl(13, OMAP_GPIO_RISING_EDGE);
-       omap_set_gpio_edge_ctrl(14, OMAP_GPIO_RISING_EDGE);
-       omap_set_gpio_edge_ctrl(15, OMAP_GPIO_RISING_EDGE);
-
-       platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
-       omap_board_config = voiceblue_config;
-       omap_board_config_size = ARRAY_SIZE(voiceblue_config);
-}
-
-static int __initdata omap_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
-
-static void __init voiceblue_map_io(void)
-{
-       omap_map_io();
-       omap_serial_init(omap_serial_ports);
-}
-
-#define MACHINE_PANICED                1
-#define MACHINE_REBOOTING      2
-#define MACHINE_REBOOT         4
-static unsigned long machine_state;
-
-static int panic_event(struct notifier_block *this, unsigned long event,
-        void *ptr)
-{
-       if (test_and_set_bit(MACHINE_PANICED, &machine_state))
-               return NOTIFY_DONE;
-
-       /* Flash Power LED
-        * (TODO: Enable clock right way (enabled in bootloader already)) */
-       omap_writeb(0x78, OMAP_LPG1_LCR);
-
-       return NOTIFY_DONE;
-}
-
-static struct notifier_block panic_block = {
-       .notifier_call  = panic_event,
-};
-
-static int __init setup_notifier(void)
-{
-       /* Setup panic notifier */
-       notifier_chain_register(&panic_notifier_list, &panic_block);
-
-       return 0;
-}
-
-postcore_initcall(setup_notifier);
-
-static int wdt_gpio_state;
-
-void voiceblue_wdt_enable(void)
-{
-       omap_set_gpio_direction(0, 0);
-       omap_set_gpio_dataout(0, 0);
-       omap_set_gpio_dataout(0, 1);
-       omap_set_gpio_dataout(0, 0);
-       wdt_gpio_state = 0;
-}
-
-void voiceblue_wdt_disable(void)
-{
-       omap_set_gpio_dataout(0, 0);
-       omap_set_gpio_dataout(0, 1);
-       omap_set_gpio_dataout(0, 0);
-       omap_set_gpio_direction(0, 1);
-}
-
-void voiceblue_wdt_ping(void)
-{
-       if (test_bit(MACHINE_REBOOT, &machine_state))
-               return;
-
-       wdt_gpio_state = !wdt_gpio_state;
-       omap_set_gpio_dataout(0, wdt_gpio_state);
-}
-
-void voiceblue_reset(void)
-{
-       set_bit(MACHINE_REBOOT, &machine_state);
-       voiceblue_wdt_enable();
-       while (1) ;
-}
-
-EXPORT_SYMBOL(voiceblue_wdt_enable);
-EXPORT_SYMBOL(voiceblue_wdt_disable);
-EXPORT_SYMBOL(voiceblue_wdt_ping);
-
-MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
-       /* Maintainer: Ladislav Michl <michl@2n.cz> */
-       .phys_ram       = 0x10000000,
-       .phys_io        = 0xfff00000,
-       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
-       .boot_params    = 0x10000100,
-       .map_io         = voiceblue_map_io,
-       .init_irq       = voiceblue_init_irq,
-       .init_machine   = voiceblue_init,
-       .timer          = &omap_timer,
-MACHINE_END
diff -urN linux/arch/arm/mach-omap/clock.c linux/arch/arm/mach-omap/clock.c
--- linux/arch/arm/mach-omap/Attic/clock.c      2005-07-13 12:48:51.887371000 
+0100     1.3
+++ linux/arch/arm/mach-omap/Attic/clock.c      1970/01/01 00:00:00+0100
@@ -1,1076 +0,0 @@
-/*
- *  linux/arch/arm/mach-omap/clock.c
- *
- *  Copyright (C) 2004 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-
-#include <asm/semaphore.h>
-#include <asm/hardware/clock.h>
-#include <asm/arch/board.h>
-#include <asm/arch/usb.h>
-
-#include "clock.h"
-
-static LIST_HEAD(clocks);
-static DECLARE_MUTEX(clocks_sem);
-static DEFINE_SPINLOCK(clockfw_lock);
-static void propagate_rate(struct clk *  clk);
-/* External clock (MCLK & BCLK) functions */
-static int set_ext_clk_rate(struct clk *  clk, unsigned long rate);
-static long round_ext_clk_rate(struct clk *  clk, unsigned long rate);
-static void init_ext_clk(struct clk *  clk);
-/* MPU virtual clock functions */
-static int select_table_rate(struct clk *  clk, unsigned long rate);
-static long round_to_table_rate(struct clk *  clk, unsigned long rate);
-void clk_setdpll(__u16, __u16);
-
-struct mpu_rate rate_table[] = {
-       /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
-        * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
-        */
-#if defined(CONFIG_OMAP_ARM_216MHZ)
-       { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_195MHZ)
-       { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_192MHZ)
-       { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
-       { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
-       {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
-       {  48000000, 12000000, 192000000, 0x0ccf, 0x2810 }, /* 4/4/4/4/8/8 */
-       {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_182MHZ)
-       { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_168MHZ)
-       { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_150MHZ)
-       { 150000000, 12000000, 150000000, 0x150a, 0x2cb0 }, /* 0/0/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_120MHZ)
-       { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
-#endif
-#if defined(CONFIG_OMAP_ARM_96MHZ)
-       {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_60MHZ)
-       {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_30MHZ)
-       {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
-#endif
-       { 0, 0, 0, 0, 0 },
-};
-
-
-static void ckctl_recalc(struct clk *  clk)
-{
-       int dsor;
-
-       /* Calculate divisor encoded as 2-bit exponent */
-       dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
-       if (unlikely(clk->rate == clk->parent->rate / dsor))
-               return; /* No change, quick exit */
-       clk->rate = clk->parent->rate / dsor;
-
-       if (unlikely(clk->flags & RATE_PROPAGATES))
-               propagate_rate(clk);
-}
-
-
-static void followparent_recalc(struct clk *  clk)
-{
-       clk->rate = clk->parent->rate;
-}
-
-
-static void watchdog_recalc(struct clk *  clk)
-{
-       clk->rate = clk->parent->rate / 14;
-}
-
-
-static struct clk ck_ref = {
-       .name           = "ck_ref",
-       .rate           = 12000000,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                         ALWAYS_ENABLED,
-};
-
-static struct clk ck_dpll1 = {
-       .name           = "ck_dpll1",
-       .parent         = &ck_ref,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                         RATE_PROPAGATES | ALWAYS_ENABLED,
-};
-
-static struct clk ck_dpll1out = {
-       .name           = "ck_dpll1out",
-       .parent         = &ck_dpll1,
-       .flags          = CLOCK_IN_OMAP16XX,
-       .enable_reg     = ARM_IDLECT2,
-       .enable_bit     = EN_CKOUT_ARM,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk arm_ck = {
-       .name           = "arm_ck",
-       .parent         = &ck_dpll1,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                         RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
-       .rate_offset    = CKCTL_ARMDIV_OFFSET,
-       .recalc         = &ckctl_recalc,
-};
-
-static struct clk armper_ck = {
-       .name           = "armper_ck",
-       .parent         = &ck_dpll1,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                         RATE_CKCTL,
-       .enable_reg     = ARM_IDLECT2,
-       .enable_bit     = EN_PERCK,
-       .rate_offset    = CKCTL_PERDIV_OFFSET,
-       .recalc         = &ckctl_recalc,
-};
-
-static struct clk arm_gpio_ck = {
-       .name           = "arm_gpio_ck",
-       .parent         = &ck_dpll1,
-       .flags          = CLOCK_IN_OMAP1510,
-       .enable_reg     = ARM_IDLECT2,
-       .enable_bit     = EN_GPIOCK,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk armxor_ck = {
-       .name           = "armxor_ck",
-       .parent         = &ck_ref,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
-       .enable_reg     = ARM_IDLECT2,
-       .enable_bit     = EN_XORPCK,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk armtim_ck = {
-       .name           = "armtim_ck",
-       .parent         = &ck_ref,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
-       .enable_reg     = ARM_IDLECT2,
-       .enable_bit     = EN_TIMCK,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk armwdt_ck = {
-       .name           = "armwdt_ck",
-       .parent         = &ck_ref,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
-       .enable_reg     = ARM_IDLECT2,
-       .enable_bit     = EN_WDTCK,
-       .recalc         = &watchdog_recalc,
-};
-
-static struct clk arminth_ck16xx = {
-       .name           = "arminth_ck",
-       .parent         = &arm_ck,
-       .flags          = CLOCK_IN_OMAP16XX,
-       .recalc         = &followparent_recalc,
-       /* Note: On 16xx the frequency can be divided by 2 by programming
-        * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
-        *
-        * 1510 version is in TC clocks.
-        */
-};
-
-static struct clk dsp_ck = {
-       .name           = "dsp_ck",
-       .parent         = &ck_dpll1,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                         RATE_CKCTL,
-       .enable_reg     = ARM_CKCTL,
-       .enable_bit     = EN_DSPCK,
-       .rate_offset    = CKCTL_DSPDIV_OFFSET,
-       .recalc         = &ckctl_recalc,
-};
-
-static struct clk dspmmu_ck = {
-       .name           = "dspmmu_ck",
-       .parent         = &ck_dpll1,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                         RATE_CKCTL | ALWAYS_ENABLED,
-       .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
-       .recalc         = &ckctl_recalc,
-};
-
-static struct clk tc_ck = {
-       .name           = "tc_ck",
-       .parent         = &ck_dpll1,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 
CLOCK_IN_OMAP730 |
-                         RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
-       .rate_offset    = CKCTL_TCDIV_OFFSET,
-       .recalc         = &ckctl_recalc,
-};
-
-static struct clk arminth_ck1510 = {
-       .name           = "arminth_ck",
-       .parent         = &tc_ck,
-       .flags          = CLOCK_IN_OMAP1510,
-       .recalc         = &followparent_recalc,
-       /* Note: On 1510 the frequency follows TC_CK
-        *
-        * 16xx version is in MPU clocks.
-        */
-};
-
-static struct clk tipb_ck = {
-       .name           = "tibp_ck",
-       .parent         = &tc_ck,
-       .flags          = CLOCK_IN_OMAP1510,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk l3_ocpi_ck = {
-       .name           = "l3_ocpi_ck",
-       .parent         = &tc_ck,
-       .flags          = CLOCK_IN_OMAP16XX,
-       .enable_reg     = ARM_IDLECT3,
-       .enable_bit     = EN_OCPI_CK,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk tc1_ck = {
-       .name           = "tc1_ck",
-       .parent         = &tc_ck,
-       .flags          = CLOCK_IN_OMAP16XX,
-       .enable_reg     = ARM_IDLECT3,
-       .enable_bit     = EN_TC1_CK,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk tc2_ck = {
-       .name           = "tc2_ck",
-       .parent         = &tc_ck,
-       .flags          = CLOCK_IN_OMAP16XX,
-       .enable_reg     = ARM_IDLECT3,
-       .enable_bit     = EN_TC2_CK,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk dma_ck = {
-       .name           = "dma_ck",
-       .parent         = &tc_ck,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk dma_lcdfree_ck = {
-       .name           = "dma_lcdfree_ck",
-       .parent         = &tc_ck,
-       .flags          = CLOCK_IN_OMAP16XX,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk api_ck = {
-       .name           = "api_ck",
-       .parent         = &tc_ck,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
-       .enable_reg     = ARM_IDLECT2,
-       .enable_bit     = EN_APICK,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk lb_ck = {
-       .name           = "lb_ck",
-       .parent         = &tc_ck,
-       .flags          = CLOCK_IN_OMAP1510,
-       .enable_reg     = ARM_IDLECT2,
-       .enable_bit     = EN_LBCK,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk rhea1_ck = {
-       .name           = "rhea1_ck",
-       .parent         = &tc_ck,
-       .flags          = CLOCK_IN_OMAP16XX,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk rhea2_ck = {
-       .name           = "rhea2_ck",
-       .parent         = &tc_ck,
-       .flags          = CLOCK_IN_OMAP16XX,
-       .recalc         = &followparent_recalc,
-};
-
-static struct clk lcd_ck = {
-       .name           = "lcd_ck",
-       .parent         = &ck_dpll1,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 
CLOCK_IN_OMAP730 |
-                         RATE_CKCTL,
-       .enable_reg     = ARM_IDLECT2,
-       .enable_bit     = EN_LCDCK,
-       .rate_offset    = CKCTL_LCDDIV_OFFSET,
-       .recalc         = &ckctl_recalc,
-};
-
-static struct clk uart1_ck = {
-       .name           = "uart1_ck",
-       /* Direct from ULPD, no parent */
-       .rate           = 48000000,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                         RATE_FIXED | ENABLE_REG_32BIT,
-       .enable_reg     = MOD_CONF_CTRL_0,
-       .enable_bit     = 29,
-       /* (Only on 1510)
-        * The "enable bit" actually chooses between 48MHz and 12MHz.
-        */
-};
-
-static struct clk uart2_ck = {
-       .name           = "uart2_ck",
-       /* Direct from ULPD, no parent */
-       .rate           = 48000000,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                         RATE_FIXED | ENABLE_REG_32BIT,
-       .enable_reg     = MOD_CONF_CTRL_0,
-       .enable_bit     = 30,
-       /* (for both 1510 and 16xx)
-        * The "enable bit" actually chooses between 48MHz and 12MHz/32kHz.
-        */
-};
-
-static struct clk uart3_ck = {
-       .name           = "uart3_ck",
-       /* Direct from ULPD, no parent */
-       .rate           = 48000000,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                         RATE_FIXED | ENABLE_REG_32BIT,
-       .enable_reg     = MOD_CONF_CTRL_0,
-       .enable_bit     = 31,
-       /* (Only on 1510)
-        * The "enable bit" actually chooses between 48MHz and 12MHz.
-        */
-};
-
-static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
-       .name           = "usb_clko",
-       /* Direct from ULPD, no parent */
-       .rate           = 6000000,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                         RATE_FIXED | ENABLE_REG_32BIT,
-       .enable_reg     = ULPD_CLOCK_CTRL,
-       .enable_bit     = USB_MCLK_EN_BIT,
-};
-
-static struct clk usb_hhc_ck1510 = {
-       .name           = "usb_hhc_ck",
-       /* Direct from ULPD, no parent */
-       .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
-       .flags          = CLOCK_IN_OMAP1510 |
-                         RATE_FIXED | ENABLE_REG_32BIT,
-       .enable_reg     = MOD_CONF_CTRL_0,
-       .enable_bit     = USB_HOST_HHC_UHOST_EN,
-};
-
-static struct clk usb_hhc_ck16xx = {
-       .name           = "usb_hhc_ck",
-       /* Direct from ULPD, no parent */
-       .rate           = 48000000,
-       /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
-       .flags          = CLOCK_IN_OMAP16XX |
-                         RATE_FIXED | ENABLE_REG_32BIT,
-       .enable_reg     = OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
-       .enable_bit     = 8 /* UHOST_EN */,
-};
-
-static struct clk mclk_1510 = {
-       .name           = "mclk",
-       /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-       .rate           = 12000000,
-       .flags          = CLOCK_IN_OMAP1510 | RATE_FIXED,
-};
-
-static struct clk mclk_16xx = {
-       .name           = "mclk",
-       /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-       .flags          = CLOCK_IN_OMAP16XX,
-       .enable_reg     = COM_CLK_DIV_CTRL_SEL,
-       .enable_bit     = COM_ULPD_PLL_CLK_REQ,
-       .set_rate       = &set_ext_clk_rate,
-       .round_rate     = &round_ext_clk_rate,
-       .init           = &init_ext_clk,
-};
-
-static struct clk bclk_1510 = {
-       .name           = "bclk",
-       /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-       .rate           = 12000000,
-       .flags          = CLOCK_IN_OMAP1510 | RATE_FIXED,
-};
-
-static struct clk bclk_16xx = {
-       .name           = "bclk",
-       /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-       .flags          = CLOCK_IN_OMAP16XX,
-       .enable_reg     = SWD_CLK_DIV_CTRL_SEL,
-       .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
-       .set_rate       = &set_ext_clk_rate,
-       .round_rate     = &round_ext_clk_rate,
-       .init           = &init_ext_clk,
-};
-
-static struct clk mmc1_ck = {
-       .name           = "mmc1_ck",
-       /* Functional clock is direct from ULPD, interface clock is ARMPER */
-       .parent         = &armper_ck,
-       .rate           = 48000000,
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                         RATE_FIXED | ENABLE_REG_32BIT,
-       .enable_reg     = MOD_CONF_CTRL_0,
-       .enable_bit     = 23,
-};
-
-static struct clk mmc2_ck = {
-       .name           = "mmc2_ck",
-       /* Functional clock is direct from ULPD, interface clock is ARMPER */
-       .parent         = &armper_ck,
-       .rate           = 48000000,
-       .flags          = CLOCK_IN_OMAP16XX |
-                         RATE_FIXED | ENABLE_REG_32BIT,
-       .enable_reg     = MOD_CONF_CTRL_0,
-       .enable_bit     = 20,
-};
-
-static struct clk virtual_ck_mpu = {
-       .name           = "mpu",
-       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                         VIRTUAL_CLOCK | ALWAYS_ENABLED,
-       .parent         = &arm_ck, /* Is smarter alias for */
-       .recalc         = &followparent_recalc,
-       .set_rate       = &select_table_rate,
-       .round_rate     = &round_to_table_rate,
-};
-
-
-static struct clk *  onchip_clks[] = {
-       /* non-ULPD clocks */
-       &ck_ref,
-       &ck_dpll1,
-       /* CK_GEN1 clocks */
-       &ck_dpll1out,
-       &arm_ck,
-       &armper_ck,
-       &arm_gpio_ck,
-       &armxor_ck,
-       &armtim_ck,
-       &armwdt_ck,
-       &arminth_ck1510,  &arminth_ck16xx,
-       /* CK_GEN2 clocks */
-       &dsp_ck,
-       &dspmmu_ck,
-       /* CK_GEN3 clocks */
-       &tc_ck,
-       &tipb_ck,
-       &l3_ocpi_ck,
-       &tc1_ck,
-       &tc2_ck,
-       &dma_ck,
-       &dma_lcdfree_ck,
-       &api_ck,
-       &lb_ck,
-       &rhea1_ck,
-       &rhea2_ck,
-       &lcd_ck,
-       /* ULPD clocks */
-       &uart1_ck,
-       &uart2_ck,
-       &uart3_ck,
-       &usb_clko,
-       &usb_hhc_ck1510, &usb_hhc_ck16xx,
-       &mclk_1510,  &mclk_16xx,
-       &bclk_1510,  &bclk_16xx,
-       &mmc1_ck,
-       &mmc2_ck,
-       /* Virtual clocks */
-       &virtual_ck_mpu,
-};
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
-       struct clk *p, *clk = ERR_PTR(-ENOENT);
-
-       down(&clocks_sem);
-       list_for_each_entry(p, &clocks, node) {
-               if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                       clk = p;
-                       break;
-               }
-       }
-       up(&clocks_sem);
-
-       return clk;
-}
-EXPORT_SYMBOL(clk_get);
-
-
-void clk_put(struct clk *clk)
-{
-       if (clk && !IS_ERR(clk))
-               module_put(clk->owner);
-}
-EXPORT_SYMBOL(clk_put);
-
-
-int __clk_enable(struct clk *clk)
-{
-       __u16 regval16;
-       __u32 regval32;
-
-       if (clk->flags & ALWAYS_ENABLED)
-               return 0;
-
-       if (unlikely(clk->enable_reg == 0)) {
-               printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
-                      clk->name);
-               return 0;
-       }
-
-       if (clk->flags & ENABLE_REG_32BIT) {
-               regval32 = omap_readl(clk->enable_reg);
-               regval32 |= (1 << clk->enable_bit);
-               omap_writel(regval32, clk->enable_reg);
-       } else {
-               regval16 = omap_readw(clk->enable_reg);
-               regval16 |= (1 << clk->enable_bit);
-               omap_writew(regval16, clk->enable_reg);
-       }
-
-       return 0;
-}
-
-
-void __clk_disable(struct clk *clk)
-{
-       __u16 regval16;
-       __u32 regval32;
-
-       if (clk->enable_reg == 0)
-               return;
-
-       if (clk->flags & ENABLE_REG_32BIT) {
-               regval32 = omap_readl(clk->enable_reg);
-               regval32 &= ~(1 << clk->enable_bit);
-               omap_writel(regval32, clk->enable_reg);
-       } else {
-               regval16 = omap_readw(clk->enable_reg);
-               regval16 &= ~(1 << clk->enable_bit);
-               omap_writew(regval16, clk->enable_reg);
-       }
-}
-
-
-void __clk_unuse(struct clk *clk)
-{
-       if (clk->usecount > 0 && !(--clk->usecount)) {
-               __clk_disable(clk);
-               if (likely(clk->parent))
-                       __clk_unuse(clk->parent);
-       }
-}
-
-
-int __clk_use(struct clk *clk)
-{
-       int ret = 0;
-       if (clk->usecount++ == 0) {
-               if (likely(clk->parent))
-                       ret = __clk_use(clk->parent);
-
-               if (unlikely(ret != 0)) {
-                       clk->usecount--;
-                       return ret;
-               }
-
-               ret = __clk_enable(clk);
-
-               if (unlikely(ret != 0) && clk->parent) {
-                       __clk_unuse(clk->parent);
-                       clk->usecount--;
-               }
-       }
-
-       return ret;
-}
-
-
-int clk_enable(struct clk *clk)
-{
-       unsigned long flags;
-       int ret;
-
-       spin_lock_irqsave(&clockfw_lock, flags);
-       ret = __clk_enable(clk);
-       spin_unlock_irqrestore(&clockfw_lock, flags);
-       return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-
-void clk_disable(struct clk *clk)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&clockfw_lock, flags);
-       __clk_disable(clk);
-       spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-
-int clk_use(struct clk *clk)
-{
-       unsigned long flags;
-       int ret = 0;
-
-       spin_lock_irqsave(&clockfw_lock, flags);
-       ret = __clk_use(clk);
-       spin_unlock_irqrestore(&clockfw_lock, flags);
-       return ret;
-}
-EXPORT_SYMBOL(clk_use);
-
-
-void clk_unuse(struct clk *clk)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&clockfw_lock, flags);
-       __clk_unuse(clk);
-       spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-EXPORT_SYMBOL(clk_unuse);
-
-
-int clk_get_usecount(struct clk *clk)
-{
-        return clk->usecount;
-}
-EXPORT_SYMBOL(clk_get_usecount);
-
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-       return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-
-static __u16 verify_ckctl_value(__u16 newval)
-{
-       /* This function checks for following limitations set
-        * by the hardware (all conditions must be true):
-        * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
-        * ARM_CK >= TC_CK
-        * DSP_CK >= TC_CK
-        * DSPMMU_CK >= TC_CK
-        *
-        * In addition following rules are enforced:
-        * LCD_CK <= TC_CK
-        * ARMPER_CK <= TC_CK
-        *
-        * However, maximum frequencies are not checked for!
-        */
-       __u8 per_exp;
-       __u8 lcd_exp;
-       __u8 arm_exp;
-       __u8 dsp_exp;
-       __u8 tc_exp;
-       __u8 dspmmu_exp;
-
-       per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
-       lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
-       arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
-       dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
-       tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
-       dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
-
-       if (dspmmu_exp < dsp_exp)
-               dspmmu_exp = dsp_exp;
-       if (dspmmu_exp > dsp_exp+1)
-               dspmmu_exp = dsp_exp+1;
-       if (tc_exp < arm_exp)
-               tc_exp = arm_exp;
-       if (tc_exp < dspmmu_exp)
-               tc_exp = dspmmu_exp;
-       if (tc_exp > lcd_exp)
-               lcd_exp = tc_exp;
-       if (tc_exp > per_exp)
-               per_exp = tc_exp;
-
-       newval &= 0xf000;
-       newval |= per_exp << CKCTL_PERDIV_OFFSET;
-       newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
-       newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
-       newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
-       newval |= tc_exp << CKCTL_TCDIV_OFFSET;
-       newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
-
-       return newval;
-}
-
-
-static int calc_dsor_exp(struct clk *clk, unsigned long rate)
-{
-       /* Note: If target frequency is too low, this function will return 4,
-        * which is invalid value. Caller must check for this value and act
-        * accordingly.
-        *
-        * Note: This function does not check for following limitations set
-        * by the hardware (all conditions must be true):
-        * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
-        * ARM_CK >= TC_CK
-        * DSP_CK >= TC_CK
-        * DSPMMU_CK >= TC_CK
-        */
-       unsigned long realrate;
-       struct clk *  parent;
-       unsigned  dsor_exp;
-
-       if (unlikely(!(clk->flags & RATE_CKCTL)))
-               return -EINVAL;
-
-       parent = clk->parent;
-       if (unlikely(parent == 0))
-               return -EIO;
-
-       realrate = parent->rate;
-       for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
-               if (realrate <= rate)
-                       break;
-
-               realrate /= 2;
-       }
-
-       return dsor_exp;
-}
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-       int dsor_exp;
-
-       if (clk->flags & RATE_FIXED)
-               return clk->rate;
-
-       if (clk->flags & RATE_CKCTL) {
-               dsor_exp = calc_dsor_exp(clk, rate);
-               if (dsor_exp < 0)
-                       return dsor_exp;
-               if (dsor_exp > 3)
-                       dsor_exp = 3;
-               return clk->parent->rate / (1 << dsor_exp);
-       }
-
-       if(clk->round_rate != 0)
-               return clk->round_rate(clk, rate);
-
-       return clk->rate;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-
-static void propagate_rate(struct clk *  clk)
-{
-       struct clk **  clkp;
-
-       for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); 
clkp++) {
-               if (likely((*clkp)->parent != clk)) continue;
-               if (likely((*clkp)->recalc))
-                       (*clkp)->recalc(*clkp);
-       }
-}
-
-
-static int select_table_rate(struct clk *  clk, unsigned long rate)
-{
-       /* Find the highest supported frequency <= rate and switch to it */
-       struct mpu_rate *  ptr;
-
-       if (clk != &virtual_ck_mpu)
-               return -EINVAL;
-
-       for (ptr = rate_table; ptr->rate; ptr++) {
-               if (ptr->xtal != ck_ref.rate)
-                       continue;
-
-               /* DPLL1 cannot be reprogrammed without risking system crash */
-               if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
-                       continue;
-
-               /* Can check only after xtal frequency check */
-               if (ptr->rate <= rate)
-                       break;
-       }
-
-       if (!ptr->rate)
-               return -EINVAL;
-
-       if (unlikely(ck_dpll1.rate == 0)) {
-               omap_writew(ptr->dpllctl_val, DPLL_CTL);
-               ck_dpll1.rate = ptr->pll_rate;
-       }
-       omap_writew(ptr->ckctl_val, ARM_CKCTL);
-       propagate_rate(&ck_dpll1);
-       return 0;
-}
-
-
-static long round_to_table_rate(struct clk *  clk, unsigned long rate)
-{
-       /* Find the highest supported frequency <= rate */
-       struct mpu_rate *  ptr;
-       long  highest_rate;
-
-       if (clk != &virtual_ck_mpu)
-               return -EINVAL;
-
-       highest_rate = -EINVAL;
-
-       for (ptr = rate_table; ptr->rate; ptr++) {
-               if (ptr->xtal != ck_ref.rate)
-                       continue;
-
-               highest_rate = ptr->rate;
-
-               /* Can check only after xtal frequency check */
-               if (ptr->rate <= rate)
-                       break;
-       }
-
-       return highest_rate;
-}
-
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-       int  ret = -EINVAL;
-       int  dsor_exp;
-       __u16  regval;
-       unsigned long  flags;
-
-       if (clk->flags & RATE_CKCTL) {
-               dsor_exp = calc_dsor_exp(clk, rate);
-               if (dsor_exp > 3)
-                       dsor_exp = -EINVAL;
-               if (dsor_exp < 0)
-                       return dsor_exp;
-
-               spin_lock_irqsave(&clockfw_lock, flags);
-               regval = omap_readw(ARM_CKCTL);
-               regval &= ~(3 << clk->rate_offset);
-               regval |= dsor_exp << clk->rate_offset;
-               regval = verify_ckctl_value(regval);
-               omap_writew(regval, ARM_CKCTL);
-               clk->rate = clk->parent->rate / (1 << dsor_exp);
-               spin_unlock_irqrestore(&clockfw_lock, flags);
-               ret = 0;
-       } else if(clk->set_rate != 0) {
-               spin_lock_irqsave(&clockfw_lock, flags);
-               ret = clk->set_rate(clk, rate);
-               spin_unlock_irqrestore(&clockfw_lock, flags);
-       }
-
-       if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
-               propagate_rate(clk);
-
-       return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-
-static unsigned calc_ext_dsor(unsigned long rate)
-{
-       unsigned dsor;
-
-       /* MCLK and BCLK divisor selection is not linear:
-        * freq = 96MHz / dsor
-        *
-        * RATIO_SEL range: dsor <-> RATIO_SEL
-        * 0..6: (RATIO_SEL+2) <-> (dsor-2)
-        * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
-        * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
-        * can not be used.
-        */
-       for (dsor = 2; dsor < 96; ++dsor) {
-               if ((dsor & 1) && dsor > 8)
-                       continue;
-               if (rate >= 96000000 / dsor)
-                       break;
-       }
-       return dsor;
-}
-
-
-static int set_ext_clk_rate(struct clk *  clk, unsigned long rate)
-{
-       unsigned dsor;
-       __u16 ratio_bits;
-
-       dsor = calc_ext_dsor(rate);
-       clk->rate = 96000000 / dsor;
-       if (dsor > 8)
-               ratio_bits = ((dsor - 8) / 2 + 6) << 2;
-       else
-               ratio_bits = (dsor - 2) << 2;
-
-       ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
-       omap_writew(ratio_bits, clk->enable_reg);
-
-       return 0;
-}
-
-
-static long round_ext_clk_rate(struct clk *  clk, unsigned long rate)
-{
-       return 96000000 / calc_ext_dsor(rate);
-}
-
-
-static void init_ext_clk(struct clk *  clk)
-{
-       unsigned dsor;
-       __u16 ratio_bits;
-
-       /* Determine current rate and ensure clock is based on 96MHz APLL */
-       ratio_bits = omap_readw(clk->enable_reg) & ~1;
-       omap_writew(ratio_bits, clk->enable_reg);
-
-       ratio_bits = (ratio_bits & 0xfc) >> 2;
-       if (ratio_bits > 6)
-               dsor = (ratio_bits - 6) * 2 + 8;
-       else
-               dsor = ratio_bits + 2;
-
-       clk-> rate = 96000000 / dsor;
-}
-
-
-int clk_register(struct clk *clk)
-{
-       down(&clocks_sem);
-       list_add(&clk->node, &clocks);
-       if (clk->init)
-               clk->init(clk);
-       up(&clocks_sem);
-       return 0;
-}
-EXPORT_SYMBOL(clk_register);
-
-void clk_unregister(struct clk *clk)
-{
-       down(&clocks_sem);
-       list_del(&clk->node);
-       up(&clocks_sem);
-}
-EXPORT_SYMBOL(clk_unregister);
-
-
-
-int __init clk_init(void)
-{
-       struct clk **  clkp;
-       const struct omap_clock_config *info;
-       int crystal_type = 0; /* Default 12 MHz */
-
-       for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); 
clkp++) {
-               if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
-                       clk_register(*clkp);
-                       continue;
-               }
-
-               if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
-                       clk_register(*clkp);
-                       continue;
-               }
-
-               if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
-                       clk_register(*clkp);
-                       continue;
-               }
-       }
-
-       info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
-       if (info != NULL) {
-               if (!cpu_is_omap1510())
-                       crystal_type = info->system_clock_type;
-       }
-
-#if defined(CONFIG_ARCH_OMAP730)
-       ck_ref.rate = 13000000;
-#elif defined(CONFIG_ARCH_OMAP16XX)
-       if (crystal_type == 2)
-               ck_ref.rate = 19200000;
-#endif
-
-       /* We want to be in syncronous scalable mode */
-       omap_writew(0x1000, ARM_SYSST);
-
-       /* Find the highest supported frequency and enable it */
-       if (select_table_rate(&virtual_ck_mpu, ~0)) {
-               printk(KERN_ERR "System frequencies not set. Check your 
config.\n");
-               /* Guess sane values (60MHz) */
-               omap_writew(0x2290, DPLL_CTL);
-               omap_writew(0x1005, ARM_CKCTL);
-               ck_dpll1.rate = 60000000;
-               propagate_rate(&ck_dpll1);
-               printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): 
%ld/%ld/%ld\n",
-                      ck_ref.rate, ck_dpll1.rate, arm_ck.rate);
-       }
-
-       /* Cache rates for clocks connected to ck_ref (not dpll1) */
-       propagate_rate(&ck_ref);
-
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
-       /* Select slicer output as OMAP input clock */
-       omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, 
OMAP730_PCC_UPLD_CTRL);
-#endif
-
-       /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
-       omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
-
-       /* Put DSP/MPUI into reset until needed */
-       omap_writew(0, ARM_RSTCT1);
-       omap_writew(1, ARM_RSTCT2);
-       omap_writew(0x400, ARM_IDLECT1);
-
-       /*
-        * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
-        * of the ARM_IDLECT2 register must be set to zero. The power-on
-        * default value of this bit is one.
-        */
-       omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
-
-       /*
-        * Only enable those clocks we will need, let the drivers
-        * enable other clocks as necessary
-        */
-       clk_use(&armper_ck);
-       clk_use(&armxor_ck);
-       clk_use(&armtim_ck);
-
-       if (cpu_is_omap1510())
-               clk_enable(&arm_gpio_ck);
-
-       return 0;
-}
diff -urN linux/arch/arm/mach-omap/clock.h linux/arch/arm/mach-omap/clock.h
--- linux/arch/arm/mach-omap/Attic/clock.h      2005-07-13 12:48:51.921590000 
+0100     1.2
+++ linux/arch/arm/mach-omap/Attic/clock.h      1970/01/01 00:00:00+0100
@@ -1,112 +0,0 @@
-/*
- *  linux/arch/arm/mach-omap/clock.h
- *
- *  Copyright (C) 2004 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_OMAP_CLOCK_H
-#define __ARCH_ARM_OMAP_CLOCK_H
-
-struct module;
-
-struct clk {
-       struct list_head        node;
-       struct module           *owner;
-       const char              *name;
-       struct clk              *parent;
-       unsigned long           rate;
-       __s8                    usecount;
-       __u16                   flags;
-       __u32                   enable_reg;
-       __u8                    enable_bit;
-       __u8                    rate_offset;
-       void                    (*recalc)(struct clk *);
-       int                     (*set_rate)(struct clk *, unsigned long);
-       long                    (*round_rate)(struct clk *, unsigned long);
-       void                    (*init)(struct clk *);
-};
-
-
-struct mpu_rate {
-       unsigned long           rate;
-       unsigned long           xtal;
-       unsigned long           pll_rate;
-       __u16                   ckctl_val;
-       __u16                   dpllctl_val;
-};
-
-
-/* Clock flags */
-#define RATE_CKCTL             1
-#define RATE_FIXED             2
-#define RATE_PROPAGATES                4
-#define VIRTUAL_CLOCK          8
-#define ALWAYS_ENABLED         16
-#define ENABLE_REG_32BIT       32
-#define CLOCK_IN_OMAP16XX      64
-#define CLOCK_IN_OMAP1510      128
-#define CLOCK_IN_OMAP730       256
-
-/* ARM_CKCTL bit shifts */
-#define CKCTL_PERDIV_OFFSET    0
-#define CKCTL_LCDDIV_OFFSET    2
-#define CKCTL_ARMDIV_OFFSET    4
-#define CKCTL_DSPDIV_OFFSET    6
-#define CKCTL_TCDIV_OFFSET     8
-#define CKCTL_DSPMMUDIV_OFFSET 10
-/*#define ARM_TIMXO            12*/
-#define EN_DSPCK               13
-/*#define ARM_INTHCK_SEL       14*/ /* Divide-by-2 for mpu inth_ck */
-
-/* ARM_IDLECT1 bit shifts */
-/*#define IDLWDT_ARM   0*/
-/*#define IDLXORP_ARM  1*/
-/*#define IDLPER_ARM   2*/
-/*#define IDLLCD_ARM   3*/
-/*#define IDLLB_ARM    4*/
-/*#define IDLHSAB_ARM  5*/
-/*#define IDLIF_ARM    6*/
-/*#define IDLDPLL_ARM  7*/
-/*#define IDLAPI_ARM   8*/
-/*#define IDLTIM_ARM   9*/
-/*#define SETARM_IDLE  11*/
-
-/* ARM_IDLECT2 bit shifts */
-#define EN_WDTCK       0
-#define EN_XORPCK      1
-#define EN_PERCK       2
-#define EN_LCDCK       3
-#define EN_LBCK                4 /* Not on 1610/1710 */
-/*#define EN_HSABCK    5*/
-#define EN_APICK       6
-#define EN_TIMCK       7
-#define DMACK_REQ      8
-#define EN_GPIOCK      9 /* Not on 1610/1710 */
-/*#define EN_LBFREECK  10*/
-#define EN_CKOUT_ARM   11
-
-/* ARM_IDLECT3 bit shifts */
-#define EN_OCPI_CK     0
-#define EN_TC1_CK      2
-#define EN_TC2_CK      4
-
-/* Various register defines for clock controls scattered around OMAP chip */
-#define USB_MCLK_EN_BIT                4       /* In ULPD_CLKC_CTRL */
-#define USB_HOST_HHC_UHOST_EN  9       /* In MOD_CONF_CTRL_0 */
-#define SWD_ULPD_PLL_CLK_REQ   1       /* In SWD_CLK_DIV_CTRL_SEL */
-#define COM_ULPD_PLL_CLK_REQ   1       /* In COM_CLK_DIV_CTRL_SEL */
-#define SWD_CLK_DIV_CTRL_SEL   0xfffe0874
-#define COM_CLK_DIV_CTRL_SEL   0xfffe0878
-
-
-int clk_register(struct clk *clk);
-void clk_unregister(struct clk *clk);
-int clk_init(void);
-
-#endif
diff -urN linux/arch/arm/mach-omap/common.c linux/arch/arm/mach-omap/common.c
--- linux/arch/arm/mach-omap/Attic/common.c     2005-07-13 12:48:51.943626000 
+0100     1.7
+++ linux/arch/arm/mach-omap/Attic/common.c     1970/01/01 00:00:00+0100
@@ -1,549 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/common.c
- *
- * Code common to all OMAP machines.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/config.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/pm.h>
-#include <linux/console.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_reg.h>
-
-#include <asm/hardware.h>
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <asm/hardware/clock.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-
-#include <asm/arch/board.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/fpga.h>
-
-#include "clock.h"
-
-#define DEBUG 1
-
-struct omap_id {
-       u16     jtag_id;        /* Used to determine OMAP type */
-       u8      die_rev;        /* Processor revision */
-       u32     omap_id;        /* OMAP revision */
-       u32     type;           /* Cpu id bits [31:08], cpu class bits [07:00] 
*/
-};
-
-/* Register values to detect the OMAP version */
-static struct omap_id omap_ids[] __initdata = {
-       { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 
0x07300100},
-       { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 
0x07300300},
-       { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 
0x15100000},
-       { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 
0x16100000},
-       { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 
0x16110000},
-       { .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 
0x16100c00},
-       { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 
0x16100d00},
-       { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 
0x1610ef00},
-       { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 
0x1610ef00},
-       { .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 
0x16110000},
-       { .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 
0x16110b00},
-       { .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 
0x16110c00},
-       { .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 
0x16212300},
-       { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 
0x16212300},
-       { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 
0x16212300},
-       { .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 
0x17100000},
-       { .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 
0x17100000},
-       { .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 
0x17100000},
-};
-
-/*
- * Get OMAP type from PROD_ID.
- * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM.
- * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense.
- * Undocumented register in TEST BLOCK is used as fallback; This seems to
- * work on 1510, 1610 & 1710. The official way hopefully will work in future
- * processors.
- */
-static u16 __init omap_get_jtag_id(void)
-{
-       u32 prod_id, omap_id;
-
-       prod_id = omap_readl(OMAP_PRODUCTION_ID_1);
-       omap_id = omap_readl(OMAP32_ID_1);
-
-       /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */
-       if (((prod_id >> 20) == 0) || (prod_id == omap_id))
-               prod_id = 0;
-       else
-               prod_id &= 0xffff;
-
-       if (prod_id)
-               return prod_id;
-
-       /* Use OMAP32_ID_1 as fallback */
-       prod_id = ((omap_id >> 12) & 0xffff);
-
-       return prod_id;
-}
-
-/*
- * Get OMAP revision from DIE_REV.
- * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID.
- * Undocumented register in the TEST BLOCK is used as fallback.
- * REVISIT: This does not seem to work on 1510
- */
-static u8 __init omap_get_die_rev(void)
-{
-       u32 die_rev;
-
-       die_rev = omap_readl(OMAP_DIE_ID_1);
-
-       /* Check for broken OMAP_DIE_ID on early 1710 */
-       if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id())
-               die_rev = 0;
-
-       die_rev = (die_rev >> 17) & 0xf;
-       if (die_rev)
-               return die_rev;
-
-       die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf;
-
-       return die_rev;
-}
-
-static void __init omap_check_revision(void)
-{
-       int i;
-       u16 jtag_id;
-       u8 die_rev;
-       u32 omap_id;
-       u8 cpu_type;
-
-       jtag_id = omap_get_jtag_id();
-       die_rev = omap_get_die_rev();
-       omap_id = omap_readl(OMAP32_ID_0);
-
-#ifdef DEBUG
-       printk("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0));
-       printk("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n",
-               omap_readl(OMAP_DIE_ID_1),
-              (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf);
-       printk("OMAP_PRODUCTION_ID_0: 0x%08x\n", 
omap_readl(OMAP_PRODUCTION_ID_0));
-       printk("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n",
-               omap_readl(OMAP_PRODUCTION_ID_1),
-               omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff);
-       printk("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0));
-       printk("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1));
-       printk("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev);
-#endif
-
-       system_serial_high = omap_readl(OMAP_DIE_ID_0);
-       system_serial_low = omap_readl(OMAP_DIE_ID_1);
-
-       /* First check only the major version in a safe way */
-       for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
-               if (jtag_id == (omap_ids[i].jtag_id)) {
-                       system_rev = omap_ids[i].type;
-                       break;
-               }
-       }
-
-       /* Check if we can find the die revision */
-       for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
-               if (jtag_id == omap_ids[i].jtag_id && die_rev == 
omap_ids[i].die_rev) {
-                       system_rev = omap_ids[i].type;
-                       break;
-               }
-       }
-
-       /* Finally check also the omap_id */
-       for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
-               if (jtag_id == omap_ids[i].jtag_id
-                   && die_rev == omap_ids[i].die_rev
-                   && omap_id == omap_ids[i].omap_id) {
-                       system_rev = omap_ids[i].type;
-                       break;
-               }
-       }
-
-       /* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */
-       cpu_type = system_rev >> 24;
-
-       switch (cpu_type) {
-       case 0x07:
-               system_rev |= 0x07;
-               break;
-       case 0x15:
-               system_rev |= 0x15;
-               break;
-       case 0x16:
-       case 0x17:
-               system_rev |= 0x16;
-               break;
-       case 0x24:
-               system_rev |= 0x24;
-               break;
-       default:
-               printk("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
-       }
-
-       printk("OMAP%04x", system_rev >> 16);
-       if ((system_rev >> 8) & 0xff)
-               printk("%x", (system_rev >> 8) & 0xff);
-       printk(" revision %i handled as %02xxx id: %08x%08x\n",
-              die_rev, system_rev & 0xff, system_serial_low,
-              system_serial_high);
-}
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP I/O mapping
- *
- * The machine specific code may provide the extra mapping besides the
- * default mapping provided here.
- * ----------------------------------------------------------------------------
- */
-
-static struct map_desc omap_io_desc[] __initdata = {
- { IO_VIRT,            IO_PHYS,             IO_SIZE,              MT_DEVICE },
-};
-
-#ifdef CONFIG_ARCH_OMAP730
-static struct map_desc omap730_io_desc[] __initdata = {
- { OMAP730_DSP_BASE,    OMAP730_DSP_START,    OMAP730_DSP_SIZE,    MT_DEVICE },
- { OMAP730_DSPREG_BASE, OMAP730_DSPREG_START, OMAP730_DSPREG_SIZE, MT_DEVICE },
- { OMAP730_SRAM_BASE,   OMAP730_SRAM_START,   OMAP730_SRAM_SIZE,   MT_DEVICE }
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP1510
-static struct map_desc omap1510_io_desc[] __initdata = {
- { OMAP1510_DSP_BASE,    OMAP1510_DSP_START,    OMAP1510_DSP_SIZE,    
MT_DEVICE },
- { OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_START, OMAP1510_DSPREG_SIZE, 
MT_DEVICE },
- { OMAP1510_SRAM_BASE,   OMAP1510_SRAM_START,   OMAP1510_SRAM_SIZE,   
MT_DEVICE }
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-static struct map_desc omap1610_io_desc[] __initdata = {
- { OMAP16XX_DSP_BASE,    OMAP16XX_DSP_START,    OMAP16XX_DSP_SIZE,    
MT_DEVICE },
- { OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_START, OMAP16XX_DSPREG_SIZE, 
MT_DEVICE },
- { OMAP16XX_SRAM_BASE,   OMAP16XX_SRAM_START,   OMAP1610_SRAM_SIZE,   
MT_DEVICE }
-};
-
-static struct map_desc omap5912_io_desc[] __initdata = {
- { OMAP16XX_DSP_BASE,    OMAP16XX_DSP_START,    OMAP16XX_DSP_SIZE,    
MT_DEVICE },
- { OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_START, OMAP16XX_DSPREG_SIZE, 
MT_DEVICE },
-/*
- * The OMAP5912 has 250kByte internal SRAM. Because the mapping is baseed on 
page
- * size (4kByte), it seems that the last 2kByte (=0x800) of the 250kByte are 
not mapped.
- * Add additional 2kByte (0x800) so that the last page is mapped and the last 
2kByte
- * can be used.
- */
- { OMAP16XX_SRAM_BASE,   OMAP16XX_SRAM_START,   OMAP5912_SRAM_SIZE + 0x800,   
MT_DEVICE }
-};
-#endif
-
-static int initialized = 0;
-
-static void __init _omap_map_io(void)
-{
-       initialized = 1;
-
-       /* We have to initialize the IO space mapping before we can run
-        * cpu_is_omapxxx() macros. */
-       iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc));
-       omap_check_revision();
-
-#ifdef CONFIG_ARCH_OMAP730
-       if (cpu_is_omap730()) {
-               iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc));
-       }
-#endif
-#ifdef CONFIG_ARCH_OMAP1510
-       if (cpu_is_omap1510()) {
-               iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
-       }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-       if (cpu_is_omap1610() || cpu_is_omap1710()) {
-               iotable_init(omap1610_io_desc, ARRAY_SIZE(omap1610_io_desc));
-       }
-       if (cpu_is_omap5912()) {
-               iotable_init(omap5912_io_desc, ARRAY_SIZE(omap5912_io_desc));
-       }
-#endif
-
-       /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
-        * on a Posted Write in the TIPB Bridge".
-        */
-       omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL);
-       omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL);
-
-       /* Must init clocks early to assure that timer interrupt works
-        */
-       clk_init();
-}
-
-/*
- * This should only get called from board specific init
- */
-void omap_map_io(void)
-{
-       if (!initialized)
-               _omap_map_io();
-}
-
-static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
-                                         int offset)
-{
-       offset <<= up->regshift;
-       return (unsigned int)__raw_readb(up->membase + offset);
-}
-
-static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
-                                   int value)
-{
-       offset <<= p->regshift;
-       __raw_writeb(value, p->membase + offset);
-}
-
-/*
- * Internal UARTs need to be initialized for the 8250 autoconfig to work
- * properly. Note that the TX watermark initialization may not be needed
- * once the 8250.c watermark handling code is merged.
- */
-static void __init omap_serial_reset(struct plat_serial8250_port *p)
-{
-       omap_serial_outp(p, UART_OMAP_MDR1, 0x07);      /* disable UART */
-       omap_serial_outp(p, UART_OMAP_SCR, 0x08);       /* TX watermark */
-       omap_serial_outp(p, UART_OMAP_MDR1, 0x00);      /* enable UART */
-
-       if (!cpu_is_omap1510()) {
-               omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
-               while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
-       }
-}
-
-static struct plat_serial8250_port serial_platform_data[] = {
-       {
-               .membase        = (char*)IO_ADDRESS(OMAP_UART1_BASE),
-               .mapbase        = (unsigned long)OMAP_UART1_BASE,
-               .irq            = INT_UART1,
-               .flags          = UPF_BOOT_AUTOCONF,
-               .iotype         = UPIO_MEM,
-               .regshift       = 2,
-               .uartclk        = OMAP16XX_BASE_BAUD * 16,
-       },
-       {
-               .membase        = (char*)IO_ADDRESS(OMAP_UART2_BASE),
-               .mapbase        = (unsigned long)OMAP_UART2_BASE,
-               .irq            = INT_UART2,
-               .flags          = UPF_BOOT_AUTOCONF,
-               .iotype         = UPIO_MEM,
-               .regshift       = 2,
-               .uartclk        = OMAP16XX_BASE_BAUD * 16,
-       },
-       {
-               .membase        = (char*)IO_ADDRESS(OMAP_UART3_BASE),
-               .mapbase        = (unsigned long)OMAP_UART3_BASE,
-               .irq            = INT_UART3,
-               .flags          = UPF_BOOT_AUTOCONF,
-               .iotype         = UPIO_MEM,
-               .regshift       = 2,
-               .uartclk        = OMAP16XX_BASE_BAUD * 16,
-       },
-       { },
-};
-
-static struct platform_device serial_device = {
-       .name                   = "serial8250",
-       .id                     = 0,
-       .dev                    = {
-               .platform_data  = serial_platform_data,
-       },
-};
-
-/*
- * Note that on Innovator-1510 UART2 pins conflict with USB2.
- * By default UART2 does not work on Innovator-1510 if you have
- * USB OHCI enabled. To use UART2, you must disable USB2 first.
- */
-void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS])
-{
-       int i;
-
-       if (cpu_is_omap730()) {
-               serial_platform_data[0].regshift = 0;
-               serial_platform_data[1].regshift = 0;
-               serial_platform_data[0].irq = INT_730_UART_MODEM_1;
-               serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
-       }
-
-       if (cpu_is_omap1510()) {
-               serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
-               serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
-               serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
-       }
-
-       for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
-               unsigned char reg;
-
-               if (ports[i] == 0) {
-                       serial_platform_data[i].membase = 0;
-                       serial_platform_data[i].mapbase = 0;
-                       continue;
-               }
-
-               switch (i) {
-               case 0:
-                       if (cpu_is_omap1510()) {
-                               omap_cfg_reg(UART1_TX);
-                               omap_cfg_reg(UART1_RTS);
-                               if (machine_is_omap_innovator()) {
-                                       reg = fpga_read(OMAP1510_FPGA_POWER);
-                                       reg |= OMAP1510_FPGA_PCR_COM1_EN;
-                                       fpga_write(reg, OMAP1510_FPGA_POWER);
-                                       udelay(10);
-                               }
-                       }
-                       break;
-               case 1:
-                       if (cpu_is_omap1510()) {
-                               omap_cfg_reg(UART2_TX);
-                               omap_cfg_reg(UART2_RTS);
-                               if (machine_is_omap_innovator()) {
-                                       reg = fpga_read(OMAP1510_FPGA_POWER);
-                                       reg |= OMAP1510_FPGA_PCR_COM2_EN;
-                                       fpga_write(reg, OMAP1510_FPGA_POWER);
-                                       udelay(10);
-                               }
-                       }
-                       break;
-               case 2:
-                       if (cpu_is_omap1510()) {
-                               omap_cfg_reg(UART3_TX);
-                               omap_cfg_reg(UART3_RX);
-                       }
-                       if (cpu_is_omap1710()) {
-                               clk_enable(clk_get(0, "uart3_ck"));
-                       }
-                       break;
-               }
-               omap_serial_reset(&serial_platform_data[i]);
-       }
-}
-
-static int __init omap_init(void)
-{
-       return platform_device_register(&serial_device);
-}
-arch_initcall(omap_init);
-
-#define NO_LENGTH_CHECK 0xffffffff
-
-extern int omap_bootloader_tag_len;
-extern u8 omap_bootloader_tag[];
-
-struct omap_board_config_kernel *omap_board_config;
-int omap_board_config_size = 0;
-
-static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
-{
-       struct omap_board_config_kernel *kinfo = NULL;
-       int i;
-
-#ifdef CONFIG_OMAP_BOOT_TAG
-       struct omap_board_config_entry *info = NULL;
-
-       if (omap_bootloader_tag_len > 4)
-               info = (struct omap_board_config_entry *) omap_bootloader_tag;
-       while (info != NULL) {
-               u8 *next;
-
-               if (info->tag == tag) {
-                       if (skip == 0)
-                               break;
-                       skip--;
-               }
-
-               if ((info->len & 0x03) != 0) {
-                       /* We bail out to avoid an alignment fault */
-                       printk(KERN_ERR "OMAP peripheral config: Length (%d) 
not word-aligned (tag %04x)\n",
-                              info->len, info->tag);
-                       return NULL;
-               }
-               next = (u8 *) info + sizeof(*info) + info->len;
-               if (next >= omap_bootloader_tag + omap_bootloader_tag_len)
-                       info = NULL;
-               else
-                       info = (struct omap_board_config_entry *) next;
-       }
-       if (info != NULL) {
-               /* Check the length as a lame attempt to check for
-                * binary inconsistancy. */
-               if (len != NO_LENGTH_CHECK) {
-                       /* Word-align len */
-                       if (len & 0x03)
-                               len = (len + 3) & ~0x03;
-                       if (info->len != len) {
-                               printk(KERN_ERR "OMAP peripheral config: Length 
mismatch with tag %x (want %d, got %d)\n",
-                                      tag, len, info->len);
-                               return NULL;
-                       }
-               }
-               if (len_out != NULL)
-                       *len_out = info->len;
-               return info->data;
-       }
-#endif
-       /* Try to find the config from the board-specific structures
-        * in the kernel. */
-       for (i = 0; i < omap_board_config_size; i++) {
-               if (omap_board_config[i].tag == tag) {
-                       kinfo = &omap_board_config[i];
-                       break;
-               }
-       }
-       if (kinfo == NULL)
-               return NULL;
-       return kinfo->data;
-}
-
-const void *__omap_get_config(u16 tag, size_t len, int nr)
-{
-        return get_config(tag, len, nr, NULL);
-}
-EXPORT_SYMBOL(__omap_get_config);
-
-const void *omap_get_var_config(u16 tag, size_t *len)
-{
-        return get_config(tag, NO_LENGTH_CHECK, 0, len);
-}
-EXPORT_SYMBOL(omap_get_var_config);
-
-static int __init omap_add_serial_console(void)
-{
-       const struct omap_uart_config *info;
-
-       info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
-       if (info != NULL && info->console_uart) {
-               static char speed[11], *opt = NULL;
-
-               if (info->console_speed) {
-                       snprintf(speed, sizeof(speed), "%u", 
info->console_speed);
-                       opt = speed;
-               }
-               return add_preferred_console("ttyS", info->console_uart - 1, 
opt);
-       }
-       return 0;
-}
-console_initcall(omap_add_serial_console);
diff -urN linux/arch/arm/mach-omap/common.h linux/arch/arm/mach-omap/common.h
--- linux/arch/arm/mach-omap/Attic/common.h     2005-07-13 12:48:51.972153000 
+0100     1.6
+++ linux/arch/arm/mach-omap/Attic/common.h     1970/01/01 00:00:00+0100
@@ -1,36 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/common.h
- *
- * Header for code common to all OMAP machines.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
-#define __ARCH_ARM_MACH_OMAP_COMMON_H
-
-struct sys_timer;
-
-extern void omap_map_io(void);
-extern struct sys_timer omap_timer;
-extern void omap_serial_init(int ports[]);
-
-#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff -urN linux/arch/arm/mach-omap/dma.c linux/arch/arm/mach-omap/dma.c
--- linux/arch/arm/mach-omap/Attic/dma.c        2005-07-13 12:48:51.994066000 
+0100     1.8
+++ linux/arch/arm/mach-omap/Attic/dma.c        1970/01/01 00:00:00+0100
@@ -1,1086 +0,0 @@
-/*
- * linux/arch/arm/omap/dma.c
- *
- * Copyright (C) 2003 Nokia Corporation
- * Author: Juha Yrjölä <juha.yrjola@nokia.com>
- * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
- * Graphics DMA and LCD DMA graphics tranformations
- * by Imre Deak <imre.deak@nokia.com>
- * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
- *
- * Support functions for the OMAP internal DMA channels.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-
-#include <asm/system.h>
-#include <asm/irq.h>
-#include <asm/hardware.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-
-#include <asm/arch/tc.h>
-
-#define OMAP_DMA_ACTIVE                0x01
-
-#define OMAP_DMA_CCR_EN                (1 << 7)
-
-#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
-
-static int enable_1510_mode = 0;
-
-struct omap_dma_lch {
-       int next_lch;
-       int dev_id;
-       u16 saved_csr;
-       u16 enabled_irqs;
-       const char *dev_name;
-       void (* callback)(int lch, u16 ch_status, void *data);
-       void *data;
-       long flags;
-};
-
-static int dma_chan_count;
-
-static spinlock_t dma_chan_lock;
-static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
-
-const static u8 dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
-       INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
-       INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
-       INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
-       INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
-       INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
-};
-
-static inline int get_gdma_dev(int req)
-{
-       u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
-       int shift = ((req - 1) % 5) * 6;
-
-       return ((omap_readl(reg) >> shift) & 0x3f) + 1;
-}
-
-static inline void set_gdma_dev(int req, int dev)
-{
-       u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
-       int shift = ((req - 1) % 5) * 6;
-       u32 l;
-
-       l = omap_readl(reg);
-       l &= ~(0x3f << shift);
-       l |= (dev - 1) << shift;
-       omap_writel(l, reg);
-}
-
-static void clear_lch_regs(int lch)
-{
-       int i;
-       u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
-
-       for (i = 0; i < 0x2c; i += 2)
-               omap_writew(0, lch_base + i);
-}
-
-void omap_set_dma_priority(int dst_port, int priority)
-{
-       unsigned long reg;
-       u32 l;
-
-       switch (dst_port) {
-       case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
-               reg = OMAP_TC_OCPT1_PRIOR;
-               break;
-       case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
-               reg = OMAP_TC_OCPT2_PRIOR;
-               break;
-       case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
-               reg = OMAP_TC_EMIFF_PRIOR;
-               break;
-       case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
-               reg = OMAP_TC_EMIFS_PRIOR;
-               break;
-       default:
-               BUG();
-               return;
-       }
-       l = omap_readl(reg);
-       l &= ~(0xf << 8);
-       l |= (priority & 0xf) << 8;
-       omap_writel(l, reg);
-}
-
-void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
-                                 int frame_count, int sync_mode)
-{
-       u16 w;
-
-       w = omap_readw(OMAP_DMA_CSDP(lch));
-       w &= ~0x03;
-       w |= data_type;
-       omap_writew(w, OMAP_DMA_CSDP(lch));
-
-       w = omap_readw(OMAP_DMA_CCR(lch));
-       w &= ~(1 << 5);
-       if (sync_mode == OMAP_DMA_SYNC_FRAME)
-               w |= 1 << 5;
-       omap_writew(w, OMAP_DMA_CCR(lch));
-
-       w = omap_readw(OMAP_DMA_CCR2(lch));
-       w &= ~(1 << 2);
-       if (sync_mode == OMAP_DMA_SYNC_BLOCK)
-               w |= 1 << 2;
-       omap_writew(w, OMAP_DMA_CCR2(lch));
-
-       omap_writew(elem_count, OMAP_DMA_CEN(lch));
-       omap_writew(frame_count, OMAP_DMA_CFN(lch));
-
-}
-void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
-{
-       u16 w;
-
-       BUG_ON(omap_dma_in_1510_mode());
-
-       w = omap_readw(OMAP_DMA_CCR2(lch)) & ~0x03;
-       switch (mode) {
-       case OMAP_DMA_CONSTANT_FILL:
-               w |= 0x01;
-               break;
-       case OMAP_DMA_TRANSPARENT_COPY:
-               w |= 0x02;
-               break;
-       case OMAP_DMA_COLOR_DIS:
-               break;
-       default:
-               BUG();
-       }
-       omap_writew(w, OMAP_DMA_CCR2(lch));
-
-       w = omap_readw(OMAP_DMA_LCH_CTRL(lch)) & ~0x0f;
-       /* Default is channel type 2D */
-       if (mode) {
-               omap_writew((u16)color, OMAP_DMA_COLOR_L(lch));
-               omap_writew((u16)(color >> 16), OMAP_DMA_COLOR_U(lch));
-               w |= 1;         /* Channel type G */
-       }
-       omap_writew(w, OMAP_DMA_LCH_CTRL(lch));
-}
-
-
-void omap_set_dma_src_params(int lch, int src_port, int src_amode,
-                            unsigned long src_start)
-{
-       u16 w;
-
-       w = omap_readw(OMAP_DMA_CSDP(lch));
-       w &= ~(0x1f << 2);
-       w |= src_port << 2;
-       omap_writew(w, OMAP_DMA_CSDP(lch));
-
-       w = omap_readw(OMAP_DMA_CCR(lch));
-       w &= ~(0x03 << 12);
-       w |= src_amode << 12;
-       omap_writew(w, OMAP_DMA_CCR(lch));
-
-       omap_writew(src_start >> 16, OMAP_DMA_CSSA_U(lch));
-       omap_writew(src_start, OMAP_DMA_CSSA_L(lch));
-}
-
-void omap_set_dma_src_index(int lch, int eidx, int fidx)
-{
-       omap_writew(eidx, OMAP_DMA_CSEI(lch));
-       omap_writew(fidx, OMAP_DMA_CSFI(lch));
-}
-
-void omap_set_dma_src_data_pack(int lch, int enable)
-{
-       u16 w;
-
-       w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 6);
-       w |= enable ? (1 << 6) : 0;
-       omap_writew(w, OMAP_DMA_CSDP(lch));
-}
-
-void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
-{
-       u16 w;
-
-       w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 7);
-       switch (burst_mode) {
-       case OMAP_DMA_DATA_BURST_DIS:
-               break;
-       case OMAP_DMA_DATA_BURST_4:
-               w |= (0x01 << 7);
-               break;
-       case OMAP_DMA_DATA_BURST_8:
-               /* not supported by current hardware
-                * w |= (0x03 << 7);
-                * fall through
-                */
-       default:
-               BUG();
-       }
-       omap_writew(w, OMAP_DMA_CSDP(lch));
-}
-
-void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
-                             unsigned long dest_start)
-{
-       u16 w;
-
-       w = omap_readw(OMAP_DMA_CSDP(lch));
-       w &= ~(0x1f << 9);
-       w |= dest_port << 9;
-       omap_writew(w, OMAP_DMA_CSDP(lch));
-
-       w = omap_readw(OMAP_DMA_CCR(lch));
-       w &= ~(0x03 << 14);
-       w |= dest_amode << 14;
-       omap_writew(w, OMAP_DMA_CCR(lch));
-
-       omap_writew(dest_start >> 16, OMAP_DMA_CDSA_U(lch));
-       omap_writew(dest_start, OMAP_DMA_CDSA_L(lch));
-}
-
-void omap_set_dma_dest_index(int lch, int eidx, int fidx)
-{
-       omap_writew(eidx, OMAP_DMA_CDEI(lch));
-       omap_writew(fidx, OMAP_DMA_CDFI(lch));
-}
-
-void omap_set_dma_dest_data_pack(int lch, int enable)
-{
-       u16 w;
-
-       w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 13);
-       w |= enable ? (1 << 13) : 0;
-       omap_writew(w, OMAP_DMA_CSDP(lch));
-}
-
-void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
-{
-       u16 w;
-
-       w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 14);
-       switch (burst_mode) {
-       case OMAP_DMA_DATA_BURST_DIS:
-               break;
-       case OMAP_DMA_DATA_BURST_4:
-               w |= (0x01 << 14);
-               break;
-       case OMAP_DMA_DATA_BURST_8:
-               w |= (0x03 << 14);
-               break;
-       default:
-               printk(KERN_ERR "Invalid DMA burst mode\n");
-               BUG();
-               return;
-       }
-       omap_writew(w, OMAP_DMA_CSDP(lch));
-}
-
-static inline void init_intr(int lch)
-{
-       u16 w;
-
-       /* Read CSR to make sure it's cleared. */
-       w = omap_readw(OMAP_DMA_CSR(lch));
-       /* Enable some nice interrupts. */
-       omap_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR(lch));
-       dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
-}
-
-static inline void enable_lnk(int lch)
-{
-       u16 w;
-
-       /* Clear the STOP_LNK bits */
-       w = omap_readw(OMAP_DMA_CLNK_CTRL(lch));
-       w &= ~(1 << 14);
-       omap_writew(w, OMAP_DMA_CLNK_CTRL(lch));
-
-       /* And set the ENABLE_LNK bits */
-       if (dma_chan[lch].next_lch != -1)
-               omap_writew(dma_chan[lch].next_lch | (1 << 15),
-                           OMAP_DMA_CLNK_CTRL(lch));
-}
-
-static inline void disable_lnk(int lch)
-{
-       u16 w;
-
-       /* Disable interrupts */
-       omap_writew(0, OMAP_DMA_CICR(lch));
-
-       /* Set the STOP_LNK bit */
-       w = omap_readw(OMAP_DMA_CLNK_CTRL(lch));
-       w |= (1 << 14);
-       w = omap_writew(w, OMAP_DMA_CLNK_CTRL(lch));
-
-       dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
-}
-
-void omap_start_dma(int lch)
-{
-       u16 w;
-
-       if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
-               int next_lch, cur_lch;
-               char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
-
-               dma_chan_link_map[lch] = 1;
-               /* Set the link register of the first channel */
-               enable_lnk(lch);
-
-               memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
-               cur_lch = dma_chan[lch].next_lch;
-               do {
-                       next_lch = dma_chan[cur_lch].next_lch;
-
-                        /* The loop case: we've been here already */
-                       if (dma_chan_link_map[cur_lch])
-                               break;
-                       /* Mark the current channel */
-                       dma_chan_link_map[cur_lch] = 1;
-
-                       enable_lnk(cur_lch);
-                       init_intr(cur_lch);
-
-                       cur_lch = next_lch;
-               } while (next_lch != -1);
-       }
-
-       init_intr(lch);
-
-       w = omap_readw(OMAP_DMA_CCR(lch));
-       w |= OMAP_DMA_CCR_EN;
-       omap_writew(w, OMAP_DMA_CCR(lch));
-       dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
-}
-
-void omap_stop_dma(int lch)
-{
-       u16 w;
-
-       if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
-               int next_lch, cur_lch = lch;
-               char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
-
-               memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
-               do {
-                       /* The loop case: we've been here already */
-                       if (dma_chan_link_map[cur_lch])
-                               break;
-                       /* Mark the current channel */
-                       dma_chan_link_map[cur_lch] = 1;
-
-                       disable_lnk(cur_lch);
-
-                       next_lch = dma_chan[cur_lch].next_lch;
-                       cur_lch = next_lch;
-               } while (next_lch != -1);
-
-               return;
-       }
-       /* Disable all interrupts on the channel */
-       omap_writew(0, OMAP_DMA_CICR(lch));
-
-       w = omap_readw(OMAP_DMA_CCR(lch));
-       w &= ~OMAP_DMA_CCR_EN;
-       omap_writew(w, OMAP_DMA_CCR(lch));
-       dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
-}
-
-void omap_enable_dma_irq(int lch, u16 bits)
-{
-       dma_chan[lch].enabled_irqs |= bits;
-}
-
-void omap_disable_dma_irq(int lch, u16 bits)
-{
-       dma_chan[lch].enabled_irqs &= ~bits;
-}
-
-static int dma_handle_ch(int ch)
-{
-       u16 csr;
-
-       if (enable_1510_mode && ch >= 6) {
-               csr = dma_chan[ch].saved_csr;
-               dma_chan[ch].saved_csr = 0;
-       } else
-               csr = omap_readw(OMAP_DMA_CSR(ch));
-       if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
-               dma_chan[ch + 6].saved_csr = csr >> 7;
-               csr &= 0x7f;
-       }
-       if (!csr)
-               return 0;
-       if (unlikely(dma_chan[ch].dev_id == -1)) {
-               printk(KERN_WARNING "Spurious interrupt from DMA channel %d 
(CSR %04x)\n",
-                      ch, csr);
-               return 0;
-       }
-       if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
-               printk(KERN_WARNING "DMA timeout with device %d\n", 
dma_chan[ch].dev_id);
-       if (unlikely(csr & OMAP_DMA_DROP_IRQ))
-               printk(KERN_WARNING "DMA synchronization event drop occurred 
with device %d\n",
-                      dma_chan[ch].dev_id);
-       if (likely(csr & OMAP_DMA_BLOCK_IRQ))
-               dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
-       if (likely(dma_chan[ch].callback != NULL))
-               dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
-       return 1;
-}
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
-{
-       int ch = ((int) dev_id) - 1;
-       int handled = 0;
-
-       for (;;) {
-               int handled_now = 0;
-
-               handled_now += dma_handle_ch(ch);
-               if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
-                       handled_now += dma_handle_ch(ch + 6);
-               if (!handled_now)
-                       break;
-               handled += handled_now;
-       }
-
-       return handled ? IRQ_HANDLED : IRQ_NONE;
-}
-
-int omap_request_dma(int dev_id, const char *dev_name,
-                    void (* callback)(int lch, u16 ch_status, void *data),
-                    void *data, int *dma_ch_out)
-{
-       int ch, free_ch = -1;
-       unsigned long flags;
-       struct omap_dma_lch *chan;
-
-       spin_lock_irqsave(&dma_chan_lock, flags);
-       for (ch = 0; ch < dma_chan_count; ch++) {
-               if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
-                       free_ch = ch;
-                       if (dev_id == 0)
-                               break;
-               }
-       }
-       if (free_ch == -1) {
-               spin_unlock_irqrestore(&dma_chan_lock, flags);
-               return -EBUSY;
-       }
-       chan = dma_chan + free_ch;
-       chan->dev_id = dev_id;
-       clear_lch_regs(free_ch);
-       spin_unlock_irqrestore(&dma_chan_lock, flags);
-
-       chan->dev_id = dev_id;
-       chan->dev_name = dev_name;
-       chan->callback = callback;
-       chan->data = data;
-       chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ | 
OMAP_DMA_BLOCK_IRQ;
-
-       if (cpu_is_omap16xx()) {
-               /* If the sync device is set, configure it dynamically. */
-               if (dev_id != 0) {
-                       set_gdma_dev(free_ch + 1, dev_id);
-                       dev_id = free_ch + 1;
-               }
-               /* Disable the 1510 compatibility mode and set the sync device
-                * id. */
-               omap_writew(dev_id | (1 << 10), OMAP_DMA_CCR(free_ch));
-       } else {
-               omap_writew(dev_id, OMAP_DMA_CCR(free_ch));
-       }
-       *dma_ch_out = free_ch;
-
-       return 0;
-}
-
-void omap_free_dma(int ch)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&dma_chan_lock, flags);
-       if (dma_chan[ch].dev_id == -1) {
-               printk("omap_dma: trying to free nonallocated DMA channel 
%d\n", ch);
-               spin_unlock_irqrestore(&dma_chan_lock, flags);
-               return;
-       }
-       dma_chan[ch].dev_id = -1;
-       spin_unlock_irqrestore(&dma_chan_lock, flags);
-
-       /* Disable all DMA interrupts for the channel. */
-       omap_writew(0, OMAP_DMA_CICR(ch));
-       /* Make sure the DMA transfer is stopped. */
-       omap_writew(0, OMAP_DMA_CCR(ch));
-}
-
-int omap_dma_in_1510_mode(void)
-{
-       return enable_1510_mode;
-}
-
-/*
- * lch_queue DMA will start right after lch_head one is finished.
- * For this DMA link to start, you still need to start (see omap_start_dma)
- * the first one. That will fire up the entire queue.
- */
-void omap_dma_link_lch (int lch_head, int lch_queue)
-{
-       if (omap_dma_in_1510_mode()) {
-               printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
-               BUG();
-               return;
-       }
-
-       if ((dma_chan[lch_head].dev_id == -1) ||
-           (dma_chan[lch_queue].dev_id == -1)) {
-               printk(KERN_ERR "omap_dma: trying to link non requested 
channels\n");
-               dump_stack();
-       }
-
-       dma_chan[lch_head].next_lch = lch_queue;
-}
-
-/*
- * Once the DMA queue is stopped, we can destroy it.
- */
-void omap_dma_unlink_lch (int lch_head, int lch_queue)
-{
-       if (omap_dma_in_1510_mode()) {
-               printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
-               BUG();
-               return;
-       }
-
-       if (dma_chan[lch_head].next_lch != lch_queue ||
-           dma_chan[lch_head].next_lch == -1) {
-               printk(KERN_ERR "omap_dma: trying to unlink non linked 
channels\n");
-               dump_stack();
-       }
-
-
-       if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
-           (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
-               printk(KERN_ERR "omap_dma: You need to stop the DMA channels 
before unlinking\n");
-               dump_stack();
-       }
-
-       dma_chan[lch_head].next_lch = -1;
-}
-
-
-static struct lcd_dma_info {
-       spinlock_t lock;
-       int reserved;
-       void (* callback)(u16 status, void *data);
-       void *cb_data;
-
-       int active;
-       unsigned long addr, size;
-       int rotate, data_type, xres, yres;
-       int vxres;
-       int mirror;
-       int xscale, yscale;
-       int ext_ctrl;
-       int src_port;
-       int single_transfer;
-} lcd_dma;
-
-void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
-                        int data_type)
-{
-       lcd_dma.addr = addr;
-       lcd_dma.data_type = data_type;
-       lcd_dma.xres = fb_xres;
-       lcd_dma.yres = fb_yres;
-}
-
-void omap_set_lcd_dma_src_port(int port)
-{
-       lcd_dma.src_port = port;
-}
-
-void omap_set_lcd_dma_ext_controller(int external)
-{
-       lcd_dma.ext_ctrl = external;
-}
-
-void omap_set_lcd_dma_single_transfer(int single)
-{
-       lcd_dma.single_transfer = single;
-}
-
-
-void omap_set_lcd_dma_b1_rotation(int rotate)
-{
-       if (omap_dma_in_1510_mode()) {
-               printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
-               BUG();
-               return;
-       }
-       lcd_dma.rotate = rotate;
-}
-
-void omap_set_lcd_dma_b1_mirror(int mirror)
-{
-       if (omap_dma_in_1510_mode()) {
-               printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
-               BUG();
-       }
-       lcd_dma.mirror = mirror;
-}
-
-void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
-{
-       if (omap_dma_in_1510_mode()) {
-               printk(KERN_ERR "DMA virtual resulotion is not supported "
-                               "in 1510 mode\n");
-               BUG();
-       }
-       lcd_dma.vxres = vxres;
-}
-
-void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
-{
-       if (omap_dma_in_1510_mode()) {
-               printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
-               BUG();
-       }
-       lcd_dma.xscale = xscale;
-       lcd_dma.yscale = yscale;
-}
-
-static void set_b1_regs(void)
-{
-       unsigned long top, bottom;
-       int es;
-       u16 w;
-       unsigned long en, fn;
-       long ei, fi;
-       unsigned long vxres;
-       unsigned int xscale, yscale;
-
-       switch (lcd_dma.data_type) {
-       case OMAP_DMA_DATA_TYPE_S8:
-               es = 1;
-               break;
-       case OMAP_DMA_DATA_TYPE_S16:
-               es = 2;
-               break;
-       case OMAP_DMA_DATA_TYPE_S32:
-               es = 4;
-               break;
-       default:
-               BUG();
-               return;
-       }
-
-       vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
-       xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
-       yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
-       BUG_ON(vxres < lcd_dma.xres);
-#define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * 
es)
-#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
-       switch (lcd_dma.rotate) {
-       case 0:
-               if (!lcd_dma.mirror) {
-                       top = PIXADDR(0, 0);
-                       bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                       /* 1510 DMA requires the bottom address to be 2 more
-                        * than the actual last memory access location. */
-                       if (omap_dma_in_1510_mode() &&
-                           lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
-                               bottom += 2;
-                       ei = PIXSTEP(0, 0, 1, 0);
-                       fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
-               } else {
-                       top = PIXADDR(lcd_dma.xres - 1, 0);
-                       bottom = PIXADDR(0, lcd_dma.yres - 1);
-                       ei = PIXSTEP(1, 0, 0, 0);
-                       fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
-               }
-               en = lcd_dma.xres;
-               fn = lcd_dma.yres;
-               break;
-       case 90:
-               if (!lcd_dma.mirror) {
-                       top = PIXADDR(0, lcd_dma.yres - 1);
-                       bottom = PIXADDR(lcd_dma.xres - 1, 0);
-                       ei = PIXSTEP(0, 1, 0, 0);
-                       fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
-               } else {
-                       top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                       bottom = PIXADDR(0, 0);
-                       ei = PIXSTEP(0, 1, 0, 0);
-                       fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
-               }
-               en = lcd_dma.yres;
-               fn = lcd_dma.xres;
-               break;
-       case 180:
-               if (!lcd_dma.mirror) {
-                       top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                       bottom = PIXADDR(0, 0);
-                       ei = PIXSTEP(1, 0, 0, 0);
-                       fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
-               } else {
-                       top = PIXADDR(0, lcd_dma.yres - 1);
-                       bottom = PIXADDR(lcd_dma.xres - 1, 0);
-                       ei = PIXSTEP(0, 0, 1, 0);
-                       fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
-               }
-               en = lcd_dma.xres;
-               fn = lcd_dma.yres;
-               break;
-       case 270:
-               if (!lcd_dma.mirror) {
-                       top = PIXADDR(lcd_dma.xres - 1, 0);
-                       bottom = PIXADDR(0, lcd_dma.yres - 1);
-                       ei = PIXSTEP(0, 0, 0, 1);
-                       fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
-               } else {
-                       top = PIXADDR(0, 0);
-                       bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                       ei = PIXSTEP(0, 0, 0, 1);
-                       fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
-               }
-               en = lcd_dma.yres;
-               fn = lcd_dma.xres;
-               break;
-       default:
-               BUG();
-               return; /* Supress warning about uninitialized vars */
-       }
-
-       if (omap_dma_in_1510_mode()) {
-               omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
-               omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
-               omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
-               omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
-
-               return;
-       }
-
-       /* 1610 regs */
-       omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
-       omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
-       omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
-       omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
-
-       omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
-       omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
-
-       w = omap_readw(OMAP1610_DMA_LCD_CSDP);
-       w &= ~0x03;
-       w |= lcd_dma.data_type;
-       omap_writew(w, OMAP1610_DMA_LCD_CSDP);
-
-       w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-       /* Always set the source port as SDRAM for now*/
-       w &= ~(0x03 << 6);
-       if (lcd_dma.ext_ctrl)
-               w |= 1 << 8;
-       else
-               w &= ~(1 << 8);
-       if (lcd_dma.callback != NULL)
-               w |= 1 << 1;            /* Block interrupt enable */
-       else
-               w &= ~(1 << 1);
-       omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-
-       if (!(lcd_dma.rotate || lcd_dma.mirror ||
-             lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
-               return;
-
-       w = omap_readw(OMAP1610_DMA_LCD_CCR);
-       /* Set the double-indexed addressing mode */
-       w |= (0x03 << 12);
-       omap_writew(w, OMAP1610_DMA_LCD_CCR);
-
-       omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
-       omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
-       omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
-}
-
-static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id, struct pt_regs 
*regs)
-{
-       u16 w;
-
-       w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-       if (unlikely(!(w & (1 << 3)))) {
-               printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
-               return IRQ_NONE;
-       }
-       /* Ack the IRQ */
-       w |= (1 << 3);
-       omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-       lcd_dma.active = 0;
-       if (lcd_dma.callback != NULL)
-               lcd_dma.callback(w, lcd_dma.cb_data);
-
-       return IRQ_HANDLED;
-}
-
-int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
-                        void *data)
-{
-       spin_lock_irq(&lcd_dma.lock);
-       if (lcd_dma.reserved) {
-               spin_unlock_irq(&lcd_dma.lock);
-               printk(KERN_ERR "LCD DMA channel already reserved\n");
-               BUG();
-               return -EBUSY;
-       }
-       lcd_dma.reserved = 1;
-       spin_unlock_irq(&lcd_dma.lock);
-       lcd_dma.callback = callback;
-       lcd_dma.cb_data = data;
-       lcd_dma.active = 0;
-       lcd_dma.single_transfer = 0;
-       lcd_dma.rotate = 0;
-       lcd_dma.vxres = 0;
-       lcd_dma.mirror = 0;
-       lcd_dma.xscale = 0;
-       lcd_dma.yscale = 0;
-       lcd_dma.ext_ctrl = 0;
-       lcd_dma.src_port = 0;
-
-       return 0;
-}
-
-void omap_free_lcd_dma(void)
-{
-       spin_lock(&lcd_dma.lock);
-       if (!lcd_dma.reserved) {
-               spin_unlock(&lcd_dma.lock);
-               printk(KERN_ERR "LCD DMA is not reserved\n");
-               BUG();
-               return;
-       }
-       if (!enable_1510_mode)
-               omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, 
OMAP1610_DMA_LCD_CCR);
-       lcd_dma.reserved = 0;
-       spin_unlock(&lcd_dma.lock);
-}
-
-void omap_enable_lcd_dma(void)
-{
-       u16 w;
-
-       /* Set the Enable bit only if an external controller is
-        * connected. Otherwise the OMAP internal controller will
-        * start the transfer when it gets enabled.
-        */
-       if (enable_1510_mode || !lcd_dma.ext_ctrl)
-               return;
-       w = omap_readw(OMAP1610_DMA_LCD_CCR);
-       w |= 1 << 7;
-       omap_writew(w, OMAP1610_DMA_LCD_CCR);
-       lcd_dma.active = 1;
-}
-
-void omap_setup_lcd_dma(void)
-{
-       BUG_ON(lcd_dma.active);
-       if (!enable_1510_mode) {
-               /* Set some reasonable defaults */
-               omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
-               omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
-               omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
-       }
-       set_b1_regs();
-       if (!enable_1510_mode) {
-               u16 w;
-
-               w = omap_readw(OMAP1610_DMA_LCD_CCR);
-               /* If DMA was already active set the end_prog bit to have
-                * the programmed register set loaded into the active
-                * register set.
-                */
-               w |= 1 << 11;           /* End_prog */
-               if (!lcd_dma.single_transfer)
-                       w |= (3 << 8);  /* Auto_init, repeat */
-               omap_writew(w, OMAP1610_DMA_LCD_CCR);
-       }
-}
-
-void omap_stop_lcd_dma(void)
-{
-       lcd_dma.active = 0;
-       if (!enable_1510_mode && lcd_dma.ext_ctrl)
-               omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~(1 << 7),
-                           OMAP1610_DMA_LCD_CCR);
-}
-
-/*
- * Clears any DMA state so the DMA engine is ready to restart with new buffers
- * through omap_start_dma(). Any buffers in flight are discarded.
- */
-void omap_clear_dma(int lch)
-{
-       unsigned long flags;
-       int status;
-
-       local_irq_save(flags);
-       omap_writew(omap_readw(OMAP_DMA_CCR(lch)) & ~OMAP_DMA_CCR_EN,
-                   OMAP_DMA_CCR(lch));
-       status = OMAP_DMA_CSR(lch);     /* clear pending interrupts */
-       local_irq_restore(flags);
-}
-
-/*
- * Returns current physical source address for the given DMA channel.
- * If the channel is running the caller must disable interrupts prior calling
- * this function and process the returned value before re-enabling interrupt to
- * prevent races with the interrupt handler. Note that in continuous mode there
- * is a chance for CSSA_L register overflow inbetween the two reads resulting
- * in incorrect return value.
- */
-dma_addr_t omap_get_dma_src_pos(int lch)
-{
-       return (dma_addr_t) (OMAP_DMA_CSSA_L(lch) |
-                            (OMAP_DMA_CSSA_U(lch) << 16));
-}
-
-/*
- * Returns current physical destination address for the given DMA channel.
- * If the channel is running the caller must disable interrupts prior calling
- * this function and process the returned value before re-enabling interrupt to
- * prevent races with the interrupt handler. Note that in continuous mode there
- * is a chance for CDSA_L register overflow inbetween the two reads resulting
- * in incorrect return value.
- */
-dma_addr_t omap_get_dma_dst_pos(int lch)
-{
-       return (dma_addr_t) (OMAP_DMA_CDSA_L(lch) |
-                            (OMAP_DMA_CDSA_U(lch) << 16));
-}
-
-static int __init omap_init_dma(void)
-{
-       int ch, r;
-
-       if (cpu_is_omap1510()) {
-               printk(KERN_INFO "DMA support for OMAP1510 initialized\n");
-               dma_chan_count = 9;
-               enable_1510_mode = 1;
-       } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
-               printk(KERN_INFO "OMAP DMA hardware version %d\n",
-                      omap_readw(OMAP_DMA_HW_ID));
-               printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
-                      (omap_readw(OMAP_DMA_CAPS_0_U) << 16) | 
omap_readw(OMAP_DMA_CAPS_0_L),
-                      (omap_readw(OMAP_DMA_CAPS_1_U) << 16) | 
omap_readw(OMAP_DMA_CAPS_1_L),
-                      omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
-                      omap_readw(OMAP_DMA_CAPS_4));
-               if (!enable_1510_mode) {
-                       u16 w;
-
-                       /* Disable OMAP 3.0/3.1 compatibility mode. */
-                       w = omap_readw(OMAP_DMA_GSCR);
-                       w |= 1 << 3;
-                       omap_writew(w, OMAP_DMA_GSCR);
-                       dma_chan_count = 16;
-               } else
-                       dma_chan_count = 9;
-       } else {
-               dma_chan_count = 0;
-               return 0;
-       }
-
-       memset(&lcd_dma, 0, sizeof(lcd_dma));
-       spin_lock_init(&lcd_dma.lock);
-       spin_lock_init(&dma_chan_lock);
-       memset(&dma_chan, 0, sizeof(dma_chan));
-
-       for (ch = 0; ch < dma_chan_count; ch++) {
-               dma_chan[ch].dev_id = -1;
-               dma_chan[ch].next_lch = -1;
-
-               if (ch >= 6 && enable_1510_mode)
-                       continue;
-
-               /* request_irq() doesn't like dev_id (ie. ch) being zero,
-                * so we have to kludge around this. */
-               r = request_irq(dma_irq[ch], dma_irq_handler, 0, "DMA",
-                               (void *) (ch + 1));
-               if (r != 0) {
-                       int i;
-
-                       printk(KERN_ERR "unable to request IRQ %d for DMA 
(error %d)\n",
-                              dma_irq[ch], r);
-                       for (i = 0; i < ch; i++)
-                               free_irq(dma_irq[i], (void *) (i + 1));
-                       return r;
-               }
-       }
-       r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, "LCD DMA", NULL);
-       if (r != 0) {
-               int i;
-
-               printk(KERN_ERR "unable to request IRQ for LCD DMA (error 
%d)\n", r);
-               for (i = 0; i < dma_chan_count; i++)
-                       free_irq(dma_irq[i], (void *) (i + 1));
-               return r;
-       }
-       return 0;
-}
-
-arch_initcall(omap_init_dma);
-
-
-EXPORT_SYMBOL(omap_get_dma_src_pos);
-EXPORT_SYMBOL(omap_get_dma_dst_pos);
-EXPORT_SYMBOL(omap_clear_dma);
-EXPORT_SYMBOL(omap_set_dma_priority);
-EXPORT_SYMBOL(omap_request_dma);
-EXPORT_SYMBOL(omap_free_dma);
-EXPORT_SYMBOL(omap_start_dma);
-EXPORT_SYMBOL(omap_stop_dma);
-EXPORT_SYMBOL(omap_enable_dma_irq);
-EXPORT_SYMBOL(omap_disable_dma_irq);
-
-EXPORT_SYMBOL(omap_set_dma_transfer_params);
-EXPORT_SYMBOL(omap_set_dma_color_mode);
-
-EXPORT_SYMBOL(omap_set_dma_src_params);
-EXPORT_SYMBOL(omap_set_dma_src_index);
-EXPORT_SYMBOL(omap_set_dma_src_data_pack);
-EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
-
-EXPORT_SYMBOL(omap_set_dma_dest_params);
-EXPORT_SYMBOL(omap_set_dma_dest_index);
-EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
-EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
-
-EXPORT_SYMBOL(omap_dma_link_lch);
-EXPORT_SYMBOL(omap_dma_unlink_lch);
-
-EXPORT_SYMBOL(omap_request_lcd_dma);
-EXPORT_SYMBOL(omap_free_lcd_dma);
-EXPORT_SYMBOL(omap_enable_lcd_dma);
-EXPORT_SYMBOL(omap_setup_lcd_dma);
-EXPORT_SYMBOL(omap_stop_lcd_dma);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1);
-EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
-EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
-
diff -urN linux/arch/arm/mach-omap/fpga.c linux/arch/arm/mach-omap/fpga.c
--- linux/arch/arm/mach-omap/Attic/fpga.c       2005-07-13 12:48:52.025750000 
+0100     1.5
+++ linux/arch/arm/mach-omap/Attic/fpga.c       1970/01/01 00:00:00+0100
@@ -1,188 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/fpga.c
- *
- * Interrupt handler for OMAP-1510 Innovator FPGA
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Copyright (C) 2002 MontaVista Software, Inc.
- *
- * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
- * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/config.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-
-#include <asm/arch/fpga.h>
-#include <asm/arch/gpio.h>
-
-static void fpga_mask_irq(unsigned int irq)
-{
-       irq -= OMAP1510_IH_FPGA_BASE;
-
-       if (irq < 8)
-               __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
-                             & ~(1 << irq)), OMAP1510_FPGA_IMR_LO);
-       else if (irq < 16)
-               __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
-                             & ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
-       else
-               __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
-                             & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
-}
-
-
-static inline u32 get_fpga_unmasked_irqs(void)
-{
-       return
-               ((__raw_readb(OMAP1510_FPGA_ISR_LO) &
-                 __raw_readb(OMAP1510_FPGA_IMR_LO))) |
-               ((__raw_readb(OMAP1510_FPGA_ISR_HI) &
-                 __raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) |
-               ((__raw_readb(INNOVATOR_FPGA_ISR2) &
-                 __raw_readb(INNOVATOR_FPGA_IMR2)) << 16);
-}
-
-
-static void fpga_ack_irq(unsigned int irq)
-{
-       /* Don't need to explicitly ACK FPGA interrupts */
-}
-
-static void fpga_unmask_irq(unsigned int irq)
-{
-       irq -= OMAP1510_IH_FPGA_BASE;
-
-       if (irq < 8)
-               __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
-                    OMAP1510_FPGA_IMR_LO);
-       else if (irq < 16)
-               __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
-                             | (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
-       else
-               __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
-                             | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
-}
-
-static void fpga_mask_ack_irq(unsigned int irq)
-{
-       fpga_mask_irq(irq);
-       fpga_ack_irq(irq);
-}
-
-void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc,
-                             struct pt_regs *regs)
-{
-       struct irqdesc *d;
-       u32 stat;
-       int fpga_irq;
-
-       stat = get_fpga_unmasked_irqs();
-
-       if (!stat)
-               return;
-
-       for (fpga_irq = OMAP1510_IH_FPGA_BASE;
-            (fpga_irq < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS)) && stat;
-            fpga_irq++, stat >>= 1) {
-               if (stat & 1) {
-                       d = irq_desc + fpga_irq;
-                       d->handle(fpga_irq, d, regs);
-               }
-       }
-}
-
-static struct irqchip omap_fpga_irq_ack = {
-       .ack            = fpga_mask_ack_irq,
-       .mask           = fpga_mask_irq,
-       .unmask         = fpga_unmask_irq,
-};
-
-
-static struct irqchip omap_fpga_irq = {
-       .ack            = fpga_ack_irq,
-       .mask           = fpga_mask_irq,
-       .unmask         = fpga_unmask_irq,
-};
-
-/*
- * All of the FPGA interrupt request inputs except for the touchscreen are
- * edge-sensitive; the touchscreen is level-sensitive.  The edge-sensitive
- * interrupts are acknowledged as a side-effect of reading the interrupt
- * status register from the FPGA.  The edge-sensitive interrupt inputs
- * cause a problem with level interrupt requests, such as Ethernet.  The
- * problem occurs when a level interrupt request is asserted while its
- * interrupt input is masked in the FPGA, which results in a missed
- * interrupt.
- *
- * In an attempt to workaround the problem with missed interrupts, the
- * mask_ack routine for all of the FPGA interrupts has been changed from
- * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
- * being serviced is left unmasked.  We can do this because the FPGA cascade
- * interrupt is installed with the SA_INTERRUPT flag, which leaves all
- * interrupts masked at the CPU while an FPGA interrupt handler executes.
- *
- * Limited testing indicates that this workaround appears to be effective
- * for the smc9194 Ethernet driver used on the Innovator.  It should work
- * on other FPGA interrupts as well, but any drivers that explicitly mask
- * interrupts at the interrupt controller via disable_irq/enable_irq
- * could pose a problem.
- */
-void omap1510_fpga_init_irq(void)
-{
-       int i;
-
-       __raw_writeb(0, OMAP1510_FPGA_IMR_LO);
-       __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
-       __raw_writeb(0, INNOVATOR_FPGA_IMR2);
-
-       for (i = OMAP1510_IH_FPGA_BASE; i < (OMAP1510_IH_FPGA_BASE + 
NR_FPGA_IRQS); i++) {
-
-               if (i == OMAP1510_INT_FPGA_TS) {
-                       /*
-                        * The touchscreen interrupt is level-sensitive, so
-                        * we'll use the regular mask_ack routine for it.
-                        */
-                       set_irq_chip(i, &omap_fpga_irq_ack);
-               }
-               else {
-                       /*
-                        * All FPGA interrupts except the touchscreen are
-                        * edge-sensitive, so we won't mask them.
-                        */
-                       set_irq_chip(i, &omap_fpga_irq);
-               }
-
-               set_irq_handler(i, do_edge_IRQ);
-               set_irq_flags(i, IRQF_VALID);
-       }
-
-       /*
-        * The FPGA interrupt line is connected to GPIO13. Claim this pin for
-        * the ARM.
-        *
-        * NOTE: For general GPIO/MPUIO access and interrupts, please see
-        * gpio.[ch]
-        */
-       omap_request_gpio(13);
-       omap_set_gpio_direction(13, 1);
-       omap_set_gpio_edge_ctrl(13, OMAP_GPIO_RISING_EDGE);
-       set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
-}
-
-EXPORT_SYMBOL(omap1510_fpga_init_irq);
diff -urN linux/arch/arm/mach-omap/gpio.c linux/arch/arm/mach-omap/gpio.c
--- linux/arch/arm/mach-omap/Attic/gpio.c       2005-07-13 12:48:52.048322000 
+0100     1.7
+++ linux/arch/arm/mach-omap/Attic/gpio.c       1970/01/01 00:00:00+0100
@@ -1,762 +0,0 @@
-/*
- *  linux/arch/arm/mach-omap/gpio.c
- *
- * Support functions for OMAP GPIO
- *
- * Copyright (C) 2003 Nokia Corporation
- * Written by Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ptrace.h>
-
-#include <asm/hardware.h>
-#include <asm/irq.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/gpio.h>
-#include <asm/mach/irq.h>
-
-#include <asm/io.h>
-
-/*
- * OMAP1510 GPIO registers
- */
-#define OMAP1510_GPIO_BASE             0xfffce000
-#define OMAP1510_GPIO_DATA_INPUT       0x00
-#define OMAP1510_GPIO_DATA_OUTPUT      0x04
-#define OMAP1510_GPIO_DIR_CONTROL      0x08
-#define OMAP1510_GPIO_INT_CONTROL      0x0c
-#define OMAP1510_GPIO_INT_MASK         0x10
-#define OMAP1510_GPIO_INT_STATUS       0x14
-#define OMAP1510_GPIO_PIN_CONTROL      0x18
-
-#define OMAP1510_IH_GPIO_BASE          64
-
-/*
- * OMAP1610 specific GPIO registers
- */
-#define OMAP1610_GPIO1_BASE            0xfffbe400
-#define OMAP1610_GPIO2_BASE            0xfffbec00
-#define OMAP1610_GPIO3_BASE            0xfffbb400
-#define OMAP1610_GPIO4_BASE            0xfffbbc00
-#define OMAP1610_GPIO_REVISION         0x0000
-#define OMAP1610_GPIO_SYSCONFIG                0x0010
-#define OMAP1610_GPIO_SYSSTATUS                0x0014
-#define OMAP1610_GPIO_IRQSTATUS1       0x0018
-#define OMAP1610_GPIO_IRQENABLE1       0x001c
-#define OMAP1610_GPIO_DATAIN           0x002c
-#define OMAP1610_GPIO_DATAOUT          0x0030
-#define OMAP1610_GPIO_DIRECTION                0x0034
-#define OMAP1610_GPIO_EDGE_CTRL1       0x0038
-#define OMAP1610_GPIO_EDGE_CTRL2       0x003c
-#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
-#define OMAP1610_GPIO_CLEAR_DATAOUT    0x00b0
-#define OMAP1610_GPIO_SET_IRQENABLE1   0x00dc
-#define OMAP1610_GPIO_SET_DATAOUT      0x00f0
-
-/*
- * OMAP730 specific GPIO registers
- */
-#define OMAP730_GPIO1_BASE             0xfffbc000
-#define OMAP730_GPIO2_BASE             0xfffbc800
-#define OMAP730_GPIO3_BASE             0xfffbd000
-#define OMAP730_GPIO4_BASE             0xfffbd800
-#define OMAP730_GPIO5_BASE             0xfffbe000
-#define OMAP730_GPIO6_BASE             0xfffbe800
-#define OMAP730_GPIO_DATA_INPUT                0x00
-#define OMAP730_GPIO_DATA_OUTPUT       0x04
-#define OMAP730_GPIO_DIR_CONTROL       0x08
-#define OMAP730_GPIO_INT_CONTROL       0x0c
-#define OMAP730_GPIO_INT_MASK          0x10
-#define OMAP730_GPIO_INT_STATUS                0x14
-
-#define OMAP_MPUIO_MASK                (~OMAP_MAX_GPIO_LINES & 0xff)
-
-struct gpio_bank {
-       u32 base;
-       u16 irq;
-       u16 virtual_irq_start;
-       u8 method;
-       u32 reserved_map;
-       spinlock_t lock;
-};
-
-#define METHOD_MPUIO           0
-#define METHOD_GPIO_1510       1
-#define METHOD_GPIO_1610       2
-#define METHOD_GPIO_730                3
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-static struct gpio_bank gpio_bank_1610[5] = {
-       { OMAP_MPUIO_BASE,     INT_MPUIO,           IH_MPUIO_BASE,     
METHOD_MPUIO},
-       { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,      IH_GPIO_BASE,      
METHOD_GPIO_1610 },
-       { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, 
METHOD_GPIO_1610 },
-       { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, 
METHOD_GPIO_1610 },
-       { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, 
METHOD_GPIO_1610 },
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP1510
-static struct gpio_bank gpio_bank_1510[2] = {
-       { OMAP_MPUIO_BASE,    INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
-       { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP730
-static struct gpio_bank gpio_bank_730[7] = {
-       { OMAP_MPUIO_BASE,     INT_730_MPUIO,       IH_MPUIO_BASE,      
METHOD_MPUIO },
-       { OMAP730_GPIO1_BASE,  INT_730_GPIO_BANK1,  IH_GPIO_BASE,       
METHOD_GPIO_730 },
-       { OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,  
METHOD_GPIO_730 },
-       { OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,  
METHOD_GPIO_730 },
-       { OMAP730_GPIO4_BASE,  INT_730_GPIO_BANK4,  IH_GPIO_BASE + 96,  
METHOD_GPIO_730 },
-       { OMAP730_GPIO5_BASE,  INT_730_GPIO_BANK5,  IH_GPIO_BASE + 128, 
METHOD_GPIO_730 },
-       { OMAP730_GPIO6_BASE,  INT_730_GPIO_BANK6,  IH_GPIO_BASE + 160, 
METHOD_GPIO_730 },
-};
-#endif
-
-static struct gpio_bank *gpio_bank;
-static int gpio_bank_count;
-
-static inline struct gpio_bank *get_gpio_bank(int gpio)
-{
-#ifdef CONFIG_ARCH_OMAP1510
-       if (cpu_is_omap1510()) {
-               if (OMAP_GPIO_IS_MPUIO(gpio))
-                       return &gpio_bank[0];
-               return &gpio_bank[1];
-       }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-       if (cpu_is_omap16xx()) {
-               if (OMAP_GPIO_IS_MPUIO(gpio))
-                       return &gpio_bank[0];
-               return &gpio_bank[1 + (gpio >> 4)];
-       }
-#endif
-#ifdef CONFIG_ARCH_OMAP730
-       if (cpu_is_omap730()) {
-               if (OMAP_GPIO_IS_MPUIO(gpio))
-                       return &gpio_bank[0];
-               return &gpio_bank[1 + (gpio >> 5)];
-       }
-#endif
-}
-
-static inline int get_gpio_index(int gpio)
-{
-       if (cpu_is_omap730())
-               return gpio & 0x1f;
-       else
-               return gpio & 0x0f;
-}
-
-static inline int gpio_valid(int gpio)
-{
-       if (gpio < 0)
-               return -1;
-       if (OMAP_GPIO_IS_MPUIO(gpio)) {
-               if ((gpio & OMAP_MPUIO_MASK) > 16)
-                       return -1;
-               return 0;
-       }
-#ifdef CONFIG_ARCH_OMAP1510
-       if (cpu_is_omap1510() && gpio < 16)
-               return 0;
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-       if ((cpu_is_omap16xx()) && gpio < 64)
-               return 0;
-#endif
-#ifdef CONFIG_ARCH_OMAP730
-       if (cpu_is_omap730() && gpio < 192)
-               return 0;
-#endif
-       return -1;
-}
-
-static int check_gpio(int gpio)
-{
-       if (unlikely(gpio_valid(gpio)) < 0) {
-               printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
-               dump_stack();
-               return -1;
-       }
-       return 0;
-}
-
-static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
-{
-       u32 reg = bank->base;
-       u32 l;
-
-       switch (bank->method) {
-       case METHOD_MPUIO:
-               reg += OMAP_MPUIO_IO_CNTL;
-               break;
-       case METHOD_GPIO_1510:
-               reg += OMAP1510_GPIO_DIR_CONTROL;
-               break;
-       case METHOD_GPIO_1610:
-               reg += OMAP1610_GPIO_DIRECTION;
-               break;
-       case METHOD_GPIO_730:
-               reg += OMAP730_GPIO_DIR_CONTROL;
-               break;
-       }
-       l = __raw_readl(reg);
-       if (is_input)
-               l |= 1 << gpio;
-       else
-               l &= ~(1 << gpio);
-       __raw_writel(l, reg);
-}
-
-void omap_set_gpio_direction(int gpio, int is_input)
-{
-       struct gpio_bank *bank;
-
-       if (check_gpio(gpio) < 0)
-               return;
-       bank = get_gpio_bank(gpio);
-       spin_lock(&bank->lock);
-       _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
-       spin_unlock(&bank->lock);
-}
-
-static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
-{
-       u32 reg = bank->base;
-       u32 l = 0;
-
-       switch (bank->method) {
-       case METHOD_MPUIO:
-               reg += OMAP_MPUIO_OUTPUT;
-               l = __raw_readl(reg);
-               if (enable)
-                       l |= 1 << gpio;
-               else
-                       l &= ~(1 << gpio);
-               break;
-       case METHOD_GPIO_1510:
-               reg += OMAP1510_GPIO_DATA_OUTPUT;
-               l = __raw_readl(reg);
-               if (enable)
-                       l |= 1 << gpio;
-               else
-                       l &= ~(1 << gpio);
-               break;
-       case METHOD_GPIO_1610:
-               if (enable)
-                       reg += OMAP1610_GPIO_SET_DATAOUT;
-               else
-                       reg += OMAP1610_GPIO_CLEAR_DATAOUT;
-               l = 1 << gpio;
-               break;
-       case METHOD_GPIO_730:
-               reg += OMAP730_GPIO_DATA_OUTPUT;
-               l = __raw_readl(reg);
-               if (enable)
-                       l |= 1 << gpio;
-               else
-                       l &= ~(1 << gpio);
-               break;
-       default:
-               BUG();
-               return;
-       }
-       __raw_writel(l, reg);
-}
-
-void omap_set_gpio_dataout(int gpio, int enable)
-{
-       struct gpio_bank *bank;
-
-       if (check_gpio(gpio) < 0)
-               return;
-       bank = get_gpio_bank(gpio);
-       spin_lock(&bank->lock);
-       _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
-       spin_unlock(&bank->lock);
-}
-
-int omap_get_gpio_datain(int gpio)
-{
-       struct gpio_bank *bank;
-       u32 reg;
-
-       if (check_gpio(gpio) < 0)
-               return -1;
-       bank = get_gpio_bank(gpio);
-       reg = bank->base;
-       switch (bank->method) {
-       case METHOD_MPUIO:
-               reg += OMAP_MPUIO_INPUT_LATCH;
-               break;
-       case METHOD_GPIO_1510:
-               reg += OMAP1510_GPIO_DATA_INPUT;
-               break;
-       case METHOD_GPIO_1610:
-               reg += OMAP1610_GPIO_DATAIN;
-               break;
-       case METHOD_GPIO_730:
-               reg += OMAP730_GPIO_DATA_INPUT;
-               break;
-       default:
-               BUG();
-               return -1;
-       }
-       return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
-}
-
-static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge)
-{
-       u32 reg = bank->base;
-       u32 l;
-
-       switch (bank->method) {
-       case METHOD_MPUIO:
-               reg += OMAP_MPUIO_GPIO_INT_EDGE;
-               l = __raw_readl(reg);
-               if (edge == OMAP_GPIO_RISING_EDGE)
-                       l |= 1 << gpio;
-               else
-                       l &= ~(1 << gpio);
-               __raw_writel(l, reg);
-               break;
-       case METHOD_GPIO_1510:
-               reg += OMAP1510_GPIO_INT_CONTROL;
-               l = __raw_readl(reg);
-               if (edge == OMAP_GPIO_RISING_EDGE)
-                       l |= 1 << gpio;
-               else
-                       l &= ~(1 << gpio);
-               __raw_writel(l, reg);
-               break;
-       case METHOD_GPIO_1610:
-               edge &= 0x03;
-               if (gpio & 0x08)
-                       reg += OMAP1610_GPIO_EDGE_CTRL2;
-               else
-                       reg += OMAP1610_GPIO_EDGE_CTRL1;
-               gpio &= 0x07;
-               l = __raw_readl(reg);
-               l &= ~(3 << (gpio << 1));
-               l |= edge << (gpio << 1);
-               __raw_writel(l, reg);
-               break;
-       case METHOD_GPIO_730:
-               reg += OMAP730_GPIO_INT_CONTROL;
-               l = __raw_readl(reg);
-               if (edge == OMAP_GPIO_RISING_EDGE)
-                       l |= 1 << gpio;
-               else
-                       l &= ~(1 << gpio);
-               __raw_writel(l, reg);
-               break;
-       default:
-               BUG();
-               return;
-       }
-}
-
-void omap_set_gpio_edge_ctrl(int gpio, int edge)
-{
-       struct gpio_bank *bank;
-
-       if (check_gpio(gpio) < 0)
-               return;
-       bank = get_gpio_bank(gpio);
-       spin_lock(&bank->lock);
-       _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), edge);
-       spin_unlock(&bank->lock);
-}
-
-
-static int _get_gpio_edge_ctrl(struct gpio_bank *bank, int gpio)
-{
-       u32 reg = bank->base, l;
-
-       switch (bank->method) {
-       case METHOD_MPUIO:
-               l = __raw_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE);
-               return (l & (1 << gpio)) ?
-                       OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
-       case METHOD_GPIO_1510:
-               l = __raw_readl(reg + OMAP1510_GPIO_INT_CONTROL);
-               return (l & (1 << gpio)) ?
-                       OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
-       case METHOD_GPIO_1610:
-               if (gpio & 0x08)
-                       reg += OMAP1610_GPIO_EDGE_CTRL2;
-               else
-                       reg += OMAP1610_GPIO_EDGE_CTRL1;
-               return (__raw_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03;
-       case METHOD_GPIO_730:
-               l = __raw_readl(reg + OMAP730_GPIO_INT_CONTROL);
-               return (l & (1 << gpio)) ?
-                       OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
-       default:
-               BUG();
-               return -1;
-       }
-}
-
-static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
-{
-       u32 reg = bank->base;
-
-       switch (bank->method) {
-       case METHOD_MPUIO:
-               /* MPUIO irqstatus is reset by reading the status register,
-                * so do nothing here */
-               return;
-       case METHOD_GPIO_1510:
-               reg += OMAP1510_GPIO_INT_STATUS;
-               break;
-       case METHOD_GPIO_1610:
-               reg += OMAP1610_GPIO_IRQSTATUS1;
-               break;
-       case METHOD_GPIO_730:
-               reg += OMAP730_GPIO_INT_STATUS;
-               break;
-       default:
-               BUG();
-               return;
-       }
-       __raw_writel(gpio_mask, reg);
-}
-
-static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
-{
-       _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
-}
-
-static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int 
enable)
-{
-       u32 reg = bank->base;
-       u32 l;
-
-       switch (bank->method) {
-       case METHOD_MPUIO:
-               reg += OMAP_MPUIO_GPIO_MASKIT;
-               l = __raw_readl(reg);
-               if (enable)
-                       l &= ~(gpio_mask);
-               else
-                       l |= gpio_mask;
-               break;
-       case METHOD_GPIO_1510:
-               reg += OMAP1510_GPIO_INT_MASK;
-               l = __raw_readl(reg);
-               if (enable)
-                       l &= ~(gpio_mask);
-               else
-                       l |= gpio_mask;
-               break;
-       case METHOD_GPIO_1610:
-               if (enable)
-                       reg += OMAP1610_GPIO_SET_IRQENABLE1;
-               else
-                       reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
-               l = gpio_mask;
-               break;
-       case METHOD_GPIO_730:
-               reg += OMAP730_GPIO_INT_MASK;
-               l = __raw_readl(reg);
-               if (enable)
-                       l &= ~(gpio_mask);
-               else
-                       l |= gpio_mask;
-               break;
-       default:
-               BUG();
-               return;
-       }
-       __raw_writel(l, reg);
-}
-
-static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int 
enable)
-{
-       _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
-}
-
-int omap_request_gpio(int gpio)
-{
-       struct gpio_bank *bank;
-
-       if (check_gpio(gpio) < 0)
-               return -EINVAL;
-
-       bank = get_gpio_bank(gpio);
-       spin_lock(&bank->lock);
-       if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
-               printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", 
gpio);
-               dump_stack();
-               spin_unlock(&bank->lock);
-               return -1;
-       }
-       bank->reserved_map |= (1 << get_gpio_index(gpio));
-#ifdef CONFIG_ARCH_OMAP1510
-       if (bank->method == METHOD_GPIO_1510) {
-               u32 reg;
-
-               /* Claim the pin for the ARM */
-               reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
-               __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), 
reg);
-       }
-#endif
-       spin_unlock(&bank->lock);
-
-       return 0;
-}
-
-void omap_free_gpio(int gpio)
-{
-       struct gpio_bank *bank;
-
-       if (check_gpio(gpio) < 0)
-               return;
-       bank = get_gpio_bank(gpio);
-       spin_lock(&bank->lock);
-       if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
-               printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
-               dump_stack();
-               spin_unlock(&bank->lock);
-               return;
-       }
-       bank->reserved_map &= ~(1 << get_gpio_index(gpio));
-       _set_gpio_direction(bank, get_gpio_index(gpio), 1);
-       _set_gpio_irqenable(bank, gpio, 0);
-       _clear_gpio_irqstatus(bank, gpio);
-       spin_unlock(&bank->lock);
-}
-
-/*
- * We need to unmask the GPIO bank interrupt as soon as possible to
- * avoid missing GPIO interrupts for other lines in the bank.
- * Then we need to mask-read-clear-unmask the triggered GPIO lines
- * in the bank to avoid missing nested interrupts for a GPIO line.
- * If we wait to unmask individual GPIO lines in the bank after the
- * line's interrupt handler has been run, we may miss some nested
- * interrupts.
- */
-static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
-                            struct pt_regs *regs)
-{
-       u32 isr_reg = 0;
-       u32 isr;
-       unsigned int gpio_irq;
-       struct gpio_bank *bank;
-
-       desc->chip->ack(irq);
-
-       bank = (struct gpio_bank *) desc->data;
-       if (bank->method == METHOD_MPUIO)
-               isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
-#ifdef CONFIG_ARCH_OMAP1510
-       if (bank->method == METHOD_GPIO_1510)
-               isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-       if (bank->method == METHOD_GPIO_1610)
-               isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
-#endif
-#ifdef CONFIG_ARCH_OMAP730
-       if (bank->method == METHOD_GPIO_730)
-               isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
-#endif
-
-       isr = __raw_readl(isr_reg);
-       _enable_gpio_irqbank(bank, isr, 0);
-       _clear_gpio_irqbank(bank, isr);
-       _enable_gpio_irqbank(bank, isr, 1);
-       desc->chip->unmask(irq);
-
-       if (unlikely(!isr))
-               return;
-
-       gpio_irq = bank->virtual_irq_start;
-       for (; isr != 0; isr >>= 1, gpio_irq++) {
-               struct irqdesc *d;
-               if (!(isr & 1))
-                       continue;
-               d = irq_desc + gpio_irq;
-               d->handle(gpio_irq, d, regs);
-       }
-}
-
-static void gpio_ack_irq(unsigned int irq)
-{
-       unsigned int gpio = irq - IH_GPIO_BASE;
-       struct gpio_bank *bank = get_gpio_bank(gpio);
-
-       _clear_gpio_irqstatus(bank, gpio);
-}
-
-static void gpio_mask_irq(unsigned int irq)
-{
-       unsigned int gpio = irq - IH_GPIO_BASE;
-       struct gpio_bank *bank = get_gpio_bank(gpio);
-
-       _set_gpio_irqenable(bank, gpio, 0);
-}
-
-static void gpio_unmask_irq(unsigned int irq)
-{
-       unsigned int gpio = irq - IH_GPIO_BASE;
-       struct gpio_bank *bank = get_gpio_bank(gpio);
-
-       if (_get_gpio_edge_ctrl(bank, get_gpio_index(gpio)) == 
OMAP_GPIO_NO_EDGE) {
-               printk(KERN_ERR "OMAP GPIO %d: trying to enable GPIO IRQ while 
no edge is set\n",
-                      gpio);
-               _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), 
OMAP_GPIO_RISING_EDGE);
-       }
-       _set_gpio_irqenable(bank, gpio, 1);
-}
-
-static void mpuio_ack_irq(unsigned int irq)
-{
-       /* The ISR is reset automatically, so do nothing here. */
-}
-
-static void mpuio_mask_irq(unsigned int irq)
-{
-       unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
-       struct gpio_bank *bank = get_gpio_bank(gpio);
-
-       _set_gpio_irqenable(bank, gpio, 0);
-}
-
-static void mpuio_unmask_irq(unsigned int irq)
-{
-       unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
-       struct gpio_bank *bank = get_gpio_bank(gpio);
-
-       _set_gpio_irqenable(bank, gpio, 1);
-}
-
-static struct irqchip gpio_irq_chip = {
-       .ack    = gpio_ack_irq,
-       .mask   = gpio_mask_irq,
-       .unmask = gpio_unmask_irq,
-};
-
-static struct irqchip mpuio_irq_chip = {
-       .ack    = mpuio_ack_irq,
-       .mask   = mpuio_mask_irq,
-       .unmask = mpuio_unmask_irq
-};
-
-static int initialized = 0;
-
-static int __init _omap_gpio_init(void)
-{
-       int i;
-       struct gpio_bank *bank;
-
-       initialized = 1;
-
-#ifdef CONFIG_ARCH_OMAP1510
-       if (cpu_is_omap1510()) {
-               printk(KERN_INFO "OMAP1510 GPIO hardware\n");
-               gpio_bank_count = 2;
-               gpio_bank = gpio_bank_1510;
-       }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-       if (cpu_is_omap16xx()) {
-               int rev;
-
-               gpio_bank_count = 5;
-               gpio_bank = gpio_bank_1610;
-               rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
-               printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
-                      (rev >> 4) & 0x0f, rev & 0x0f);
-       }
-#endif
-#ifdef CONFIG_ARCH_OMAP730
-       if (cpu_is_omap730()) {
-               printk(KERN_INFO "OMAP730 GPIO hardware\n");
-               gpio_bank_count = 7;
-               gpio_bank = gpio_bank_730;
-       }
-#endif
-       for (i = 0; i < gpio_bank_count; i++) {
-               int j, gpio_count = 16;
-
-               bank = &gpio_bank[i];
-               bank->reserved_map = 0;
-               bank->base = IO_ADDRESS(bank->base);
-               spin_lock_init(&bank->lock);
-               if (bank->method == METHOD_MPUIO) {
-                       omap_writew(0xFFFF, OMAP_MPUIO_BASE + 
OMAP_MPUIO_GPIO_MASKIT);
-               }
-#ifdef CONFIG_ARCH_OMAP1510
-               if (bank->method == METHOD_GPIO_1510) {
-                       __raw_writew(0xffff, bank->base + 
OMAP1510_GPIO_INT_MASK);
-                       __raw_writew(0x0000, bank->base + 
OMAP1510_GPIO_INT_STATUS);
-               }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-               if (bank->method == METHOD_GPIO_1610) {
-                       __raw_writew(0x0000, bank->base + 
OMAP1610_GPIO_IRQENABLE1);
-                       __raw_writew(0xffff, bank->base + 
OMAP1610_GPIO_IRQSTATUS1);
-               }
-#endif
-#ifdef CONFIG_ARCH_OMAP730
-               if (bank->method == METHOD_GPIO_730) {
-                       __raw_writel(0xffffffff, bank->base + 
OMAP730_GPIO_INT_MASK);
-                       __raw_writel(0x00000000, bank->base + 
OMAP730_GPIO_INT_STATUS);
-
-                       gpio_count = 32; /* 730 has 32-bit GPIOs */
-               }
-#endif
-               for (j = bank->virtual_irq_start;
-                    j < bank->virtual_irq_start + gpio_count; j++) {
-                       if (bank->method == METHOD_MPUIO)
-                               set_irq_chip(j, &mpuio_irq_chip);
-                       else
-                               set_irq_chip(j, &gpio_irq_chip);
-                       set_irq_handler(j, do_simple_IRQ);
-                       set_irq_flags(j, IRQF_VALID);
-               }
-               set_irq_chained_handler(bank->irq, gpio_irq_handler);
-               set_irq_data(bank->irq, bank);
-       }
-
-       /* Enable system clock for GPIO module.
-        * The CAM_CLK_CTRL *is* really the right place. */
-       if (cpu_is_omap1610() || cpu_is_omap1710())
-               omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, 
ULPD_CAM_CLK_CTRL);
-
-       return 0;
-}
-
-/*
- * This may get called early from board specific init
- */
-int omap_gpio_init(void)
-{
-       if (!initialized)
-               return _omap_gpio_init();
-       else
-               return 0;
-}
-
-EXPORT_SYMBOL(omap_request_gpio);
-EXPORT_SYMBOL(omap_free_gpio);
-EXPORT_SYMBOL(omap_set_gpio_direction);
-EXPORT_SYMBOL(omap_set_gpio_dataout);
-EXPORT_SYMBOL(omap_get_gpio_datain);
-EXPORT_SYMBOL(omap_set_gpio_edge_ctrl);
-
-arch_initcall(omap_gpio_init);
diff -urN linux/arch/arm/mach-omap/irq.c linux/arch/arm/mach-omap/irq.c
--- linux/arch/arm/mach-omap/Attic/irq.c        2005-07-13 12:48:52.079519000 
+0100     1.6
+++ linux/arch/arm/mach-omap/Attic/irq.c        1970/01/01 00:00:00+0100
@@ -1,219 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/irq.c
- *
- * Interrupt handler for all OMAP boards
- *
- * Copyright (C) 2004 Nokia Corporation
- * Written by Tony Lindgren <tony@atomide.com>
- * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * Completely re-written to support various OMAP chips with bank specific
- * interrupt handlers.
- *
- * Some snippets of the code taken from the older OMAP interrupt handler
- * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
- *
- * GPIO interrupt handler moved to gpio.c by Juha Yrjola
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ptrace.h>
-
-#include <asm/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <asm/arch/gpio.h>
-
-#include <asm/io.h>
-
-#define IRQ_BANK(irq) ((irq) >> 5)
-#define IRQ_BIT(irq)  ((irq) & 0x1f)
-
-struct omap_irq_bank {
-       unsigned long base_reg;
-       unsigned long trigger_map;
-};
-
-static unsigned int irq_bank_count = 0;
-static struct omap_irq_bank *irq_banks;
-
-static inline unsigned int irq_bank_readl(int bank, int offset)
-{
-       return omap_readl(irq_banks[bank].base_reg + offset);
-}
-
-static inline void irq_bank_writel(unsigned long value, int bank, int offset)
-{
-       omap_writel(value, irq_banks[bank].base_reg + offset);
-}
-
-static void omap_ack_irq(unsigned int irq)
-{
-       if (irq > 31)
-               omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
-
-       omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
-}
-
-static void omap_mask_irq(unsigned int irq)
-{
-       int bank = IRQ_BANK(irq);
-       u32 l;
-
-       l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
-       l |= 1 << IRQ_BIT(irq);
-       omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
-}
-
-static void omap_unmask_irq(unsigned int irq)
-{
-       int bank = IRQ_BANK(irq);
-       u32 l;
-
-       l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
-       l &= ~(1 << IRQ_BIT(irq));
-       omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
-}
-
-static void omap_mask_ack_irq(unsigned int irq)
-{
-       omap_mask_irq(irq);
-       omap_ack_irq(irq);
-}
-
-/*
- * Allows tuning the IRQ type and priority
- *
- * NOTE: There is currently no OMAP fiq handler for Linux. Read the
- *      mailing list threads on FIQ handlers if you are planning to
- *      add a FIQ handler for OMAP.
- */
-static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
-{
-       signed int bank;
-       unsigned long val, offset;
-
-       bank = IRQ_BANK(irq);
-       /* FIQ is only available on bank 0 interrupts */
-       fiq = bank ? 0 : (fiq & 0x1);
-       val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
-       offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
-       irq_bank_writel(val, bank, offset);
-}
-
-#ifdef CONFIG_ARCH_OMAP730
-static struct omap_irq_bank omap730_irq_banks[] = {
-       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3f8e22f },
-       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb9c1f2 },
-       { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0x800040f3 },
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP1510
-static struct omap_irq_bank omap1510_irq_banks[] = {
-       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3febfff },
-       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xffbfffed },
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-
-static struct omap_irq_bank omap1610_irq_banks[] = {
-       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3fefe8f },
-       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb7c1fd },
-       { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0xfffff7ff },
-       { .base_reg = OMAP_IH2_BASE + 0x200,    .trigger_map = 0xffffffff },
-};
-#endif
-
-static struct irqchip omap_irq_chip = {
-       .ack    = omap_mask_ack_irq,
-       .mask   = omap_mask_irq,
-       .unmask = omap_unmask_irq,
-};
-
-void __init omap_init_irq(void)
-{
-       int i, j;
-
-#ifdef CONFIG_ARCH_OMAP730
-       if (cpu_is_omap730()) {
-               irq_banks = omap730_irq_banks;
-               irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
-       }
-#endif
-#ifdef CONFIG_ARCH_OMAP1510
-       if (cpu_is_omap1510()) {
-               irq_banks = omap1510_irq_banks;
-               irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
-       }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-       if (cpu_is_omap16xx()) {
-               irq_banks = omap1610_irq_banks;
-               irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
-       }
-#endif
-       printk("Total of %i interrupts in %i interrupt banks\n",
-              irq_bank_count * 32, irq_bank_count);
-
-       /* Mask and clear all interrupts */
-       for (i = 0; i < irq_bank_count; i++) {
-               irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
-               irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
-       }
-
-       /* Clear any pending interrupts */
-       irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
-       irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
-
-       /* Enable interrupts in global mask */
-       if (cpu_is_omap730()) {
-               irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
-       }
-
-       /* Install the interrupt handlers for each bank */
-       for (i = 0; i < irq_bank_count; i++) {
-               for (j = i * 32; j < (i + 1) * 32; j++) {
-                       int irq_trigger;
-
-                       irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
-                       omap_irq_set_cfg(j, 0, 0, irq_trigger);
-
-                       set_irq_chip(j, &omap_irq_chip);
-                       set_irq_handler(j, do_level_IRQ);
-                       set_irq_flags(j, IRQF_VALID);
-               }
-       }
-
-       /* Unmask level 2 handler */
-       if (cpu_is_omap730()) {
-               omap_unmask_irq(INT_730_IH2_IRQ);
-       } else {
-               omap_unmask_irq(INT_IH2_IRQ);
-       }
-}
diff -urN linux/arch/arm/mach-omap/leds-h2p2-debug.c 
linux/arch/arm/mach-omap/leds-h2p2-debug.c
--- linux/arch/arm/mach-omap/Attic/leds-h2p2-debug.c    2005-07-13 
12:48:52.102691000 +0100     1.2
+++ linux/arch/arm/mach-omap/Attic/leds-h2p2-debug.c    1970/01/01 00:00:00+0100
@@ -1,144 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/leds-h2p2-debug.c
- *
- * Copyright 2003 by Texas Instruments Incorporated
- *
- * There are 16 LEDs on the debug board (all green); four may be used
- * for logical 'green', 'amber', 'red', and 'blue' (after "claiming").
- *
- * The "surfer" expansion board and H2 sample board also have two-color
- * green+red LEDs (in parallel), used here for timer and idle indicators.
- */
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/sched.h>
-#include <linux/version.h>
-
-#include <asm/io.h>
-#include <asm/hardware.h>
-#include <asm/leds.h>
-#include <asm/system.h>
-
-#include <asm/arch/fpga.h>
-#include <asm/arch/gpio.h>
-
-#include "leds.h"
-
-
-#define GPIO_LED_RED           3
-#define GPIO_LED_GREEN         OMAP_MPUIO(4)
-
-
-#define LED_STATE_ENABLED      0x01
-#define LED_STATE_CLAIMED      0x02
-#define LED_TIMER_ON           0x04
-
-#define GPIO_IDLE              GPIO_LED_GREEN
-#define GPIO_TIMER             GPIO_LED_RED
-
-
-void h2p2_dbg_leds_event(led_event_t evt)
-{
-       unsigned long flags;
-
-       static struct h2p2_dbg_fpga __iomem *fpga;
-       static u16 led_state, hw_led_state;
-
-       local_irq_save(flags);
-
-       if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-               goto done;
-
-       switch (evt) {
-       case led_start:
-               if (!fpga)
-                       fpga = ioremap(H2P2_DBG_FPGA_START,
-                                               H2P2_DBG_FPGA_SIZE);
-               if (fpga) {
-                       led_state |= LED_STATE_ENABLED;
-                       __raw_writew(~0, &fpga->leds);
-               }
-               break;
-
-       case led_stop:
-       case led_halted:
-               /* all leds off during suspend or shutdown */
-               omap_set_gpio_dataout(GPIO_TIMER, 0);
-               omap_set_gpio_dataout(GPIO_IDLE, 0);
-               __raw_writew(~0, &fpga->leds);
-               led_state &= ~LED_STATE_ENABLED;
-               if (evt == led_halted) {
-                       iounmap(fpga);
-                       fpga = NULL;
-               }
-               goto done;
-
-       case led_claim:
-               led_state |= LED_STATE_CLAIMED;
-               hw_led_state = 0;
-               break;
-
-       case led_release:
-               led_state &= ~LED_STATE_CLAIMED;
-               break;
-
-#ifdef CONFIG_LEDS_TIMER
-       case led_timer:
-               led_state ^= LED_TIMER_ON;
-               omap_set_gpio_dataout(GPIO_TIMER, led_state & LED_TIMER_ON);
-               goto done;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-       case led_idle_start:
-               omap_set_gpio_dataout(GPIO_IDLE, 1);
-               goto done;
-
-       case led_idle_end:
-               omap_set_gpio_dataout(GPIO_IDLE, 0);
-               goto done;
-#endif
-
-       case led_green_on:
-               hw_led_state |= H2P2_DBG_FPGA_LED_GREEN;
-               break;
-       case led_green_off:
-               hw_led_state &= ~H2P2_DBG_FPGA_LED_GREEN;
-               break;
-
-       case led_amber_on:
-               hw_led_state |= H2P2_DBG_FPGA_LED_AMBER;
-               break;
-       case led_amber_off:
-               hw_led_state &= ~H2P2_DBG_FPGA_LED_AMBER;
-               break;
-
-       case led_red_on:
-               hw_led_state |= H2P2_DBG_FPGA_LED_RED;
-               break;
-       case led_red_off:
-               hw_led_state &= ~H2P2_DBG_FPGA_LED_RED;
-               break;
-
-       case led_blue_on:
-               hw_led_state |= H2P2_DBG_FPGA_LED_BLUE;
-               break;
-       case led_blue_off:
-               hw_led_state &= ~H2P2_DBG_FPGA_LED_BLUE;
-               break;
-
-       default:
-               break;
-       }
-
-
-       /*
-        *  Actually burn the LEDs
-        */
-       if (led_state & LED_STATE_CLAIMED)
-               __raw_writew(~hw_led_state, &fpga->leds);
-
-done:
-       local_irq_restore(flags);
-}
diff -urN linux/arch/arm/mach-omap/leds-innovator.c 
linux/arch/arm/mach-omap/leds-innovator.c
--- linux/arch/arm/mach-omap/Attic/leds-innovator.c     2005-07-13 
12:48:52.128735000 +0100     1.1
+++ linux/arch/arm/mach-omap/Attic/leds-innovator.c     1970/01/01 00:00:00+0100
@@ -1,103 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/leds-innovator.c
- */
-#include <linux/config.h>
-#include <linux/init.h>
-
-#include <asm/hardware.h>
-#include <asm/leds.h>
-#include <asm/system.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED      1
-#define LED_STATE_CLAIMED      2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void innovator_leds_event(led_event_t evt)
-{
-       unsigned long flags;
-
-       local_irq_save(flags);
-
-       switch (evt) {
-       case led_start:
-               hw_led_state = 0;
-               led_state = LED_STATE_ENABLED;
-               break;
-
-       case led_stop:
-               led_state &= ~LED_STATE_ENABLED;
-               hw_led_state = 0;
-               break;
-
-       case led_claim:
-               led_state |= LED_STATE_CLAIMED;
-               hw_led_state = 0;
-               break;
-
-       case led_release:
-               led_state &= ~LED_STATE_CLAIMED;
-               hw_led_state = 0;
-               break;
-
-#ifdef CONFIG_LEDS_TIMER
-       case led_timer:
-               if (!(led_state & LED_STATE_CLAIMED))
-                       hw_led_state ^= 0;
-               break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-       case led_idle_start:
-               if (!(led_state & LED_STATE_CLAIMED))
-                       hw_led_state |= 0;
-               break;
-
-       case led_idle_end:
-               if (!(led_state & LED_STATE_CLAIMED))
-                       hw_led_state &= ~0;
-               break;
-#endif
-
-       case led_halted:
-               break;
-
-       case led_green_on:
-               if (led_state & LED_STATE_CLAIMED)
-                       hw_led_state &= ~0;
-               break;
-
-       case led_green_off:
-               if (led_state & LED_STATE_CLAIMED)
-                       hw_led_state |= 0;
-               break;
-
-       case led_amber_on:
-               break;
-
-       case led_amber_off:
-               break;
-
-       case led_red_on:
-               if (led_state & LED_STATE_CLAIMED)
-                       hw_led_state &= ~0;
-               break;
-
-       case led_red_off:
-               if (led_state & LED_STATE_CLAIMED)
-                       hw_led_state |= 0;
-               break;
-
-       default:
-               break;
-       }
-
-       if (led_state & LED_STATE_ENABLED)
-               ;
-
-       local_irq_restore(flags);
-}
diff -urN linux/arch/arm/mach-omap/leds-osk.c 
linux/arch/arm/mach-omap/leds-osk.c
--- linux/arch/arm/mach-omap/Attic/leds-osk.c   2005-07-13 12:48:52.150497000 
+0100     1.1
+++ linux/arch/arm/mach-omap/Attic/leds-osk.c   1970/01/01 00:00:00+0100
@@ -1,198 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/leds-osk.c
- *
- * LED driver for OSK, and optionally Mistral QVGA, boards
- */
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/workqueue.h>
-
-#include <asm/hardware.h>
-#include <asm/leds.h>
-#include <asm/system.h>
-
-#include <asm/arch/gpio.h>
-#include <asm/arch/tps65010.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED      (1 << 0)
-#define LED_STATE_CLAIMED      (1 << 1)
-static u8 led_state;
-
-#define        GREEN_LED               (1 << 0)        /* TPS65010 LED1 */
-#define        AMBER_LED               (1 << 1)        /* TPS65010 LED2 */
-#define        RED_LED                 (1 << 2)        /* TPS65010 GPIO2 */
-#define        TIMER_LED               (1 << 3)        /* Mistral board */
-#define        IDLE_LED                (1 << 4)        /* Mistral board */
-static u8 hw_led_state;
-
-
-/* TPS65010 leds are changed using i2c -- from a task context.
- * Using one of these for the "idle" LED would be impractical...
- */
-#define        TPS_LEDS        (GREEN_LED | RED_LED | AMBER_LED)
-
-static u8 tps_leds_change;
-
-static void tps_work(void *unused)
-{
-       for (;;) {
-               u8      leds;
-
-               local_irq_disable();
-               leds = tps_leds_change;
-               tps_leds_change = 0;
-               local_irq_enable();
-
-               if (!leds)
-                       break;
-
-               /* careful:  the set_led() value is on/off/blink */
-               if (leds & GREEN_LED)
-                       tps65010_set_led(LED1, !!(hw_led_state & GREEN_LED));
-               if (leds & AMBER_LED)
-                       tps65010_set_led(LED2, !!(hw_led_state & AMBER_LED));
-
-               /* the gpio led doesn't have that issue */
-               if (leds & RED_LED)
-                       tps65010_set_gpio_out_value(GPIO2,
-                                       !(hw_led_state & RED_LED));
-       }
-}
-
-static DECLARE_WORK(work, tps_work, NULL);
-
-#ifdef CONFIG_FB_OMAP
-
-/* For now, all system indicators require the Mistral board, since that
- * LED can be manipulated without a task context.  This LED is either red,
- * or green, but not both; it can't give the full "disco led" effect.
- */
-
-#define GPIO_LED_RED           3
-#define GPIO_LED_GREEN         OMAP_MPUIO(4)
-
-static void mistral_setled(void)
-{
-       int     red = 0;
-       int     green = 0;
-
-       if (hw_led_state & TIMER_LED)
-               red = 1;
-       else if (hw_led_state & IDLE_LED)
-               green = 1;
-       // else both sides are disabled
-
-       omap_set_gpio_dataout(GPIO_LED_GREEN, green);
-       omap_set_gpio_dataout(GPIO_LED_RED, red);
-}
-
-#endif
-
-void osk_leds_event(led_event_t evt)
-{
-       unsigned long   flags;
-       u16             leds;
-
-       local_irq_save(flags);
-
-       if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-               goto done;
-
-       leds = hw_led_state;
-       switch (evt) {
-       case led_start:
-               led_state |= LED_STATE_ENABLED;
-               hw_led_state = 0;
-               leds = ~0;
-               break;
-
-       case led_halted:
-       case led_stop:
-               led_state &= ~LED_STATE_ENABLED;
-               hw_led_state = 0;
-               // NOTE:  work may still be pending!!
-               break;
-
-       case led_claim:
-               led_state |= LED_STATE_CLAIMED;
-               hw_led_state = 0;
-               leds = ~0;
-               break;
-
-       case led_release:
-               led_state &= ~LED_STATE_CLAIMED;
-               hw_led_state = 0;
-               break;
-
-#ifdef CONFIG_FB_OMAP
-
-#ifdef CONFIG_LEDS_TIMER
-       case led_timer:
-               hw_led_state ^= TIMER_LED;
-               mistral_setled();
-               break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-       case led_idle_start:
-               hw_led_state |= IDLE_LED;
-               mistral_setled();
-               break;
-
-       case led_idle_end:
-               hw_led_state &= ~IDLE_LED;
-               mistral_setled();
-               break;
-#endif
-
-#endif /* CONFIG_FB_OMAP */
-
-       /* "green" == tps LED1 (leftmost, normally power-good)
-        * works only with DC adapter, not on battery power!
-        */
-       case led_green_on:
-               if (led_state & LED_STATE_CLAIMED)
-                       hw_led_state |= GREEN_LED;
-               break;
-       case led_green_off:
-               if (led_state & LED_STATE_CLAIMED)
-                       hw_led_state &= ~GREEN_LED;
-               break;
-
-       /* "amber" == tps LED2 (middle) */
-       case led_amber_on:
-               if (led_state & LED_STATE_CLAIMED)
-                       hw_led_state |= AMBER_LED;
-               break;
-       case led_amber_off:
-               if (led_state & LED_STATE_CLAIMED)
-                       hw_led_state &= ~AMBER_LED;
-               break;
-
-       /* "red" == LED on tps gpio3 (rightmost) */
-       case led_red_on:
-               if (led_state & LED_STATE_CLAIMED)
-                       hw_led_state |= RED_LED;
-               break;
-       case led_red_off:
-               if (led_state & LED_STATE_CLAIMED)
-                       hw_led_state &= ~RED_LED;
-               break;
-
-       default:
-               break;
-       }
-
-       leds ^= hw_led_state;
-       leds &= TPS_LEDS;
-       if (leds && (led_state & LED_STATE_CLAIMED)) {
-               tps_leds_change |= leds;
-               schedule_work(&work);
-       }
-
-done:
-       local_irq_restore(flags);
-}
diff -urN linux/arch/arm/mach-omap/leds.c linux/arch/arm/mach-omap/leds.c
--- linux/arch/arm/mach-omap/Attic/leds.c       2005-07-13 12:48:52.172995000 
+0100     1.4
+++ linux/arch/arm/mach-omap/Attic/leds.c       1970/01/01 00:00:00+0100
@@ -1,61 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/leds.c
- *
- * OMAP LEDs dispatcher
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-
-#include "leds.h"
-
-static int __init
-omap_leds_init(void)
-{
-       if (machine_is_omap_innovator())
-               leds_event = innovator_leds_event;
-
-       else if (machine_is_omap_h2() || machine_is_omap_perseus2())
-               leds_event = h2p2_dbg_leds_event;
-
-       else if (machine_is_omap_osk())
-               leds_event = osk_leds_event;
-
-       else
-               return -1;
-
-       if (machine_is_omap_h2()
-                       || machine_is_omap_perseus2()
-                       || machine_is_omap_osk()) {
-
-               /* LED1/LED2 pins can be used as GPIO (as done here), or by
-                * the LPG (works even in deep sleep!), to drive a bicolor
-                * LED on the H2 sample board, and another on the H2/P2
-                * "surfer" expansion board.
-                *
-                * The same pins drive a LED on the OSK Mistral board, but
-                * that's a different kind of LED (just one color at a time).
-                */
-               omap_cfg_reg(P18_1610_GPIO3);
-               if (omap_request_gpio(3) == 0)
-                       omap_set_gpio_direction(3, 0);
-               else
-                       printk(KERN_WARNING "LED: can't get GPIO3/red?\n");
-
-               omap_cfg_reg(MPUIO4);
-               if (omap_request_gpio(OMAP_MPUIO(4)) == 0)
-                       omap_set_gpio_direction(OMAP_MPUIO(4), 0);
-               else
-                       printk(KERN_WARNING "LED: can't get MPUIO4/green?\n");
-       }
-
-       leds_event(led_start);
-       return 0;
-}
-
-__initcall(omap_leds_init);
diff -urN linux/arch/arm/mach-omap/leds.h linux/arch/arm/mach-omap/leds.h
--- linux/arch/arm/mach-omap/Attic/leds.h       2005-07-13 12:48:52.187396000 
+0100     1.3
+++ linux/arch/arm/mach-omap/Attic/leds.h       1970/01/01 00:00:00+0100
@@ -1,3 +0,0 @@
-extern void innovator_leds_event(led_event_t evt);
-extern void h2p2_dbg_leds_event(led_event_t evt);
-extern void osk_leds_event(led_event_t evt);
diff -urN linux/arch/arm/mach-omap/mcbsp.c linux/arch/arm/mach-omap/mcbsp.c
--- linux/arch/arm/mach-omap/Attic/mcbsp.c      2005-07-13 12:48:52.213554000 
+0100     1.2
+++ linux/arch/arm/mach-omap/Attic/mcbsp.c      1970/01/01 00:00:00+0100
@@ -1,685 +0,0 @@
-/*
- * linux/arch/arm/omap/mcbsp.c
- *
- * Copyright (C) 2004 Nokia Corporation
- * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Multichannel mode not supported.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/wait.h>
-#include <linux/completion.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-
-#include <asm/delay.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-
-#include <asm/arch/dma.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/mcbsp.h>
-
-#include <asm/hardware/clock.h>
-
-#ifdef CONFIG_MCBSP_DEBUG
-#define DBG(x...)      printk(x)
-#else
-#define DBG(x...)      do { } while (0)
-#endif
-
-struct omap_mcbsp {
-       u32                          io_base;
-       u8                           id;
-       u8                           free;
-       omap_mcbsp_word_length       rx_word_length;
-       omap_mcbsp_word_length       tx_word_length;
-
-       /* IRQ based TX/RX */
-       int                          rx_irq;
-       int                          tx_irq;
-
-       /* DMA stuff */
-       u8                           dma_rx_sync;
-       short                        dma_rx_lch;
-       u8                           dma_tx_sync;
-       short                        dma_tx_lch;
-
-       /* Completion queues */
-       struct completion            tx_irq_completion;
-       struct completion            rx_irq_completion;
-       struct completion            tx_dma_completion;
-       struct completion            rx_dma_completion;
-
-       spinlock_t                   lock;
-};
-
-static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
-static struct clk *mcbsp_dsp_ck = 0;
-static struct clk *mcbsp_api_ck = 0;
-
-
-static void omap_mcbsp_dump_reg(u8 id)
-{
-       DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
-       DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
-       DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
-       DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
-       DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
-       DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
-       DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
-       DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
-       DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
-       DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
-       DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
-       DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
-       DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
-       DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
-       DBG("***********************\n");
-}
-
-
-static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id, struct 
pt_regs *regs)
-{
-       struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id);
-
-       DBG("TX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_tx->io_base, 
SPCR2));
-
-       complete(&mcbsp_tx->tx_irq_completion);
-       return IRQ_HANDLED;
-}
-
-static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id, struct 
pt_regs *regs)
-{
-       struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id);
-
-       DBG("RX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_rx->io_base, 
SPCR2));
-
-       complete(&mcbsp_rx->rx_irq_completion);
-       return IRQ_HANDLED;
-}
-
-
-static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
-{
-       struct omap_mcbsp * mcbsp_dma_tx = (struct omap_mcbsp *)(data);
-
-       DBG("TX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, 
SPCR2));
-
-       /* We can free the channels */
-       omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
-       mcbsp_dma_tx->dma_tx_lch = -1;
-
-       complete(&mcbsp_dma_tx->tx_dma_completion);
-}
-
-static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
-{
-       struct omap_mcbsp * mcbsp_dma_rx = (struct omap_mcbsp *)(data);
-
-       DBG("RX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, 
SPCR2));
-
-       /* We can free the channels */
-       omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
-       mcbsp_dma_rx->dma_rx_lch = -1;
-
-       complete(&mcbsp_dma_rx->rx_dma_completion);
-}
-
-
-/*
- * omap_mcbsp_config simply write a config to the
- * appropriate McBSP.
- * You either call this function or set the McBSP registers
- * by yourself before calling omap_mcbsp_start().
- */
-
-void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * 
config)
-{
-       u32 io_base = mcbsp[id].io_base;
-
-       DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id+1, io_base);
-
-       /* We write the given config */
-       OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
-       OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
-       OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
-       OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
-       OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
-       OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
-       OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
-       OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
-       OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
-       OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
-       OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
-}
-
-
-
-static int omap_mcbsp_check(unsigned int id)
-{
-       if (cpu_is_omap730()) {
-               if (id > OMAP_MAX_MCBSP_COUNT - 1) {
-                      printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", 
id + 1);
-                      return -1;
-               }
-               return 0;
-       }
-
-       if (cpu_is_omap1510() || cpu_is_omap1610() || cpu_is_omap1710()) {
-               if (id > OMAP_MAX_MCBSP_COUNT) {
-                       printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", 
id + 1);
-                       return -1;
-               }
-               return 0;
-       }
-
-       return -1;
-}
-
-#define EN_XORPCK              1
-#define DSP_RSTCT2              0xe1008014
-
-static void omap_mcbsp_dsp_request(void)
-{
-       if (cpu_is_omap1510() || cpu_is_omap1610() || cpu_is_omap1710()) {
-               omap_writew((omap_readw(ARM_RSTCT1) | (1 << 1) | (1 << 2)),
-                           ARM_RSTCT1);
-               clk_enable(mcbsp_dsp_ck);
-               clk_enable(mcbsp_api_ck);
-
-               /* enable 12MHz clock to mcbsp 1 & 3 */
-               __raw_writew(__raw_readw(DSP_IDLECT2) | (1 << EN_XORPCK),
-                            DSP_IDLECT2);
-               __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
-                            DSP_RSTCT2);
-       }
-}
-
-static void omap_mcbsp_dsp_free(void)
-{
-       /* Useless for now */
-}
-
-
-int omap_mcbsp_request(unsigned int id)
-{
-       int err;
-
-       if (omap_mcbsp_check(id) < 0)
-               return -EINVAL;
-
-       /*
-        * On 1510, 1610 and 1710, McBSP1 and McBSP3
-        * are DSP public peripherals.
-        */
-       if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
-               omap_mcbsp_dsp_request();
-
-       spin_lock(&mcbsp[id].lock);
-       if (!mcbsp[id].free) {
-               printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", 
id + 1);
-               spin_unlock(&mcbsp[id].lock);
-               return -1;
-       }
-
-       mcbsp[id].free = 0;
-       spin_unlock(&mcbsp[id].lock);
-
-       /* We need to get IRQs here */
-       err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
-                         "McBSP",
-                         (void *) (&mcbsp[id]));
-       if (err != 0) {
-               printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for 
McBSP%d\n",
-                      mcbsp[id].tx_irq, mcbsp[id].id);
-               return err;
-       }
-
-       init_completion(&(mcbsp[id].tx_irq_completion));
-
-
-       err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
-                         "McBSP",
-                         (void *) (&mcbsp[id]));
-       if (err != 0) {
-               printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for 
McBSP%d\n",
-                      mcbsp[id].rx_irq, mcbsp[id].id);
-               free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
-               return err;
-       }
-
-       init_completion(&(mcbsp[id].rx_irq_completion));
-       return 0;
-
-}
-
-void omap_mcbsp_free(unsigned int id)
-{
-       if (omap_mcbsp_check(id) < 0)
-               return;
-
-       if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
-               omap_mcbsp_dsp_free();
-
-       spin_lock(&mcbsp[id].lock);
-       if (mcbsp[id].free) {
-               printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 
1);
-               spin_unlock(&mcbsp[id].lock);
-               return;
-       }
-
-       mcbsp[id].free = 1;
-       spin_unlock(&mcbsp[id].lock);
-
-       /* Free IRQs */
-       free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
-       free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
-}
-
-/*
- * Here we start the McBSP, by enabling the sample
- * generator, both transmitter and receivers,
- * and the frame sync.
- */
-void omap_mcbsp_start(unsigned int id)
-{
-       u32 io_base;
-       u16 w;
-
-       if (omap_mcbsp_check(id) < 0)
-               return;
-
-       io_base = mcbsp[id].io_base;
-
-       mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 
0x7);
-       mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 
0x7);
-
-       /* Start the sample generator */
-       w = OMAP_MCBSP_READ(io_base, SPCR2);
-       OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
-
-       /* Enable transmitter and receiver */
-       w = OMAP_MCBSP_READ(io_base, SPCR2);
-       OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
-
-       w = OMAP_MCBSP_READ(io_base, SPCR1);
-       OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
-
-       udelay(100);
-
-       /* Start frame sync */
-       w = OMAP_MCBSP_READ(io_base, SPCR2);
-       OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
-
-       /* Dump McBSP Regs */
-       omap_mcbsp_dump_reg(id);
-
-}
-
-void omap_mcbsp_stop(unsigned int id)
-{
-       u32 io_base;
-       u16 w;
-
-       if (omap_mcbsp_check(id) < 0)
-               return;
-
-       io_base = mcbsp[id].io_base;
-
-        /* Reset transmitter */
-       w = OMAP_MCBSP_READ(io_base, SPCR2);
-       OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
-
-       /* Reset receiver */
-       w = OMAP_MCBSP_READ(io_base, SPCR1);
-       OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
-
-       /* Reset the sample rate generator */
-       w = OMAP_MCBSP_READ(io_base, SPCR2);
-       OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
-}
-
-
-/*
- * IRQ based word transmission.
- */
-void omap_mcbsp_xmit_word(unsigned int id, u32 word)
-{
-       u32 io_base;
-       omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
-
-       if (omap_mcbsp_check(id) < 0)
-               return;
-
-       io_base = mcbsp[id].io_base;
-
-       wait_for_completion(&(mcbsp[id].tx_irq_completion));
-
-       if (word_length > OMAP_MCBSP_WORD_16)
-               OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
-       OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
-}
-
-u32 omap_mcbsp_recv_word(unsigned int id)
-{
-       u32 io_base;
-       u16 word_lsb, word_msb = 0;
-       omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
-
-       if (omap_mcbsp_check(id) < 0)
-               return -EINVAL;
-
-       io_base = mcbsp[id].io_base;
-
-       wait_for_completion(&(mcbsp[id].rx_irq_completion));
-
-       if (word_length > OMAP_MCBSP_WORD_16)
-               word_msb = OMAP_MCBSP_READ(io_base, DRR2);
-       word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
-
-       return (word_lsb | (word_msb << 16));
-}
-
-
-/*
- * Simple DMA based buffer rx/tx routines.
- * Nothing fancy, just a single buffer tx/rx through DMA.
- * The DMA resources are released once the transfer is done.
- * For anything fancier, you should use your own customized DMA
- * routines and callbacks.
- */
-int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int 
length)
-{
-       int dma_tx_ch;
-
-       if (omap_mcbsp_check(id) < 0)
-               return -EINVAL;
-
-       if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", 
omap_mcbsp_tx_dma_callback,
-                            &mcbsp[id],
-                            &dma_tx_ch)) {
-               printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d 
TX. Trying IRQ based TX\n", id+1);
-               return -EAGAIN;
-       }
-       mcbsp[id].dma_tx_lch = dma_tx_ch;
-
-       DBG("TX DMA on channel %d\n", dma_tx_ch);
-
-       init_completion(&(mcbsp[id].tx_dma_completion));
-
-       omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
-                                    OMAP_DMA_DATA_TYPE_S16,
-                                    length >> 1, 1,
-                                    OMAP_DMA_SYNC_ELEMENT);
-
-       omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
-                                OMAP_DMA_PORT_TIPB,
-                                OMAP_DMA_AMODE_CONSTANT,
-                                mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1);
-
-       omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
-                               OMAP_DMA_PORT_EMIFF,
-                               OMAP_DMA_AMODE_POST_INC,
-                               buffer);
-
-       omap_start_dma(mcbsp[id].dma_tx_lch);
-       wait_for_completion(&(mcbsp[id].tx_dma_completion));
-       return 0;
-}
-
-
-int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int 
length)
-{
-       int dma_rx_ch;
-
-       if (omap_mcbsp_check(id) < 0)
-               return -EINVAL;
-
-       if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", 
omap_mcbsp_rx_dma_callback,
-                            &mcbsp[id],
-                            &dma_rx_ch)) {
-               printk("Unable to request DMA channel for McBSP%d RX. Trying 
IRQ based RX\n", id+1);
-               return -EAGAIN;
-       }
-       mcbsp[id].dma_rx_lch = dma_rx_ch;
-
-       DBG("RX DMA on channel %d\n", dma_rx_ch);
-
-       init_completion(&(mcbsp[id].rx_dma_completion));
-
-       omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
-                                    OMAP_DMA_DATA_TYPE_S16,
-                                    length >> 1, 1,
-                                    OMAP_DMA_SYNC_ELEMENT);
-
-       omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
-                               OMAP_DMA_PORT_TIPB,
-                               OMAP_DMA_AMODE_CONSTANT,
-                               mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1);
-
-       omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
-                                OMAP_DMA_PORT_EMIFF,
-                                OMAP_DMA_AMODE_POST_INC,
-                                buffer);
-
-       omap_start_dma(mcbsp[id].dma_rx_lch);
-       wait_for_completion(&(mcbsp[id].rx_dma_completion));
-       return 0;
-}
-
-
-/*
- * SPI wrapper.
- * Since SPI setup is much simpler than the generic McBSP one,
- * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
- * Once this is done, you can call omap_mcbsp_start().
- */
-void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg 
* spi_cfg)
-{
-       struct omap_mcbsp_reg_cfg mcbsp_cfg;
-
-       if (omap_mcbsp_check(id) < 0)
-               return;
-
-       memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
-
-       /* SPI has only one frame */
-       mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
-       mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
-
-        /* Clock stop mode */
-       if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
-               mcbsp_cfg.spcr1 |= (1 << 12);
-       else
-               mcbsp_cfg.spcr1 |= (3 << 11);
-
-       /* Set clock parities */
-       if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
-               mcbsp_cfg.pcr0 |= CLKRP;
-       else
-               mcbsp_cfg.pcr0 &= ~CLKRP;
-
-       if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
-               mcbsp_cfg.pcr0 &= ~CLKXP;
-       else
-               mcbsp_cfg.pcr0 |= CLKXP;
-
-       /* Set SCLKME to 0 and CLKSM to 1 */
-       mcbsp_cfg.pcr0 &= ~SCLKME;
-       mcbsp_cfg.srgr2 |= CLKSM;
-
-       /* Set FSXP */
-       if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
-               mcbsp_cfg.pcr0 &= ~FSXP;
-       else
-               mcbsp_cfg.pcr0 |= FSXP;
-
-       if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
-               mcbsp_cfg.pcr0 |= CLKXM;
-               mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
-               mcbsp_cfg.pcr0 |= FSXM;
-               mcbsp_cfg.srgr2 &= ~FSGM;
-               mcbsp_cfg.xcr2 |= XDATDLY(1);
-               mcbsp_cfg.rcr2 |= RDATDLY(1);
-       }
-       else {
-               mcbsp_cfg.pcr0 &= ~CLKXM;
-               mcbsp_cfg.srgr1 |= CLKGDV(1);
-               mcbsp_cfg.pcr0 &= ~FSXM;
-               mcbsp_cfg.xcr2 &= ~XDATDLY(3);
-               mcbsp_cfg.rcr2 &= ~RDATDLY(3);
-       }
-
-       mcbsp_cfg.xcr2 &= ~XPHASE;
-       mcbsp_cfg.rcr2 &= ~RPHASE;
-
-       omap_mcbsp_config(id, &mcbsp_cfg);
-}
-
-
-/*
- * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
- * 730 has only 2 McBSP, and both of them are MPU peripherals.
- */
-struct omap_mcbsp_info {
-       u32 virt_base;
-       u8 dma_rx_sync, dma_tx_sync;
-       u16 rx_irq, tx_irq;
-};
-
-#ifdef CONFIG_ARCH_OMAP730
-static const struct omap_mcbsp_info mcbsp_730[] = {
-       [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
-               .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
-               .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
-               .rx_irq = INT_730_McBSP1RX,
-               .tx_irq = INT_730_McBSP1TX },
-       [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
-               .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
-               .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
-               .rx_irq = INT_730_McBSP2RX,
-               .tx_irq = INT_730_McBSP2TX },
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP1510
-static const struct omap_mcbsp_info mcbsp_1510[] = {
-       [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
-               .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
-               .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
-               .rx_irq = INT_McBSP1RX,
-               .tx_irq = INT_McBSP1TX },
-       [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
-               .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
-               .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
-               .rx_irq = INT_1510_SPI_RX,
-               .tx_irq = INT_1510_SPI_TX },
-       [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
-               .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
-               .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
-               .rx_irq = INT_McBSP3RX,
-               .tx_irq = INT_McBSP3TX },
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-static const struct omap_mcbsp_info mcbsp_1610[] = {
-       [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
-               .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
-               .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
-               .rx_irq = INT_McBSP1RX,
-               .tx_irq = INT_McBSP1TX },
-       [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
-               .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
-               .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
-               .rx_irq = INT_1610_McBSP2_RX,
-               .tx_irq = INT_1610_McBSP2_TX },
-       [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
-               .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
-               .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
-               .rx_irq = INT_McBSP3RX,
-               .tx_irq = INT_McBSP3TX },
-};
-#endif
-
-static int __init omap_mcbsp_init(void)
-{
-       int mcbsp_count = 0, i;
-       static const struct omap_mcbsp_info *mcbsp_info;
-
-       printk("Initializing OMAP McBSP system\n");
-
-       mcbsp_dsp_ck = clk_get(0, "dsp_ck");
-       if (IS_ERR(mcbsp_dsp_ck)) {
-               printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
-               return PTR_ERR(mcbsp_dsp_ck);
-       }
-       mcbsp_api_ck = clk_get(0, "api_ck");
-       if (IS_ERR(mcbsp_dsp_ck)) {
-               printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
-               return PTR_ERR(mcbsp_api_ck);
-       }
-
-#ifdef CONFIG_ARCH_OMAP730
-       if (cpu_is_omap730()) {
-               mcbsp_info = mcbsp_730;
-               mcbsp_count = ARRAY_SIZE(mcbsp_730);
-       }
-#endif
-#ifdef CONFIG_ARCH_OMAP1510
-       if (cpu_is_omap1510()) {
-               mcbsp_info = mcbsp_1510;
-               mcbsp_count = ARRAY_SIZE(mcbsp_1510);
-       }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-       if (cpu_is_omap1610() || cpu_is_omap1710()) {
-               mcbsp_info = mcbsp_1610;
-               mcbsp_count = ARRAY_SIZE(mcbsp_1610);
-       }
-#endif
-       for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
-               if (i >= mcbsp_count) {
-                       mcbsp[i].io_base = 0;
-                       mcbsp[i].free = 0;
-                        continue;
-               }
-               mcbsp[i].id = i + 1;
-               mcbsp[i].free = 1;
-               mcbsp[i].dma_tx_lch = -1;
-               mcbsp[i].dma_rx_lch = -1;
-
-               mcbsp[i].io_base = mcbsp_info[i].virt_base;
-               mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
-               mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
-               mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
-               mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
-               spin_lock_init(&mcbsp[i].lock);
-       }
-
-       return 0;
-}
-
-
-arch_initcall(omap_mcbsp_init);
-
-EXPORT_SYMBOL(omap_mcbsp_config);
-EXPORT_SYMBOL(omap_mcbsp_request);
-EXPORT_SYMBOL(omap_mcbsp_free);
-EXPORT_SYMBOL(omap_mcbsp_start);
-EXPORT_SYMBOL(omap_mcbsp_stop);
-EXPORT_SYMBOL(omap_mcbsp_xmit_word);
-EXPORT_SYMBOL(omap_mcbsp_recv_word);
-EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
-EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
-EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
diff -urN linux/arch/arm/mach-omap/mux.c linux/arch/arm/mach-omap/mux.c
--- linux/arch/arm/mach-omap/Attic/mux.c        2005-07-13 12:48:52.241296000 
+0100     1.4
+++ linux/arch/arm/mach-omap/Attic/mux.c        1970/01/01 00:00:00+0100
@@ -1,163 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/mux.c
- *
- * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
- *
- * Copyright (C) 2003 Nokia Corporation
- *
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#include <linux/config.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <linux/spinlock.h>
-
-#define __MUX_C__
-#include <asm/arch/mux.h>
-
-#ifdef CONFIG_OMAP_MUX
-
-/*
- * Sets the Omap MUX and PULL_DWN registers based on the table
- */
-int __init_or_module
-omap_cfg_reg(const reg_cfg_t reg_cfg)
-{
-       static DEFINE_SPINLOCK(mux_spin_lock);
-
-       unsigned long flags;
-       reg_cfg_set *cfg;
-       unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
-               pull_orig = 0, pull = 0;
-       unsigned int mask, warn = 0;
-
-       if (reg_cfg > ARRAY_SIZE(reg_cfg_table)) {
-               printk(KERN_ERR "MUX: reg_cfg %d\n", reg_cfg);
-               return -EINVAL;
-       }
-
-       cfg = &reg_cfg_table[reg_cfg];
-
-       /*
-        * We do a pretty long section here with lock on, but pin muxing
-        * should only happen on driver init for each driver, so it's not time
-        * critical.
-        */
-       spin_lock_irqsave(&mux_spin_lock, flags);
-
-       /* Check the mux register in question */
-       if (cfg->mux_reg) {
-               unsigned        tmp1, tmp2;
-
-               reg_orig = omap_readl(cfg->mux_reg);
-
-               /* The mux registers always seem to be 3 bits long */
-               mask = (0x7 << cfg->mask_offset);
-               tmp1 = reg_orig & mask;
-               reg = reg_orig & ~mask;
-
-               tmp2 = (cfg->mask << cfg->mask_offset);
-               reg |= tmp2;
-
-               if (tmp1 != tmp2)
-                       warn = 1;
-
-               omap_writel(reg, cfg->mux_reg);
-       }
-
-       /* Check for pull up or pull down selection on 1610 */
-       if (!cpu_is_omap1510()) {
-               if (cfg->pu_pd_reg && cfg->pull_val) {
-                       pu_pd_orig = omap_readl(cfg->pu_pd_reg);
-                       mask = 1 << cfg->pull_bit;
-
-                       if (cfg->pu_pd_val) {
-                               if (!(pu_pd_orig & mask))
-                                       warn = 1;
-                               /* Use pull up */
-                               pu_pd = pu_pd_orig | mask;
-                       } else {
-                               if (pu_pd_orig & mask)
-                                       warn = 1;
-                               /* Use pull down */
-                               pu_pd = pu_pd_orig & ~mask;
-                       }
-                       omap_writel(pu_pd, cfg->pu_pd_reg);
-               }
-       }
-
-       /* Check for an associated pull down register */
-       if (cfg->pull_reg) {
-               pull_orig = omap_readl(cfg->pull_reg);
-               mask = 1 << cfg->pull_bit;
-
-               if (cfg->pull_val) {
-                       if (pull_orig & mask)
-                               warn = 1;
-                       /* Low bit = pull enabled */
-                       pull = pull_orig & ~mask;
-               } else {
-                       if (!(pull_orig & mask))
-                               warn = 1;
-                       /* High bit = pull disabled */
-                       pull = pull_orig | mask;
-               }
-
-               omap_writel(pull, cfg->pull_reg);
-       }
-
-       if (warn) {
-#ifdef CONFIG_OMAP_MUX_WARNINGS
-               printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
-#endif
-       }
-
-#ifdef CONFIG_OMAP_MUX_DEBUG
-       if (cfg->debug || warn) {
-               printk("MUX: Setting register %s\n", cfg->name);
-               printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
-                      cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
-
-               if (!cpu_is_omap1510()) {
-                       if (cfg->pu_pd_reg && cfg->pull_val) {
-                               printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
-                                      cfg->pu_pd_name, cfg->pu_pd_reg,
-                                      pu_pd_orig, pu_pd);
-                       }
-               }
-
-               if (cfg->pull_reg)
-                       printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
-                              cfg->pull_name, cfg->pull_reg, pull_orig, pull);
-       }
-#endif
-
-       spin_unlock_irqrestore(&mux_spin_lock, flags);
-
-#ifdef CONFIG_OMAP_MUX_ERRORS
-       return warn ? -ETXTBSY : 0;
-#else
-       return 0;
-#endif
-}
-
-EXPORT_SYMBOL(omap_cfg_reg);
-
-#endif /* CONFIG_OMAP_MUX */
diff -urN linux/arch/arm/mach-omap/ocpi.c linux/arch/arm/mach-omap/ocpi.c
--- linux/arch/arm/mach-omap/Attic/ocpi.c       2005-07-13 12:48:52.277100000 
+0100     1.6
+++ linux/arch/arm/mach-omap/Attic/ocpi.c       1970/01/01 00:00:00+0100
@@ -1,114 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/ocpi.c
- *
- * Minimal OCP bus support for omap16xx
- *
- * Copyright (C) 2003 - 2005 Nokia Corporation
- * Written by Tony Lindgren <tony@atomide.com>
- *
- * Modified for clock framework by Paul Mundt <paul.mundt@nokia.com>.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/config.h>
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/err.h>
-
-#include <asm/io.h>
-#include <asm/hardware/clock.h>
-#include <asm/arch/hardware.h>
-
-#define OCPI_BASE              0xfffec320
-#define OCPI_FAULT             (OCPI_BASE + 0x00)
-#define OCPI_CMD_FAULT         (OCPI_BASE + 0x04)
-#define OCPI_SINT0             (OCPI_BASE + 0x08)
-#define OCPI_TABORT            (OCPI_BASE + 0x0c)
-#define OCPI_SINT1             (OCPI_BASE + 0x10)
-#define OCPI_PROT              (OCPI_BASE + 0x14)
-#define OCPI_SEC               (OCPI_BASE + 0x18)
-
-/* USB OHCI OCPI access error registers */
-#define HOSTUEADDR     0xfffba0e0
-#define HOSTUESTATUS   0xfffba0e4
-
-static struct clk *ocpi_ck;
-
-/*
- * Enables device access to OMAP buses via the OCPI bridge
- * FIXME: Add locking
- */
-int ocpi_enable(void)
-{
-       unsigned int val;
-
-       if (!cpu_is_omap16xx())
-               return -ENODEV;
-
-       /* Make sure there's clock for OCPI */
-       clk_enable(ocpi_ck);
-
-       /* Enable access for OHCI in OCPI */
-       val = omap_readl(OCPI_PROT);
-       val &= ~0xff;
-       //val &= (1 << 0);      /* Allow access only to EMIFS */
-       omap_writel(val, OCPI_PROT);
-
-       val = omap_readl(OCPI_SEC);
-       val &= ~0xff;
-       omap_writel(val, OCPI_SEC);
-
-       return 0;
-}
-EXPORT_SYMBOL(ocpi_enable);
-
-static int __init omap_ocpi_init(void)
-{
-       if (!cpu_is_omap16xx())
-               return -ENODEV;
-
-       ocpi_ck = clk_get(NULL, "l3_ocpi_ck");
-       if (IS_ERR(ocpi_ck))
-               return PTR_ERR(ocpi_ck);
-
-       clk_use(ocpi_ck);
-       ocpi_enable();
-       printk("OMAP OCPI interconnect driver loaded\n");
-
-       return 0;
-}
-
-static void __exit omap_ocpi_exit(void)
-{
-       /* REVISIT: Disable OCPI */
-
-       if (!cpu_is_omap16xx())
-               return;
-
-       clk_unuse(ocpi_ck);
-       clk_put(ocpi_ck);
-}
-
-MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
-MODULE_DESCRIPTION("OMAP OCPI bus controller module");
-MODULE_LICENSE("GPL");
-module_init(omap_ocpi_init);
-module_exit(omap_ocpi_exit);
diff -urN linux/arch/arm/mach-omap/pm.c linux/arch/arm/mach-omap/pm.c
--- linux/arch/arm/mach-omap/Attic/pm.c 2005-07-13 12:48:52.319322000 +0100     
1.4
+++ linux/arch/arm/mach-omap/Attic/pm.c 1970/01/01 00:00:00+0100
@@ -1,632 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/pm.c
- *
- * OMAP Power Management Routines
- *
- * Original code for the SA11x0:
- * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
- *
- * Modified for the PXA250 by Nicolas Pitre:
- * Copyright (c) 2002 Monta Vista Software, Inc.
- *
- * Modified for the OMAP1510 by David Singleton:
- * Copyright (c) 2002 Monta Vista Software, Inc.
- *
- * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/pm.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/pm.h>
-
-#include <asm/io.h>
-#include <asm/mach/time.h>
-#include <asm/mach-types.h>
-
-#include <asm/arch/omap16xx.h>
-#include <asm/arch/pm.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/tps65010.h>
-
-#include "clock.h"
-
-static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
-static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
-static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
-static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
-
-/*
- * Let's power down on idle, but only if we are really
- * idle, because once we start down the path of
- * going idle we continue to do idle even if we get
- * a clock tick interrupt . .
- */
-void omap_pm_idle(void)
-{
-       int (*func_ptr)(void) = 0;
-       unsigned int mask32 = 0;
-
-       /*
-        * If the DSP is being used let's just idle the CPU, the overhead
-        * to wake up from Big Sleep is big, milliseconds versus micro
-        * seconds for wait for interrupt.
-        */
-
-       local_irq_disable();
-       local_fiq_disable();
-       if (need_resched()) {
-               local_fiq_enable();
-               local_irq_enable();
-               return;
-       }
-       mask32 = omap_readl(ARM_SYSST);
-
-       /*
-        * Since an interrupt may set up a timer, we don't want to
-        * reprogram the hardware timer with interrupts enabled.
-        * Re-enable interrupts only after returning from idle.
-        */
-       timer_dyn_reprogram();
-
-       if ((mask32 & DSP_IDLE) == 0) {
-               __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
-       } else {
-
-               if (cpu_is_omap1510()) {
-                       func_ptr = (void *)(OMAP1510_SRAM_IDLE_SUSPEND);
-               } else if (cpu_is_omap1610() || cpu_is_omap1710()) {
-                       func_ptr = (void *)(OMAP1610_SRAM_IDLE_SUSPEND);
-               } else if (cpu_is_omap5912()) {
-                       func_ptr = (void *)(OMAP5912_SRAM_IDLE_SUSPEND);
-               }
-
-               func_ptr();
-       }
-       local_fiq_enable();
-       local_irq_enable();
-}
-
-/*
- * Configuration of the wakeup event is board specific. For the
- * moment we put it into this helper function. Later it may move
- * to board specific files.
- */
-static void omap_pm_wakeup_setup(void)
-{
-       /*
-        * Enable ARM XOR clock and release peripheral from reset by
-        * writing 1 to PER_EN bit in ARM_RSTCT2, this is required
-        * for UART configuration to use UART2 to wake up.
-        */
-
-       omap_writel(omap_readl(ARM_IDLECT2) | ENABLE_XORCLK, ARM_IDLECT2);
-       omap_writel(omap_readl(ARM_RSTCT2) | PER_EN, ARM_RSTCT2);
-       omap_writew(MODEM_32K_EN, ULPD_CLOCK_CTRL);
-
-       /*
-        * Turn off all interrupts except L1-2nd level cascade,
-        * and the L2 wakeup interrupts: keypad and UART2.
-        */
-
-       omap_writel(~IRQ_LEVEL2, OMAP_IH1_MIR);
-
-       if (cpu_is_omap1510()) {
-               omap_writel(~(IRQ_UART2 | IRQ_KEYBOARD),  OMAP_IH2_MIR);
-       }
-
-       if (cpu_is_omap16xx()) {
-               omap_writel(~(IRQ_UART2 | IRQ_KEYBOARD), OMAP_IH2_0_MIR);
-
-               omap_writel(~0x0, OMAP_IH2_1_MIR);
-               omap_writel(~0x0, OMAP_IH2_2_MIR);
-               omap_writel(~0x0, OMAP_IH2_3_MIR);
-       }
-
-       /*  New IRQ agreement */
-       omap_writel(1, OMAP_IH1_CONTROL);
-
-       /* external PULL to down, bit 22 = 0 */
-       omap_writel(omap_readl(PULL_DWN_CTRL_2) & ~(1<<22), PULL_DWN_CTRL_2);
-}
-
-void omap_pm_suspend(void)
-{
-       unsigned int mask32 = 0;
-       unsigned long arg0 = 0, arg1 = 0;
-       int (*func_ptr)(unsigned short, unsigned short) = 0;
-       unsigned short save_dsp_idlect2;
-
-       printk("PM: OMAP%x is entering deep sleep now ...\n", system_rev);
-
-       if (machine_is_omap_osk()) {
-               /* Stop LED1 (D9) blink */
-               tps65010_set_led(LED1, OFF);
-       }
-
-       /*
-        * Step 1: turn off interrupts
-        */
-
-       local_irq_disable();
-       local_fiq_disable();
-
-       /*
-        * Step 2: save registers
-        *
-        * The omap is a strange/beautiful device. The caches, memory
-        * and register state are preserved across power saves.
-        * We have to save and restore very little register state to
-        * idle the omap.
-         *
-        * Save interrupt, MPUI, ARM and UPLD control registers.
-        */
-
-       if (cpu_is_omap1510()) {
-               MPUI1510_SAVE(OMAP_IH1_MIR);
-               MPUI1510_SAVE(OMAP_IH2_MIR);
-               MPUI1510_SAVE(MPUI_CTRL);
-               MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
-               MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
-               MPUI1510_SAVE(EMIFS_CONFIG);
-               MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
-       } else if (cpu_is_omap16xx()) {
-               MPUI1610_SAVE(OMAP_IH1_MIR);
-               MPUI1610_SAVE(OMAP_IH2_0_MIR);
-               MPUI1610_SAVE(OMAP_IH2_1_MIR);
-               MPUI1610_SAVE(OMAP_IH2_2_MIR);
-               MPUI1610_SAVE(OMAP_IH2_3_MIR);
-               MPUI1610_SAVE(MPUI_CTRL);
-               MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
-               MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
-               MPUI1610_SAVE(EMIFS_CONFIG);
-               MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
-       }
-
-       ARM_SAVE(ARM_CKCTL);
-       ARM_SAVE(ARM_IDLECT1);
-       ARM_SAVE(ARM_IDLECT2);
-       ARM_SAVE(ARM_EWUPCT);
-       ARM_SAVE(ARM_RSTCT1);
-       ARM_SAVE(ARM_RSTCT2);
-       ARM_SAVE(ARM_SYSST);
-       ULPD_SAVE(ULPD_CLOCK_CTRL);
-       ULPD_SAVE(ULPD_STATUS_REQ);
-
-       /*
-        * Step 3: LOW_PWR signal enabling
-        *
-        * Allow the LOW_PWR signal to be visible on MPUIO5 ball.
-        */
-       if (cpu_is_omap1510()) {
-               /* POWER_CTRL_REG = 0x1 (LOW_POWER is available) */
-               omap_writew(omap_readw(ULPD_POWER_CTRL) |
-                           OMAP1510_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL);
-       } else if (cpu_is_omap16xx()) {
-               /* POWER_CTRL_REG = 0x1 (LOW_POWER is available) */
-               omap_writew(omap_readw(ULPD_POWER_CTRL) |
-                           OMAP1610_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL);
-       }
-
-       /* configure LOW_PWR pin */
-       omap_cfg_reg(T20_1610_LOW_PWR);
-
-       /*
-        * Step 4: OMAP DSP Shutdown
-        */
-
-       /* Set DSP_RST = 1 and DSP_EN = 0, put DSP block into reset */
-       omap_writel((omap_readl(ARM_RSTCT1) | DSP_RST) & ~DSP_ENABLE,
-                   ARM_RSTCT1);
-
-       /* Set DSP boot mode to DSP-IDLE, DSP_BOOT_MODE = 0x2 */
-        omap_writel(DSP_IDLE_MODE, MPUI_DSP_BOOT_CONFIG);
-
-       /* Set EN_DSPCK = 0, stop DSP block clock */
-       omap_writel(omap_readl(ARM_CKCTL) & ~DSP_CLOCK_ENABLE, ARM_CKCTL);
-
-       /* Stop any DSP domain clocks */
-       omap_writel(omap_readl(ARM_IDLECT2) | (1<<EN_APICK), ARM_IDLECT2);
-       save_dsp_idlect2 = __raw_readw(DSP_IDLECT2);
-       __raw_writew(0, DSP_IDLECT2);
-
-       /*
-        * Step 5: Wakeup Event Setup
-        */
-
-       omap_pm_wakeup_setup();
-
-       /*
-        * Step 6a: ARM and Traffic controller shutdown
-        *
-        * Step 6 starts here with clock and watchdog disable
-        */
-
-       /* stop clocks */
-       mask32 = omap_readl(ARM_IDLECT2);
-       mask32 &= ~(1<<EN_WDTCK);  /* bit 0 -> 0 (WDT clock) */
-       mask32 |=  (1<<EN_XORPCK); /* bit 1 -> 1 (XORPCK clock) */
-       mask32 &= ~(1<<EN_PERCK);  /* bit 2 -> 0 (MPUPER_CK clock) */
-       mask32 &= ~(1<<EN_LCDCK);  /* bit 3 -> 0 (LCDC clock) */
-       mask32 &= ~(1<<EN_LBCK);   /* bit 4 -> 0 (local bus clock) */
-       mask32 |=  (1<<EN_APICK);  /* bit 6 -> 1 (MPUI clock) */
-       mask32 &= ~(1<<EN_TIMCK);  /* bit 7 -> 0 (MPU timer clock) */
-       mask32 &= ~(1<<DMACK_REQ); /* bit 8 -> 0 (DMAC clock) */
-       mask32 &= ~(1<<EN_GPIOCK); /* bit 9 -> 0 (GPIO clock) */
-       omap_writel(mask32, ARM_IDLECT2);
-
-       /* disable ARM watchdog */
-       omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
-       omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
-
-       /*
-        * Step 6b: ARM and Traffic controller shutdown
-        *
-        * Step 6 continues here. Prepare jump to power management
-        * assembly code in internal SRAM.
-        *
-        * Since the omap_cpu_suspend routine has been copied to
-        * SRAM, we'll do an indirect procedure call to it and pass the
-        * contents of arm_idlect1 and arm_idlect2 so it can restore
-        * them when it wakes up and it will return.
-        */
-
-       arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
-       arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
-
-       if (cpu_is_omap1510()) {
-               func_ptr = (void *)(OMAP1510_SRAM_API_SUSPEND);
-       } else if (cpu_is_omap1610() || cpu_is_omap1710()) {
-               func_ptr = (void *)(OMAP1610_SRAM_API_SUSPEND);
-       } else if (cpu_is_omap5912()) {
-               func_ptr = (void *)(OMAP5912_SRAM_API_SUSPEND);
-       }
-
-       /*
-        * Step 6c: ARM and Traffic controller shutdown
-        *
-        * Jump to assembly code. The processor will stay there
-        * until wake up.
-        */
-
-        func_ptr(arg0, arg1);
-
-       /*
-        * If we are here, processor is woken up!
-        */
-
-       if (cpu_is_omap1510()) {
-               /* POWER_CTRL_REG = 0x0 (LOW_POWER is disabled) */
-               omap_writew(omap_readw(ULPD_POWER_CTRL) &
-                           ~OMAP1510_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL);
-       } else if (cpu_is_omap16xx()) {
-               /* POWER_CTRL_REG = 0x0 (LOW_POWER is disabled) */
-               omap_writew(omap_readw(ULPD_POWER_CTRL) &
-                           ~OMAP1610_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL);
-       }
-
-
-       /* Restore DSP clocks */
-       omap_writel(omap_readl(ARM_IDLECT2) | (1<<EN_APICK), ARM_IDLECT2);
-       __raw_writew(save_dsp_idlect2, DSP_IDLECT2);
-       ARM_RESTORE(ARM_IDLECT2);
-
-       /*
-        * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
-        */
-
-       ARM_RESTORE(ARM_CKCTL);
-       ARM_RESTORE(ARM_EWUPCT);
-       ARM_RESTORE(ARM_RSTCT1);
-       ARM_RESTORE(ARM_RSTCT2);
-       ARM_RESTORE(ARM_SYSST);
-       ULPD_RESTORE(ULPD_CLOCK_CTRL);
-       ULPD_RESTORE(ULPD_STATUS_REQ);
-
-       if (cpu_is_omap1510()) {
-               MPUI1510_RESTORE(MPUI_CTRL);
-               MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
-               MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
-               MPUI1510_RESTORE(EMIFS_CONFIG);
-               MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
-               MPUI1510_RESTORE(OMAP_IH1_MIR);
-               MPUI1510_RESTORE(OMAP_IH2_MIR);
-       } else if (cpu_is_omap16xx()) {
-               MPUI1610_RESTORE(MPUI_CTRL);
-               MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
-               MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
-               MPUI1610_RESTORE(EMIFS_CONFIG);
-               MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
-
-               MPUI1610_RESTORE(OMAP_IH1_MIR);
-               MPUI1610_RESTORE(OMAP_IH2_0_MIR);
-               MPUI1610_RESTORE(OMAP_IH2_1_MIR);
-               MPUI1610_RESTORE(OMAP_IH2_2_MIR);
-               MPUI1610_RESTORE(OMAP_IH2_3_MIR);
-       }
-
-       /*
-        * Reenable interrupts
-        */
-
-       local_irq_enable();
-       local_fiq_enable();
-
-       printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
-
-       if (machine_is_omap_osk()) {
-               /* Let LED1 (D9) blink again */
-               tps65010_set_led(LED1, BLINK);
-       }
-}
-
-#if defined(DEBUG) && defined(CONFIG_PROC_FS)
-static int g_read_completed;
-
-/*
- * Read system PM registers for debugging
- */
-static int omap_pm_read_proc(
-       char *page_buffer,
-       char **my_first_byte,
-       off_t virtual_start,
-       int length,
-       int *eof,
-       void *data)
-{
-       int my_buffer_offset = 0;
-       char * const my_base = page_buffer;
-
-       ARM_SAVE(ARM_CKCTL);
-       ARM_SAVE(ARM_IDLECT1);
-       ARM_SAVE(ARM_IDLECT2);
-       ARM_SAVE(ARM_EWUPCT);
-       ARM_SAVE(ARM_RSTCT1);
-       ARM_SAVE(ARM_RSTCT2);
-       ARM_SAVE(ARM_SYSST);
-
-       ULPD_SAVE(ULPD_IT_STATUS);
-       ULPD_SAVE(ULPD_CLOCK_CTRL);
-       ULPD_SAVE(ULPD_SOFT_REQ);
-       ULPD_SAVE(ULPD_STATUS_REQ);
-       ULPD_SAVE(ULPD_DPLL_CTRL);
-       ULPD_SAVE(ULPD_POWER_CTRL);
-
-       if (cpu_is_omap1510()) {
-               MPUI1510_SAVE(MPUI_CTRL);
-               MPUI1510_SAVE(MPUI_DSP_STATUS);
-               MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
-               MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
-               MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
-               MPUI1510_SAVE(EMIFS_CONFIG);
-       } else if (cpu_is_omap16xx()) {
-               MPUI1610_SAVE(MPUI_CTRL);
-               MPUI1610_SAVE(MPUI_DSP_STATUS);
-               MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
-               MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
-               MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
-               MPUI1610_SAVE(EMIFS_CONFIG);
-       }
-
-       if (virtual_start == 0) {
-               g_read_completed = 0;
-
-               my_buffer_offset += sprintf(my_base + my_buffer_offset,
-                  "ARM_CKCTL_REG:            0x%-8x     \n"
-                  "ARM_IDLECT1_REG:          0x%-8x     \n"
-                  "ARM_IDLECT2_REG:          0x%-8x     \n"
-                  "ARM_EWUPCT_REG:           0x%-8x     \n"
-                  "ARM_RSTCT1_REG:           0x%-8x     \n"
-                  "ARM_RSTCT2_REG:           0x%-8x     \n"
-                  "ARM_SYSST_REG:            0x%-8x     \n"
-                  "ULPD_IT_STATUS_REG:       0x%-4x     \n"
-                  "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
-                  "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
-                  "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
-                  "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
-                  "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
-                  ARM_SHOW(ARM_CKCTL),
-                  ARM_SHOW(ARM_IDLECT1),
-                  ARM_SHOW(ARM_IDLECT2),
-                  ARM_SHOW(ARM_EWUPCT),
-                  ARM_SHOW(ARM_RSTCT1),
-                  ARM_SHOW(ARM_RSTCT2),
-                  ARM_SHOW(ARM_SYSST),
-                  ULPD_SHOW(ULPD_IT_STATUS),
-                  ULPD_SHOW(ULPD_CLOCK_CTRL),
-                  ULPD_SHOW(ULPD_SOFT_REQ),
-                  ULPD_SHOW(ULPD_DPLL_CTRL),
-                  ULPD_SHOW(ULPD_STATUS_REQ),
-                  ULPD_SHOW(ULPD_POWER_CTRL));
-
-               if (cpu_is_omap1510()) {
-                       my_buffer_offset += sprintf(my_base + my_buffer_offset,
-                          "MPUI1510_CTRL_REG             0x%-8x \n"
-                          "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
-                          "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
-                          "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
-                          "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
-                          "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
-                          MPUI1510_SHOW(MPUI_CTRL),
-                          MPUI1510_SHOW(MPUI_DSP_STATUS),
-                          MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
-                          MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
-                          MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
-                          MPUI1510_SHOW(EMIFS_CONFIG));
-               } else if (cpu_is_omap16xx()) {
-                       my_buffer_offset += sprintf(my_base + my_buffer_offset,
-                          "MPUI1610_CTRL_REG             0x%-8x \n"
-                          "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
-                          "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
-                          "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
-                          "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
-                          "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
-                          MPUI1610_SHOW(MPUI_CTRL),
-                          MPUI1610_SHOW(MPUI_DSP_STATUS),
-                          MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
-                          MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
-                          MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
-                          MPUI1610_SHOW(EMIFS_CONFIG));
-               }
-
-               g_read_completed++;
-       } else if (g_read_completed >= 1) {
-                *eof = 1;
-                return 0;
-       }
-       g_read_completed++;
-
-       *my_first_byte = page_buffer;
-       return  my_buffer_offset;
-}
-
-static void omap_pm_init_proc(void)
-{
-       struct proc_dir_entry *entry;
-
-       entry = create_proc_read_entry("driver/omap_pm",
-                                      S_IWUSR | S_IRUGO, NULL,
-                                      omap_pm_read_proc, 0);
-}
-
-#endif /* DEBUG && CONFIG_PROC_FS */
-
-/*
- *     omap_pm_prepare - Do preliminary suspend work.
- *     @state:         suspend state we're entering.
- *
- */
-//#include <asm/arch/hardware.h>
-
-static int omap_pm_prepare(suspend_state_t state)
-{
-       int error = 0;
-
-       switch (state)
-       {
-       case PM_SUSPEND_STANDBY:
-       case PM_SUSPEND_MEM:
-               break;
-
-       case PM_SUSPEND_DISK:
-               return -ENOTSUPP;
-
-       default:
-               return -EINVAL;
-       }
-
-       return error;
-}
-
-
-/*
- *     omap_pm_enter - Actually enter a sleep state.
- *     @state:         State we're entering.
- *
- */
-
-static int omap_pm_enter(suspend_state_t state)
-{
-       switch (state)
-       {
-       case PM_SUSPEND_STANDBY:
-       case PM_SUSPEND_MEM:
-               omap_pm_suspend();
-               break;
-
-       case PM_SUSPEND_DISK:
-               return -ENOTSUPP;
-
-       default:
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-
-/**
- *     omap_pm_finish - Finish up suspend sequence.
- *     @state:         State we're coming out of.
- *
- *     This is called after we wake back up (or if entering the sleep state
- *     failed).
- */
-
-static int omap_pm_finish(suspend_state_t state)
-{
-       return 0;
-}
-
-
-struct pm_ops omap_pm_ops ={
-       .pm_disk_mode = 0,
-        .prepare        = omap_pm_prepare,
-        .enter          = omap_pm_enter,
-        .finish         = omap_pm_finish,
-};
-
-static int __init omap_pm_init(void)
-{
-       printk("Power Management for TI OMAP.\n");
-       pm_idle = omap_pm_idle;
-       /*
-        * We copy the assembler sleep/wakeup routines to SRAM.
-        * These routines need to be in SRAM as that's the only
-        * memory the MPU can see when it wakes up.
-        */
-
-#ifdef CONFIG_ARCH_OMAP1510
-       if (cpu_is_omap1510()) {
-               memcpy((void *)OMAP1510_SRAM_IDLE_SUSPEND,
-                      omap1510_idle_loop_suspend,
-                      omap1510_idle_loop_suspend_sz);
-               memcpy((void *)OMAP1510_SRAM_API_SUSPEND, omap1510_cpu_suspend,
-                      omap1510_cpu_suspend_sz);
-       } else
-#endif
-       if (cpu_is_omap1610() || cpu_is_omap1710()) {
-               memcpy((void *)OMAP1610_SRAM_IDLE_SUSPEND,
-                      omap1610_idle_loop_suspend,
-                      omap1610_idle_loop_suspend_sz);
-               memcpy((void *)OMAP1610_SRAM_API_SUSPEND, omap1610_cpu_suspend,
-                      omap1610_cpu_suspend_sz);
-       } else if (cpu_is_omap5912()) {
-               memcpy((void *)OMAP5912_SRAM_IDLE_SUSPEND,
-                      omap1610_idle_loop_suspend,
-                      omap1610_idle_loop_suspend_sz);
-               memcpy((void *)OMAP5912_SRAM_API_SUSPEND, omap1610_cpu_suspend,
-                      omap1610_cpu_suspend_sz);
-       }
-
-       pm_set_ops(&omap_pm_ops);
-
-#if defined(DEBUG) && defined(CONFIG_PROC_FS)
-       omap_pm_init_proc();
-#endif
-
-       return 0;
-}
-__initcall(omap_pm_init);
-
diff -urN linux/arch/arm/mach-omap/sleep.S linux/arch/arm/mach-omap/sleep.S
--- linux/arch/arm/mach-omap/Attic/sleep.S      2005-07-13 12:48:52.377177000 
+0100     1.1
+++ linux/arch/arm/mach-omap/Attic/sleep.S      1970/01/01 00:00:00+0100
@@ -1,314 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/sleep.S
- *
- * Low-level OMAP1510/1610 sleep/wakeUp support
- *
- * Initial SA1110 code:
- * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
- *
- * Adapted for PXA by Nicolas Pitre:
- * Copyright (c) 2002 Monta Vista Software, Inc.
- *
- * Support for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/config.h>
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/arch/io.h>
-#include <asm/arch/pm.h>
-
-               .text
-
-/*
- * Forces OMAP into idle state
- *
- * omapXXXX_idle_loop_suspend()
- *
- * Note: This code get's copied to internal SRAM at boot. When the OMAP
- *      wakes up it continues execution at the point it went to sleep.
- *
- * Note: Because of slightly different configuration values we have
- *       processor specific functions here.
- */
-
-#ifdef CONFIG_ARCH_OMAP1510
-ENTRY(omap1510_idle_loop_suspend)
-
-       stmfd   sp!, {r0 - r12, lr}             @ save registers on stack
-
-       @ load base address of ARM_IDLECT1 and ARM_IDLECT2
-       mov     r4, #CLKGEN_REG_ASM_BASE & 0xff000000
-       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
-       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
-
-       @ turn off clock domains
-       @ get ARM_IDLECT2 into r2
-       ldrh    r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-       mov     r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
-       orr     r5,r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
-       strh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-
-       @ request ARM idle
-       @ get ARM_IDLECT1 into r1
-       ldrh    r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
-       orr     r3, r1, #OMAP1510_IDLE_LOOP_REQUEST & 0xffff
-       strh    r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
-
-       mov     r5, #IDLE_WAIT_CYCLES & 0xff
-       orr     r5, r5, #IDLE_WAIT_CYCLES & 0xff00
-l_1510:        subs    r5, r5, #1
-       bne     l_1510
-/*
- * Let's wait for the next clock tick to wake us up.
- */
-       mov     r0, #0
-       mcr     p15, 0, r0, c7, c0, 4           @ wait for interrupt
-/*
- * omap1510_idle_loop_suspend()'s resume point.
- *
- * It will just start executing here, so we'll restore stuff from the
- * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
- */
-
-       @ restore ARM_IDLECT1 and ARM_IDLECT2 and return
-       @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
-       strh    r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-       strh    r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
-
-       ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
-
-ENTRY(omap1510_idle_loop_suspend_sz)
-       .word   . - omap1510_idle_loop_suspend
-#endif /* CONFIG_ARCH_OMAP1510 */
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-ENTRY(omap1610_idle_loop_suspend)
-
-       stmfd   sp!, {r0 - r12, lr}             @ save registers on stack
-
-       @ load base address of ARM_IDLECT1 and ARM_IDLECT2
-       mov     r4, #CLKGEN_REG_ASM_BASE & 0xff000000
-       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
-       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
-
-       @ turn off clock domains
-       @ get ARM_IDLECT2 into r2
-       ldrh    r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-       mov     r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff
-       orr     r5,r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff00
-       strh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-
-       @ request ARM idle
-       @ get ARM_IDLECT1 into r1
-       ldrh    r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
-       orr     r3, r1, #OMAP1610_IDLE_LOOP_REQUEST & 0xffff
-       strh    r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
-
-       mov     r5, #IDLE_WAIT_CYCLES & 0xff
-       orr     r5, r5, #IDLE_WAIT_CYCLES & 0xff00
-l_1610:        subs    r5, r5, #1
-       bne     l_1610
-/*
- * Let's wait for the next clock tick to wake us up.
- */
-       mov     r0, #0
-       mcr     p15, 0, r0, c7, c0, 4           @ wait for interrupt
-/*
- * omap1610_idle_loop_suspend()'s resume point.
- *
- * It will just start executing here, so we'll restore stuff from the
- * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
- */
-
-       @ restore ARM_IDLECT1 and ARM_IDLECT2 and return
-       @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
-       strh    r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-       strh    r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
-
-       ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
-
-ENTRY(omap1610_idle_loop_suspend_sz)
-       .word   . - omap1610_idle_loop_suspend
-#endif /* CONFIG_ARCH_OMAP16XX */
-
-/*
- * Forces OMAP into deep sleep state
- *
- * omapXXXX_cpu_suspend()
- *
- * The values of the registers ARM_IDLECT1 and ARM_IDLECT2 are passed
- * as arg0 and arg1 from caller. arg0 is stored in register r0 and arg1
- * in register r1.
- *
- * Note: This code get's copied to internal SRAM at boot. When the OMAP
- *      wakes up it continues execution at the point it went to sleep.
- *
- * Note: Because of errata work arounds we have processor specific functions
- *       here. They are mostly the same, but slightly different.
- *
- */
-
-#ifdef CONFIG_ARCH_OMAP1510
-ENTRY(omap1510_cpu_suspend)
-
-       @ save registers on stack
-       stmfd   sp!, {r0 - r12, lr}
-
-       @ load base address of Traffic Controller
-       mov     r4, #TCMIF_ASM_BASE & 0xff000000
-       orr     r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
-       orr     r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
-
-       @ work around errata of OMAP1510 PDE bit for TC shut down
-       @ clear PDE bit
-       ldr     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
-       bic     r5, r5, #PDE_BIT & 0xff
-       str     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
-
-       @ set PWD_EN bit
-       and     r5, r5, #PWD_EN_BIT & 0xff
-       str     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
-
-       @ prepare to put SDRAM into self-refresh manually
-       ldr     r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
-       orr     r5, r5, #SELF_REFRESH_MODE & 0xff000000
-       orr     r5, r5, #SELF_REFRESH_MODE & 0x000000ff
-       str     r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
-
-       @ prepare to put EMIFS to Sleep
-       ldr     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
-       orr     r5, r5, #IDLE_EMIFS_REQUEST & 0xff
-       str     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
-
-       @ load base address of ARM_IDLECT1 and ARM_IDLECT2
-       mov     r4, #CLKGEN_REG_ASM_BASE & 0xff000000
-       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
-       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
-
-       @ turn off clock domains
-       mov     r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
-       orr     r5,r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
-       strh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-
-       @ request ARM idle
-       mov     r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff
-       orr     r3, r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff00
-       strh    r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
-
-       mov     r5, #IDLE_WAIT_CYCLES & 0xff
-       orr     r5, r5, #IDLE_WAIT_CYCLES & 0xff00
-l_1510_2:
-       subs    r5, r5, #1
-       bne     l_1510_2
-/*
- * Let's wait for the next wake up event to wake us up. r0 can't be
- * used here because r0 holds ARM_IDLECT1
- */
-       mov     r2, #0
-       mcr     p15, 0, r2, c7, c0, 4           @ wait for interrupt
-/*
- * omap1510_cpu_suspend()'s resume point.
- *
- * It will just start executing here, so we'll restore stuff from the
- * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
- */
-       strh    r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-       strh    r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
-
-       @ restore regs and return
-       ldmfd   sp!, {r0 - r12, pc}
-
-ENTRY(omap1510_cpu_suspend_sz)
-       .word   . - omap1510_cpu_suspend
-#endif /* CONFIG_ARCH_OMAP1510 */
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-ENTRY(omap1610_cpu_suspend)
-
-       @ save registers on stack
-       stmfd   sp!, {r0 - r12, lr}
-
-       @ load base address of Traffic Controller
-       mov     r4, #TCMIF_ASM_BASE & 0xff000000
-       orr     r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
-       orr     r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
-
-       @ prepare to put SDRAM into self-refresh manually
-       ldr     r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
-       orr     r5, r5, #SELF_REFRESH_MODE & 0xff000000
-       orr     r5, r5, #SELF_REFRESH_MODE & 0x000000ff
-       str     r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
-
-       @ prepare to put EMIFS to Sleep
-       ldr     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
-       orr     r5, r5, #IDLE_EMIFS_REQUEST & 0xff
-       str     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
-
-       @ load base address of ARM_IDLECT1 and ARM_IDLECT2
-       mov     r4, #CLKGEN_REG_ASM_BASE & 0xff000000
-       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
-       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
-
-       @ turn off clock domains
-       mov     r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff
-       orr     r5,r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff00
-       strh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-
-       @ work around errata of OMAP1610/5912. Enable (!) peripheral
-       @ clock to let the chip go into deep sleep
-       ldrh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-       orr     r5,r5, #EN_PERCK_BIT & 0xff
-       strh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-
-       @ request ARM idle
-       mov     r3, #OMAP1610_DEEP_SLEEP_REQUEST & 0xff
-       orr     r3, r3, #OMAP1610_DEEP_SLEEP_REQUEST & 0xff00
-       strh    r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
-
-       mov     r5, #IDLE_WAIT_CYCLES & 0xff
-       orr     r5, r5, #IDLE_WAIT_CYCLES & 0xff00
-l_1610_2:
-       subs    r5, r5, #1
-       bne     l_1610_2
-/*
- * Let's wait for the next wake up event to wake us up. r0 can't be
- * used here because r0 holds ARM_IDLECT1
- */
-       mov     r2, #0
-       mcr     p15, 0, r2, c7, c0, 4           @ wait for interrupt
-/*
- * omap1610_cpu_suspend()'s resume point.
- *
- * It will just start executing here, so we'll restore stuff from the
- * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
- */
-       strh    r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-       strh    r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
-
-       @ restore regs and return
-       ldmfd   sp!, {r0 - r12, pc}
-
-ENTRY(omap1610_cpu_suspend_sz)
-       .word   . - omap1610_cpu_suspend
-#endif /* CONFIG_ARCH_OMAP16XX */
diff -urN linux/arch/arm/mach-omap/time.c linux/arch/arm/mach-omap/time.c
--- linux/arch/arm/mach-omap/Attic/time.c       2005-07-13 12:48:52.427019000 
+0100     1.7
+++ linux/arch/arm/mach-omap/Attic/time.c       1970/01/01 00:00:00+0100
@@ -1,424 +0,0 @@
-/*
- * linux/arch/arm/mach-omap/time.c
- *
- * OMAP Timers
- *
- * Copyright (C) 2004 Nokia Corporation
- * Partial timer rewrite and additional dynamic tick timer support by
- * Tony Lindgen <tony@atomide.com> and
- * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- *
- * MPU timer code based on the older MPU timer code for OMAP
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-
-#include <asm/system.h>
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <asm/leds.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-
-struct sys_timer omap_timer;
-
-#ifdef CONFIG_OMAP_MPU_TIMER
-
-/*
- * ---------------------------------------------------------------------------
- * MPU timer
- * ---------------------------------------------------------------------------
- */
-#define OMAP_MPU_TIMER1_BASE           (0xfffec500)
-#define OMAP_MPU_TIMER2_BASE           (0xfffec600)
-#define OMAP_MPU_TIMER3_BASE           (0xfffec700)
-#define OMAP_MPU_TIMER_BASE            OMAP_MPU_TIMER1_BASE
-#define OMAP_MPU_TIMER_OFFSET          0x100
-
-#define MPU_TIMER_FREE                 (1 << 6)
-#define MPU_TIMER_CLOCK_ENABLE         (1 << 5)
-#define MPU_TIMER_AR                   (1 << 1)
-#define MPU_TIMER_ST                   (1 << 0)
-
-/* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c,
- * converted to use kHz by Kevin Hilman */
-/* convert from cycles(64bits) => nanoseconds (64bits)
- *  basic equation:
- *             ns = cycles / (freq / ns_per_sec)
- *             ns = cycles * (ns_per_sec / freq)
- *             ns = cycles * (10^9 / (cpu_khz * 10^3))
- *             ns = cycles * (10^6 / cpu_khz)
- *
- *     Then we use scaling math (suggested by george at mvista.com) to get:
- *             ns = cycles * (10^6 * SC / cpu_khz / SC
- *             ns = cycles * cyc2ns_scale / SC
- *
- *     And since SC is a constant power of two, we can convert the div
- *  into a shift.
- *                     -johnstul at us.ibm.com "math is hard, lets go 
shopping!"
- */
-static unsigned long cyc2ns_scale;
-#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
-
-static inline void set_cyc2ns_scale(unsigned long cpu_khz)
-{
-       cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
-}
-
-static inline unsigned long long cycles_2_ns(unsigned long long cyc)
-{
-       return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
-}
-
-/*
- * MPU_TICKS_PER_SEC must be an even number, otherwise machinecycles_to_usecs
- * will break. On P2, the timer count rate is 6.5 MHz after programming PTV
- * with 0. This divides the 13MHz input by 2, and is undocumented.
- */
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
-/* REVISIT: This ifdef construct should be replaced by a query to clock
- * framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz.
- */
-#define MPU_TICKS_PER_SEC              (13000000 / 2)
-#else
-#define MPU_TICKS_PER_SEC              (12000000 / 2)
-#endif
-
-#define MPU_TIMER_TICK_PERIOD          ((MPU_TICKS_PER_SEC / HZ) - 1)
-
-typedef struct {
-       u32 cntl;                       /* CNTL_TIMER, R/W */
-       u32 load_tim;                   /* LOAD_TIM,   W */
-       u32 read_tim;                   /* READ_TIM,   R */
-} omap_mpu_timer_regs_t;
-
-#define omap_mpu_timer_base(n)                                         \
-((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE +     \
-                                (n)*OMAP_MPU_TIMER_OFFSET))
-
-static inline unsigned long omap_mpu_timer_read(int nr)
-{
-       volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
-       return timer->read_tim;
-}
-
-static inline void omap_mpu_timer_start(int nr, unsigned long load_val)
-{
-       volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
-
-       timer->cntl = MPU_TIMER_CLOCK_ENABLE;
-       udelay(1);
-       timer->load_tim = load_val;
-        udelay(1);
-       timer->cntl = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST);
-}
-
-unsigned long omap_mpu_timer_ticks_to_usecs(unsigned long nr_ticks)
-{
-       unsigned long long nsec;
-
-       nsec = cycles_2_ns((unsigned long long)nr_ticks);
-       return (unsigned long)nsec / 1000;
-}
-
-/*
- * Last processed system timer interrupt
- */
-static unsigned long omap_mpu_timer_last = 0;
-
-/*
- * Returns elapsed usecs since last system timer interrupt
- */
-static unsigned long omap_mpu_timer_gettimeoffset(void)
-{
-       unsigned long now = 0 - omap_mpu_timer_read(0);
-       unsigned long elapsed = now - omap_mpu_timer_last;
-
-       return omap_mpu_timer_ticks_to_usecs(elapsed);
-}
-
-/*
- * Elapsed time between interrupts is calculated using timer0.
- * Latency during the interrupt is calculated using timer1.
- * Both timer0 and timer1 are counting at 6MHz (P2 6.5MHz).
- */
-static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id,
-                                       struct pt_regs *regs)
-{
-       unsigned long now, latency;
-
-       write_seqlock(&xtime_lock);
-       now = 0 - omap_mpu_timer_read(0);
-       latency = MPU_TICKS_PER_SEC / HZ - omap_mpu_timer_read(1);
-       omap_mpu_timer_last = now - latency;
-       timer_tick(regs);
-       write_sequnlock(&xtime_lock);
-
-       return IRQ_HANDLED;
-}
-
-static struct irqaction omap_mpu_timer_irq = {
-       .name           = "mpu timer",
-       .flags          = SA_INTERRUPT | SA_TIMER,
-       .handler        = omap_mpu_timer_interrupt,
-};
-
-static unsigned long omap_mpu_timer1_overflows;
-static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id,
-                                            struct pt_regs *regs)
-{
-       omap_mpu_timer1_overflows++;
-       return IRQ_HANDLED;
-}
-
-static struct irqaction omap_mpu_timer1_irq = {
-       .name           = "mpu timer1 overflow",
-       .flags          = SA_INTERRUPT,
-       .handler        = omap_mpu_timer1_interrupt,
-};
-
-static __init void omap_init_mpu_timer(void)
-{
-       set_cyc2ns_scale(MPU_TICKS_PER_SEC / 1000);
-       omap_timer.offset = omap_mpu_timer_gettimeoffset;
-       setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
-       setup_irq(INT_TIMER2, &omap_mpu_timer_irq);
-       omap_mpu_timer_start(0, 0xffffffff);
-       omap_mpu_timer_start(1, MPU_TIMER_TICK_PERIOD);
-}
-
-/*
- * Scheduler clock - returns current time in nanosec units.
- */
-unsigned long long sched_clock(void)
-{
-       unsigned long ticks = 0 - omap_mpu_timer_read(0);
-       unsigned long long ticks64;
-
-       ticks64 = omap_mpu_timer1_overflows;
-       ticks64 <<= 32;
-       ticks64 |= ticks;
-
-       return cycles_2_ns(ticks64);
-}
-#endif /* CONFIG_OMAP_MPU_TIMER */
-
-#ifdef CONFIG_OMAP_32K_TIMER
-
-#ifdef CONFIG_ARCH_OMAP1510
-#error OMAP 32KHz timer does not currently work on 1510!
-#endif
-
-/*
- * ---------------------------------------------------------------------------
- * 32KHz OS timer
- *
- * This currently works only on 16xx, as 1510 does not have the continuous
- * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
- * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
- * on 1510 would be possible, but the timer would not be as accurate as
- * with the 32KHz synchronized timer.
- * ---------------------------------------------------------------------------
- */
-#define OMAP_32K_TIMER_BASE            0xfffb9000
-#define OMAP_32K_TIMER_CR              0x08
-#define OMAP_32K_TIMER_TVR             0x00
-#define OMAP_32K_TIMER_TCR             0x04
-
-#define OMAP_32K_TICKS_PER_HZ          (32768 / HZ)
-
-/*
- * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
- * so with HZ = 100, TVR = 327.68.
- */
-#define OMAP_32K_TIMER_TICK_PERIOD     ((32768 / HZ) - 1)
-#define TIMER_32K_SYNCHRONIZED         0xfffbc410
-
-#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate)                    \
-                               (((nr_jiffies) * (clock_rate)) / HZ)
-
-static inline void omap_32k_timer_write(int val, int reg)
-{
-       omap_writew(val, reg + OMAP_32K_TIMER_BASE);
-}
-
-static inline unsigned long omap_32k_timer_read(int reg)
-{
-       return omap_readl(reg + OMAP_32K_TIMER_BASE) & 0xffffff;
-}
-
-/*
- * The 32KHz synchronized timer is an additional timer on 16xx.
- * It is always running.
- */
-static inline unsigned long omap_32k_sync_timer_read(void)
-{
-       return omap_readl(TIMER_32K_SYNCHRONIZED);
-}
-
-static inline void omap_32k_timer_start(unsigned long load_val)
-{
-       omap_32k_timer_write(load_val, OMAP_32K_TIMER_TVR);
-       omap_32k_timer_write(0x0f, OMAP_32K_TIMER_CR);
-}
-
-static inline void omap_32k_timer_stop(void)
-{
-       omap_32k_timer_write(0x0, OMAP_32K_TIMER_CR);
-}
-
-/*
- * Rounds down to nearest usec
- */
-static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
-{
-       return (ticks_32k * 5*5*5*5*5*5) >> 9;
-}
-
-static unsigned long omap_32k_last_tick = 0;
-
-/*
- * Returns elapsed usecs since last 32k timer interrupt
- */
-static unsigned long omap_32k_timer_gettimeoffset(void)
-{
-       unsigned long now = omap_32k_sync_timer_read();
-       return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
-}
-
-/*
- * Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
- * function is also called from other interrupts to remove latency
- * issues with dynamic tick. In the dynamic tick case, we need to lock
- * with irqsave.
- */
-static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
-                                           struct pt_regs *regs)
-{
-       unsigned long flags;
-       unsigned long now;
-
-       write_seqlock_irqsave(&xtime_lock, flags);
-       now = omap_32k_sync_timer_read();
-
-       while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) {
-               omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
-               timer_tick(regs);
-       }
-
-       /* Restart timer so we don't drift off due to modulo or dynamic tick.
-        * By default we program the next timer to be continuous to avoid
-        * latencies during high system load. During dynamic tick operation the
-        * continuous timer can be overridden from pm_idle to be longer.
-        */
-       omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
-       write_sequnlock_irqrestore(&xtime_lock, flags);
-
-       return IRQ_HANDLED;
-}
-
-#ifdef CONFIG_NO_IDLE_HZ
-/*
- * Programs the next timer interrupt needed. Called when dynamic tick is
- * enabled, and to reprogram the ticks to skip from pm_idle. Note that
- * we can keep the timer continuous, and don't need to set it to run in
- * one-shot mode. This is because the timer will get reprogrammed again
- * after next interrupt.
- */
-void omap_32k_timer_reprogram(unsigned long next_tick)
-{
-       omap_32k_timer_start(JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1);
-}
-
-static struct irqaction omap_32k_timer_irq;
-extern struct timer_update_handler timer_update;
-
-static int omap_32k_timer_enable_dyn_tick(void)
-{
-       /* No need to reprogram timer, just use the next interrupt */
-       return 0;
-}
-
-static int omap_32k_timer_disable_dyn_tick(void)
-{
-       omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
-       return 0;
-}
-
-static struct dyn_tick_timer omap_dyn_tick_timer = {
-       .enable         = omap_32k_timer_enable_dyn_tick,
-       .disable        = omap_32k_timer_disable_dyn_tick,
-       .reprogram      = omap_32k_timer_reprogram,
-       .handler        = omap_32k_timer_interrupt,
-};
-#endif /* CONFIG_NO_IDLE_HZ */
-
-static struct irqaction omap_32k_timer_irq = {
-       .name           = "32KHz timer",
-       .flags          = SA_INTERRUPT | SA_TIMER,
-       .handler        = omap_32k_timer_interrupt,
-};
-
-static __init void omap_init_32k_timer(void)
-{
-
-#ifdef CONFIG_NO_IDLE_HZ
-       omap_timer.dyn_tick = &omap_dyn_tick_timer;
-#endif
-
-       setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
-       omap_timer.offset  = omap_32k_timer_gettimeoffset;
-       omap_32k_last_tick = omap_32k_sync_timer_read();
-       omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
-}
-#endif /* CONFIG_OMAP_32K_TIMER */
-
-/*
- * ---------------------------------------------------------------------------
- * Timer initialization
- * ---------------------------------------------------------------------------
- */
-void __init omap_timer_init(void)
-{
-#if defined(CONFIG_OMAP_MPU_TIMER)
-       omap_init_mpu_timer();
-#elif defined(CONFIG_OMAP_32K_TIMER)
-       omap_init_32k_timer();
-#else
-#error No system timer selected in Kconfig!
-#endif
-}
-
-struct sys_timer omap_timer = {
-       .init           = omap_timer_init,
-       .offset         = NULL,         /* Initialized later */
-};
diff -urN linux/arch/arm/mach-omap/usb.c linux/arch/arm/mach-omap/usb.c
--- linux/arch/arm/mach-omap/Attic/usb.c        2005-07-13 12:48:52.480259000 
+0100     1.5
+++ linux/arch/arm/mach-omap/Attic/usb.c        1970/01/01 00:00:00+0100
@@ -1,593 +0,0 @@
-/*
- * arch/arm/mach-omap/usb.c -- platform level USB initialization
- *
- * Copyright (C) 2004 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#undef DEBUG
-
-#include <linux/config.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/usb_otg.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/system.h>
-#include <asm/hardware.h>
-#include <asm/mach-types.h>
-
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/board.h>
-
-/* These routines should handle the standard chip-specific modes
- * for usb0/1/2 ports, covering basic mux and transceiver setup.
- *
- * Some board-*.c files will need to set up additional mux options,
- * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup.
- */
-
-/* TESTED ON:
- *  - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables
- *  - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables
- *  - 5912 OSK UDC, with *nonstandard* A-to-A cable
- *  - 1510 Innovator UDC with bundled usb0 cable
- *  - 1510 Innovator OHCI with bundled usb1/usb2 cable
- *  - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS
- *  - 1710 custom development board using alternate pin group
- *  - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables
- */
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef CONFIG_ARCH_OMAP_OTG
-
-static struct otg_transceiver *xceiv;
-
-/**
- * otg_get_transceiver - find the (single) OTG transceiver driver
- *
- * Returns the transceiver driver, after getting a refcount to it; or
- * null if there is no such transceiver.  The caller is responsible for
- * releasing that count.
- */
-struct otg_transceiver *otg_get_transceiver(void)
-{
-       if (xceiv)
-               get_device(xceiv->dev);
-       return xceiv;
-}
-EXPORT_SYMBOL(otg_get_transceiver);
-
-int otg_set_transceiver(struct otg_transceiver *x)
-{
-       if (xceiv && x)
-               return -EBUSY;
-       xceiv = x;
-       return 0;
-}
-EXPORT_SYMBOL(otg_set_transceiver);
-
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
-{
-       u32     syscon1 = 0;
-
-       if (nwires == 0) {
-               if (!cpu_is_omap15xx()) {
-                       /* pulldown D+/D- */
-                       USB_TRANSCEIVER_CTRL_REG &= ~(3 << 1);
-               }
-               return 0;
-       }
-
-       if (is_device)
-               omap_cfg_reg(W4_USB_PUEN);
-
-       /* internal transceiver */
-       if (nwires == 2) {
-               // omap_cfg_reg(P9_USB_DP);
-               // omap_cfg_reg(R8_USB_DM);
-
-               if (cpu_is_omap15xx()) {
-                       /* This works on 1510-Innovator */
-                       return 0;
-               }
-
-               /* NOTES:
-                *  - peripheral should configure VBUS detection!
-                *  - only peripherals may use the internal D+/D- pulldowns
-                *  - OTG support on this port not yet written
-                */
-
-               USB_TRANSCEIVER_CTRL_REG &= ~(7 << 4);
-               if (!is_device)
-                       USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
-
-               return 3 << 16;
-       }
-
-       /* alternate pin config, external transceiver */
-       if (cpu_is_omap15xx()) {
-               printk(KERN_ERR "no usb0 alt pin config on 15xx\n");
-               return 0;
-       }
-
-       omap_cfg_reg(V6_USB0_TXD);
-       omap_cfg_reg(W9_USB0_TXEN);
-       omap_cfg_reg(W5_USB0_SE0);
-
-       /* NOTE:  SPEED and SUSP aren't configured here */
-
-       if (nwires != 3)
-               omap_cfg_reg(Y5_USB0_RCV);
-       if (nwires != 6)
-               USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
-
-       switch (nwires) {
-       case 3:
-               syscon1 = 2;
-               break;
-       case 4:
-               syscon1 = 1;
-               break;
-       case 6:
-               syscon1 = 3;
-               omap_cfg_reg(AA9_USB0_VP);
-               omap_cfg_reg(R9_USB0_VM);
-               USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
-               break;
-       default:
-               printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-                       0, nwires);
-       }
-       return syscon1 << 16;
-}
-
-static u32 __init omap_usb1_init(unsigned nwires)
-{
-       u32     syscon1 = 0;
-
-       if (nwires != 6 && !cpu_is_omap15xx())
-               USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R;
-       if (nwires == 0)
-               return 0;
-
-       /* external transceiver */
-       omap_cfg_reg(USB1_TXD);
-       omap_cfg_reg(USB1_TXEN);
-       if (cpu_is_omap15xx()) {
-               omap_cfg_reg(USB1_SEO);
-               omap_cfg_reg(USB1_SPEED);
-               // SUSP
-       } else if (cpu_is_omap1610() || cpu_is_omap5912()) {
-               omap_cfg_reg(W13_1610_USB1_SE0);
-               omap_cfg_reg(R13_1610_USB1_SPEED);
-               // SUSP
-       } else if (cpu_is_omap1710()) {
-               omap_cfg_reg(R13_1710_USB1_SE0);
-               // SUSP
-       } else {
-               pr_debug("usb unrecognized\n");
-       }
-       if (nwires != 3)
-               omap_cfg_reg(USB1_RCV);
-
-       switch (nwires) {
-       case 3:
-               syscon1 = 2;
-               break;
-       case 4:
-               syscon1 = 1;
-               break;
-       case 6:
-               syscon1 = 3;
-               omap_cfg_reg(USB1_VP);
-               omap_cfg_reg(USB1_VM);
-               if (!cpu_is_omap15xx())
-                       USB_TRANSCEIVER_CTRL_REG |= CONF_USB1_UNI_R;
-               break;
-       default:
-               printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-                       1, nwires);
-       }
-       return syscon1 << 20;
-}
-
-static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
-{
-       u32     syscon1 = 0;
-
-       /* NOTE erratum: must leave USB2_UNI_R set if usb0 in use */
-       if (alt_pingroup || nwires == 0)
-               return 0;
-       if (nwires != 6 && !cpu_is_omap15xx())
-               USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
-
-       /* external transceiver */
-       if (cpu_is_omap15xx()) {
-               omap_cfg_reg(USB2_TXD);
-               omap_cfg_reg(USB2_TXEN);
-               omap_cfg_reg(USB2_SEO);
-               if (nwires != 3)
-                       omap_cfg_reg(USB2_RCV);
-               /* there is no USB2_SPEED */
-       } else if (cpu_is_omap16xx()) {
-               omap_cfg_reg(V6_USB2_TXD);
-               omap_cfg_reg(W9_USB2_TXEN);
-               omap_cfg_reg(W5_USB2_SE0);
-               if (nwires != 3)
-                       omap_cfg_reg(Y5_USB2_RCV);
-               // FIXME omap_cfg_reg(USB2_SPEED);
-       } else {
-               pr_debug("usb unrecognized\n");
-       }
-       // omap_cfg_reg(USB2_SUSP);
-
-       switch (nwires) {
-       case 3:
-               syscon1 = 2;
-               break;
-       case 4:
-               syscon1 = 1;
-               break;
-       case 6:
-               syscon1 = 3;
-               if (cpu_is_omap15xx()) {
-                       omap_cfg_reg(USB2_VP);
-                       omap_cfg_reg(USB2_VM);
-               } else {
-                       omap_cfg_reg(AA9_USB2_VP);
-                       omap_cfg_reg(R9_USB2_VM);
-                       USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
-               }
-               break;
-       default:
-               printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-                       2, nwires);
-       }
-       return syscon1 << 24;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#if    defined(CONFIG_USB_GADGET_OMAP) || \
-       defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) || \
-       (defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG))
-static void usb_release(struct device *dev)
-{
-       /* normally not freed */
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET_OMAP
-
-static struct resource udc_resources[] = {
-       /* order is significant! */
-       {               /* registers */
-               .start          = UDC_BASE,
-               .end            = UDC_BASE + 0xff,
-               .flags          = IORESOURCE_MEM,
-       }, {            /* general IRQ */
-               .start          = IH2_BASE + 20,
-               .flags          = IORESOURCE_IRQ,
-       }, {            /* PIO IRQ */
-               .start          = IH2_BASE + 30,
-               .flags          = IORESOURCE_IRQ,
-       }, {            /* SOF IRQ */
-               .start          = IH2_BASE + 29,
-               .flags          = IORESOURCE_IRQ,
-       },
-};
-
-static u64 udc_dmamask = ~(u32)0;
-
-static struct platform_device udc_device = {
-       .name           = "omap_udc",
-       .id             = -1,
-       .dev = {
-               .release                = usb_release,
-               .dma_mask               = &udc_dmamask,
-               .coherent_dma_mask      = 0xffffffff,
-       },
-       .num_resources  = ARRAY_SIZE(udc_resources),
-       .resource       = udc_resources,
-};
-
-#endif
-
-#if    defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32)0;
-
-static struct resource ohci_resources[] = {
-       {
-               .start  = OMAP_OHCI_BASE,
-               .end    = OMAP_OHCI_BASE + 4096,
-               .flags  = IORESOURCE_MEM,
-       },
-       {
-               .start  = INT_USB_HHC_1,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device ohci_device = {
-       .name                   = "ohci",
-       .id                     = -1,
-       .dev = {
-               .release                = usb_release,
-               .dma_mask               = &ohci_dmamask,
-               .coherent_dma_mask      = 0xffffffff,
-       },
-       .num_resources  = ARRAY_SIZE(ohci_resources),
-       .resource               = ohci_resources,
-};
-
-#endif
-
-#if    defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
-
-static struct resource otg_resources[] = {
-       /* order is significant! */
-       {
-               .start          = OTG_BASE,
-               .end            = OTG_BASE + 0xff,
-               .flags          = IORESOURCE_MEM,
-       }, {
-               .start          = IH2_BASE + 8,
-               .flags          = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device otg_device = {
-       .name           = "omap_otg",
-       .id             = -1,
-       .dev = {
-               .release                = usb_release,
-       },
-       .num_resources  = ARRAY_SIZE(otg_resources),
-       .resource       = otg_resources,
-};
-
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-#define ULPD_CLOCK_CTRL_REG    __REG16(ULPD_CLOCK_CTRL)
-#define ULPD_SOFT_REQ_REG      __REG16(ULPD_SOFT_REQ)
-
-
-// FIXME correct answer depends on hmc_mode,
-// as does any nonzero value for config->otg port number
-#ifdef CONFIG_USB_GADGET_OMAP
-#define        is_usb0_device(config)  1
-#else
-#define        is_usb0_device(config)  0
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef CONFIG_ARCH_OMAP_OTG
-
-void __init
-omap_otg_init(struct omap_usb_config *config)
-{
-       u32             syscon = OTG_SYSCON_1_REG & 0xffff;
-       int             status;
-       int             alt_pingroup = 0;
-
-       /* NOTE:  no bus or clock setup (yet?) */
-
-       syscon = OTG_SYSCON_1_REG & 0xffff;
-       if (!(syscon & OTG_RESET_DONE))
-               pr_debug("USB resets not complete?\n");
-
-       // OTG_IRQ_EN_REG = 0;
-
-       /* pin muxing and transceiver pinouts */
-       if (config->pins[0] > 2)        /* alt pingroup 2 */
-               alt_pingroup = 1;
-       syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config));
-       syscon |= omap_usb1_init(config->pins[1]);
-       syscon |= omap_usb2_init(config->pins[2], alt_pingroup);
-       pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
-       OTG_SYSCON_1_REG = syscon;
-
-       syscon = config->hmc_mode;
-       syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
-#ifdef CONFIG_USB_OTG
-       if (config->otg)
-               syscon |= OTG_EN;
-#endif
-       pr_debug("USB_TRANSCEIVER_CTRL_REG = %03x\n", USB_TRANSCEIVER_CTRL_REG);
-       pr_debug("OTG_SYSCON_2_REG = %08x\n", syscon);
-       OTG_SYSCON_2_REG = syscon;
-
-       printk("USB: hmc %d", config->hmc_mode);
-       if (alt_pingroup)
-               printk(", usb2 alt %d wires", config->pins[2]);
-       else if (config->pins[0])
-               printk(", usb0 %d wires%s", config->pins[0],
-                       is_usb0_device(config) ? " (dev)" : "");
-       if (config->pins[1])
-               printk(", usb1 %d wires", config->pins[1]);
-       if (!alt_pingroup && config->pins[2])
-               printk(", usb2 %d wires", config->pins[2]);
-       if (config->otg)
-               printk(", Mini-AB on usb%d", config->otg - 1);
-       printk("\n");
-
-       /* leave USB clocks/controllers off until needed */
-       ULPD_SOFT_REQ_REG &= ~SOFT_USB_CLK_REQ;
-       ULPD_CLOCK_CTRL_REG &= ~USB_MCLK_EN;
-       ULPD_CLOCK_CTRL_REG |= DIS_USB_PVCI_CLK;
-       syscon = OTG_SYSCON_1_REG;
-       syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
-
-#ifdef CONFIG_USB_GADGET_OMAP
-       if (config->otg || config->register_dev) {
-               syscon &= ~DEV_IDLE_EN;
-               udc_device.dev.platform_data = config;
-               /* FIXME patch IRQ numbers for omap730 */
-               status = platform_device_register(&udc_device);
-               if (status)
-                       pr_debug("can't register UDC device, %d\n", status);
-       }
-#endif
-
-#if    defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-       if (config->otg || config->register_host) {
-               syscon &= ~HST_IDLE_EN;
-               ohci_device.dev.platform_data = config;
-               if (cpu_is_omap730())
-                       ohci_resources[1].start = INT_730_USB_HHC_1;
-               status = platform_device_register(&ohci_device);
-               if (status)
-                       pr_debug("can't register OHCI device, %d\n", status);
-       }
-#endif
-
-#ifdef CONFIG_USB_OTG
-       if (config->otg) {
-               syscon &= ~OTG_IDLE_EN;
-               otg_device.dev.platform_data = config;
-               if (cpu_is_omap730())
-                       otg_resources[1].start = INT_730_USB_OTG;
-               status = platform_device_register(&otg_device);
-               if (status)
-                       pr_debug("can't register OTG device, %d\n", status);
-       }
-#endif
-       pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
-       OTG_SYSCON_1_REG = syscon;
-
-       status = 0;
-}
-
-#else
-static inline void omap_otg_init(struct omap_usb_config *config) {}
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef CONFIG_ARCH_OMAP1510
-
-#define ULPD_DPLL_CTRL_REG     __REG16(ULPD_DPLL_CTRL)
-#define DPLL_IOB               (1 << 13)
-#define DPLL_PLL_ENABLE                (1 << 4)
-#define DPLL_LOCK              (1 << 0)
-
-#define ULPD_APLL_CTRL_REG     __REG16(ULPD_APLL_CTRL)
-#define APLL_NDPLL_SWITCH      (1 << 0)
-
-
-static void __init omap_1510_usb_init(struct omap_usb_config *config)
-{
-       int status;
-       unsigned int val;
-
-       omap_usb0_init(config->pins[0], is_usb0_device(config));
-       omap_usb1_init(config->pins[1]);
-       omap_usb2_init(config->pins[2], 0);
-
-       val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
-       val |= (config->hmc_mode << 1);
-       omap_writel(val, MOD_CONF_CTRL_0);
-
-       printk("USB: hmc %d", config->hmc_mode);
-       if (config->pins[0])
-               printk(", usb0 %d wires%s", config->pins[0],
-                       is_usb0_device(config) ? " (dev)" : "");
-       if (config->pins[1])
-               printk(", usb1 %d wires", config->pins[1]);
-       if (config->pins[2])
-               printk(", usb2 %d wires", config->pins[2]);
-       printk("\n");
-
-       /* use DPLL for 48 MHz function clock */
-       pr_debug("APLL %04x DPLL %04x REQ %04x\n", ULPD_APLL_CTRL_REG,
-                       ULPD_DPLL_CTRL_REG, ULPD_SOFT_REQ_REG);
-       ULPD_APLL_CTRL_REG &= ~APLL_NDPLL_SWITCH;
-       ULPD_DPLL_CTRL_REG |= DPLL_IOB | DPLL_PLL_ENABLE;
-       ULPD_SOFT_REQ_REG |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
-       while (!(ULPD_DPLL_CTRL_REG & DPLL_LOCK))
-               cpu_relax();
-
-#ifdef CONFIG_USB_GADGET_OMAP
-       if (config->register_dev) {
-               udc_device.dev.platform_data = config;
-               status = platform_device_register(&udc_device);
-               if (status)
-                       pr_debug("can't register UDC device, %d\n", status);
-               /* udc driver gates 48MHz by D+ pullup */
-       }
-#endif
-
-#if    defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-       if (config->register_host) {
-               ohci_device.dev.platform_data = config;
-               status = platform_device_register(&ohci_device);
-               if (status)
-                       pr_debug("can't register OHCI device, %d\n", status);
-               /* hcd explicitly gates 48MHz */
-       }
-#endif
-}
-
-#else
-static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-static struct omap_usb_config platform_data;
-
-static int __init
-omap_usb_init(void)
-{
-       const struct omap_usb_config *config;
-
-       config = omap_get_config(OMAP_TAG_USB, struct omap_usb_config);
-       if (config == NULL) {
-               printk(KERN_ERR "USB: No board-specific "
-                               "platform config found\n");
-               return -ENODEV;
-       }
-       platform_data = *config;
-
-       if (cpu_is_omap730() || cpu_is_omap16xx())
-               omap_otg_init(&platform_data);
-       else if (cpu_is_omap15xx())
-               omap_1510_usb_init(&platform_data);
-       else {
-               printk(KERN_ERR "USB: No init for your chip yet\n");
-               return -ENODEV;
-       }
-       return 0;
-}
-
-subsys_initcall(omap_usb_init);
diff -urN linux/arch/arm/mach-omap1/Kconfig linux/arch/arm/mach-omap1/Kconfig
--- linux/arch/arm/mach-omap1/Kconfig   1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/Kconfig   2005-07-13 12:48:52.782915000 +0100     
1.1
@@ -0,0 +1,144 @@
+comment "OMAP Core Type"
+       depends on ARCH_OMAP1
+
+config ARCH_OMAP730
+       depends on ARCH_OMAP1
+       bool "OMAP730 Based System"
+       select ARCH_OMAP_OTG
+
+config ARCH_OMAP1510
+       depends on ARCH_OMAP1
+       default y
+       bool "OMAP1510 Based System"
+
+config ARCH_OMAP16XX
+       depends on ARCH_OMAP1
+       bool "OMAP16xx Based System"
+       select ARCH_OMAP_OTG
+
+comment "OMAP Board Type"
+       depends on ARCH_OMAP1
+
+config MACH_OMAP_INNOVATOR
+       bool "TI Innovator"
+       depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX)
+       help
+          TI OMAP 1510 or 1610 Innovator board support. Say Y here if you
+          have such a board.
+
+config MACH_OMAP_H2
+       bool "TI H2 Support"
+       depends on ARCH_OMAP1 && ARCH_OMAP16XX
+       help
+         TI OMAP 1610/1611B H2 board support. Say Y here if you have such
+         a board.
+
+config MACH_OMAP_H3
+       bool "TI H3 Support"
+       depends on ARCH_OMAP1 && ARCH_OMAP16XX
+       help
+         TI OMAP 1710 H3 board support. Say Y here if you have such
+         a board.
+
+config MACH_OMAP_OSK
+       bool "TI OSK Support"
+       depends on ARCH_OMAP1 && ARCH_OMAP16XX
+       help
+         TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here
+          if you have such a board.
+
+config MACH_OMAP_PERSEUS2
+       bool "TI Perseus2"
+       depends on ARCH_OMAP1 && ARCH_OMAP730
+       help
+         Support for TI OMAP 730 Perseus2 board. Say Y here if you have such
+         a board.
+
+config MACH_VOICEBLUE
+       bool "Voiceblue"
+       depends on ARCH_OMAP1 && ARCH_OMAP1510
+       help
+         Support for Voiceblue GSM/VoIP gateway. Say Y here if you have
+         such a board.
+
+config MACH_NETSTAR
+       bool "NetStar"
+       depends on ARCH_OMAP1 && ARCH_OMAP1510
+       help
+         Support for NetStar PBX. Say Y here if you have such a board.
+
+config MACH_OMAP_GENERIC
+       bool "Generic OMAP board"
+       depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX)
+       help
+          Support for generic OMAP-1510, 1610 or 1710 board with
+          no FPGA. Can be used as template for porting Linux to
+          custom OMAP boards. Say Y here if you have a custom
+          board.
+
+comment "OMAP CPU Speed"
+       depends on ARCH_OMAP1
+
+config OMAP_CLOCKS_SET_BY_BOOTLOADER
+       bool "OMAP clocks set by bootloader"
+       depends on ARCH_OMAP1
+       help
+         Enable this option to prevent the kernel from overriding the clock
+         frequencies programmed by bootloader for MPU, DSP, MMUs, TC,
+         internal LCD controller and MPU peripherals.
+
+config OMAP_ARM_216MHZ
+       bool "OMAP ARM 216 MHz CPU (1710 only)"
+        depends on ARCH_OMAP1 && ARCH_OMAP16XX
+        help
+          Enable 216 MHz clock for OMAP1710 CPU. If unsure, say N.
+
+config OMAP_ARM_195MHZ
+       bool "OMAP ARM 195 MHz CPU"
+       depends on ARCH_OMAP1 && ARCH_OMAP730
+       help
+          Enable 195MHz clock for OMAP CPU. If unsure, say N.
+
+config OMAP_ARM_192MHZ
+       bool "OMAP ARM 192 MHz CPU"
+       depends on ARCH_OMAP1 && ARCH_OMAP16XX
+       help
+          Enable 192MHz clock for OMAP CPU. If unsure, say N.
+
+config OMAP_ARM_182MHZ
+       bool "OMAP ARM 182 MHz CPU"
+       depends on ARCH_OMAP1 && ARCH_OMAP730
+       help
+          Enable 182MHz clock for OMAP CPU. If unsure, say N.
+
+config OMAP_ARM_168MHZ
+       bool "OMAP ARM 168 MHz CPU"
+       depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX || 
ARCH_OMAP730)
+       help
+          Enable 168MHz clock for OMAP CPU. If unsure, say N.
+
+config OMAP_ARM_150MHZ
+       bool "OMAP ARM 150 MHz CPU"
+       depends on ARCH_OMAP1 && ARCH_OMAP1510
+       help
+         Enable 150MHz clock for OMAP CPU. If unsure, say N.
+
+config OMAP_ARM_120MHZ
+       bool "OMAP ARM 120 MHz CPU"
+       depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX || 
ARCH_OMAP730)
+       help
+          Enable 120MHz clock for OMAP CPU. If unsure, say N.
+
+config OMAP_ARM_60MHZ
+       bool "OMAP ARM 60 MHz CPU"
+       depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX || 
ARCH_OMAP730)
+        default y
+       help
+          Enable 60MHz clock for OMAP CPU. If unsure, say Y.
+
+config OMAP_ARM_30MHZ
+       bool "OMAP ARM 30 MHz CPU"
+       depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX || 
ARCH_OMAP730)
+       help
+          Enable 30MHz clock for OMAP CPU. If unsure, say N.
+
diff -urN linux/arch/arm/mach-omap1/Makefile linux/arch/arm/mach-omap1/Makefile
--- linux/arch/arm/mach-omap1/Makefile  1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/Makefile  2005-07-13 12:48:52.808046000 +0100     
1.1
@@ -0,0 +1,30 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common support
+obj-y := io.o id.o irq.o time.o serial.o
+led-y := leds.o
+
+# Specific board support
+obj-$(CONFIG_MACH_OMAP_H2)             += board-h2.o
+obj-$(CONFIG_MACH_OMAP_INNOVATOR)      += board-innovator.o
+obj-$(CONFIG_MACH_OMAP_GENERIC)                += board-generic.o
+obj-$(CONFIG_MACH_OMAP_PERSEUS2)       += board-perseus2.o
+obj-$(CONFIG_MACH_OMAP_OSK)            += board-osk.o
+obj-$(CONFIG_MACH_OMAP_H3)             += board-h3.o
+obj-$(CONFIG_MACH_VOICEBLUE)           += board-voiceblue.o
+obj-$(CONFIG_MACH_NETSTAR)             += board-netstar.o
+
+ifeq ($(CONFIG_ARCH_OMAP1510),y)
+# Innovator-1510 FPGA
+obj-$(CONFIG_MACH_OMAP_INNOVATOR)      += fpga.o
+endif
+
+# LEDs support
+led-$(CONFIG_MACH_OMAP_H2)             += leds-h2p2-debug.o
+led-$(CONFIG_MACH_OMAP_INNOVATOR)      += leds-innovator.o
+led-$(CONFIG_MACH_OMAP_PERSEUS2)       += leds-h2p2-debug.o
+led-$(CONFIG_MACH_OMAP_OSK)            += leds-osk.o
+obj-$(CONFIG_LEDS)                     += $(led-y)
+
diff -urN linux/arch/arm/mach-omap1/Makefile.boot 
linux/arch/arm/mach-omap1/Makefile.boot
--- linux/arch/arm/mach-omap1/Makefile.boot     1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/Makefile.boot     2005-07-13 12:48:52.832466000 
+0100     1.1
@@ -0,0 +1,3 @@
+   zreladdr-y          := 0x10008000
+params_phys-y          := 0x10000100
+initrd_phys-y          := 0x10800000
diff -urN linux/arch/arm/mach-omap1/board-generic.c 
linux/arch/arm/mach-omap1/board-generic.c
--- linux/arch/arm/mach-omap1/board-generic.c   1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/board-generic.c   2005-07-13 12:48:52.856077000 
+0100     1.1
@@ -0,0 +1,99 @@
+/*
+ * linux/arch/arm/mach-omap1/board-generic.c
+ *
+ * Modified from board-innovator1510.c
+ *
+ * Code for generic OMAP board. Should work on many OMAP systems where
+ * the device drivers take care of all the necessary hardware initialization.
+ * Do not put any board specific code to this file; create a new machine
+ * type if you need custom low-level initializations.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/usb.h>
+#include <asm/arch/board.h>
+#include <asm/arch/common.h>
+
+static int __initdata generic_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
+
+static void __init omap_generic_init_irq(void)
+{
+       omap_init_irq();
+}
+
+/* assume no Mini-AB port */
+
+#ifdef CONFIG_ARCH_OMAP1510
+static struct omap_usb_config generic1510_usb_config __initdata = {
+       .register_host  = 1,
+       .register_dev   = 1,
+       .hmc_mode       = 16,
+       .pins[0]        = 3,
+};
+#endif
+
+#if defined(CONFIG_ARCH_OMAP16XX)
+static struct omap_usb_config generic1610_usb_config __initdata = {
+       .register_host  = 1,
+       .register_dev   = 1,
+       .hmc_mode       = 16,
+       .pins[0]        = 6,
+};
+#endif
+
+static struct omap_board_config_kernel generic_config[] = {
+       { OMAP_TAG_USB,           NULL },
+};
+
+static void __init omap_generic_init(void)
+{
+       /*
+        * Make sure the serial ports are muxed on at this point.
+        * You have to mux them off in device drivers later on
+        * if not needed.
+        */
+#ifdef CONFIG_ARCH_OMAP1510
+       if (cpu_is_omap1510()) {
+               generic_config[0].data = &generic1510_usb_config;
+       }
+#endif
+#if defined(CONFIG_ARCH_OMAP16XX)
+       if (!cpu_is_omap1510()) {
+               generic_config[0].data = &generic1610_usb_config;
+       }
+#endif
+       omap_board_config = generic_config;
+       omap_board_config_size = ARRAY_SIZE(generic_config);
+       omap_serial_init(generic_serial_ports);
+}
+
+static void __init omap_generic_map_io(void)
+{
+       omap_map_common_io()
+}
+
+MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
+       /* Maintainer: Tony Lindgren <tony@atomide.com> */
+       .phys_ram       = 0x10000000,
+       .phys_io        = 0xfff00000,
+       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
+       .boot_params    = 0x10000100,
+       .map_io         = omap_generic_map_io,
+       .init_irq       = omap_generic_init_irq,
+       .init_machine   = omap_generic_init,
+       .timer          = &omap_timer,
+MACHINE_END
diff -urN linux/arch/arm/mach-omap1/board-h2.c 
linux/arch/arm/mach-omap1/board-h2.c
--- linux/arch/arm/mach-omap1/board-h2.c        1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/board-h2.c        2005-07-13 12:48:52.889968000 
+0100     1.1
@@ -0,0 +1,188 @@
+/*
+ * linux/arch/arm/mach-omap1/board-h2.c
+ *
+ * Board specific inits for OMAP-1610 H2
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
+ *
+ * H2 specific changes and cleanup
+ * Copyright (C) 2004 Nokia Corporation by Imre Deak <imre.deak@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/tc.h>
+#include <asm/arch/usb.h>
+#include <asm/arch/common.h>
+
+extern int omap_gpio_init(void);
+
+static int __initdata h2_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
+
+static struct mtd_partition h2_partitions[] = {
+       /* bootloader (U-Boot, etc) in first sector */
+       {
+             .name             = "bootloader",
+             .offset           = 0,
+             .size             = SZ_128K,
+             .mask_flags       = MTD_WRITEABLE, /* force read-only */
+       },
+       /* bootloader params in the next sector */
+       {
+             .name             = "params",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = SZ_128K,
+             .mask_flags       = 0,
+       },
+       /* kernel */
+       {
+             .name             = "kernel",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = SZ_2M,
+             .mask_flags       = 0
+       },
+       /* file system */
+       {
+             .name             = "filesystem",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = MTDPART_SIZ_FULL,
+             .mask_flags       = 0
+       }
+};
+
+static struct flash_platform_data h2_flash_data = {
+       .map_name       = "cfi_probe",
+       .width          = 2,
+       .parts          = h2_partitions,
+       .nr_parts       = ARRAY_SIZE(h2_partitions),
+};
+
+static struct resource h2_flash_resource = {
+       .start          = OMAP_CS2B_PHYS,
+       .end            = OMAP_CS2B_PHYS + OMAP_CS2B_SIZE - 1,
+       .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device h2_flash_device = {
+       .name           = "omapflash",
+       .id             = 0,
+       .dev            = {
+               .platform_data  = &h2_flash_data,
+       },
+       .num_resources  = 1,
+       .resource       = &h2_flash_resource,
+};
+
+static struct resource h2_smc91x_resources[] = {
+       [0] = {
+               .start  = OMAP1610_ETHR_START,          /* Physical */
+               .end    = OMAP1610_ETHR_START + 0xf,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = OMAP_GPIO_IRQ(0),
+               .end    = OMAP_GPIO_IRQ(0),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device h2_smc91x_device = {
+       .name           = "smc91x",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(h2_smc91x_resources),
+       .resource       = h2_smc91x_resources,
+};
+
+static struct platform_device *h2_devices[] __initdata = {
+       &h2_flash_device,
+       &h2_smc91x_device,
+};
+
+static void __init h2_init_smc91x(void)
+{
+       if ((omap_request_gpio(0)) < 0) {
+               printk("Error requesting gpio 0 for smc91x irq\n");
+               return;
+       }
+       omap_set_gpio_edge_ctrl(0, OMAP_GPIO_FALLING_EDGE);
+}
+
+void h2_init_irq(void)
+{
+       omap_init_irq();
+       omap_gpio_init();
+       h2_init_smc91x();
+}
+
+static struct omap_usb_config h2_usb_config __initdata = {
+       /* usb1 has a Mini-AB port and external isp1301 transceiver */
+       .otg            = 2,
+
+#ifdef CONFIG_USB_GADGET_OMAP
+       .hmc_mode       = 19,   // 0:host(off) 1:dev|otg 2:disabled
+       // .hmc_mode    = 21,   // 0:host(off) 1:dev(loopback) 2:host(loopback)
+#elif  defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+       /* needs OTG cable, or NONSTANDARD (B-to-MiniB) */
+       .hmc_mode       = 20,   // 1:dev|otg(off) 1:host 2:disabled
+#endif
+
+       .pins[1]        = 3,
+};
+
+static struct omap_mmc_config h2_mmc_config __initdata = {
+       .mmc_blocks             = 1,
+       .mmc1_power_pin         = -1,   /* tps65010 gpio3 */
+       .mmc1_switch_pin        = OMAP_MPUIO(1),
+};
+
+static struct omap_board_config_kernel h2_config[] = {
+       { OMAP_TAG_USB,           &h2_usb_config },
+       { OMAP_TAG_MMC,           &h2_mmc_config },
+};
+
+static void __init h2_init(void)
+{
+       platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
+       omap_board_config = h2_config;
+       omap_board_config_size = ARRAY_SIZE(h2_config);
+}
+
+static void __init h2_map_io(void)
+{
+       omap_map_common_io();
+       omap_serial_init(h2_serial_ports);
+}
+
+MACHINE_START(OMAP_H2, "TI-H2")
+       /* Maintainer: Imre Deak <imre.deak@nokia.com> */
+       .phys_ram       = 0x10000000,
+       .phys_io        = 0xfff00000,
+       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
+       .boot_params    = 0x10000100,
+       .map_io         = h2_map_io,
+       .init_irq       = h2_init_irq,
+       .init_machine   = h2_init,
+       .timer          = &omap_timer,
+MACHINE_END
diff -urN linux/arch/arm/mach-omap1/board-h3.c 
linux/arch/arm/mach-omap1/board-h3.c
--- linux/arch/arm/mach-omap1/board-h3.c        1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/board-h3.c        2005-07-13 12:48:53.215582000 
+0100     1.1
@@ -0,0 +1,206 @@
+/*
+ * linux/arch/arm/mach-omap1/board-h3.c
+ *
+ * This file contains OMAP1710 H3 specific code.
+ *
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/major.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/tc.h>
+#include <asm/arch/usb.h>
+#include <asm/arch/common.h>
+
+extern int omap_gpio_init(void);
+
+static int __initdata h3_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
+
+static struct mtd_partition h3_partitions[] = {
+       /* bootloader (U-Boot, etc) in first sector */
+       {
+             .name             = "bootloader",
+             .offset           = 0,
+             .size             = SZ_128K,
+             .mask_flags       = MTD_WRITEABLE, /* force read-only */
+       },
+       /* bootloader params in the next sector */
+       {
+             .name             = "params",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = SZ_128K,
+             .mask_flags       = 0,
+       },
+       /* kernel */
+       {
+             .name             = "kernel",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = SZ_2M,
+             .mask_flags       = 0
+       },
+       /* file system */
+       {
+             .name             = "filesystem",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = MTDPART_SIZ_FULL,
+             .mask_flags       = 0
+       }
+};
+
+static struct flash_platform_data h3_flash_data = {
+       .map_name       = "cfi_probe",
+       .width          = 2,
+       .parts          = h3_partitions,
+       .nr_parts       = ARRAY_SIZE(h3_partitions),
+};
+
+static struct resource h3_flash_resource = {
+       .start          = OMAP_CS2B_PHYS,
+       .end            = OMAP_CS2B_PHYS + OMAP_CS2B_SIZE - 1,
+       .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device flash_device = {
+       .name           = "omapflash",
+       .id             = 0,
+       .dev            = {
+               .platform_data  = &h3_flash_data,
+       },
+       .num_resources  = 1,
+       .resource       = &h3_flash_resource,
+};
+
+static struct resource smc91x_resources[] = {
+       [0] = {
+               .start  = OMAP1710_ETHR_START,          /* Physical */
+               .end    = OMAP1710_ETHR_START + 0xf,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = OMAP_GPIO_IRQ(40),
+               .end    = OMAP_GPIO_IRQ(40),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device smc91x_device = {
+       .name           = "smc91x",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(smc91x_resources),
+       .resource       = smc91x_resources,
+};
+
+#define GPTIMER_BASE           0xFFFB1400
+#define GPTIMER_REGS(x)        (0xFFFB1400 + (x * 0x800))
+#define GPTIMER_REGS_SIZE      0x46
+
+static struct resource intlat_resources[] = {
+       [0] = {
+               .start  = GPTIMER_REGS(0),            /* Physical */
+               .end    = GPTIMER_REGS(0) + GPTIMER_REGS_SIZE,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = INT_1610_GPTIMER1,
+               .end    = INT_1610_GPTIMER1,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device intlat_device = {
+       .name      = "omap_intlat",
+       .id          = 0,
+       .num_resources  = ARRAY_SIZE(intlat_resources),
+       .resource       = intlat_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+       &flash_device,
+        &smc91x_device,
+       &intlat_device,
+};
+
+static struct omap_usb_config h3_usb_config __initdata = {
+       /* usb1 has a Mini-AB port and external isp1301 transceiver */
+       .otg        = 2,
+
+#ifdef CONFIG_USB_GADGET_OMAP
+       .hmc_mode       = 19,   /* 0:host(off) 1:dev|otg 2:disabled */
+#elif  defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+       /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
+       .hmc_mode       = 20,   /* 1:dev|otg(off) 1:host 2:disabled */
+#endif
+
+       .pins[1]        = 3,
+};
+
+static struct omap_board_config_kernel h3_config[] = {
+       { OMAP_TAG_USB,  &h3_usb_config },
+};
+
+static void __init h3_init(void)
+{
+       (void) platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+static void __init h3_init_smc91x(void)
+{
+       omap_cfg_reg(W15_1710_GPIO40);
+       if (omap_request_gpio(40) < 0) {
+               printk("Error requesting gpio 40 for smc91x irq\n");
+               return;
+       }
+       omap_set_gpio_edge_ctrl(40, OMAP_GPIO_FALLING_EDGE);
+}
+
+void h3_init_irq(void)
+{
+       omap_init_irq();
+       omap_gpio_init();
+       h3_init_smc91x();
+}
+
+static void __init h3_map_io(void)
+{
+       omap_map_common_io();
+       omap_serial_init(h3_serial_ports);
+}
+
+MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
+       /* Maintainer: Texas Instruments, Inc. */
+       .phys_ram       = 0x10000000,
+       .phys_io        = 0xfff00000,
+       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
+       .boot_params    = 0x10000100,
+       .map_io         = h3_map_io,
+       .init_irq       = h3_init_irq,
+       .init_machine   = h3_init,
+       .timer          = &omap_timer,
+MACHINE_END
diff -urN linux/arch/arm/mach-omap1/board-innovator.c 
linux/arch/arm/mach-omap1/board-innovator.c
--- linux/arch/arm/mach-omap1/board-innovator.c 1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/board-innovator.c 2005-07-13 12:48:53.232618000 
+0100     1.1
@@ -0,0 +1,281 @@
+/*
+ * linux/arch/arm/mach-omap1/board-innovator.c
+ *
+ * Board specific inits for OMAP-1510 and OMAP-1610 Innovator
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/fpga.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/tc.h>
+#include <asm/arch/usb.h>
+#include <asm/arch/common.h>
+
+static int __initdata innovator_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
+
+static struct mtd_partition innovator_partitions[] = {
+       /* bootloader (U-Boot, etc) in first sector */
+       {
+             .name             = "bootloader",
+             .offset           = 0,
+             .size             = SZ_128K,
+             .mask_flags       = MTD_WRITEABLE, /* force read-only */
+       },
+       /* bootloader params in the next sector */
+       {
+             .name             = "params",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = SZ_128K,
+             .mask_flags       = 0,
+       },
+       /* kernel */
+       {
+             .name             = "kernel",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = SZ_2M,
+             .mask_flags       = 0
+       },
+       /* rest of flash1 is a file system */
+       {
+             .name             = "rootfs",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = SZ_16M - SZ_2M - 2 * SZ_128K,
+             .mask_flags       = 0
+       },
+       /* file system */
+       {
+             .name             = "filesystem",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = MTDPART_SIZ_FULL,
+             .mask_flags       = 0
+       }
+};
+
+static struct flash_platform_data innovator_flash_data = {
+       .map_name       = "cfi_probe",
+       .width          = 2,
+       .parts          = innovator_partitions,
+       .nr_parts       = ARRAY_SIZE(innovator_partitions),
+};
+
+static struct resource innovator_flash_resource = {
+       .start          = OMAP_CS0_PHYS,
+       .end            = OMAP_CS0_PHYS + SZ_32M - 1,
+       .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device innovator_flash_device = {
+       .name           = "omapflash",
+       .id             = 0,
+       .dev            = {
+               .platform_data  = &innovator_flash_data,
+       },
+       .num_resources  = 1,
+       .resource       = &innovator_flash_resource,
+};
+
+#ifdef CONFIG_ARCH_OMAP1510
+
+/* Only FPGA needs to be mapped here. All others are done with ioremap */
+static struct map_desc innovator1510_io_desc[] __initdata = {
+{ OMAP1510_FPGA_BASE, OMAP1510_FPGA_START, OMAP1510_FPGA_SIZE,
+       MT_DEVICE },
+};
+
+static struct resource innovator1510_smc91x_resources[] = {
+       [0] = {
+               .start  = OMAP1510_FPGA_ETHR_START,     /* Physical */
+               .end    = OMAP1510_FPGA_ETHR_START + 0xf,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = OMAP1510_INT_ETHER,
+               .end    = OMAP1510_INT_ETHER,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device innovator1510_smc91x_device = {
+       .name           = "smc91x",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(innovator1510_smc91x_resources),
+       .resource       = innovator1510_smc91x_resources,
+};
+
+static struct platform_device *innovator1510_devices[] __initdata = {
+       &innovator_flash_device,
+       &innovator1510_smc91x_device,
+};
+
+#endif /* CONFIG_ARCH_OMAP1510 */
+
+#ifdef CONFIG_ARCH_OMAP16XX
+
+static struct resource innovator1610_smc91x_resources[] = {
+       [0] = {
+               .start  = INNOVATOR1610_ETHR_START,             /* Physical */
+               .end    = INNOVATOR1610_ETHR_START + 0xf,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = OMAP_GPIO_IRQ(0),
+               .end    = OMAP_GPIO_IRQ(0),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device innovator1610_smc91x_device = {
+       .name           = "smc91x",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(innovator1610_smc91x_resources),
+       .resource       = innovator1610_smc91x_resources,
+};
+
+static struct platform_device *innovator1610_devices[] __initdata = {
+       &innovator_flash_device,
+       &innovator1610_smc91x_device,
+};
+
+#endif /* CONFIG_ARCH_OMAP16XX */
+
+static void __init innovator_init_smc91x(void)
+{
+       if (cpu_is_omap1510()) {
+               fpga_write(fpga_read(OMAP1510_FPGA_RST) & ~1,
+                          OMAP1510_FPGA_RST);
+               udelay(750);
+       } else {
+               if ((omap_request_gpio(0)) < 0) {
+                       printk("Error requesting gpio 0 for smc91x irq\n");
+                       return;
+               }
+               omap_set_gpio_edge_ctrl(0, OMAP_GPIO_RISING_EDGE);
+       }
+}
+
+void innovator_init_irq(void)
+{
+       omap_init_irq();
+       omap_gpio_init();
+#ifdef CONFIG_ARCH_OMAP1510
+       if (cpu_is_omap1510()) {
+               omap1510_fpga_init_irq();
+       }
+#endif
+       innovator_init_smc91x();
+}
+
+#ifdef CONFIG_ARCH_OMAP1510
+static struct omap_usb_config innovator1510_usb_config __initdata = {
+       /* for bundled non-standard host and peripheral cables */
+       .hmc_mode       = 4,
+
+       .register_host  = 1,
+       .pins[1]        = 6,
+       .pins[2]        = 6,            /* Conflicts with UART2 */
+
+       .register_dev   = 1,
+       .pins[0]        = 2,
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP16XX
+static struct omap_usb_config h2_usb_config __initdata = {
+       /* usb1 has a Mini-AB port and external isp1301 transceiver */
+       .otg            = 2,
+
+#ifdef CONFIG_USB_GADGET_OMAP
+       .hmc_mode       = 19,   // 0:host(off) 1:dev|otg 2:disabled
+       // .hmc_mode    = 21,   // 0:host(off) 1:dev(loopback) 2:host(loopback)
+#elif  defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+       /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
+       .hmc_mode       = 20,   // 1:dev|otg(off) 1:host 2:disabled
+#endif
+
+       .pins[1]        = 3,
+};
+#endif
+
+static struct omap_board_config_kernel innovator_config[] = {
+       { OMAP_TAG_USB,         NULL },
+};
+
+static void __init innovator_init(void)
+{
+#ifdef CONFIG_ARCH_OMAP1510
+       if (cpu_is_omap1510()) {
+               platform_add_devices(innovator1510_devices, 
ARRAY_SIZE(innovator1510_devices));
+       }
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+       if (!cpu_is_omap1510()) {
+               platform_add_devices(innovator1610_devices, 
ARRAY_SIZE(innovator1610_devices));
+       }
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1510
+       if (cpu_is_omap1510())
+               innovator_config[0].data = &innovator1510_usb_config;
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+       if (cpu_is_omap1610())
+               innovator_config[0].data = &h2_usb_config;
+#endif
+       omap_board_config = innovator_config;
+       omap_board_config_size = ARRAY_SIZE(innovator_config);
+}
+
+static void __init innovator_map_io(void)
+{
+       omap_map_common_io();
+
+#ifdef CONFIG_ARCH_OMAP1510
+       if (cpu_is_omap1510()) {
+               iotable_init(innovator1510_io_desc, 
ARRAY_SIZE(innovator1510_io_desc));
+               udelay(10);     /* Delay needed for FPGA */
+
+               /* Dump the Innovator FPGA rev early - useful info for support. 
*/
+               printk("Innovator FPGA Rev %d.%d Board Rev %d\n",
+                      fpga_read(OMAP1510_FPGA_REV_HIGH),
+                      fpga_read(OMAP1510_FPGA_REV_LOW),
+                      fpga_read(OMAP1510_FPGA_BOARD_REV));
+       }
+#endif
+       omap_serial_init(innovator_serial_ports);
+}
+
+MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
+       /* Maintainer: MontaVista Software, Inc. */
+       .phys_ram       = 0x10000000,
+       .phys_io        = 0xfff00000,
+       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
+       .boot_params    = 0x10000100,
+       .map_io         = innovator_map_io,
+       .init_irq       = innovator_init_irq,
+       .init_machine   = innovator_init,
+       .timer          = &omap_timer,
+MACHINE_END
diff -urN linux/arch/arm/mach-omap1/board-netstar.c 
linux/arch/arm/mach-omap1/board-netstar.c
--- linux/arch/arm/mach-omap1/board-netstar.c   1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/board-netstar.c   2005-07-13 12:48:53.251103000 
+0100     1.1
@@ -0,0 +1,152 @@
+/*
+ * Modified from board-generic.c
+ *
+ * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
+ *
+ * Code for Netstar OMAP board.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/usb.h>
+#include <asm/arch/common.h>
+
+extern void __init omap_init_time(void);
+extern int omap_gpio_init(void);
+
+static struct resource netstar_smc91x_resources[] = {
+       [0] = {
+               .start  = OMAP_CS1_PHYS + 0x300,
+               .end    = OMAP_CS1_PHYS + 0x300 + 16,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = OMAP_GPIO_IRQ(8),
+               .end    = OMAP_GPIO_IRQ(8),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device netstar_smc91x_device = {
+       .name           = "smc91x",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(netstar_smc91x_resources),
+       .resource       = netstar_smc91x_resources,
+};
+
+static struct platform_device *netstar_devices[] __initdata = {
+       &netstar_smc91x_device,
+};
+
+static void __init netstar_init_irq(void)
+{
+       omap_init_irq();
+       omap_gpio_init();
+}
+
+static void __init netstar_init(void)
+{
+       /* green LED */
+       omap_request_gpio(4);
+       omap_set_gpio_direction(4, 0);
+       /* smc91x reset */
+       omap_request_gpio(7);
+       omap_set_gpio_direction(7, 0);
+       omap_set_gpio_dataout(7, 1);
+       udelay(2);      /* wait at least 100ns */
+       omap_set_gpio_dataout(7, 0);
+       mdelay(50);     /* 50ms until PHY ready */
+       /* smc91x interrupt pin */
+       omap_request_gpio(8);
+       omap_set_gpio_edge_ctrl(8, OMAP_GPIO_RISING_EDGE);
+
+       omap_request_gpio(12);
+       omap_request_gpio(13);
+       omap_request_gpio(14);
+       omap_request_gpio(15);
+       omap_set_gpio_edge_ctrl(12, OMAP_GPIO_FALLING_EDGE);
+       omap_set_gpio_edge_ctrl(13, OMAP_GPIO_FALLING_EDGE);
+       omap_set_gpio_edge_ctrl(14, OMAP_GPIO_FALLING_EDGE);
+       omap_set_gpio_edge_ctrl(15, OMAP_GPIO_FALLING_EDGE);
+
+       platform_add_devices(netstar_devices, ARRAY_SIZE(netstar_devices));
+
+       /* Switch on green LED */
+       omap_set_gpio_dataout(4, 0);
+       /* Switch off red LED */
+       omap_writeb(0x00, OMAP_LPG1_PMR);       /* Disable clock */
+       omap_writeb(0x80, OMAP_LPG1_LCR);
+}
+
+static int __initdata omap_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
+
+static void __init netstar_map_io(void)
+{
+       omap_map_common_io();
+       omap_serial_init(omap_serial_ports);
+}
+
+#define MACHINE_PANICED                1
+#define MACHINE_REBOOTING      2
+#define MACHINE_REBOOT         4
+static unsigned long machine_state;
+
+static int panic_event(struct notifier_block *this, unsigned long event,
+        void *ptr)
+{
+       if (test_and_set_bit(MACHINE_PANICED, &machine_state))
+               return NOTIFY_DONE;
+
+       /* Switch off green LED */
+       omap_set_gpio_dataout(4, 1);
+       /* Flash red LED */
+       omap_writeb(0x78, OMAP_LPG1_LCR);
+       omap_writeb(0x01, OMAP_LPG1_PMR);       /* Enable clock */
+
+       return NOTIFY_DONE;
+}
+
+static struct notifier_block panic_block = {
+       .notifier_call  = panic_event,
+};
+
+static int __init netstar_late_init(void)
+{
+       /* TODO: Setup front panel switch here */
+
+       /* Setup panic notifier */
+       notifier_chain_register(&panic_notifier_list, &panic_block);
+
+       return 0;
+}
+
+postcore_initcall(netstar_late_init);
+
+MACHINE_START(NETSTAR, "NetStar OMAP5910")
+       /* Maintainer: Ladislav Michl <michl@2n.cz> */
+       .phys_ram       = 0x10000000,
+       .phys_io        = 0xfff00000,
+       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
+       .boot_params    = 0x10000100,
+       .map_io         = netstar_map_io,
+       .init_irq       = netstar_init_irq,
+       .init_machine   = netstar_init,
+       .timer          = &omap_timer,
+MACHINE_END
diff -urN linux/arch/arm/mach-omap1/board-osk.c 
linux/arch/arm/mach-omap1/board-osk.c
--- linux/arch/arm/mach-omap1/board-osk.c       1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/board-osk.c       2005-07-13 12:48:53.267672000 
+0100     1.1
@@ -0,0 +1,170 @@
+/*
+ * linux/arch/arm/mach-omap1/board-osk.c
+ *
+ * Board specific init for OMAP5912 OSK
+ *
+ * Written by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/usb.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/tc.h>
+#include <asm/arch/common.h>
+
+static struct map_desc osk5912_io_desc[] __initdata = {
+{ OMAP_OSK_NOR_FLASH_BASE, OMAP_OSK_NOR_FLASH_START, OMAP_OSK_NOR_FLASH_SIZE,
+       MT_DEVICE },
+};
+
+static int __initdata osk_serial_ports[OMAP_MAX_NR_PORTS] = {1, 0, 0};
+
+static struct resource osk5912_smc91x_resources[] = {
+       [0] = {
+               .start  = OMAP_OSK_ETHR_START,          /* Physical */
+               .end    = OMAP_OSK_ETHR_START + 0xf,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = OMAP_GPIO_IRQ(0),
+               .end    = OMAP_GPIO_IRQ(0),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device osk5912_smc91x_device = {
+       .name           = "smc91x",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(osk5912_smc91x_resources),
+       .resource       = osk5912_smc91x_resources,
+};
+
+static struct resource osk5912_cf_resources[] = {
+       [0] = {
+               .start  = OMAP_GPIO_IRQ(62),
+               .end    = OMAP_GPIO_IRQ(62),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device osk5912_cf_device = {
+       .name           = "omap_cf",
+       .id             = -1,
+       .dev = {
+               .platform_data  = (void *) 2 /* CS2 */,
+       },
+       .num_resources  = ARRAY_SIZE(osk5912_cf_resources),
+       .resource       = osk5912_cf_resources,
+};
+
+static struct platform_device *osk5912_devices[] __initdata = {
+       &osk5912_smc91x_device,
+       &osk5912_cf_device,
+};
+
+static void __init osk_init_smc91x(void)
+{
+       if ((omap_request_gpio(0)) < 0) {
+               printk("Error requesting gpio 0 for smc91x irq\n");
+               return;
+       }
+       omap_set_gpio_edge_ctrl(0, OMAP_GPIO_RISING_EDGE);
+
+       /* Check EMIFS wait states to fix errors with SMC_GET_PKT_HDR */
+       EMIFS_CCS(1) |= 0x2;
+}
+
+static void __init osk_init_cf(void)
+{
+       omap_cfg_reg(M7_1610_GPIO62);
+       if ((omap_request_gpio(62)) < 0) {
+               printk("Error requesting gpio 62 for CF irq\n");
+               return;
+       }
+       /* it's really active-low */
+       omap_set_gpio_edge_ctrl(62, OMAP_GPIO_FALLING_EDGE);
+}
+
+void osk_init_irq(void)
+{
+       omap_init_irq();
+       omap_gpio_init();
+       osk_init_smc91x();
+       osk_init_cf();
+}
+
+static struct omap_usb_config osk_usb_config __initdata = {
+       /* has usb host connector (A) ... for development it can also
+        * be used, with a NONSTANDARD gender-bending cable/dongle, as
+        * a peripheral.
+        */
+#ifdef CONFIG_USB_GADGET_OMAP
+       .register_dev   = 1,
+       .hmc_mode       = 0,
+#else
+       .register_host  = 1,
+       .hmc_mode       = 16,
+       .rwc            = 1,
+#endif
+       .pins[0]        = 2,
+};
+
+static struct omap_board_config_kernel osk_config[] = {
+       { OMAP_TAG_USB,           &osk_usb_config },
+};
+
+static void __init osk_init(void)
+{
+       platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
+       omap_board_config = osk_config;
+       omap_board_config_size = ARRAY_SIZE(osk_config);
+       USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
+}
+
+static void __init osk_map_io(void)
+{
+       omap_map_common_io();
+       iotable_init(osk5912_io_desc, ARRAY_SIZE(osk5912_io_desc));
+       omap_serial_init(osk_serial_ports);
+}
+
+MACHINE_START(OMAP_OSK, "TI-OSK")
+       /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
+       .phys_ram       = 0x10000000,
+       .phys_io        = 0xfff00000,
+       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
+       .boot_params    = 0x10000100,
+       .map_io         = osk_map_io,
+       .init_irq       = osk_init_irq,
+       .init_machine   = osk_init,
+       .timer          = &omap_timer,
+MACHINE_END
diff -urN linux/arch/arm/mach-omap1/board-perseus2.c 
linux/arch/arm/mach-omap1/board-perseus2.c
--- linux/arch/arm/mach-omap1/board-perseus2.c  1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/board-perseus2.c  2005-07-13 12:48:53.284706000 
+0100     1.1
@@ -0,0 +1,190 @@
+/*
+ * linux/arch/arm/mach-omap1/board-perseus2.c
+ *
+ * Modified from board-generic.c
+ *
+ * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
+ * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/fpga.h>
+#include <asm/arch/common.h>
+
+static struct resource smc91x_resources[] = {
+       [0] = {
+               .start  = H2P2_DBG_FPGA_ETHR_START,     /* Physical */
+               .end    = H2P2_DBG_FPGA_ETHR_START + 0xf,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = INT_730_MPU_EXT_NIRQ,
+               .end    = 0,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static int __initdata p2_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 0};
+
+static struct mtd_partition p2_partitions[] = {
+       /* bootloader (U-Boot, etc) in first sector */
+       {
+             .name             = "bootloader",
+             .offset           = 0,
+             .size             = SZ_128K,
+             .mask_flags       = MTD_WRITEABLE, /* force read-only */
+       },
+       /* bootloader params in the next sector */
+       {
+             .name             = "params",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = SZ_128K,
+             .mask_flags       = 0,
+       },
+       /* kernel */
+       {
+             .name             = "kernel",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = SZ_2M,
+             .mask_flags       = 0
+       },
+       /* rest of flash is a file system */
+       {
+             .name             = "rootfs",
+             .offset           = MTDPART_OFS_APPEND,
+             .size             = MTDPART_SIZ_FULL,
+             .mask_flags       = 0
+       },
+};
+
+static struct flash_platform_data p2_flash_data = {
+       .map_name       = "cfi_probe",
+       .width          = 2,
+       .parts          = p2_partitions,
+       .nr_parts       = ARRAY_SIZE(p2_partitions),
+};
+
+static struct resource p2_flash_resource = {
+       .start          = OMAP_FLASH_0_START,
+       .end            = OMAP_FLASH_0_START + OMAP_FLASH_0_SIZE - 1,
+       .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device p2_flash_device = {
+       .name           = "omapflash",
+       .id             = 0,
+       .dev            = {
+               .platform_data  = &p2_flash_data,
+       },
+       .num_resources  = 1,
+       .resource       = &p2_flash_resource,
+};
+
+static struct platform_device smc91x_device = {
+       .name           = "smc91x",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(smc91x_resources),
+       .resource       = smc91x_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+       &p2_flash_device,
+       &smc91x_device,
+};
+
+static void __init omap_perseus2_init(void)
+{
+       (void) platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+static void __init perseus2_init_smc91x(void)
+{
+       fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
+       mdelay(50);
+       fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
+                  H2P2_DBG_FPGA_LAN_RESET);
+       mdelay(50);
+}
+
+void omap_perseus2_init_irq(void)
+{
+       omap_init_irq();
+       omap_gpio_init();
+       perseus2_init_smc91x();
+}
+
+/* Only FPGA needs to be mapped here. All others are done with ioremap */
+static struct map_desc omap_perseus2_io_desc[] __initdata = {
+       {H2P2_DBG_FPGA_BASE, H2P2_DBG_FPGA_START, H2P2_DBG_FPGA_SIZE,
+        MT_DEVICE},
+};
+
+static void __init omap_perseus2_map_io(void)
+{
+       omap_map_common_io();
+       iotable_init(omap_perseus2_io_desc,
+                    ARRAY_SIZE(omap_perseus2_io_desc));
+
+       /* Early, board-dependent init */
+
+       /*
+        * Hold GSM Reset until needed
+        */
+       omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
+
+       /*
+        * UARTs -> done automagically by 8250 driver
+        */
+
+       /*
+        * CSx timings, GPIO Mux ... setup
+        */
+
+       /* Flash: CS0 timings setup */
+       omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
+       omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
+
+       /*
+        * Ethernet support trough the debug board
+        * CS1 timings setup
+        */
+       omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
+       omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
+
+       /*
+        * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
+        * It is used as the Ethernet controller interrupt
+        */
+       omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, 
OMAP730_IO_CONF_9);
+       omap_serial_init(p2_serial_ports);
+}
+
+MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
+       /* Maintainer: Kevin Hilman <kjh@hilman.org> */
+       .phys_ram       = 0x10000000,
+       .phys_io        = 0xfff00000,
+       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
+       .boot_params    = 0x10000100,
+       .map_io         = omap_perseus2_map_io,
+       .init_irq       = omap_perseus2_init_irq,
+       .init_machine   = omap_perseus2_init,
+       .timer          = &omap_timer,
+MACHINE_END
diff -urN linux/arch/arm/mach-omap1/board-voiceblue.c 
linux/arch/arm/mach-omap1/board-voiceblue.c
--- linux/arch/arm/mach-omap1/board-voiceblue.c 1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/board-voiceblue.c 2005-07-13 12:48:53.302787000 
+0100     1.1
@@ -0,0 +1,257 @@
+/*
+ * linux/arch/arm/mach-omap1/board-voiceblue.c
+ *
+ * Modified from board-generic.c
+ *
+ * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
+ *
+ * Code for OMAP5910 based VoiceBlue board (VoIP to GSM gateway).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_reg.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/tc.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/usb.h>
+#include <asm/arch/common.h>
+
+extern void omap_init_time(void);
+extern int omap_gpio_init(void);
+
+static struct plat_serial8250_port voiceblue_ports[] = {
+       {
+               .mapbase        = (unsigned long)(OMAP_CS1_PHYS + 0x40000),
+               .irq            = OMAP_GPIO_IRQ(12),
+               .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
+               .iotype         = UPIO_MEM,
+               .regshift       = 1,
+               .uartclk        = 3686400,
+       },
+       {
+               .mapbase        = (unsigned long)(OMAP_CS1_PHYS + 0x50000),
+               .irq            = OMAP_GPIO_IRQ(13),
+               .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
+               .iotype         = UPIO_MEM,
+               .regshift       = 1,
+               .uartclk        = 3686400,
+       },
+       {
+               .mapbase        = (unsigned long)(OMAP_CS1_PHYS + 0x60000),
+               .irq            = OMAP_GPIO_IRQ(14),
+               .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
+               .iotype         = UPIO_MEM,
+               .regshift       = 1,
+               .uartclk        = 3686400,
+       },
+       {
+               .mapbase        = (unsigned long)(OMAP_CS1_PHYS + 0x70000),
+               .irq            = OMAP_GPIO_IRQ(15),
+               .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
+               .iotype         = UPIO_MEM,
+               .regshift       = 1,
+               .uartclk        = 3686400,
+       },
+       { },
+};
+
+static struct platform_device serial_device = {
+       .name                   = "serial8250",
+       .id                     = 1,
+       .dev                    = {
+               .platform_data  = voiceblue_ports,
+       },
+};
+
+static int __init ext_uart_init(void)
+{
+       return platform_device_register(&serial_device);
+}
+arch_initcall(ext_uart_init);
+
+static struct resource voiceblue_smc91x_resources[] = {
+       [0] = {
+               .start  = OMAP_CS2_PHYS + 0x300,
+               .end    = OMAP_CS2_PHYS + 0x300 + 16,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = OMAP_GPIO_IRQ(8),
+               .end    = OMAP_GPIO_IRQ(8),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device voiceblue_smc91x_device = {
+       .name           = "smc91x",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(voiceblue_smc91x_resources),
+       .resource       = voiceblue_smc91x_resources,
+};
+
+static struct platform_device *voiceblue_devices[] __initdata = {
+       &voiceblue_smc91x_device,
+};
+
+static struct omap_usb_config voiceblue_usb_config __initdata = {
+       .hmc_mode       = 3,
+       .register_host  = 1,
+       .register_dev   = 1,
+       .pins[0]        = 2,
+       .pins[1]        = 6,
+       .pins[2]        = 6,
+};
+
+static struct omap_board_config_kernel voiceblue_config[] = {
+       { OMAP_TAG_USB, &voiceblue_usb_config },
+};
+
+static void __init voiceblue_init_irq(void)
+{
+       omap_init_irq();
+       omap_gpio_init();
+}
+
+static void __init voiceblue_init(void)
+{
+       /* There is a good chance board is going up, so enable Power LED
+        * (it is connected through invertor) */
+       omap_writeb(0x00, OMAP_LPG1_LCR);
+       /* Watchdog */
+       omap_request_gpio(0);
+       /* smc91x reset */
+       omap_request_gpio(7);
+       omap_set_gpio_direction(7, 0);
+       omap_set_gpio_dataout(7, 1);
+       udelay(2);      /* wait at least 100ns */
+       omap_set_gpio_dataout(7, 0);
+       mdelay(50);     /* 50ms until PHY ready */
+       /* smc91x interrupt pin */
+       omap_request_gpio(8);
+       omap_set_gpio_edge_ctrl(8, OMAP_GPIO_RISING_EDGE);
+       /* 16C554 reset*/
+       omap_request_gpio(6);
+       omap_set_gpio_direction(6, 0);
+       omap_set_gpio_dataout(6, 0);
+       /* 16C554 interrupt pins */
+       omap_request_gpio(12);
+       omap_request_gpio(13);
+       omap_request_gpio(14);
+       omap_request_gpio(15);
+       omap_set_gpio_edge_ctrl(12, OMAP_GPIO_RISING_EDGE);
+       omap_set_gpio_edge_ctrl(13, OMAP_GPIO_RISING_EDGE);
+       omap_set_gpio_edge_ctrl(14, OMAP_GPIO_RISING_EDGE);
+       omap_set_gpio_edge_ctrl(15, OMAP_GPIO_RISING_EDGE);
+
+       platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
+       omap_board_config = voiceblue_config;
+       omap_board_config_size = ARRAY_SIZE(voiceblue_config);
+}
+
+static int __initdata omap_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
+
+static void __init voiceblue_map_io(void)
+{
+       omap_map_common_io();
+       omap_serial_init(omap_serial_ports);
+}
+
+#define MACHINE_PANICED                1
+#define MACHINE_REBOOTING      2
+#define MACHINE_REBOOT         4
+static unsigned long machine_state;
+
+static int panic_event(struct notifier_block *this, unsigned long event,
+        void *ptr)
+{
+       if (test_and_set_bit(MACHINE_PANICED, &machine_state))
+               return NOTIFY_DONE;
+
+       /* Flash Power LED
+        * (TODO: Enable clock right way (enabled in bootloader already)) */
+       omap_writeb(0x78, OMAP_LPG1_LCR);
+
+       return NOTIFY_DONE;
+}
+
+static struct notifier_block panic_block = {
+       .notifier_call  = panic_event,
+};
+
+static int __init setup_notifier(void)
+{
+       /* Setup panic notifier */
+       notifier_chain_register(&panic_notifier_list, &panic_block);
+
+       return 0;
+}
+
+postcore_initcall(setup_notifier);
+
+static int wdt_gpio_state;
+
+void voiceblue_wdt_enable(void)
+{
+       omap_set_gpio_direction(0, 0);
+       omap_set_gpio_dataout(0, 0);
+       omap_set_gpio_dataout(0, 1);
+       omap_set_gpio_dataout(0, 0);
+       wdt_gpio_state = 0;
+}
+
+void voiceblue_wdt_disable(void)
+{
+       omap_set_gpio_dataout(0, 0);
+       omap_set_gpio_dataout(0, 1);
+       omap_set_gpio_dataout(0, 0);
+       omap_set_gpio_direction(0, 1);
+}
+
+void voiceblue_wdt_ping(void)
+{
+       if (test_bit(MACHINE_REBOOT, &machine_state))
+               return;
+
+       wdt_gpio_state = !wdt_gpio_state;
+       omap_set_gpio_dataout(0, wdt_gpio_state);
+}
+
+void voiceblue_reset(void)
+{
+       set_bit(MACHINE_REBOOT, &machine_state);
+       voiceblue_wdt_enable();
+       while (1) ;
+}
+
+EXPORT_SYMBOL(voiceblue_wdt_enable);
+EXPORT_SYMBOL(voiceblue_wdt_disable);
+EXPORT_SYMBOL(voiceblue_wdt_ping);
+
+MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
+       /* Maintainer: Ladislav Michl <michl@2n.cz> */
+       .phys_ram       = 0x10000000,
+       .phys_io        = 0xfff00000,
+       .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
+       .boot_params    = 0x10000100,
+       .map_io         = voiceblue_map_io,
+       .init_irq       = voiceblue_init_irq,
+       .init_machine   = voiceblue_init,
+       .timer          = &omap_timer,
+MACHINE_END
diff -urN linux/arch/arm/mach-omap1/fpga.c linux/arch/arm/mach-omap1/fpga.c
--- linux/arch/arm/mach-omap1/fpga.c    1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/fpga.c    2005-07-13 12:48:53.320675000 +0100     
1.1
@@ -0,0 +1,188 @@
+/*
+ * linux/arch/arm/mach-omap/fpga.c
+ *
+ * Interrupt handler for OMAP-1510 Innovator FPGA
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/fpga.h>
+#include <asm/arch/gpio.h>
+
+static void fpga_mask_irq(unsigned int irq)
+{
+       irq -= OMAP1510_IH_FPGA_BASE;
+
+       if (irq < 8)
+               __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
+                             & ~(1 << irq)), OMAP1510_FPGA_IMR_LO);
+       else if (irq < 16)
+               __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
+                             & ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
+       else
+               __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
+                             & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
+}
+
+
+static inline u32 get_fpga_unmasked_irqs(void)
+{
+       return
+               ((__raw_readb(OMAP1510_FPGA_ISR_LO) &
+                 __raw_readb(OMAP1510_FPGA_IMR_LO))) |
+               ((__raw_readb(OMAP1510_FPGA_ISR_HI) &
+                 __raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) |
+               ((__raw_readb(INNOVATOR_FPGA_ISR2) &
+                 __raw_readb(INNOVATOR_FPGA_IMR2)) << 16);
+}
+
+
+static void fpga_ack_irq(unsigned int irq)
+{
+       /* Don't need to explicitly ACK FPGA interrupts */
+}
+
+static void fpga_unmask_irq(unsigned int irq)
+{
+       irq -= OMAP1510_IH_FPGA_BASE;
+
+       if (irq < 8)
+               __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
+                    OMAP1510_FPGA_IMR_LO);
+       else if (irq < 16)
+               __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
+                             | (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
+       else
+               __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
+                             | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
+}
+
+static void fpga_mask_ack_irq(unsigned int irq)
+{
+       fpga_mask_irq(irq);
+       fpga_ack_irq(irq);
+}
+
+void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc,
+                             struct pt_regs *regs)
+{
+       struct irqdesc *d;
+       u32 stat;
+       int fpga_irq;
+
+       stat = get_fpga_unmasked_irqs();
+
+       if (!stat)
+               return;
+
+       for (fpga_irq = OMAP1510_IH_FPGA_BASE;
+            (fpga_irq < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS)) && stat;
+            fpga_irq++, stat >>= 1) {
+               if (stat & 1) {
+                       d = irq_desc + fpga_irq;
+                       d->handle(fpga_irq, d, regs);
+               }
+       }
+}
+
+static struct irqchip omap_fpga_irq_ack = {
+       .ack            = fpga_mask_ack_irq,
+       .mask           = fpga_mask_irq,
+       .unmask         = fpga_unmask_irq,
+};
+
+
+static struct irqchip omap_fpga_irq = {
+       .ack            = fpga_ack_irq,
+       .mask           = fpga_mask_irq,
+       .unmask         = fpga_unmask_irq,
+};
+
+/*
+ * All of the FPGA interrupt request inputs except for the touchscreen are
+ * edge-sensitive; the touchscreen is level-sensitive.  The edge-sensitive
+ * interrupts are acknowledged as a side-effect of reading the interrupt
+ * status register from the FPGA.  The edge-sensitive interrupt inputs
+ * cause a problem with level interrupt requests, such as Ethernet.  The
+ * problem occurs when a level interrupt request is asserted while its
+ * interrupt input is masked in the FPGA, which results in a missed
+ * interrupt.
+ *
+ * In an attempt to workaround the problem with missed interrupts, the
+ * mask_ack routine for all of the FPGA interrupts has been changed from
+ * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
+ * being serviced is left unmasked.  We can do this because the FPGA cascade
+ * interrupt is installed with the SA_INTERRUPT flag, which leaves all
+ * interrupts masked at the CPU while an FPGA interrupt handler executes.
+ *
+ * Limited testing indicates that this workaround appears to be effective
+ * for the smc9194 Ethernet driver used on the Innovator.  It should work
+ * on other FPGA interrupts as well, but any drivers that explicitly mask
+ * interrupts at the interrupt controller via disable_irq/enable_irq
+ * could pose a problem.
+ */
+void omap1510_fpga_init_irq(void)
+{
+       int i;
+
+       __raw_writeb(0, OMAP1510_FPGA_IMR_LO);
+       __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
+       __raw_writeb(0, INNOVATOR_FPGA_IMR2);
+
+       for (i = OMAP1510_IH_FPGA_BASE; i < (OMAP1510_IH_FPGA_BASE + 
NR_FPGA_IRQS); i++) {
+
+               if (i == OMAP1510_INT_FPGA_TS) {
+                       /*
+                        * The touchscreen interrupt is level-sensitive, so
+                        * we'll use the regular mask_ack routine for it.
+                        */
+                       set_irq_chip(i, &omap_fpga_irq_ack);
+               }
+               else {
+                       /*
+                        * All FPGA interrupts except the touchscreen are
+                        * edge-sensitive, so we won't mask them.
+                        */
+                       set_irq_chip(i, &omap_fpga_irq);
+               }
+
+               set_irq_handler(i, do_edge_IRQ);
+               set_irq_flags(i, IRQF_VALID);
+       }
+
+       /*
+        * The FPGA interrupt line is connected to GPIO13. Claim this pin for
+        * the ARM.
+        *
+        * NOTE: For general GPIO/MPUIO access and interrupts, please see
+        * gpio.[ch]
+        */
+       omap_request_gpio(13);
+       omap_set_gpio_direction(13, 1);
+       omap_set_gpio_edge_ctrl(13, OMAP_GPIO_RISING_EDGE);
+       set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
+}
+
+EXPORT_SYMBOL(omap1510_fpga_init_irq);
diff -urN linux/arch/arm/mach-omap1/id.c linux/arch/arm/mach-omap1/id.c
--- linux/arch/arm/mach-omap1/id.c      1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/id.c      2005-07-13 12:48:53.337638000 +0100     
1.1
@@ -0,0 +1,188 @@
+/*
+ * linux/arch/arm/mach-omap1/id.c
+ *
+ * OMAP1 CPU identification code
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+
+struct omap_id {
+       u16     jtag_id;        /* Used to determine OMAP type */
+       u8      die_rev;        /* Processor revision */
+       u32     omap_id;        /* OMAP revision */
+       u32     type;           /* Cpu id bits [31:08], cpu class bits [07:00] 
*/
+};
+
+/* Register values to detect the OMAP version */
+static struct omap_id omap_ids[] __initdata = {
+       { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 
0x07300100},
+       { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 
0x07300300},
+       { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 
0x15100000},
+       { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 
0x16100000},
+       { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 
0x16110000},
+       { .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 
0x16100c00},
+       { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 
0x16100d00},
+       { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 
0x1610ef00},
+       { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 
0x1610ef00},
+       { .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 
0x16110000},
+       { .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 
0x16110b00},
+       { .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 
0x16110c00},
+       { .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 
0x16212300},
+       { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 
0x16212300},
+       { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 
0x16212300},
+       { .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 
0x17100000},
+       { .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 
0x17100000},
+       { .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 
0x17100000},
+};
+
+/*
+ * Get OMAP type from PROD_ID.
+ * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM.
+ * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense.
+ * Undocumented register in TEST BLOCK is used as fallback; This seems to
+ * work on 1510, 1610 & 1710. The official way hopefully will work in future
+ * processors.
+ */
+static u16 __init omap_get_jtag_id(void)
+{
+       u32 prod_id, omap_id;
+
+       prod_id = omap_readl(OMAP_PRODUCTION_ID_1);
+       omap_id = omap_readl(OMAP32_ID_1);
+
+       /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */
+       if (((prod_id >> 20) == 0) || (prod_id == omap_id))
+               prod_id = 0;
+       else
+               prod_id &= 0xffff;
+
+       if (prod_id)
+               return prod_id;
+
+       /* Use OMAP32_ID_1 as fallback */
+       prod_id = ((omap_id >> 12) & 0xffff);
+
+       return prod_id;
+}
+
+/*
+ * Get OMAP revision from DIE_REV.
+ * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID.
+ * Undocumented register in the TEST BLOCK is used as fallback.
+ * REVISIT: This does not seem to work on 1510
+ */
+static u8 __init omap_get_die_rev(void)
+{
+       u32 die_rev;
+
+       die_rev = omap_readl(OMAP_DIE_ID_1);
+
+       /* Check for broken OMAP_DIE_ID on early 1710 */
+       if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id())
+               die_rev = 0;
+
+       die_rev = (die_rev >> 17) & 0xf;
+       if (die_rev)
+               return die_rev;
+
+       die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf;
+
+       return die_rev;
+}
+
+void __init omap_check_revision(void)
+{
+       int i;
+       u16 jtag_id;
+       u8 die_rev;
+       u32 omap_id;
+       u8 cpu_type;
+
+       jtag_id = omap_get_jtag_id();
+       die_rev = omap_get_die_rev();
+       omap_id = omap_readl(OMAP32_ID_0);
+
+#ifdef DEBUG
+       printk("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0));
+       printk("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n",
+               omap_readl(OMAP_DIE_ID_1),
+              (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf);
+       printk("OMAP_PRODUCTION_ID_0: 0x%08x\n", 
omap_readl(OMAP_PRODUCTION_ID_0));
+       printk("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n",
+               omap_readl(OMAP_PRODUCTION_ID_1),
+               omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff);
+       printk("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0));
+       printk("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1));
+       printk("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev);
+#endif
+
+       system_serial_high = omap_readl(OMAP_DIE_ID_0);
+       system_serial_low = omap_readl(OMAP_DIE_ID_1);
+
+       /* First check only the major version in a safe way */
+       for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
+               if (jtag_id == (omap_ids[i].jtag_id)) {
+                       system_rev = omap_ids[i].type;
+                       break;
+               }
+       }
+
+       /* Check if we can find the die revision */
+       for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
+               if (jtag_id == omap_ids[i].jtag_id && die_rev == 
omap_ids[i].die_rev) {
+                       system_rev = omap_ids[i].type;
+                       break;
+               }
+       }
+
+       /* Finally check also the omap_id */
+       for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
+               if (jtag_id == omap_ids[i].jtag_id
+                   && die_rev == omap_ids[i].die_rev
+                   && omap_id == omap_ids[i].omap_id) {
+                       system_rev = omap_ids[i].type;
+                       break;
+               }
+       }
+
+       /* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */
+       cpu_type = system_rev >> 24;
+
+       switch (cpu_type) {
+       case 0x07:
+               system_rev |= 0x07;
+               break;
+       case 0x15:
+               system_rev |= 0x15;
+               break;
+       case 0x16:
+       case 0x17:
+               system_rev |= 0x16;
+               break;
+       case 0x24:
+               system_rev |= 0x24;
+               break;
+       default:
+               printk("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
+       }
+
+       printk("OMAP%04x", system_rev >> 16);
+       if ((system_rev >> 8) & 0xff)
+               printk("%x", (system_rev >> 8) & 0xff);
+       printk(" revision %i handled as %02xxx id: %08x%08x\n",
+              die_rev, system_rev & 0xff, system_serial_low,
+              system_serial_high);
+}
+
diff -urN linux/arch/arm/mach-omap1/io.c linux/arch/arm/mach-omap1/io.c
--- linux/arch/arm/mach-omap1/io.c      1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/io.c      2005-07-13 12:48:53.357583000 +0100     
1.1
@@ -0,0 +1,115 @@
+/*
+ * linux/arch/arm/mach-omap1/io.c
+ *
+ * OMAP1 I/O mapping code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/mach/map.h>
+#include <asm/io.h>
+#include <asm/arch/tc.h>
+
+extern int clk_init(void);
+extern void omap_check_revision(void);
+
+/*
+ * The machine specific code may provide the extra mapping besides the
+ * default mapping provided here.
+ */
+static struct map_desc omap_io_desc[] __initdata = {
+ { IO_VIRT,            IO_PHYS,             IO_SIZE,              MT_DEVICE },
+};
+
+#ifdef CONFIG_ARCH_OMAP730
+static struct map_desc omap730_io_desc[] __initdata = {
+ { OMAP730_DSP_BASE,    OMAP730_DSP_START,    OMAP730_DSP_SIZE,    MT_DEVICE },
+ { OMAP730_DSPREG_BASE, OMAP730_DSPREG_START, OMAP730_DSPREG_SIZE, MT_DEVICE },
+ { OMAP730_SRAM_BASE,   OMAP730_SRAM_START,   OMAP730_SRAM_SIZE,   MT_DEVICE }
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1510
+static struct map_desc omap1510_io_desc[] __initdata = {
+ { OMAP1510_DSP_BASE,    OMAP1510_DSP_START,    OMAP1510_DSP_SIZE,    
MT_DEVICE },
+ { OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_START, OMAP1510_DSPREG_SIZE, 
MT_DEVICE },
+ { OMAP1510_SRAM_BASE,   OMAP1510_SRAM_START,   OMAP1510_SRAM_SIZE,   
MT_DEVICE }
+};
+#endif
+
+#if defined(CONFIG_ARCH_OMAP16XX)
+static struct map_desc omap1610_io_desc[] __initdata = {
+ { OMAP16XX_DSP_BASE,    OMAP16XX_DSP_START,    OMAP16XX_DSP_SIZE,    
MT_DEVICE },
+ { OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_START, OMAP16XX_DSPREG_SIZE, 
MT_DEVICE },
+ { OMAP16XX_SRAM_BASE,   OMAP16XX_SRAM_START,   OMAP1610_SRAM_SIZE,   
MT_DEVICE }
+};
+
+static struct map_desc omap5912_io_desc[] __initdata = {
+ { OMAP16XX_DSP_BASE,    OMAP16XX_DSP_START,    OMAP16XX_DSP_SIZE,    
MT_DEVICE },
+ { OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_START, OMAP16XX_DSPREG_SIZE, 
MT_DEVICE },
+/*
+ * The OMAP5912 has 250kByte internal SRAM. Because the mapping is baseed on 
page
+ * size (4kByte), it seems that the last 2kByte (=0x800) of the 250kByte are 
not mapped.
+ * Add additional 2kByte (0x800) so that the last page is mapped and the last 
2kByte
+ * can be used.
+ */
+ { OMAP16XX_SRAM_BASE,   OMAP16XX_SRAM_START,   OMAP5912_SRAM_SIZE + 0x800,   
MT_DEVICE }
+};
+#endif
+
+static int initialized = 0;
+
+static void __init _omap_map_io(void)
+{
+       initialized = 1;
+
+       /* We have to initialize the IO space mapping before we can run
+        * cpu_is_omapxxx() macros. */
+       iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc));
+       omap_check_revision();
+
+#ifdef CONFIG_ARCH_OMAP730
+       if (cpu_is_omap730()) {
+               iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc));
+       }
+#endif
+#ifdef CONFIG_ARCH_OMAP1510
+       if (cpu_is_omap1510()) {
+               iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
+       }
+#endif
+#if defined(CONFIG_ARCH_OMAP16XX)
+       if (cpu_is_omap1610() || cpu_is_omap1710()) {
+               iotable_init(omap1610_io_desc, ARRAY_SIZE(omap1610_io_desc));
+       }
+       if (cpu_is_omap5912()) {
+               iotable_init(omap5912_io_desc, ARRAY_SIZE(omap5912_io_desc));
+       }
+#endif
+
+       /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
+        * on a Posted Write in the TIPB Bridge".
+        */
+       omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL);
+       omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL);
+
+       /* Must init clocks early to assure that timer interrupt works
+        */
+       clk_init();
+}
+
+/*
+ * This should only get called from board specific init
+ */
+void omap_map_common_io(void)
+{
+       if (!initialized)
+               _omap_map_io();
+}
diff -urN linux/arch/arm/mach-omap1/irq.c linux/arch/arm/mach-omap1/irq.c
--- linux/arch/arm/mach-omap1/irq.c     1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/irq.c     2005-07-13 12:48:53.373705000 +0100     
1.1
@@ -0,0 +1,234 @@
+/*
+ * linux/arch/arm/mach-omap/irq.c
+ *
+ * Interrupt handler for all OMAP boards
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * Completely re-written to support various OMAP chips with bank specific
+ * interrupt handlers.
+ *
+ * Some snippets of the code taken from the older OMAP interrupt handler
+ * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * GPIO interrupt handler moved to gpio.c by Juha Yrjola
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <asm/arch/gpio.h>
+
+#include <asm/io.h>
+
+#define IRQ_BANK(irq) ((irq) >> 5)
+#define IRQ_BIT(irq)  ((irq) & 0x1f)
+
+struct omap_irq_bank {
+       unsigned long base_reg;
+       unsigned long trigger_map;
+       unsigned long wake_enable;
+};
+
+static unsigned int irq_bank_count = 0;
+static struct omap_irq_bank *irq_banks;
+
+static inline unsigned int irq_bank_readl(int bank, int offset)
+{
+       return omap_readl(irq_banks[bank].base_reg + offset);
+}
+
+static inline void irq_bank_writel(unsigned long value, int bank, int offset)
+{
+       omap_writel(value, irq_banks[bank].base_reg + offset);
+}
+
+static void omap_ack_irq(unsigned int irq)
+{
+       if (irq > 31)
+               omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
+
+       omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
+}
+
+static void omap_mask_irq(unsigned int irq)
+{
+       int bank = IRQ_BANK(irq);
+       u32 l;
+
+       l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
+       l |= 1 << IRQ_BIT(irq);
+       omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
+}
+
+static void omap_unmask_irq(unsigned int irq)
+{
+       int bank = IRQ_BANK(irq);
+       u32 l;
+
+       l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
+       l &= ~(1 << IRQ_BIT(irq));
+       omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
+}
+
+static void omap_mask_ack_irq(unsigned int irq)
+{
+       omap_mask_irq(irq);
+       omap_ack_irq(irq);
+}
+
+static int omap_wake_irq(unsigned int irq, unsigned int enable)
+{
+       int bank = IRQ_BANK(irq);
+
+       if (enable)
+               irq_banks[bank].wake_enable |= IRQ_BIT(irq);
+       else
+               irq_banks[bank].wake_enable &= ~IRQ_BIT(irq);
+
+       return 0;
+}
+
+
+/*
+ * Allows tuning the IRQ type and priority
+ *
+ * NOTE: There is currently no OMAP fiq handler for Linux. Read the
+ *      mailing list threads on FIQ handlers if you are planning to
+ *      add a FIQ handler for OMAP.
+ */
+static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
+{
+       signed int bank;
+       unsigned long val, offset;
+
+       bank = IRQ_BANK(irq);
+       /* FIQ is only available on bank 0 interrupts */
+       fiq = bank ? 0 : (fiq & 0x1);
+       val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
+       offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
+       irq_bank_writel(val, bank, offset);
+}
+
+#ifdef CONFIG_ARCH_OMAP730
+static struct omap_irq_bank omap730_irq_banks[] = {
+       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3f8e22f },
+       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb9c1f2 },
+       { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0x800040f3 },
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1510
+static struct omap_irq_bank omap1510_irq_banks[] = {
+       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3febfff },
+       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xffbfffed },
+};
+#endif
+
+#if defined(CONFIG_ARCH_OMAP16XX)
+
+static struct omap_irq_bank omap1610_irq_banks[] = {
+       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3fefe8f },
+       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb7c1fd },
+       { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0xffffb7ff },
+       { .base_reg = OMAP_IH2_BASE + 0x200,    .trigger_map = 0xffffffff },
+};
+#endif
+
+static struct irqchip omap_irq_chip = {
+       .ack    = omap_mask_ack_irq,
+       .mask   = omap_mask_irq,
+       .unmask = omap_unmask_irq,
+       .wake   = omap_wake_irq,
+};
+
+void __init omap_init_irq(void)
+{
+       int i, j;
+
+#ifdef CONFIG_ARCH_OMAP730
+       if (cpu_is_omap730()) {
+               irq_banks = omap730_irq_banks;
+               irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
+       }
+#endif
+#ifdef CONFIG_ARCH_OMAP1510
+       if (cpu_is_omap1510()) {
+               irq_banks = omap1510_irq_banks;
+               irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
+       }
+#endif
+#if defined(CONFIG_ARCH_OMAP16XX)
+       if (cpu_is_omap16xx()) {
+               irq_banks = omap1610_irq_banks;
+               irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
+       }
+#endif
+       printk("Total of %i interrupts in %i interrupt banks\n",
+              irq_bank_count * 32, irq_bank_count);
+
+       /* Mask and clear all interrupts */
+       for (i = 0; i < irq_bank_count; i++) {
+               irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
+               irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
+       }
+
+       /* Clear any pending interrupts */
+       irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
+       irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
+
+       /* Enable interrupts in global mask */
+       if (cpu_is_omap730()) {
+               irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
+       }
+
+       /* Install the interrupt handlers for each bank */
+       for (i = 0; i < irq_bank_count; i++) {
+               for (j = i * 32; j < (i + 1) * 32; j++) {
+                       int irq_trigger;
+
+                       irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
+                       omap_irq_set_cfg(j, 0, 0, irq_trigger);
+
+                       set_irq_chip(j, &omap_irq_chip);
+                       set_irq_handler(j, do_level_IRQ);
+                       set_irq_flags(j, IRQF_VALID);
+               }
+       }
+
+       /* Unmask level 2 handler */
+       if (cpu_is_omap730()) {
+               omap_unmask_irq(INT_730_IH2_IRQ);
+       } else {
+               omap_unmask_irq(INT_IH2_IRQ);
+       }
+}
diff -urN linux/arch/arm/mach-omap1/leds-h2p2-debug.c 
linux/arch/arm/mach-omap1/leds-h2p2-debug.c
--- linux/arch/arm/mach-omap1/leds-h2p2-debug.c 1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/leds-h2p2-debug.c 2005-07-13 12:48:53.391621000 
+0100     1.1
@@ -0,0 +1,144 @@
+/*
+ * linux/arch/arm/mach-omap/leds-h2p2-debug.c
+ *
+ * Copyright 2003 by Texas Instruments Incorporated
+ *
+ * There are 16 LEDs on the debug board (all green); four may be used
+ * for logical 'green', 'amber', 'red', and 'blue' (after "claiming").
+ *
+ * The "surfer" expansion board and H2 sample board also have two-color
+ * green+red LEDs (in parallel), used here for timer and idle indicators.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/version.h>
+
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+
+#include <asm/arch/fpga.h>
+#include <asm/arch/gpio.h>
+
+#include "leds.h"
+
+
+#define GPIO_LED_RED           3
+#define GPIO_LED_GREEN         OMAP_MPUIO(4)
+
+
+#define LED_STATE_ENABLED      0x01
+#define LED_STATE_CLAIMED      0x02
+#define LED_TIMER_ON           0x04
+
+#define GPIO_IDLE              GPIO_LED_GREEN
+#define GPIO_TIMER             GPIO_LED_RED
+
+
+void h2p2_dbg_leds_event(led_event_t evt)
+{
+       unsigned long flags;
+
+       static struct h2p2_dbg_fpga __iomem *fpga;
+       static u16 led_state, hw_led_state;
+
+       local_irq_save(flags);
+
+       if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
+               goto done;
+
+       switch (evt) {
+       case led_start:
+               if (!fpga)
+                       fpga = ioremap(H2P2_DBG_FPGA_START,
+                                               H2P2_DBG_FPGA_SIZE);
+               if (fpga) {
+                       led_state |= LED_STATE_ENABLED;
+                       __raw_writew(~0, &fpga->leds);
+               }
+               break;
+
+       case led_stop:
+       case led_halted:
+               /* all leds off during suspend or shutdown */
+               omap_set_gpio_dataout(GPIO_TIMER, 0);
+               omap_set_gpio_dataout(GPIO_IDLE, 0);
+               __raw_writew(~0, &fpga->leds);
+               led_state &= ~LED_STATE_ENABLED;
+               if (evt == led_halted) {
+                       iounmap(fpga);
+                       fpga = NULL;
+               }
+               goto done;
+
+       case led_claim:
+               led_state |= LED_STATE_CLAIMED;
+               hw_led_state = 0;
+               break;
+
+       case led_release:
+               led_state &= ~LED_STATE_CLAIMED;
+               break;
+
+#ifdef CONFIG_LEDS_TIMER
+       case led_timer:
+               led_state ^= LED_TIMER_ON;
+               omap_set_gpio_dataout(GPIO_TIMER, led_state & LED_TIMER_ON);
+               goto done;
+#endif
+
+#ifdef CONFIG_LEDS_CPU
+       case led_idle_start:
+               omap_set_gpio_dataout(GPIO_IDLE, 1);
+               goto done;
+
+       case led_idle_end:
+               omap_set_gpio_dataout(GPIO_IDLE, 0);
+               goto done;
+#endif
+
+       case led_green_on:
+               hw_led_state |= H2P2_DBG_FPGA_LED_GREEN;
+               break;
+       case led_green_off:
+               hw_led_state &= ~H2P2_DBG_FPGA_LED_GREEN;
+               break;
+
+       case led_amber_on:
+               hw_led_state |= H2P2_DBG_FPGA_LED_AMBER;
+               break;
+       case led_amber_off:
+               hw_led_state &= ~H2P2_DBG_FPGA_LED_AMBER;
+               break;
+
+       case led_red_on:
+               hw_led_state |= H2P2_DBG_FPGA_LED_RED;
+               break;
+       case led_red_off:
+               hw_led_state &= ~H2P2_DBG_FPGA_LED_RED;
+               break;
+
+       case led_blue_on:
+               hw_led_state |= H2P2_DBG_FPGA_LED_BLUE;
+               break;
+       case led_blue_off:
+               hw_led_state &= ~H2P2_DBG_FPGA_LED_BLUE;
+               break;
+
+       default:
+               break;
+       }
+
+
+       /*
+        *  Actually burn the LEDs
+        */
+       if (led_state & LED_STATE_CLAIMED)
+               __raw_writew(~hw_led_state, &fpga->leds);
+
+done:
+       local_irq_restore(flags);
+}
diff -urN linux/arch/arm/mach-omap1/leds-innovator.c 
linux/arch/arm/mach-omap1/leds-innovator.c
--- linux/arch/arm/mach-omap1/leds-innovator.c  1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/leds-innovator.c  2005-07-13 12:48:53.408581000 
+0100     1.1
@@ -0,0 +1,103 @@
+/*
+ * linux/arch/arm/mach-omap/leds-innovator.c
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+
+#include "leds.h"
+
+
+#define LED_STATE_ENABLED      1
+#define LED_STATE_CLAIMED      2
+
+static unsigned int led_state;
+static unsigned int hw_led_state;
+
+void innovator_leds_event(led_event_t evt)
+{
+       unsigned long flags;
+
+       local_irq_save(flags);
+
+       switch (evt) {
+       case led_start:
+               hw_led_state = 0;
+               led_state = LED_STATE_ENABLED;
+               break;
+
+       case led_stop:
+               led_state &= ~LED_STATE_ENABLED;
+               hw_led_state = 0;
+               break;
+
+       case led_claim:
+               led_state |= LED_STATE_CLAIMED;
+               hw_led_state = 0;
+               break;
+
+       case led_release:
+               led_state &= ~LED_STATE_CLAIMED;
+               hw_led_state = 0;
+               break;
+
+#ifdef CONFIG_LEDS_TIMER
+       case led_timer:
+               if (!(led_state & LED_STATE_CLAIMED))
+                       hw_led_state ^= 0;
+               break;
+#endif
+
+#ifdef CONFIG_LEDS_CPU
+       case led_idle_start:
+               if (!(led_state & LED_STATE_CLAIMED))
+                       hw_led_state |= 0;
+               break;
+
+       case led_idle_end:
+               if (!(led_state & LED_STATE_CLAIMED))
+                       hw_led_state &= ~0;
+               break;
+#endif
+
+       case led_halted:
+               break;
+
+       case led_green_on:
+               if (led_state & LED_STATE_CLAIMED)
+                       hw_led_state &= ~0;
+               break;
+
+       case led_green_off:
+               if (led_state & LED_STATE_CLAIMED)
+                       hw_led_state |= 0;
+               break;
+
+       case led_amber_on:
+               break;
+
+       case led_amber_off:
+               break;
+
+       case led_red_on:
+               if (led_state & LED_STATE_CLAIMED)
+                       hw_led_state &= ~0;
+               break;
+
+       case led_red_off:
+               if (led_state & LED_STATE_CLAIMED)
+                       hw_led_state |= 0;
+               break;
+
+       default:
+               break;
+       }
+
+       if (led_state & LED_STATE_ENABLED)
+               ;
+
+       local_irq_restore(flags);
+}
diff -urN linux/arch/arm/mach-omap1/leds-osk.c 
linux/arch/arm/mach-omap1/leds-osk.c
--- linux/arch/arm/mach-omap1/leds-osk.c        1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/leds-osk.c        2005-07-13 12:48:53.424653000 
+0100     1.1
@@ -0,0 +1,194 @@
+/*
+ * linux/arch/arm/mach-omap/leds-osk.c
+ *
+ * LED driver for OSK, and optionally Mistral QVGA, boards
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/workqueue.h>
+
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/tps65010.h>
+
+#include "leds.h"
+
+
+#define LED_STATE_ENABLED      (1 << 0)
+#define LED_STATE_CLAIMED      (1 << 1)
+static u8 led_state;
+
+#define        GREEN_LED               (1 << 0)        /* TPS65010 LED1 */
+#define        AMBER_LED               (1 << 1)        /* TPS65010 LED2 */
+#define        RED_LED                 (1 << 2)        /* TPS65010 GPIO2 */
+#define        TIMER_LED               (1 << 3)        /* Mistral board */
+#define        IDLE_LED                (1 << 4)        /* Mistral board */
+static u8 hw_led_state;
+
+
+/* TPS65010 leds are changed using i2c -- from a task context.
+ * Using one of these for the "idle" LED would be impractical...
+ */
+#define        TPS_LEDS        (GREEN_LED | RED_LED | AMBER_LED)
+
+static u8 tps_leds_change;
+
+static void tps_work(void *unused)
+{
+       for (;;) {
+               u8      leds;
+
+               local_irq_disable();
+               leds = tps_leds_change;
+               tps_leds_change = 0;
+               local_irq_enable();
+
+               if (!leds)
+                       break;
+
+               /* careful:  the set_led() value is on/off/blink */
+               if (leds & GREEN_LED)
+                       tps65010_set_led(LED1, !!(hw_led_state & GREEN_LED));
+               if (leds & AMBER_LED)
+                       tps65010_set_led(LED2, !!(hw_led_state & AMBER_LED));
+
+               /* the gpio led doesn't have that issue */
+               if (leds & RED_LED)
+                       tps65010_set_gpio_out_value(GPIO2,
+                                       !(hw_led_state & RED_LED));
+       }
+}
+
+static DECLARE_WORK(work, tps_work, NULL);
+
+#ifdef CONFIG_FB_OMAP
+
+/* For now, all system indicators require the Mistral board, since that
+ * LED can be manipulated without a task context.  This LED is either red,
+ * or green, but not both; it can't give the full "disco led" effect.
+ */
+
+#define GPIO_LED_RED           3
+#define GPIO_LED_GREEN         OMAP_MPUIO(4)
+
+static void mistral_setled(void)
+{
+       int     red = 0;
+       int     green = 0;
+
+       if (hw_led_state & TIMER_LED)
+               red = 1;
+       else if (hw_led_state & IDLE_LED)
+               green = 1;
+       // else both sides are disabled
+
+       omap_set_gpio_dataout(GPIO_LED_GREEN, green);
+       omap_set_gpio_dataout(GPIO_LED_RED, red);
+}
+
+#endif
+
+void osk_leds_event(led_event_t evt)
+{
+       unsigned long   flags;
+       u16             leds;
+
+       local_irq_save(flags);
+
+       if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
+               goto done;
+
+       leds = hw_led_state;
+       switch (evt) {
+       case led_start:
+               led_state |= LED_STATE_ENABLED;
+               hw_led_state = 0;
+               leds = ~0;
+               break;
+
+       case led_halted:
+       case led_stop:
+               led_state &= ~LED_STATE_ENABLED;
+               hw_led_state = 0;
+               // NOTE:  work may still be pending!!
+               break;
+
+       case led_claim:
+               led_state |= LED_STATE_CLAIMED;
+               hw_led_state = 0;
+               leds = ~0;
+               break;
+
+       case led_release:
+               led_state &= ~LED_STATE_CLAIMED;
+               hw_led_state = 0;
+               break;
+
+#ifdef CONFIG_FB_OMAP
+
+       case led_timer:
+               hw_led_state ^= TIMER_LED;
+               mistral_setled();
+               break;
+
+       case led_idle_start:
+               hw_led_state |= IDLE_LED;
+               mistral_setled();
+               break;
+
+       case led_idle_end:
+               hw_led_state &= ~IDLE_LED;
+               mistral_setled();
+               break;
+
+#endif /* CONFIG_FB_OMAP */
+
+       /* "green" == tps LED1 (leftmost, normally power-good)
+        * works only with DC adapter, not on battery power!
+        */
+       case led_green_on:
+               if (led_state & LED_STATE_CLAIMED)
+                       hw_led_state |= GREEN_LED;
+               break;
+       case led_green_off:
+               if (led_state & LED_STATE_CLAIMED)
+                       hw_led_state &= ~GREEN_LED;
+               break;
+
+       /* "amber" == tps LED2 (middle) */
+       case led_amber_on:
+               if (led_state & LED_STATE_CLAIMED)
+                       hw_led_state |= AMBER_LED;
+               break;
+       case led_amber_off:
+               if (led_state & LED_STATE_CLAIMED)
+                       hw_led_state &= ~AMBER_LED;
+               break;
+
+       /* "red" == LED on tps gpio3 (rightmost) */
+       case led_red_on:
+               if (led_state & LED_STATE_CLAIMED)
+                       hw_led_state |= RED_LED;
+               break;
+       case led_red_off:
+               if (led_state & LED_STATE_CLAIMED)
+                       hw_led_state &= ~RED_LED;
+               break;
+
+       default:
+               break;
+       }
+
+       leds ^= hw_led_state;
+       leds &= TPS_LEDS;
+       if (leds && (led_state & LED_STATE_CLAIMED)) {
+               tps_leds_change |= leds;
+               schedule_work(&work);
+       }
+
+done:
+       local_irq_restore(flags);
+}
diff -urN linux/arch/arm/mach-omap1/leds.c linux/arch/arm/mach-omap1/leds.c
--- linux/arch/arm/mach-omap1/leds.c    1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/leds.c    2005-07-13 12:48:53.441795000 +0100     
1.1
@@ -0,0 +1,61 @@
+/*
+ * linux/arch/arm/mach-omap/leds.c
+ *
+ * OMAP LEDs dispatcher
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "leds.h"
+
+static int __init
+omap_leds_init(void)
+{
+       if (machine_is_omap_innovator())
+               leds_event = innovator_leds_event;
+
+       else if (machine_is_omap_h2() || machine_is_omap_perseus2())
+               leds_event = h2p2_dbg_leds_event;
+
+       else if (machine_is_omap_osk())
+               leds_event = osk_leds_event;
+
+       else
+               return -1;
+
+       if (machine_is_omap_h2()
+                       || machine_is_omap_perseus2()
+                       || machine_is_omap_osk()) {
+
+               /* LED1/LED2 pins can be used as GPIO (as done here), or by
+                * the LPG (works even in deep sleep!), to drive a bicolor
+                * LED on the H2 sample board, and another on the H2/P2
+                * "surfer" expansion board.
+                *
+                * The same pins drive a LED on the OSK Mistral board, but
+                * that's a different kind of LED (just one color at a time).
+                */
+               omap_cfg_reg(P18_1610_GPIO3);
+               if (omap_request_gpio(3) == 0)
+                       omap_set_gpio_direction(3, 0);
+               else
+                       printk(KERN_WARNING "LED: can't get GPIO3/red?\n");
+
+               omap_cfg_reg(MPUIO4);
+               if (omap_request_gpio(OMAP_MPUIO(4)) == 0)
+                       omap_set_gpio_direction(OMAP_MPUIO(4), 0);
+               else
+                       printk(KERN_WARNING "LED: can't get MPUIO4/green?\n");
+       }
+
+       leds_event(led_start);
+       return 0;
+}
+
+__initcall(omap_leds_init);
diff -urN linux/arch/arm/mach-omap1/leds.h linux/arch/arm/mach-omap1/leds.h
--- linux/arch/arm/mach-omap1/leds.h    1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/leds.h    2005-07-13 12:48:53.457719000 +0100     
1.1
@@ -0,0 +1,3 @@
+extern void innovator_leds_event(led_event_t evt);
+extern void h2p2_dbg_leds_event(led_event_t evt);
+extern void osk_leds_event(led_event_t evt);
diff -urN linux/arch/arm/mach-omap1/serial.c linux/arch/arm/mach-omap1/serial.c
--- linux/arch/arm/mach-omap1/serial.c  1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/serial.c  2005-07-13 12:48:53.472598000 +0100     
1.1
@@ -0,0 +1,200 @@
+/*
+ * linux/arch/arm/mach-omap1/id.c
+ *
+ * OMAP1 CPU identification code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_reg.h>
+
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/clock.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/fpga.h>
+
+static struct clk * uart1_ck = NULL;
+static struct clk * uart2_ck = NULL;
+static struct clk * uart3_ck = NULL;
+
+static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
+                                         int offset)
+{
+       offset <<= up->regshift;
+       return (unsigned int)__raw_readb(up->membase + offset);
+}
+
+static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
+                                   int value)
+{
+       offset <<= p->regshift;
+       __raw_writeb(value, p->membase + offset);
+}
+
+/*
+ * Internal UARTs need to be initialized for the 8250 autoconfig to work
+ * properly. Note that the TX watermark initialization may not be needed
+ * once the 8250.c watermark handling code is merged.
+ */
+static void __init omap_serial_reset(struct plat_serial8250_port *p)
+{
+       omap_serial_outp(p, UART_OMAP_MDR1, 0x07);      /* disable UART */
+       omap_serial_outp(p, UART_OMAP_SCR, 0x08);       /* TX watermark */
+       omap_serial_outp(p, UART_OMAP_MDR1, 0x00);      /* enable UART */
+
+       if (!cpu_is_omap1510()) {
+               omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
+               while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
+       }
+}
+
+static struct plat_serial8250_port serial_platform_data[] = {
+       {
+               .membase        = (char*)IO_ADDRESS(OMAP_UART1_BASE),
+               .mapbase        = (unsigned long)OMAP_UART1_BASE,
+               .irq            = INT_UART1,
+               .flags          = UPF_BOOT_AUTOCONF,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = OMAP16XX_BASE_BAUD * 16,
+       },
+       {
+               .membase        = (char*)IO_ADDRESS(OMAP_UART2_BASE),
+               .mapbase        = (unsigned long)OMAP_UART2_BASE,
+               .irq            = INT_UART2,
+               .flags          = UPF_BOOT_AUTOCONF,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = OMAP16XX_BASE_BAUD * 16,
+       },
+       {
+               .membase        = (char*)IO_ADDRESS(OMAP_UART3_BASE),
+               .mapbase        = (unsigned long)OMAP_UART3_BASE,
+               .irq            = INT_UART3,
+               .flags          = UPF_BOOT_AUTOCONF,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = OMAP16XX_BASE_BAUD * 16,
+       },
+       { },
+};
+
+static struct platform_device serial_device = {
+       .name                   = "serial8250",
+       .id                     = 0,
+       .dev                    = {
+               .platform_data  = serial_platform_data,
+       },
+};
+
+/*
+ * Note that on Innovator-1510 UART2 pins conflict with USB2.
+ * By default UART2 does not work on Innovator-1510 if you have
+ * USB OHCI enabled. To use UART2, you must disable USB2 first.
+ */
+void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS])
+{
+       int i;
+
+       if (cpu_is_omap730()) {
+               serial_platform_data[0].regshift = 0;
+               serial_platform_data[1].regshift = 0;
+               serial_platform_data[0].irq = INT_730_UART_MODEM_1;
+               serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
+       }
+
+       if (cpu_is_omap1510()) {
+               serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
+               serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
+               serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
+       }
+
+       for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+               unsigned char reg;
+
+               if (ports[i] == 0) {
+                       serial_platform_data[i].membase = NULL;
+                       serial_platform_data[i].mapbase = 0;
+                       continue;
+               }
+
+               switch (i) {
+               case 0:
+                       uart1_ck = clk_get(NULL, "uart1_ck");
+                       if (IS_ERR(uart1_ck))
+                               printk("Could not get uart1_ck\n");
+                       else {
+                               clk_use(uart1_ck);
+                               if (cpu_is_omap1510())
+                                       clk_set_rate(uart1_ck, 12000000);
+                       }
+                       if (cpu_is_omap1510()) {
+                               omap_cfg_reg(UART1_TX);
+                               omap_cfg_reg(UART1_RTS);
+                               if (machine_is_omap_innovator()) {
+                                       reg = fpga_read(OMAP1510_FPGA_POWER);
+                                       reg |= OMAP1510_FPGA_PCR_COM1_EN;
+                                       fpga_write(reg, OMAP1510_FPGA_POWER);
+                                       udelay(10);
+                               }
+                       }
+                       break;
+               case 1:
+                       uart2_ck = clk_get(NULL, "uart2_ck");
+                       if (IS_ERR(uart2_ck))
+                               printk("Could not get uart2_ck\n");
+                       else {
+                               clk_use(uart2_ck);
+                               if (cpu_is_omap1510())
+                                       clk_set_rate(uart2_ck, 12000000);
+                               else
+                                       clk_set_rate(uart2_ck, 48000000);
+                       }
+                       if (cpu_is_omap1510()) {
+                               omap_cfg_reg(UART2_TX);
+                               omap_cfg_reg(UART2_RTS);
+                               if (machine_is_omap_innovator()) {
+                                       reg = fpga_read(OMAP1510_FPGA_POWER);
+                                       reg |= OMAP1510_FPGA_PCR_COM2_EN;
+                                       fpga_write(reg, OMAP1510_FPGA_POWER);
+                                       udelay(10);
+                               }
+                       }
+                       break;
+               case 2:
+                       uart3_ck = clk_get(NULL, "uart3_ck");
+                       if (IS_ERR(uart3_ck))
+                               printk("Could not get uart3_ck\n");
+                       else {
+                               clk_use(uart3_ck);
+                               if (cpu_is_omap1510())
+                                       clk_set_rate(uart3_ck, 12000000);
+                       }
+                       if (cpu_is_omap1510()) {
+                               omap_cfg_reg(UART3_TX);
+                               omap_cfg_reg(UART3_RX);
+                       }
+                       break;
+               }
+               omap_serial_reset(&serial_platform_data[i]);
+       }
+}
+
+static int __init omap_init(void)
+{
+       return platform_device_register(&serial_device);
+}
+arch_initcall(omap_init);
diff -urN linux/arch/arm/mach-omap1/time.c linux/arch/arm/mach-omap1/time.c
--- linux/arch/arm/mach-omap1/time.c    1970/01/01 00:00:00
+++ linux/arch/arm/mach-omap1/time.c    2005-07-13 12:48:53.488048000 +0100     
1.1
@@ -0,0 +1,436 @@
+/*
+ * linux/arch/arm/mach-omap1/time.c
+ *
+ * OMAP Timers
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Partial timer rewrite and additional dynamic tick timer support by
+ * Tony Lindgen <tony@atomide.com> and
+ * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *
+ * MPU timer code based on the older MPU timer code for OMAP
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/leds.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+
+struct sys_timer omap_timer;
+
+#ifdef CONFIG_OMAP_MPU_TIMER
+
+/*
+ * ---------------------------------------------------------------------------
+ * MPU timer
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP_MPU_TIMER_BASE            OMAP_MPU_TIMER1_BASE
+#define OMAP_MPU_TIMER_OFFSET          0x100
+
+/* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c,
+ * converted to use kHz by Kevin Hilman */
+/* convert from cycles(64bits) => nanoseconds (64bits)
+ *  basic equation:
+ *             ns = cycles / (freq / ns_per_sec)
+ *             ns = cycles * (ns_per_sec / freq)
+ *             ns = cycles * (10^9 / (cpu_khz * 10^3))
+ *             ns = cycles * (10^6 / cpu_khz)
+ *
+ *     Then we use scaling math (suggested by george at mvista.com) to get:
+ *             ns = cycles * (10^6 * SC / cpu_khz / SC
+ *             ns = cycles * cyc2ns_scale / SC
+ *
+ *     And since SC is a constant power of two, we can convert the div
+ *  into a shift.
+ *                     -johnstul at us.ibm.com "math is hard, lets go 
shopping!"
+ */
+static unsigned long cyc2ns_scale;
+#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
+
+static inline void set_cyc2ns_scale(unsigned long cpu_khz)
+{
+       cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
+}
+
+static inline unsigned long long cycles_2_ns(unsigned long long cyc)
+{
+       return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
+}
+
+/*
+ * MPU_TICKS_PER_SEC must be an even number, otherwise machinecycles_to_usecs
+ * will break. On P2, the timer count rate is 6.5 MHz after programming PTV
+ * with 0. This divides the 13MHz input by 2, and is undocumented.
+ */
+#ifdef CONFIG_MACH_OMAP_PERSEUS2
+/* REVISIT: This ifdef construct should be replaced by a query to clock
+ * framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz.
+ */
+#define MPU_TICKS_PER_SEC              (13000000 / 2)
+#else
+#define MPU_TICKS_PER_SEC              (12000000 / 2)
+#endif
+
+#define MPU_TIMER_TICK_PERIOD          ((MPU_TICKS_PER_SEC / HZ) - 1)
+
+typedef struct {
+       u32 cntl;                       /* CNTL_TIMER, R/W */
+       u32 load_tim;                   /* LOAD_TIM,   W */
+       u32 read_tim;                   /* READ_TIM,   R */
+} omap_mpu_timer_regs_t;
+
+#define omap_mpu_timer_base(n)                                         \
+((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE +     \
+                                (n)*OMAP_MPU_TIMER_OFFSET))
+
+static inline unsigned long omap_mpu_timer_read(int nr)
+{
+       volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
+       return timer->read_tim;
+}
+
+static inline void omap_mpu_timer_start(int nr, unsigned long load_val)
+{
+       volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
+
+       timer->cntl = MPU_TIMER_CLOCK_ENABLE;
+       udelay(1);
+       timer->load_tim = load_val;
+        udelay(1);
+       timer->cntl = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST);
+}
+
+unsigned long omap_mpu_timer_ticks_to_usecs(unsigned long nr_ticks)
+{
+       unsigned long long nsec;
+
+       nsec = cycles_2_ns((unsigned long long)nr_ticks);
+       return (unsigned long)nsec / 1000;
+}
+
+/*
+ * Last processed system timer interrupt
+ */
+static unsigned long omap_mpu_timer_last = 0;
+
+/*
+ * Returns elapsed usecs since last system timer interrupt
+ */
+static unsigned long omap_mpu_timer_gettimeoffset(void)
+{
+       unsigned long now = 0 - omap_mpu_timer_read(0);
+       unsigned long elapsed = now - omap_mpu_timer_last;
+
+       return omap_mpu_timer_ticks_to_usecs(elapsed);
+}
+
+/*
+ * Elapsed time between interrupts is calculated using timer0.
+ * Latency during the interrupt is calculated using timer1.
+ * Both timer0 and timer1 are counting at 6MHz (P2 6.5MHz).
+ */
+static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id,
+                                       struct pt_regs *regs)
+{
+       unsigned long now, latency;
+
+       write_seqlock(&xtime_lock);
+       now = 0 - omap_mpu_timer_read(0);
+       latency = MPU_TICKS_PER_SEC / HZ - omap_mpu_timer_read(1);
+       omap_mpu_timer_last = now - latency;
+       timer_tick(regs);
+       write_sequnlock(&xtime_lock);
+
+       return IRQ_HANDLED;
+}
+
+static struct irqaction omap_mpu_timer_irq = {
+       .name           = "mpu timer",
+       .flags          = SA_INTERRUPT | SA_TIMER,
+       .handler        = omap_mpu_timer_interrupt,
+};
+
+static unsigned long omap_mpu_timer1_overflows;
+static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id,
+                                            struct pt_regs *regs)
+{
+       omap_mpu_timer1_overflows++;
+       return IRQ_HANDLED;
+}
+
+static struct irqaction omap_mpu_timer1_irq = {
+       .name           = "mpu timer1 overflow",
+       .flags          = SA_INTERRUPT,
+       .handler        = omap_mpu_timer1_interrupt,
+};
+
+static __init void omap_init_mpu_timer(void)
+{
+       set_cyc2ns_scale(MPU_TICKS_PER_SEC / 1000);
+       omap_timer.offset = omap_mpu_timer_gettimeoffset;
+       setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
+       setup_irq(INT_TIMER2, &omap_mpu_timer_irq);
+       omap_mpu_timer_start(0, 0xffffffff);
+       omap_mpu_timer_start(1, MPU_TIMER_TICK_PERIOD);
+}
+
+/*
+ * Scheduler clock - returns current time in nanosec units.
+ */
+unsigned long long sched_clock(void)
+{
+       unsigned long ticks = 0 - omap_mpu_timer_read(0);
+       unsigned long long ticks64;
+
+       ticks64 = omap_mpu_timer1_overflows;
+       ticks64 <<= 32;
+       ticks64 |= ticks;
+
+       return cycles_2_ns(ticks64);
+}
+#endif /* CONFIG_OMAP_MPU_TIMER */
+
+#ifdef CONFIG_OMAP_32K_TIMER
+
+#ifdef CONFIG_ARCH_OMAP1510
+#error OMAP 32KHz timer does not currently work on 1510!
+#endif
+
+/*
+ * ---------------------------------------------------------------------------
+ * 32KHz OS timer
+ *
+ * This currently works only on 16xx, as 1510 does not have the continuous
+ * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
+ * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
+ * on 1510 would be possible, but the timer would not be as accurate as
+ * with the 32KHz synchronized timer.
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP_32K_TIMER_BASE            0xfffb9000
+#define OMAP_32K_TIMER_CR              0x08
+#define OMAP_32K_TIMER_TVR             0x00
+#define OMAP_32K_TIMER_TCR             0x04
+
+#define OMAP_32K_TICKS_PER_HZ          (32768 / HZ)
+#if (32768 % HZ) != 0
+/* We cannot ignore modulo.
+ * Potential error can be as high as several percent.
+ */
+#define OMAP_32K_TICK_MODULO           (32768 % HZ)
+static unsigned modulo_count = 0; /* Counts 1/HZ units */
+#endif
+
+/*
+ * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
+ * so with HZ = 100, TVR = 327.68.
+ */
+#define OMAP_32K_TIMER_TICK_PERIOD     ((32768 / HZ) - 1)
+#define TIMER_32K_SYNCHRONIZED         0xfffbc410
+
+#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate)                    \
+                               (((nr_jiffies) * (clock_rate)) / HZ)
+
+static inline void omap_32k_timer_write(int val, int reg)
+{
+       omap_writew(val, reg + OMAP_32K_TIMER_BASE);
+}
+
+static inline unsigned long omap_32k_timer_read(int reg)
+{
+       return omap_readl(reg + OMAP_32K_TIMER_BASE) & 0xffffff;
+}
+
+/*
+ * The 32KHz synchronized timer is an additional timer on 16xx.
+ * It is always running.
+ */
+static inline unsigned long omap_32k_sync_timer_read(void)
+{
+       return omap_readl(TIMER_32K_SYNCHRONIZED);
+}
+
+static inline void omap_32k_timer_start(unsigned long load_val)
+{
+       omap_32k_timer_write(load_val, OMAP_32K_TIMER_TVR);
+       omap_32k_timer_write(0x0f, OMAP_32K_TIMER_CR);
+}
+
+static inline void omap_32k_timer_stop(void)
+{
+       omap_32k_timer_write(0x0, OMAP_32K_TIMER_CR);
+}
+
+/*
+ * Rounds down to nearest usec
+ */
+static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
+{
+       return (ticks_32k * 5*5*5*5*5*5) >> 9;
+}
+
+static unsigned long omap_32k_last_tick = 0;
+
+/*
+ * Returns elapsed usecs since last 32k timer interrupt
+ */
+static unsigned long omap_32k_timer_gettimeoffset(void)
+{
+       unsigned long now = omap_32k_sync_timer_read();
+       return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
+}
+
+/*
+ * Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
+ * function is also called from other interrupts to remove latency
+ * issues with dynamic tick. In the dynamic tick case, we need to lock
+ * with irqsave.
+ */
+static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
+                                           struct pt_regs *regs)
+{
+       unsigned long flags;
+       unsigned long now;
+
+       write_seqlock_irqsave(&xtime_lock, flags);
+       now = omap_32k_sync_timer_read();
+
+       while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) {
+#ifdef OMAP_32K_TICK_MODULO
+               /* Modulo addition may put omap_32k_last_tick ahead of now
+                * and cause unwanted repetition of the while loop.
+                */
+               if (unlikely(now - omap_32k_last_tick == ~0))
+                       break;
+
+               modulo_count += OMAP_32K_TICK_MODULO;
+               if (modulo_count > HZ) {
+                       ++omap_32k_last_tick;
+                       modulo_count -= HZ;
+               }
+#endif
+               omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
+               timer_tick(regs);
+       }
+
+       /* Restart timer so we don't drift off due to modulo or dynamic tick.
+        * By default we program the next timer to be continuous to avoid
+        * latencies during high system load. During dynamic tick operation the
+        * continuous timer can be overridden from pm_idle to be longer.
+        */
+       omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
+       write_sequnlock_irqrestore(&xtime_lock, flags);
+
+       return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NO_IDLE_HZ
+/*
+ * Programs the next timer interrupt needed. Called when dynamic tick is
+ * enabled, and to reprogram the ticks to skip from pm_idle. Note that
+ * we can keep the timer continuous, and don't need to set it to run in
+ * one-shot mode. This is because the timer will get reprogrammed again
+ * after next interrupt.
+ */
+void omap_32k_timer_reprogram(unsigned long next_tick)
+{
+       omap_32k_timer_start(JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1);
+}
+
+static struct irqaction omap_32k_timer_irq;
+extern struct timer_update_handler timer_update;
+
+static int omap_32k_timer_enable_dyn_tick(void)
+{
+       /* No need to reprogram timer, just use the next interrupt */
+       return 0;
+}
+
+static int omap_32k_timer_disable_dyn_tick(void)
+{
+       omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
+       return 0;
+}
+
+static struct dyn_tick_timer omap_dyn_tick_timer = {
+       .enable         = omap_32k_timer_enable_dyn_tick,
+       .disable        = omap_32k_timer_disable_dyn_tick,
+       .reprogram      = omap_32k_timer_reprogram,
+       .handler        = omap_32k_timer_interrupt,
+};
+#endif /* CONFIG_NO_IDLE_HZ */
+
+static struct irqaction omap_32k_timer_irq = {
+       .name           = "32KHz timer",
+       .flags          = SA_INTERRUPT | SA_TIMER,
+       .handler        = omap_32k_timer_interrupt,
+};
+
+static __init void omap_init_32k_timer(void)
+{
+
+#ifdef CONFIG_NO_IDLE_HZ
+       omap_timer.dyn_tick = &omap_dyn_tick_timer;
+#endif
+
+       setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
+       omap_timer.offset  = omap_32k_timer_gettimeoffset;
+       omap_32k_last_tick = omap_32k_sync_timer_read();
+       omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
+}
+#endif /* CONFIG_OMAP_32K_TIMER */
+
+/*
+ * ---------------------------------------------------------------------------
+ * Timer initialization
+ * ---------------------------------------------------------------------------
+ */
+static void __init omap_timer_init(void)
+{
+#if defined(CONFIG_OMAP_MPU_TIMER)
+       omap_init_mpu_timer();
+#elif defined(CONFIG_OMAP_32K_TIMER)
+       omap_init_32k_timer();
+#else
+#error No system timer selected in Kconfig!
+#endif
+}
+
+struct sys_timer omap_timer = {
+       .init           = omap_timer_init,
+       .offset         = NULL,         /* Initialized later */
+};
diff -urN linux/arch/arm/mm/Kconfig linux/arch/arm/mm/Kconfig
--- linux/arch/arm/mm/Kconfig   2005/07/11 20:46:04     1.20
+++ linux/arch/arm/mm/Kconfig   2005/07/13 11:48:53     1.21
@@ -101,7 +101,7 @@
 
 # ARM925T
 config CPU_ARM925T
-       bool "Support ARM925T processor" if ARCH_OMAP
+       bool "Support ARM925T processor" if ARCH_OMAP1
        depends on ARCH_OMAP1510
        default y if ARCH_OMAP1510
        select CPU_32v4
diff -urN linux/arch/arm/mm/mm-armv.c linux/arch/arm/mm/mm-armv.c
--- linux/arch/arm/mm/mm-armv.c 2005/07/12 09:19:00     1.50
+++ linux/arch/arm/mm/mm-armv.c 2005/07/13 11:48:53     1.51
@@ -399,7 +399,7 @@
                ecc_mask = 0;
        }
 
-       if (cpu_arch <= CPU_ARCH_ARMv5) {
+       if (cpu_arch <= CPU_ARCH_ARMv5TEJ) {
                for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
                        if (mem_types[i].prot_l1)
                                mem_types[i].prot_l1 |= PMD_BIT4;
@@ -584,7 +584,7 @@
                pmdval = (i << PGDIR_SHIFT) |
                         PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
                         PMD_TYPE_SECT;
-               if (cpu_arch <= CPU_ARCH_ARMv5)
+               if (cpu_arch <= CPU_ARCH_ARMv5TEJ)
                        pmdval |= PMD_BIT4;
                pmd = pmd_off(pgd, i << PGDIR_SHIFT);
                pmd[0] = __pmd(pmdval);
diff -urN linux/arch/arm/mm/proc-v6.S linux/arch/arm/mm/proc-v6.S
--- linux/arch/arm/mm/proc-v6.S 2005/07/11 20:46:04     1.7
+++ linux/arch/arm/mm/proc-v6.S 2005/07/13 11:48:53     1.8
@@ -200,7 +200,7 @@
        mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
 #ifdef CONFIG_VFP
        mrc     p15, 0, r0, c1, c0, 2
-       orr     r0, r0, #(3 << 20)
+       orr     r0, r0, #(0xf << 20)
        mcr     p15, 0, r0, c1, c0, 2           @ Enable full access to VFP
 #endif
        mrc     p15, 0, r0, c1, c0, 0           @ read control register
diff -urN linux/arch/arm/plat-omap/Kconfig linux/arch/arm/plat-omap/Kconfig
--- linux/arch/arm/plat-omap/Kconfig    1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/Kconfig    2005-07-13 12:48:53.769494000 +0100     
1.1
@@ -0,0 +1,112 @@
+if ARCH_OMAP
+
+menu "TI OMAP Implementations"
+
+config ARCH_OMAP_OTG
+       bool
+
+choice
+       prompt "OMAP System Type"
+       default ARCH_OMAP1
+
+config ARCH_OMAP1
+       bool "TI OMAP1"
+
+config ARCH_OMAP2
+       bool "TI OMAP2"
+
+endchoice
+
+comment "OMAP Feature Selections"
+
+config OMAP_RESET_CLOCKS
+       bool "Reset unused clocks during boot"
+       depends on ARCH_OMAP
+       default n
+       help
+         Say Y if you want to reset unused clocks during boot.
+         This option saves power, but assumes all drivers are
+         using the clock framework. Broken drivers that do not
+         yet use clock framework may not work with this option.
+         If you are booting from another operating system, you
+         probably do not want this option enabled until your
+         device drivers work properly.
+
+config OMAP_MUX
+       bool "OMAP multiplexing support"
+        depends on ARCH_OMAP
+       default y
+        help
+          Pin multiplexing support for OMAP boards. If your bootloader
+          sets the multiplexing correctly, say N. Otherwise, or if unsure,
+          say Y.
+
+config OMAP_MUX_DEBUG
+       bool "Multiplexing debug output"
+        depends on OMAP_MUX
+        default n
+        help
+          Makes the multiplexing functions print out a lot of debug info.
+          This is useful if you want to find out the correct values of the
+          multiplexing registers.
+
+config OMAP_MUX_WARNINGS
+       bool "Warn about pins the bootloader didn't set up"
+        depends on OMAP_MUX
+        default y
+        help
+         Choose Y here to warn whenever driver initialization logic needs
+         to change the pin multiplexing setup.  When there are no warnings
+         printed, it's safe to deselect OMAP_MUX for your product.
+
+choice
+        prompt "System timer"
+       default OMAP_MPU_TIMER
+
+config OMAP_MPU_TIMER
+       bool "Use mpu timer"
+       help
+         Select this option if you want to use the OMAP mpu timer. This
+         timer provides more intra-tick resolution than the 32KHz timer,
+         but consumes more power.
+
+config OMAP_32K_TIMER
+       bool "Use 32KHz timer"
+       depends on ARCH_OMAP16XX
+       help
+         Select this option if you want to enable the OMAP 32KHz timer.
+         This timer saves power compared to the OMAP_MPU_TIMER, and has
+         support for no tick during idle. The 32KHz timer provides less
+         intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
+         currently only available for OMAP-16xx.
+
+endchoice
+
+config OMAP_32K_TIMER_HZ
+       int "Kernel internal timer frequency for 32KHz timer"
+       range 32 1024
+       depends on OMAP_32K_TIMER
+       default "128"
+       help
+         Kernel internal timer frequency should be a divisor of 32768,
+         such as 64 or 128.
+
+choice
+       prompt "Low-level debug console UART"
+       depends on ARCH_OMAP
+       default OMAP_LL_DEBUG_UART1
+
+config OMAP_LL_DEBUG_UART1
+       bool "UART1"
+
+config OMAP_LL_DEBUG_UART2
+       bool "UART2"
+
+config OMAP_LL_DEBUG_UART3
+       bool "UART3"
+
+endchoice
+
+endmenu
+
+endif
diff -urN linux/arch/arm/plat-omap/Makefile linux/arch/arm/plat-omap/Makefile
--- linux/arch/arm/plat-omap/Makefile   1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/Makefile   2005-07-13 12:48:53.791189000 +0100     
1.1
@@ -0,0 +1,17 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common support
+obj-y := common.o dma.o clock.o mux.o gpio.o mcbsp.o usb.o
+obj-m :=
+obj-n :=
+obj-  :=
+
+# OCPI interconnect support for 1710, 1610 and 5912
+obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
+
+# Power Management
+obj-$(CONFIG_PM) += pm.o sleep.o
+
+obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
diff -urN linux/arch/arm/plat-omap/clock.c linux/arch/arm/plat-omap/clock.c
--- linux/arch/arm/plat-omap/clock.c    1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/clock.c    2005-07-13 12:48:53.811901000 +0100     
1.1
@@ -0,0 +1,1323 @@
+/*
+ *  linux/arch/arm/plat-omap/clock.c
+ *
+ *  Copyright (C) 2004 Nokia corporation
+ *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+
+#include <asm/io.h>
+#include <asm/semaphore.h>
+#include <asm/hardware/clock.h>
+#include <asm/arch/board.h>
+#include <asm/arch/usb.h>
+
+#include "clock.h"
+
+static LIST_HEAD(clocks);
+static DECLARE_MUTEX(clocks_sem);
+static DEFINE_SPINLOCK(clockfw_lock);
+static void propagate_rate(struct clk *  clk);
+/* UART clock function */
+static int set_uart_rate(struct clk * clk, unsigned long rate);
+/* External clock (MCLK & BCLK) functions */
+static int set_ext_clk_rate(struct clk *  clk, unsigned long rate);
+static long round_ext_clk_rate(struct clk *  clk, unsigned long rate);
+static void init_ext_clk(struct clk *  clk);
+/* MPU virtual clock functions */
+static int select_table_rate(struct clk *  clk, unsigned long rate);
+static long round_to_table_rate(struct clk *  clk, unsigned long rate);
+void clk_setdpll(__u16, __u16);
+
+static struct mpu_rate rate_table[] = {
+       /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
+        * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
+        */
+#if defined(CONFIG_OMAP_ARM_216MHZ)
+       { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_195MHZ)
+       { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_192MHZ)
+       { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
+       { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
+       {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
+       {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/8/4/4/8/8 */
+       {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_182MHZ)
+       { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_168MHZ)
+       { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_150MHZ)
+       { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
+#endif
+#if defined(CONFIG_OMAP_ARM_120MHZ)
+       { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
+#endif
+#if defined(CONFIG_OMAP_ARM_96MHZ)
+       {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
+#endif
+#if defined(CONFIG_OMAP_ARM_60MHZ)
+       {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
+#endif
+#if defined(CONFIG_OMAP_ARM_30MHZ)
+       {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
+#endif
+       { 0, 0, 0, 0, 0 },
+};
+
+
+static void ckctl_recalc(struct clk *  clk);
+int __clk_enable(struct clk *clk);
+void __clk_disable(struct clk *clk);
+void __clk_unuse(struct clk *clk);
+int __clk_use(struct clk *clk);
+
+
+static void followparent_recalc(struct clk *  clk)
+{
+       clk->rate = clk->parent->rate;
+}
+
+
+static void watchdog_recalc(struct clk *  clk)
+{
+       clk->rate = clk->parent->rate / 14;
+}
+
+static void uart_recalc(struct clk * clk)
+{
+       unsigned int val = omap_readl(clk->enable_reg);
+       if (val & clk->enable_bit)
+               clk->rate = 48000000;
+       else
+               clk->rate = 12000000;
+}
+
+static struct clk ck_ref = {
+       .name           = "ck_ref",
+       .rate           = 12000000,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+                         ALWAYS_ENABLED,
+};
+
+static struct clk ck_dpll1 = {
+       .name           = "ck_dpll1",
+       .parent         = &ck_ref,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+                         RATE_PROPAGATES | ALWAYS_ENABLED,
+};
+
+static struct clk ck_dpll1out = {
+       .name           = "ck_dpll1out",
+       .parent         = &ck_dpll1,
+       .flags          = CLOCK_IN_OMAP16XX,
+       .enable_reg     = ARM_IDLECT2,
+       .enable_bit     = EN_CKOUT_ARM,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk arm_ck = {
+       .name           = "arm_ck",
+       .parent         = &ck_dpll1,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+                         RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .rate_offset    = CKCTL_ARMDIV_OFFSET,
+       .recalc         = &ckctl_recalc,
+};
+
+static struct clk armper_ck = {
+       .name           = "armper_ck",
+       .parent         = &ck_dpll1,
+       .flags          = CLOCK_IN_OMAP730 | CLOCK_IN_OMAP1510 | 
CLOCK_IN_OMAP16XX |
+                         RATE_CKCTL,
+       .enable_reg     = ARM_IDLECT2,
+       .enable_bit     = EN_PERCK,
+       .rate_offset    = CKCTL_PERDIV_OFFSET,
+       .recalc         = &ckctl_recalc,
+};
+
+static struct clk arm_gpio_ck = {
+       .name           = "arm_gpio_ck",
+       .parent         = &ck_dpll1,
+       .flags          = CLOCK_IN_OMAP1510,
+       .enable_reg     = ARM_IDLECT2,
+       .enable_bit     = EN_GPIOCK,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk armxor_ck = {
+       .name           = "armxor_ck",
+       .parent         = &ck_ref,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
+       .enable_reg     = ARM_IDLECT2,
+       .enable_bit     = EN_XORPCK,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk armtim_ck = {
+       .name           = "armtim_ck",
+       .parent         = &ck_ref,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
+       .enable_reg     = ARM_IDLECT2,
+       .enable_bit     = EN_TIMCK,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk armwdt_ck = {
+       .name           = "armwdt_ck",
+       .parent         = &ck_ref,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
+       .enable_reg     = ARM_IDLECT2,
+       .enable_bit     = EN_WDTCK,
+       .recalc         = &watchdog_recalc,
+};
+
+static struct clk arminth_ck16xx = {
+       .name           = "arminth_ck",
+       .parent         = &arm_ck,
+       .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
+       .recalc         = &followparent_recalc,
+       /* Note: On 16xx the frequency can be divided by 2 by programming
+        * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
+        *
+        * 1510 version is in TC clocks.
+        */
+};
+
+static struct clk dsp_ck = {
+       .name           = "dsp_ck",
+       .parent         = &ck_dpll1,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+                         RATE_CKCTL,
+       .enable_reg     = ARM_CKCTL,
+       .enable_bit     = EN_DSPCK,
+       .rate_offset    = CKCTL_DSPDIV_OFFSET,
+       .recalc         = &ckctl_recalc,
+};
+
+static struct clk dspmmu_ck = {
+       .name           = "dspmmu_ck",
+       .parent         = &ck_dpll1,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+                         RATE_CKCTL | ALWAYS_ENABLED,
+       .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
+       .recalc         = &ckctl_recalc,
+};
+
+static struct clk dspper_ck = {
+       .name           = "dspper_ck",
+       .parent         = &ck_dpll1,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+                         RATE_CKCTL | DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
+       .enable_reg     = DSP_IDLECT2,
+       .enable_bit     = EN_PERCK,
+       .rate_offset    = CKCTL_PERDIV_OFFSET,
+       .recalc         = &followparent_recalc,
+       //.recalc               = &ckctl_recalc,
+};
+
+static struct clk dspxor_ck = {
+       .name           = "dspxor_ck",
+       .parent         = &ck_ref,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+                         DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
+       .enable_reg     = DSP_IDLECT2,
+       .enable_bit     = EN_XORPCK,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk dsptim_ck = {
+       .name           = "dsptim_ck",
+       .parent         = &ck_ref,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+                         DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
+       .enable_reg     = DSP_IDLECT2,
+       .enable_bit     = EN_DSPTIMCK,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk tc_ck = {
+       .name           = "tc_ck",
+       .parent         = &ck_dpll1,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 
CLOCK_IN_OMAP730 |
+                         RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .rate_offset    = CKCTL_TCDIV_OFFSET,
+       .recalc         = &ckctl_recalc,
+};
+
+static struct clk arminth_ck1510 = {
+       .name           = "arminth_ck",
+       .parent         = &tc_ck,
+       .flags          = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
+       .recalc         = &followparent_recalc,
+       /* Note: On 1510 the frequency follows TC_CK
+        *
+        * 16xx version is in MPU clocks.
+        */
+};
+
+static struct clk tipb_ck = {
+       .name           = "tibp_ck",
+       .parent         = &tc_ck,
+       .flags          = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk l3_ocpi_ck = {
+       .name           = "l3_ocpi_ck",
+       .parent         = &tc_ck,
+       .flags          = CLOCK_IN_OMAP16XX,
+       .enable_reg     = ARM_IDLECT3,
+       .enable_bit     = EN_OCPI_CK,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk tc1_ck = {
+       .name           = "tc1_ck",
+       .parent         = &tc_ck,
+       .flags          = CLOCK_IN_OMAP16XX,
+       .enable_reg     = ARM_IDLECT3,
+       .enable_bit     = EN_TC1_CK,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk tc2_ck = {
+       .name           = "tc2_ck",
+       .parent         = &tc_ck,
+       .flags          = CLOCK_IN_OMAP16XX,
+       .enable_reg     = ARM_IDLECT3,
+       .enable_bit     = EN_TC2_CK,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk dma_ck = {
+       .name           = "dma_ck",
+       .parent         = &tc_ck,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+                         ALWAYS_ENABLED,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk dma_lcdfree_ck = {
+       .name           = "dma_lcdfree_ck",
+       .parent         = &tc_ck,
+       .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk api_ck = {
+       .name           = "api_ck",
+       .parent         = &tc_ck,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
+       .enable_reg     = ARM_IDLECT2,
+       .enable_bit     = EN_APICK,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk lb_ck = {
+       .name           = "lb_ck",
+       .parent         = &tc_ck,
+       .flags          = CLOCK_IN_OMAP1510,
+       .enable_reg     = ARM_IDLECT2,
+       .enable_bit     = EN_LBCK,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk rhea1_ck = {
+       .name           = "rhea1_ck",
+       .parent         = &tc_ck,
+       .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk rhea2_ck = {
+       .name           = "rhea2_ck",
+       .parent         = &tc_ck,
+       .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk lcd_ck = {
+       .name           = "lcd_ck",
+       .parent         = &ck_dpll1,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 
CLOCK_IN_OMAP730 |
+                         RATE_CKCTL,
+       .enable_reg     = ARM_IDLECT2,
+       .enable_bit     = EN_LCDCK,
+       .rate_offset    = CKCTL_LCDDIV_OFFSET,
+       .recalc         = &ckctl_recalc,
+};
+
+static struct clk uart1_1510 = {
+       .name           = "uart1_ck",
+       /* Direct from ULPD, no parent */
+       .rate           = 12000000,
+       .flags          = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
+       .enable_reg     = MOD_CONF_CTRL_0,
+       .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
+       .set_rate       = &set_uart_rate,
+       .recalc         = &uart_recalc,
+};
+
+static struct clk uart1_16xx = {
+       .name           = "uart1_ck",
+       /* Direct from ULPD, no parent */
+       .rate           = 48000000,
+       .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
+       .enable_reg     = MOD_CONF_CTRL_0,
+       .enable_bit     = 29,
+};
+
+static struct clk uart2_ck = {
+       .name           = "uart2_ck",
+       /* Direct from ULPD, no parent */
+       .rate           = 12000000,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 
ENABLE_REG_32BIT,
+       .enable_reg     = MOD_CONF_CTRL_0,
+       .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
+       .set_rate       = &set_uart_rate,
+       .recalc         = &uart_recalc,
+};
+
+static struct clk uart3_1510 = {
+       .name           = "uart3_ck",
+       /* Direct from ULPD, no parent */
+       .rate           = 12000000,
+       .flags          = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
+       .enable_reg     = MOD_CONF_CTRL_0,
+       .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
+       .set_rate       = &set_uart_rate,
+       .recalc         = &uart_recalc,
+};
+
+static struct clk uart3_16xx = {
+       .name           = "uart3_ck",
+       /* Direct from ULPD, no parent */
+       .rate           = 48000000,
+       .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
+       .enable_reg     = MOD_CONF_CTRL_0,
+       .enable_bit     = 31,
+};
+
+static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
+       .name           = "usb_clko",
+       /* Direct from ULPD, no parent */
+       .rate           = 6000000,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+                         RATE_FIXED | ENABLE_REG_32BIT,
+       .enable_reg     = ULPD_CLOCK_CTRL,
+       .enable_bit     = USB_MCLK_EN_BIT,
+};
+
+static struct clk usb_hhc_ck1510 = {
+       .name           = "usb_hhc_ck",
+       /* Direct from ULPD, no parent */
+       .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
+       .flags          = CLOCK_IN_OMAP1510 |
+                         RATE_FIXED | ENABLE_REG_32BIT,
+       .enable_reg     = MOD_CONF_CTRL_0,
+       .enable_bit     = USB_HOST_HHC_UHOST_EN,
+};
+
+static struct clk usb_hhc_ck16xx = {
+       .name           = "usb_hhc_ck",
+       /* Direct from ULPD, no parent */
+       .rate           = 48000000,
+       /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
+       .flags          = CLOCK_IN_OMAP16XX |
+                         RATE_FIXED | ENABLE_REG_32BIT,
+       .enable_reg     = OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
+       .enable_bit     = 8 /* UHOST_EN */,
+};
+
+static struct clk mclk_1510 = {
+       .name           = "mclk",
+       /* Direct from ULPD, no parent. May be enabled by ext hardware. */
+       .rate           = 12000000,
+       .flags          = CLOCK_IN_OMAP1510 | RATE_FIXED,
+};
+
+static struct clk mclk_16xx = {
+       .name           = "mclk",
+       /* Direct from ULPD, no parent. May be enabled by ext hardware. */
+       .flags          = CLOCK_IN_OMAP16XX,
+       .enable_reg     = COM_CLK_DIV_CTRL_SEL,
+       .enable_bit     = COM_ULPD_PLL_CLK_REQ,
+       .set_rate       = &set_ext_clk_rate,
+       .round_rate     = &round_ext_clk_rate,
+       .init           = &init_ext_clk,
+};
+
+static struct clk bclk_1510 = {
+       .name           = "bclk",
+       /* Direct from ULPD, no parent. May be enabled by ext hardware. */
+       .rate           = 12000000,
+       .flags          = CLOCK_IN_OMAP1510 | RATE_FIXED,
+};
+
+static struct clk bclk_16xx = {
+       .name           = "bclk",
+       /* Direct from ULPD, no parent. May be enabled by ext hardware. */
+       .flags          = CLOCK_IN_OMAP16XX,
+       .enable_reg     = SWD_CLK_DIV_CTRL_SEL,
+       .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
+       .set_rate       = &set_ext_clk_rate,
+       .round_rate     = &round_ext_clk_rate,
+       .init           = &init_ext_clk,
+};
+
+static struct clk mmc1_ck = {
+       .name           = "mmc1_ck",
+       /* Functional clock is direct from ULPD, interface clock is ARMPER */
+       .parent         = &armper_ck,
+       .rate           = 48000000,
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+                         RATE_FIXED | ENABLE_REG_32BIT,
+       .enable_reg     = MOD_CONF_CTRL_0,
+       .enable_bit     = 23,
+};
+
+static struct clk mmc2_ck = {
+       .name           = "mmc2_ck",
+       /* Functional clock is direct from ULPD, interface clock is ARMPER */
+       .parent         = &armper_ck,
+       .rate           = 48000000,
+       .flags          = CLOCK_IN_OMAP16XX |
+                         RATE_FIXED | ENABLE_REG_32BIT,
+       .enable_reg     = MOD_CONF_CTRL_0,
+       .enable_bit     = 20,
+};
+
+static struct clk virtual_ck_mpu = {
+       .name           = "mpu",
+       .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
+                         VIRTUAL_CLOCK | ALWAYS_ENABLED,
+       .parent         = &arm_ck, /* Is smarter alias for */
+       .recalc         = &followparent_recalc,
+       .set_rate       = &select_table_rate,
+       .round_rate     = &round_to_table_rate,
+};
+
+
+static struct clk *  onchip_clks[] = {
+       /* non-ULPD clocks */
+       &ck_ref,
+       &ck_dpll1,
+       /* CK_GEN1 clocks */
+       &ck_dpll1out,
+       &arm_ck,
+       &armper_ck,
+       &arm_gpio_ck,
+       &armxor_ck,
+       &armtim_ck,
+       &armwdt_ck,
+       &arminth_ck1510,  &arminth_ck16xx,
+       /* CK_GEN2 clocks */
+       &dsp_ck,
+       &dspmmu_ck,
+       &dspper_ck,
+       &dspxor_ck,
+       &dsptim_ck,
+       /* CK_GEN3 clocks */
+       &tc_ck,
+       &tipb_ck,
+       &l3_ocpi_ck,
+       &tc1_ck,
+       &tc2_ck,
+       &dma_ck,
+       &dma_lcdfree_ck,
+       &api_ck,
+       &lb_ck,
+       &rhea1_ck,
+       &rhea2_ck,
+       &lcd_ck,
+       /* ULPD clocks */
+       &uart1_1510,
+       &uart1_16xx,
+       &uart2_ck,
+       &uart3_1510,
+       &uart3_16xx,
+       &usb_clko,
+       &usb_hhc_ck1510, &usb_hhc_ck16xx,
+       &mclk_1510,  &mclk_16xx,
+       &bclk_1510,  &bclk_16xx,
+       &mmc1_ck,
+       &mmc2_ck,
+       /* Virtual clocks */
+       &virtual_ck_mpu,
+};
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+       struct clk *p, *clk = ERR_PTR(-ENOENT);
+
+       down(&clocks_sem);
+       list_for_each_entry(p, &clocks, node) {
+               if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
+                       clk = p;
+                       break;
+               }
+       }
+       up(&clocks_sem);
+
+       return clk;
+}
+EXPORT_SYMBOL(clk_get);
+
+
+void clk_put(struct clk *clk)
+{
+       if (clk && !IS_ERR(clk))
+               module_put(clk->owner);
+}
+EXPORT_SYMBOL(clk_put);
+
+
+int __clk_enable(struct clk *clk)
+{
+       __u16 regval16;
+       __u32 regval32;
+
+       if (clk->flags & ALWAYS_ENABLED)
+               return 0;
+
+       if (unlikely(clk->enable_reg == 0)) {
+               printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
+                      clk->name);
+               return 0;
+       }
+
+       if (clk->flags & DSP_DOMAIN_CLOCK) {
+               __clk_use(&api_ck);
+       }
+
+       if (clk->flags & ENABLE_REG_32BIT) {
+               if (clk->flags & VIRTUAL_IO_ADDRESS) {
+                       regval32 = __raw_readl(clk->enable_reg);
+                       regval32 |= (1 << clk->enable_bit);
+                       __raw_writel(regval32, clk->enable_reg);
+               } else {
+                       regval32 = omap_readl(clk->enable_reg);
+                       regval32 |= (1 << clk->enable_bit);
+                       omap_writel(regval32, clk->enable_reg);
+               }
+       } else {
+               if (clk->flags & VIRTUAL_IO_ADDRESS) {
+                       regval16 = __raw_readw(clk->enable_reg);
+                       regval16 |= (1 << clk->enable_bit);
+                       __raw_writew(regval16, clk->enable_reg);
+               } else {
+                       regval16 = omap_readw(clk->enable_reg);
+                       regval16 |= (1 << clk->enable_bit);
+                       omap_writew(regval16, clk->enable_reg);
+               }
+       }
+
+       if (clk->flags & DSP_DOMAIN_CLOCK) {
+               __clk_unuse(&api_ck);
+       }
+
+       return 0;
+}
+
+
+void __clk_disable(struct clk *clk)
+{
+       __u16 regval16;
+       __u32 regval32;
+
+       if (clk->enable_reg == 0)
+               return;
+
+       if (clk->flags & DSP_DOMAIN_CLOCK) {
+               __clk_use(&api_ck);
+       }
+
+       if (clk->flags & ENABLE_REG_32BIT) {
+               if (clk->flags & VIRTUAL_IO_ADDRESS) {
+                       regval32 = __raw_readl(clk->enable_reg);
+                       regval32 &= ~(1 << clk->enable_bit);
+                       __raw_writel(regval32, clk->enable_reg);
+               } else {
+                       regval32 = omap_readl(clk->enable_reg);
+                       regval32 &= ~(1 << clk->enable_bit);
+                       omap_writel(regval32, clk->enable_reg);
+               }
+       } else {
+               if (clk->flags & VIRTUAL_IO_ADDRESS) {
+                       regval16 = __raw_readw(clk->enable_reg);
+                       regval16 &= ~(1 << clk->enable_bit);
+                       __raw_writew(regval16, clk->enable_reg);
+               } else {
+                       regval16 = omap_readw(clk->enable_reg);
+                       regval16 &= ~(1 << clk->enable_bit);
+                       omap_writew(regval16, clk->enable_reg);
+               }
+       }
+
+       if (clk->flags & DSP_DOMAIN_CLOCK) {
+               __clk_unuse(&api_ck);
+       }
+}
+
+
+void __clk_unuse(struct clk *clk)
+{
+       if (clk->usecount > 0 && !(--clk->usecount)) {
+               __clk_disable(clk);
+               if (likely(clk->parent))
+                       __clk_unuse(clk->parent);
+       }
+}
+
+
+int __clk_use(struct clk *clk)
+{
+       int ret = 0;
+       if (clk->usecount++ == 0) {
+               if (likely(clk->parent))
+                       ret = __clk_use(clk->parent);
+
+               if (unlikely(ret != 0)) {
+                       clk->usecount--;
+                       return ret;
+               }
+
+               ret = __clk_enable(clk);
+
+               if (unlikely(ret != 0) && clk->parent) {
+                       __clk_unuse(clk->parent);
+                       clk->usecount--;
+               }
+       }
+
+       return ret;
+}
+
+
+int clk_enable(struct clk *clk)
+{
+       unsigned long flags;
+       int ret;
+
+       spin_lock_irqsave(&clockfw_lock, flags);
+       ret = __clk_enable(clk);
+       spin_unlock_irqrestore(&clockfw_lock, flags);
+       return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+
+void clk_disable(struct clk *clk)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&clockfw_lock, flags);
+       __clk_disable(clk);
+       spin_unlock_irqrestore(&clockfw_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+
+int clk_use(struct clk *clk)
+{
+       unsigned long flags;
+       int ret = 0;
+
+       spin_lock_irqsave(&clockfw_lock, flags);
+       ret = __clk_use(clk);
+       spin_unlock_irqrestore(&clockfw_lock, flags);
+       return ret;
+}
+EXPORT_SYMBOL(clk_use);
+
+
+void clk_unuse(struct clk *clk)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&clockfw_lock, flags);
+       __clk_unuse(clk);
+       spin_unlock_irqrestore(&clockfw_lock, flags);
+}
+EXPORT_SYMBOL(clk_unuse);
+
+
+int clk_get_usecount(struct clk *clk)
+{
+        return clk->usecount;
+}
+EXPORT_SYMBOL(clk_get_usecount);
+
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+       return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+
+static __u16 verify_ckctl_value(__u16 newval)
+{
+       /* This function checks for following limitations set
+        * by the hardware (all conditions must be true):
+        * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
+        * ARM_CK >= TC_CK
+        * DSP_CK >= TC_CK
+        * DSPMMU_CK >= TC_CK
+        *
+        * In addition following rules are enforced:
+        * LCD_CK <= TC_CK
+        * ARMPER_CK <= TC_CK
+        *
+        * However, maximum frequencies are not checked for!
+        */
+       __u8 per_exp;
+       __u8 lcd_exp;
+       __u8 arm_exp;
+       __u8 dsp_exp;
+       __u8 tc_exp;
+       __u8 dspmmu_exp;
+
+       per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
+       lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
+       arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
+       dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
+       tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
+       dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
+
+       if (dspmmu_exp < dsp_exp)
+               dspmmu_exp = dsp_exp;
+       if (dspmmu_exp > dsp_exp+1)
+               dspmmu_exp = dsp_exp+1;
+       if (tc_exp < arm_exp)
+               tc_exp = arm_exp;
+       if (tc_exp < dspmmu_exp)
+               tc_exp = dspmmu_exp;
+       if (tc_exp > lcd_exp)
+               lcd_exp = tc_exp;
+       if (tc_exp > per_exp)
+               per_exp = tc_exp;
+
+       newval &= 0xf000;
+       newval |= per_exp << CKCTL_PERDIV_OFFSET;
+       newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
+       newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
+       newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
+       newval |= tc_exp << CKCTL_TCDIV_OFFSET;
+       newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
+
+       return newval;
+}
+
+
+static int calc_dsor_exp(struct clk *clk, unsigned long rate)
+{
+       /* Note: If target frequency is too low, this function will return 4,
+        * which is invalid value. Caller must check for this value and act
+        * accordingly.
+        *
+        * Note: This function does not check for following limitations set
+        * by the hardware (all conditions must be true):
+        * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
+        * ARM_CK >= TC_CK
+        * DSP_CK >= TC_CK
+        * DSPMMU_CK >= TC_CK
+        */
+       unsigned long realrate;
+       struct clk *  parent;
+       unsigned  dsor_exp;
+
+       if (unlikely(!(clk->flags & RATE_CKCTL)))
+               return -EINVAL;
+
+       parent = clk->parent;
+       if (unlikely(parent == 0))
+               return -EIO;
+
+       realrate = parent->rate;
+       for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
+               if (realrate <= rate)
+                       break;
+
+               realrate /= 2;
+       }
+
+       return dsor_exp;
+}
+
+
+static void ckctl_recalc(struct clk *  clk)
+{
+       int dsor;
+
+       /* Calculate divisor encoded as 2-bit exponent */
+       if (clk->flags & DSP_DOMAIN_CLOCK) {
+               /* The clock control bits are in DSP domain,
+                * so api_ck is needed for access.
+                * Note that DSP_CKCTL virt addr = phys addr, so
+                * we must use __raw_readw() instead of omap_readw().
+                */
+               __clk_use(&api_ck);
+               dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
+               __clk_unuse(&api_ck);
+       } else {
+               dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
+       }
+       if (unlikely(clk->rate == clk->parent->rate / dsor))
+               return; /* No change, quick exit */
+       clk->rate = clk->parent->rate / dsor;
+
+       if (unlikely(clk->flags & RATE_PROPAGATES))
+               propagate_rate(clk);
+}
+
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+       int dsor_exp;
+
+       if (clk->flags & RATE_FIXED)
+               return clk->rate;
+
+       if (clk->flags & RATE_CKCTL) {
+               dsor_exp = calc_dsor_exp(clk, rate);
+               if (dsor_exp < 0)
+                       return dsor_exp;
+               if (dsor_exp > 3)
+                       dsor_exp = 3;
+               return clk->parent->rate / (1 << dsor_exp);
+       }
+
+       if(clk->round_rate != 0)
+               return clk->round_rate(clk, rate);
+
+       return clk->rate;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+
+static void propagate_rate(struct clk *  clk)
+{
+       struct clk **  clkp;
+
+       for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); 
clkp++) {
+               if (likely((*clkp)->parent != clk)) continue;
+               if (likely((*clkp)->recalc))
+                       (*clkp)->recalc(*clkp);
+       }
+}
+
+
+static int select_table_rate(struct clk *  clk, unsigned long rate)
+{
+       /* Find the highest supported frequency <= rate and switch to it */
+       struct mpu_rate *  ptr;
+
+       if (clk != &virtual_ck_mpu)
+               return -EINVAL;
+
+       for (ptr = rate_table; ptr->rate; ptr++) {
+               if (ptr->xtal != ck_ref.rate)
+                       continue;
+
+               /* DPLL1 cannot be reprogrammed without risking system crash */
+               if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
+                       continue;
+
+               /* Can check only after xtal frequency check */
+               if (ptr->rate <= rate)
+                       break;
+       }
+
+       if (!ptr->rate)
+               return -EINVAL;
+
+       if (!ptr->rate)
+               return -EINVAL;
+
+       if (unlikely(ck_dpll1.rate == 0)) {
+               omap_writew(ptr->dpllctl_val, DPLL_CTL);
+               ck_dpll1.rate = ptr->pll_rate;
+       }
+       omap_writew(ptr->ckctl_val, ARM_CKCTL);
+       propagate_rate(&ck_dpll1);
+       return 0;
+}
+
+
+static long round_to_table_rate(struct clk *  clk, unsigned long rate)
+{
+       /* Find the highest supported frequency <= rate */
+       struct mpu_rate *  ptr;
+       long  highest_rate;
+
+       if (clk != &virtual_ck_mpu)
+               return -EINVAL;
+
+       highest_rate = -EINVAL;
+
+       for (ptr = rate_table; ptr->rate; ptr++) {
+               if (ptr->xtal != ck_ref.rate)
+                       continue;
+
+               highest_rate = ptr->rate;
+
+               /* Can check only after xtal frequency check */
+               if (ptr->rate <= rate)
+                       break;
+       }
+
+       return highest_rate;
+}
+
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+       int  ret = -EINVAL;
+       int  dsor_exp;
+       __u16  regval;
+       unsigned long  flags;
+
+       if (clk->flags & RATE_CKCTL) {
+               dsor_exp = calc_dsor_exp(clk, rate);
+               if (dsor_exp > 3)
+                       dsor_exp = -EINVAL;
+               if (dsor_exp < 0)
+                       return dsor_exp;
+
+               spin_lock_irqsave(&clockfw_lock, flags);
+               regval = omap_readw(ARM_CKCTL);
+               regval &= ~(3 << clk->rate_offset);
+               regval |= dsor_exp << clk->rate_offset;
+               regval = verify_ckctl_value(regval);
+               omap_writew(regval, ARM_CKCTL);
+               clk->rate = clk->parent->rate / (1 << dsor_exp);
+               spin_unlock_irqrestore(&clockfw_lock, flags);
+               ret = 0;
+       } else if(clk->set_rate != 0) {
+               spin_lock_irqsave(&clockfw_lock, flags);
+               ret = clk->set_rate(clk, rate);
+               spin_unlock_irqrestore(&clockfw_lock, flags);
+       }
+
+       if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
+               propagate_rate(clk);
+
+       return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+
+static unsigned calc_ext_dsor(unsigned long rate)
+{
+       unsigned dsor;
+
+       /* MCLK and BCLK divisor selection is not linear:
+        * freq = 96MHz / dsor
+        *
+        * RATIO_SEL range: dsor <-> RATIO_SEL
+        * 0..6: (RATIO_SEL+2) <-> (dsor-2)
+        * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
+        * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
+        * can not be used.
+        */
+       for (dsor = 2; dsor < 96; ++dsor) {
+               if ((dsor & 1) && dsor > 8)
+                       continue;
+               if (rate >= 96000000 / dsor)
+                       break;
+       }
+       return dsor;
+}
+
+/* Only needed on 1510 */
+static int set_uart_rate(struct clk * clk, unsigned long rate)
+{
+       unsigned int val;
+
+       val = omap_readl(clk->enable_reg);
+       if (rate == 12000000)
+               val &= ~(1 << clk->enable_bit);
+       else if (rate == 48000000)
+               val |= (1 << clk->enable_bit);
+       else
+               return -EINVAL;
+       omap_writel(val, clk->enable_reg);
+       clk->rate = rate;
+
+       return 0;
+}
+
+static int set_ext_clk_rate(struct clk *  clk, unsigned long rate)
+{
+       unsigned dsor;
+       __u16 ratio_bits;
+
+       dsor = calc_ext_dsor(rate);
+       clk->rate = 96000000 / dsor;
+       if (dsor > 8)
+               ratio_bits = ((dsor - 8) / 2 + 6) << 2;
+       else
+               ratio_bits = (dsor - 2) << 2;
+
+       ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
+       omap_writew(ratio_bits, clk->enable_reg);
+
+       return 0;
+}
+
+
+static long round_ext_clk_rate(struct clk *  clk, unsigned long rate)
+{
+       return 96000000 / calc_ext_dsor(rate);
+}
+
+
+static void init_ext_clk(struct clk *  clk)
+{
+       unsigned dsor;
+       __u16 ratio_bits;
+
+       /* Determine current rate and ensure clock is based on 96MHz APLL */
+       ratio_bits = omap_readw(clk->enable_reg) & ~1;
+       omap_writew(ratio_bits, clk->enable_reg);
+
+       ratio_bits = (ratio_bits & 0xfc) >> 2;
+       if (ratio_bits > 6)
+               dsor = (ratio_bits - 6) * 2 + 8;
+       else
+               dsor = ratio_bits + 2;
+
+       clk-> rate = 96000000 / dsor;
+}
+
+
+int clk_register(struct clk *clk)
+{
+       down(&clocks_sem);
+       list_add(&clk->node, &clocks);
+       if (clk->init)
+               clk->init(clk);
+       up(&clocks_sem);
+       return 0;
+}
+EXPORT_SYMBOL(clk_register);
+
+void clk_unregister(struct clk *clk)
+{
+       down(&clocks_sem);
+       list_del(&clk->node);
+       up(&clocks_sem);
+}
+EXPORT_SYMBOL(clk_unregister);
+
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+/*
+ * Resets some clocks that may be left on from bootloader,
+ * but leaves serial clocks on. See also omap_late_clk_reset().
+ */
+static inline void omap_early_clk_reset(void)
+{
+       //omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
+}
+#else
+#define omap_early_clk_reset() {}
+#endif
+
+int __init clk_init(void)
+{
+       struct clk **  clkp;
+       const struct omap_clock_config *info;
+       int crystal_type = 0; /* Default 12 MHz */
+
+       omap_early_clk_reset();
+
+       for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); 
clkp++) {
+               if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
+                       clk_register(*clkp);
+                       continue;
+               }
+
+               if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
+                       clk_register(*clkp);
+                       continue;
+               }
+
+               if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
+                       clk_register(*clkp);
+                       continue;
+               }
+       }
+
+       info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
+       if (info != NULL) {
+               if (!cpu_is_omap1510())
+                       crystal_type = info->system_clock_type;
+       }
+
+#if defined(CONFIG_ARCH_OMAP730)
+       ck_ref.rate = 13000000;
+#elif defined(CONFIG_ARCH_OMAP16XX)
+       if (crystal_type == 2)
+               ck_ref.rate = 19200000;
+#endif
+
+       printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
+              omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
+              omap_readw(ARM_CKCTL));
+
+       /* We want to be in syncronous scalable mode */
+       omap_writew(0x1000, ARM_SYSST);
+
+#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
+       /* Use values set by bootloader. Determine PLL rate and recalculate
+        * dependent clocks as if kernel had changed PLL or divisors.
+        */
+       {
+               unsigned pll_ctl_val = omap_readw(DPLL_CTL);
+
+               ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
+               if (pll_ctl_val & 0x10) {
+                       /* PLL enabled, apply multiplier and divisor */
+                       if (pll_ctl_val & 0xf80)
+                               ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
+                       ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
+               } else {
+                       /* PLL disabled, apply bypass divisor */
+                       switch (pll_ctl_val & 0xc) {
+                       case 0:
+                               break;
+                       case 0x4:
+                               ck_dpll1.rate /= 2;
+                               break;
+                       default:
+                               ck_dpll1.rate /= 4;
+                               break;
+                       }
+               }
+       }
+       propagate_rate(&ck_dpll1);
+#else
+       /* Find the highest supported frequency and enable it */
+       if (select_table_rate(&virtual_ck_mpu, ~0)) {
+               printk(KERN_ERR "System frequencies not set. Check your 
config.\n");
+               /* Guess sane values (60MHz) */
+               omap_writew(0x2290, DPLL_CTL);
+               omap_writew(0x1005, ARM_CKCTL);
+               ck_dpll1.rate = 60000000;
+               propagate_rate(&ck_dpll1);
+       }
+#endif
+       /* Cache rates for clocks connected to ck_ref (not dpll1) */
+       propagate_rate(&ck_ref);
+       printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld/%ld 
MHz\n",
+              ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
+              ck_dpll1.rate, arm_ck.rate);
+
+#ifdef CONFIG_MACH_OMAP_PERSEUS2
+       /* Select slicer output as OMAP input clock */
+       omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, 
OMAP730_PCC_UPLD_CTRL);
+#endif
+
+       /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
+       omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
+
+       /* Put DSP/MPUI into reset until needed */
+       omap_writew(0, ARM_RSTCT1);
+       omap_writew(1, ARM_RSTCT2);
+       omap_writew(0x400, ARM_IDLECT1);
+
+       /*
+        * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
+        * of the ARM_IDLECT2 register must be set to zero. The power-on
+        * default value of this bit is one.
+        */
+       omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
+
+       /*
+        * Only enable those clocks we will need, let the drivers
+        * enable other clocks as necessary
+        */
+       clk_use(&armper_ck);
+       clk_use(&armxor_ck);
+       clk_use(&armtim_ck);
+
+       if (cpu_is_omap1510())
+               clk_enable(&arm_gpio_ck);
+
+       return 0;
+}
+
+
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+
+static int __init omap_late_clk_reset(void)
+{
+       /* Turn off all unused clocks */
+       struct clk *p;
+       __u32 regval32;
+
+       omap_writew(0, SOFT_REQ_REG);
+       omap_writew(0, SOFT_REQ_REG2);
+
+       list_for_each_entry(p, &clocks, node) {
+               if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) ||
+                       p->enable_reg == 0)
+                       continue;
+
+               /* Assume no DSP clocks have been activated by bootloader */
+               if (p->flags & DSP_DOMAIN_CLOCK)
+                       continue;
+
+               /* Is the clock already disabled? */
+               if (p->flags & ENABLE_REG_32BIT) {
+                       if (p->flags & VIRTUAL_IO_ADDRESS)
+                               regval32 = __raw_readl(p->enable_reg);
+                       else
+                               regval32 = omap_readl(p->enable_reg);
+               } else {
+                       if (p->flags & VIRTUAL_IO_ADDRESS)
+                               regval32 = __raw_readw(p->enable_reg);
+                       else
+                               regval32 = omap_readw(p->enable_reg);
+               }
+
+               if ((regval32 & (1 << p->enable_bit)) == 0)
+                       continue;
+
+               /* FIXME: This clock seems to be necessary but no-one
+                * has asked for its activation. */
+               if (p == &tc2_ck         // FIX: pm.c (SRAM), CCP, Camera
+                   || p == &ck_dpll1out // FIX: SoSSI, SSR
+                   || p == &arm_gpio_ck // FIX: GPIO code for 1510
+                   ) {
+                       printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
+                              p->name);
+                       continue;
+               }
+
+               printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name);
+               __clk_disable(p);
+               printk(" done\n");
+       }
+
+       return 0;
+}
+
+late_initcall(omap_late_clk_reset);
+
+#endif
diff -urN linux/arch/arm/plat-omap/clock.h linux/arch/arm/plat-omap/clock.h
--- linux/arch/arm/plat-omap/clock.h    1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/clock.h    2005-07-13 12:48:53.845970000 +0100     
1.1
@@ -0,0 +1,120 @@
+/*
+ *  linux/arch/arm/plat-omap/clock.h
+ *
+ *  Copyright (C) 2004 Nokia corporation
+ *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_OMAP_CLOCK_H
+#define __ARCH_ARM_OMAP_CLOCK_H
+
+struct module;
+
+struct clk {
+       struct list_head        node;
+       struct module           *owner;
+       const char              *name;
+       struct clk              *parent;
+       unsigned long           rate;
+       __s8                    usecount;
+       __u16                   flags;
+       __u32                   enable_reg;
+       __u8                    enable_bit;
+       __u8                    rate_offset;
+       void                    (*recalc)(struct clk *);
+       int                     (*set_rate)(struct clk *, unsigned long);
+       long                    (*round_rate)(struct clk *, unsigned long);
+       void                    (*init)(struct clk *);
+};
+
+
+struct mpu_rate {
+       unsigned long           rate;
+       unsigned long           xtal;
+       unsigned long           pll_rate;
+       __u16                   ckctl_val;
+       __u16                   dpllctl_val;
+};
+
+
+/* Clock flags */
+#define RATE_CKCTL             1
+#define RATE_FIXED             2
+#define RATE_PROPAGATES                4
+#define VIRTUAL_CLOCK          8
+#define ALWAYS_ENABLED         16
+#define ENABLE_REG_32BIT       32
+#define CLOCK_IN_OMAP16XX      64
+#define CLOCK_IN_OMAP1510      128
+#define CLOCK_IN_OMAP730       256
+#define DSP_DOMAIN_CLOCK       512
+#define VIRTUAL_IO_ADDRESS     1024
+
+/* ARM_CKCTL bit shifts */
+#define CKCTL_PERDIV_OFFSET    0
+#define CKCTL_LCDDIV_OFFSET    2
+#define CKCTL_ARMDIV_OFFSET    4
+#define CKCTL_DSPDIV_OFFSET    6
+#define CKCTL_TCDIV_OFFSET     8
+#define CKCTL_DSPMMUDIV_OFFSET 10
+/*#define ARM_TIMXO            12*/
+#define EN_DSPCK               13
+/*#define ARM_INTHCK_SEL       14*/ /* Divide-by-2 for mpu inth_ck */
+/* DSP_CKCTL bit shifts */
+#define CKCTL_DSPPERDIV_OFFSET 0
+
+/* ARM_IDLECT1 bit shifts */
+/*#define IDLWDT_ARM   0*/
+/*#define IDLXORP_ARM  1*/
+/*#define IDLPER_ARM   2*/
+/*#define IDLLCD_ARM   3*/
+/*#define IDLLB_ARM    4*/
+/*#define IDLHSAB_ARM  5*/
+/*#define IDLIF_ARM    6*/
+/*#define IDLDPLL_ARM  7*/
+/*#define IDLAPI_ARM   8*/
+/*#define IDLTIM_ARM   9*/
+/*#define SETARM_IDLE  11*/
+
+/* ARM_IDLECT2 bit shifts */
+#define EN_WDTCK       0
+#define EN_XORPCK      1
+#define EN_PERCK       2
+#define EN_LCDCK       3
+#define EN_LBCK                4 /* Not on 1610/1710 */
+/*#define EN_HSABCK    5*/
+#define EN_APICK       6
+#define EN_TIMCK       7
+#define DMACK_REQ      8
+#define EN_GPIOCK      9 /* Not on 1610/1710 */
+/*#define EN_LBFREECK  10*/
+#define EN_CKOUT_ARM   11
+
+/* ARM_IDLECT3 bit shifts */
+#define EN_OCPI_CK     0
+#define EN_TC1_CK      2
+#define EN_TC2_CK      4
+
+/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
+#define EN_DSPTIMCK    5
+
+/* Various register defines for clock controls scattered around OMAP chip */
+#define USB_MCLK_EN_BIT                4       /* In ULPD_CLKC_CTRL */
+#define USB_HOST_HHC_UHOST_EN  9       /* In MOD_CONF_CTRL_0 */
+#define SWD_ULPD_PLL_CLK_REQ   1       /* In SWD_CLK_DIV_CTRL_SEL */
+#define COM_ULPD_PLL_CLK_REQ   1       /* In COM_CLK_DIV_CTRL_SEL */
+#define SWD_CLK_DIV_CTRL_SEL   0xfffe0874
+#define COM_CLK_DIV_CTRL_SEL   0xfffe0878
+#define SOFT_REQ_REG           0xfffe0834
+#define SOFT_REQ_REG2          0xfffe0880
+
+int clk_register(struct clk *clk);
+void clk_unregister(struct clk *clk);
+int clk_init(void);
+
+#endif
diff -urN linux/arch/arm/plat-omap/common.c linux/arch/arm/plat-omap/common.c
--- linux/arch/arm/plat-omap/common.c   1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/common.c   2005-07-13 12:48:53.871831000 +0100     
1.1
@@ -0,0 +1,135 @@
+/*
+ * linux/arch/arm/plat-omap/common.c
+ *
+ * Code common to all OMAP machines.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/console.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_reg.h>
+
+#include <asm/hardware.h>
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/clock.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/fpga.h>
+
+#include "clock.h"
+
+#define NO_LENGTH_CHECK 0xffffffff
+
+extern int omap_bootloader_tag_len;
+extern u8 omap_bootloader_tag[];
+
+struct omap_board_config_kernel *omap_board_config;
+int omap_board_config_size = 0;
+
+static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
+{
+       struct omap_board_config_kernel *kinfo = NULL;
+       int i;
+
+#ifdef CONFIG_OMAP_BOOT_TAG
+       struct omap_board_config_entry *info = NULL;
+
+       if (omap_bootloader_tag_len > 4)
+               info = (struct omap_board_config_entry *) omap_bootloader_tag;
+       while (info != NULL) {
+               u8 *next;
+
+               if (info->tag == tag) {
+                       if (skip == 0)
+                               break;
+                       skip--;
+               }
+
+               if ((info->len & 0x03) != 0) {
+                       /* We bail out to avoid an alignment fault */
+                       printk(KERN_ERR "OMAP peripheral config: Length (%d) 
not word-aligned (tag %04x)\n",
+                              info->len, info->tag);
+                       return NULL;
+               }
+               next = (u8 *) info + sizeof(*info) + info->len;
+               if (next >= omap_bootloader_tag + omap_bootloader_tag_len)
+                       info = NULL;
+               else
+                       info = (struct omap_board_config_entry *) next;
+       }
+       if (info != NULL) {
+               /* Check the length as a lame attempt to check for
+                * binary inconsistancy. */
+               if (len != NO_LENGTH_CHECK) {
+                       /* Word-align len */
+                       if (len & 0x03)
+                               len = (len + 3) & ~0x03;
+                       if (info->len != len) {
+                               printk(KERN_ERR "OMAP peripheral config: Length 
mismatch with tag %x (want %d, got %d)\n",
+                                      tag, len, info->len);
+                               return NULL;
+                       }
+               }
+               if (len_out != NULL)
+                       *len_out = info->len;
+               return info->data;
+       }
+#endif
+       /* Try to find the config from the board-specific structures
+        * in the kernel. */
+       for (i = 0; i < omap_board_config_size; i++) {
+               if (omap_board_config[i].tag == tag) {
+                       kinfo = &omap_board_config[i];
+                       break;
+               }
+       }
+       if (kinfo == NULL)
+               return NULL;
+       return kinfo->data;
+}
+
+const void *__omap_get_config(u16 tag, size_t len, int nr)
+{
+        return get_config(tag, len, nr, NULL);
+}
+EXPORT_SYMBOL(__omap_get_config);
+
+const void *omap_get_var_config(u16 tag, size_t *len)
+{
+        return get_config(tag, NO_LENGTH_CHECK, 0, len);
+}
+EXPORT_SYMBOL(omap_get_var_config);
+
+static int __init omap_add_serial_console(void)
+{
+       const struct omap_serial_console_config *info;
+
+       info = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
+                              struct omap_serial_console_config);
+       if (info != NULL && info->console_uart) {
+               static char speed[11], *opt = NULL;
+
+               if (info->console_speed) {
+                       snprintf(speed, sizeof(speed), "%u", 
info->console_speed);
+                       opt = speed;
+               }
+               return add_preferred_console("ttyS", info->console_uart - 1, 
opt);
+       }
+       return 0;
+}
+console_initcall(omap_add_serial_console);
diff -urN linux/arch/arm/plat-omap/cpu-omap.c 
linux/arch/arm/plat-omap/cpu-omap.c
--- linux/arch/arm/plat-omap/cpu-omap.c 1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/cpu-omap.c 2005-07-13 12:48:53.893937000 +0100     
1.1
@@ -0,0 +1,128 @@
+/*
+ *  linux/arch/arm/plat-omap/cpu-omap.c
+ *
+ *  CPU frequency scaling for OMAP
+ *
+ *  Copyright (C) 2005 Nokia Corporation
+ *  Written by Tony Lindgren <tony@atomide.com>
+ *
+ *  Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/cpufreq.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/err.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/system.h>
+
+#include <asm/hardware/clock.h>
+
+/* TODO: Add support for SDRAM timing changes */
+
+int omap_verify_speed(struct cpufreq_policy *policy)
+{
+       struct clk * mpu_clk;
+
+       if (policy->cpu)
+               return -EINVAL;
+
+       cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
+                                    policy->cpuinfo.max_freq);
+       mpu_clk = clk_get(NULL, "mpu");
+       if (IS_ERR(mpu_clk))
+               return PTR_ERR(mpu_clk);
+       policy->min = clk_round_rate(mpu_clk, policy->min * 1000) / 1000;
+       policy->max = clk_round_rate(mpu_clk, policy->max * 1000) / 1000;
+       cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
+                                    policy->cpuinfo.max_freq);
+       clk_put(mpu_clk);
+
+       return 0;
+}
+
+unsigned int omap_getspeed(unsigned int cpu)
+{
+       struct clk * mpu_clk;
+       unsigned long rate;
+
+       if (cpu)
+               return 0;
+
+       mpu_clk = clk_get(NULL, "mpu");
+       if (IS_ERR(mpu_clk))
+               return 0;
+       rate = clk_get_rate(mpu_clk) / 1000;
+       clk_put(mpu_clk);
+
+       return rate;
+}
+
+static int omap_target(struct cpufreq_policy *policy,
+                      unsigned int target_freq,
+                      unsigned int relation)
+{
+       struct clk * mpu_clk;
+       struct cpufreq_freqs freqs;
+       int ret = 0;
+
+       mpu_clk = clk_get(NULL, "mpu");
+       if (IS_ERR(mpu_clk))
+               return PTR_ERR(mpu_clk);
+
+       freqs.old = omap_getspeed(0);
+       freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
+       freqs.cpu = 0;
+
+       cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+       ret = clk_set_rate(mpu_clk, target_freq * 1000);
+       cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+       clk_put(mpu_clk);
+
+       return ret;
+}
+
+static int __init omap_cpu_init(struct cpufreq_policy *policy)
+{
+       struct clk * mpu_clk;
+
+       mpu_clk = clk_get(NULL, "mpu");
+       if (IS_ERR(mpu_clk))
+               return PTR_ERR(mpu_clk);
+
+       if (policy->cpu != 0)
+               return -EINVAL;
+       policy->cur = policy->min = policy->max = omap_getspeed(0);
+       policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+       policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000;
+       policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, 216000000) / 1000;
+       policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+       clk_put(mpu_clk);
+
+       return 0;
+}
+
+static struct cpufreq_driver omap_driver = {
+       .flags          = CPUFREQ_STICKY,
+       .verify         = omap_verify_speed,
+       .target         = omap_target,
+       .get            = omap_getspeed,
+       .init           = omap_cpu_init,
+       .name           = "omap",
+};
+
+static int __init omap_cpufreq_init(void)
+{
+       return cpufreq_register_driver(&omap_driver);
+}
+
+arch_initcall(omap_cpufreq_init);
diff -urN linux/arch/arm/plat-omap/dma.c linux/arch/arm/plat-omap/dma.c
--- linux/arch/arm/plat-omap/dma.c      1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/dma.c      2005-07-13 12:48:53.916837000 +0100     
1.1
@@ -0,0 +1,1116 @@
+/*
+ * linux/arch/arm/plat-omap/dma.c
+ *
+ * Copyright (C) 2003 Nokia Corporation
+ * Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
+ * Graphics DMA and LCD DMA graphics tranformations
+ * by Imre Deak <imre.deak@nokia.com>
+ * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * Support functions for the OMAP internal DMA channels.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+
+#include <asm/arch/tc.h>
+
+#define OMAP_DMA_ACTIVE                0x01
+
+#define OMAP_DMA_CCR_EN                (1 << 7)
+
+#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
+
+static int enable_1510_mode = 0;
+
+struct omap_dma_lch {
+       int next_lch;
+       int dev_id;
+       u16 saved_csr;
+       u16 enabled_irqs;
+       const char *dev_name;
+       void (* callback)(int lch, u16 ch_status, void *data);
+       void *data;
+       long flags;
+};
+
+static int dma_chan_count;
+
+static spinlock_t dma_chan_lock;
+static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
+
+const static u8 dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
+       INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
+       INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
+       INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
+       INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
+       INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
+};
+
+static inline int get_gdma_dev(int req)
+{
+       u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
+       int shift = ((req - 1) % 5) * 6;
+
+       return ((omap_readl(reg) >> shift) & 0x3f) + 1;
+}
+
+static inline void set_gdma_dev(int req, int dev)
+{
+       u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
+       int shift = ((req - 1) % 5) * 6;
+       u32 l;
+
+       l = omap_readl(reg);
+       l &= ~(0x3f << shift);
+       l |= (dev - 1) << shift;
+       omap_writel(l, reg);
+}
+
+static void clear_lch_regs(int lch)
+{
+       int i;
+       u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
+
+       for (i = 0; i < 0x2c; i += 2)
+               omap_writew(0, lch_base + i);
+}
+
+void omap_set_dma_priority(int dst_port, int priority)
+{
+       unsigned long reg;
+       u32 l;
+
+       switch (dst_port) {
+       case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
+               reg = OMAP_TC_OCPT1_PRIOR;
+               break;
+       case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
+               reg = OMAP_TC_OCPT2_PRIOR;
+               break;
+       case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
+               reg = OMAP_TC_EMIFF_PRIOR;
+               break;
+       case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
+               reg = OMAP_TC_EMIFS_PRIOR;
+               break;
+       default:
+               BUG();
+               return;
+       }
+       l = omap_readl(reg);
+       l &= ~(0xf << 8);
+       l |= (priority & 0xf) << 8;
+       omap_writel(l, reg);
+}
+
+void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
+                                 int frame_count, int sync_mode)
+{
+       u16 w;
+
+       w = omap_readw(OMAP_DMA_CSDP(lch));
+       w &= ~0x03;
+       w |= data_type;
+       omap_writew(w, OMAP_DMA_CSDP(lch));
+
+       w = omap_readw(OMAP_DMA_CCR(lch));
+       w &= ~(1 << 5);
+       if (sync_mode == OMAP_DMA_SYNC_FRAME)
+               w |= 1 << 5;
+       omap_writew(w, OMAP_DMA_CCR(lch));
+
+       w = omap_readw(OMAP_DMA_CCR2(lch));
+       w &= ~(1 << 2);
+       if (sync_mode == OMAP_DMA_SYNC_BLOCK)
+               w |= 1 << 2;
+       omap_writew(w, OMAP_DMA_CCR2(lch));
+
+       omap_writew(elem_count, OMAP_DMA_CEN(lch));
+       omap_writew(frame_count, OMAP_DMA_CFN(lch));
+
+}
+void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
+{
+       u16 w;
+
+       BUG_ON(omap_dma_in_1510_mode());
+
+       w = omap_readw(OMAP_DMA_CCR2(lch)) & ~0x03;
+       switch (mode) {
+       case OMAP_DMA_CONSTANT_FILL:
+               w |= 0x01;
+               break;
+       case OMAP_DMA_TRANSPARENT_COPY:
+               w |= 0x02;
+               break;
+       case OMAP_DMA_COLOR_DIS:
+               break;
+       default:
+               BUG();
+       }
+       omap_writew(w, OMAP_DMA_CCR2(lch));
+
+       w = omap_readw(OMAP_DMA_LCH_CTRL(lch)) & ~0x0f;
+       /* Default is channel type 2D */
+       if (mode) {
+               omap_writew((u16)color, OMAP_DMA_COLOR_L(lch));
+               omap_writew((u16)(color >> 16), OMAP_DMA_COLOR_U(lch));
+               w |= 1;         /* Channel type G */
+       }
+       omap_writew(w, OMAP_DMA_LCH_CTRL(lch));
+}
+
+
+void omap_set_dma_src_params(int lch, int src_port, int src_amode,
+                            unsigned long src_start)
+{
+       u16 w;
+
+       w = omap_readw(OMAP_DMA_CSDP(lch));
+       w &= ~(0x1f << 2);
+       w |= src_port << 2;
+       omap_writew(w, OMAP_DMA_CSDP(lch));
+
+       w = omap_readw(OMAP_DMA_CCR(lch));
+       w &= ~(0x03 << 12);
+       w |= src_amode << 12;
+       omap_writew(w, OMAP_DMA_CCR(lch));
+
+       omap_writew(src_start >> 16, OMAP_DMA_CSSA_U(lch));
+       omap_writew(src_start, OMAP_DMA_CSSA_L(lch));
+}
+
+void omap_set_dma_src_index(int lch, int eidx, int fidx)
+{
+       omap_writew(eidx, OMAP_DMA_CSEI(lch));
+       omap_writew(fidx, OMAP_DMA_CSFI(lch));
+}
+
+void omap_set_dma_src_data_pack(int lch, int enable)
+{
+       u16 w;
+
+       w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 6);
+       w |= enable ? (1 << 6) : 0;
+       omap_writew(w, OMAP_DMA_CSDP(lch));
+}
+
+void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
+{
+       u16 w;
+
+       w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 7);
+       switch (burst_mode) {
+       case OMAP_DMA_DATA_BURST_DIS:
+               break;
+       case OMAP_DMA_DATA_BURST_4:
+               w |= (0x01 << 7);
+               break;
+       case OMAP_DMA_DATA_BURST_8:
+               /* not supported by current hardware
+                * w |= (0x03 << 7);
+                * fall through
+                */
+       default:
+               BUG();
+       }
+       omap_writew(w, OMAP_DMA_CSDP(lch));
+}
+
+void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
+                             unsigned long dest_start)
+{
+       u16 w;
+
+       w = omap_readw(OMAP_DMA_CSDP(lch));
+       w &= ~(0x1f << 9);
+       w |= dest_port << 9;
+       omap_writew(w, OMAP_DMA_CSDP(lch));
+
+       w = omap_readw(OMAP_DMA_CCR(lch));
+       w &= ~(0x03 << 14);
+       w |= dest_amode << 14;
+       omap_writew(w, OMAP_DMA_CCR(lch));
+
+       omap_writew(dest_start >> 16, OMAP_DMA_CDSA_U(lch));
+       omap_writew(dest_start, OMAP_DMA_CDSA_L(lch));
+}
+
+void omap_set_dma_dest_index(int lch, int eidx, int fidx)
+{
+       omap_writew(eidx, OMAP_DMA_CDEI(lch));
+       omap_writew(fidx, OMAP_DMA_CDFI(lch));
+}
+
+void omap_set_dma_dest_data_pack(int lch, int enable)
+{
+       u16 w;
+
+       w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 13);
+       w |= enable ? (1 << 13) : 0;
+       omap_writew(w, OMAP_DMA_CSDP(lch));
+}
+
+void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
+{
+       u16 w;
+
+       w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 14);
+       switch (burst_mode) {
+       case OMAP_DMA_DATA_BURST_DIS:
+               break;
+       case OMAP_DMA_DATA_BURST_4:
+               w |= (0x01 << 14);
+               break;
+       case OMAP_DMA_DATA_BURST_8:
+               w |= (0x03 << 14);
+               break;
+       default:
+               printk(KERN_ERR "Invalid DMA burst mode\n");
+               BUG();
+               return;
+       }
+       omap_writew(w, OMAP_DMA_CSDP(lch));
+}
+
+static inline void init_intr(int lch)
+{
+       u16 w;
+
+       /* Read CSR to make sure it's cleared. */
+       w = omap_readw(OMAP_DMA_CSR(lch));
+       /* Enable some nice interrupts. */
+       omap_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR(lch));
+       dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
+}
+
+static inline void enable_lnk(int lch)
+{
+       u16 w;
+
+       /* Clear the STOP_LNK bits */
+       w = omap_readw(OMAP_DMA_CLNK_CTRL(lch));
+       w &= ~(1 << 14);
+       omap_writew(w, OMAP_DMA_CLNK_CTRL(lch));
+
+       /* And set the ENABLE_LNK bits */
+       if (dma_chan[lch].next_lch != -1)
+               omap_writew(dma_chan[lch].next_lch | (1 << 15),
+                           OMAP_DMA_CLNK_CTRL(lch));
+}
+
+static inline void disable_lnk(int lch)
+{
+       u16 w;
+
+       /* Disable interrupts */
+       omap_writew(0, OMAP_DMA_CICR(lch));
+
+       /* Set the STOP_LNK bit */
+       w = omap_readw(OMAP_DMA_CLNK_CTRL(lch));
+       w |= (1 << 14);
+       w = omap_writew(w, OMAP_DMA_CLNK_CTRL(lch));
+
+       dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
+}
+
+void omap_start_dma(int lch)
+{
+       u16 w;
+
+       if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
+               int next_lch, cur_lch;
+               char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
+
+               dma_chan_link_map[lch] = 1;
+               /* Set the link register of the first channel */
+               enable_lnk(lch);
+
+               memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
+               cur_lch = dma_chan[lch].next_lch;
+               do {
+                       next_lch = dma_chan[cur_lch].next_lch;
+
+                        /* The loop case: we've been here already */
+                       if (dma_chan_link_map[cur_lch])
+                               break;
+                       /* Mark the current channel */
+                       dma_chan_link_map[cur_lch] = 1;
+
+                       enable_lnk(cur_lch);
+                       init_intr(cur_lch);
+
+                       cur_lch = next_lch;
+               } while (next_lch != -1);
+       }
+
+       init_intr(lch);
+
+       w = omap_readw(OMAP_DMA_CCR(lch));
+       w |= OMAP_DMA_CCR_EN;
+       omap_writew(w, OMAP_DMA_CCR(lch));
+       dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
+}
+
+void omap_stop_dma(int lch)
+{
+       u16 w;
+
+       if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
+               int next_lch, cur_lch = lch;
+               char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
+
+               memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
+               do {
+                       /* The loop case: we've been here already */
+                       if (dma_chan_link_map[cur_lch])
+                               break;
+                       /* Mark the current channel */
+                       dma_chan_link_map[cur_lch] = 1;
+
+                       disable_lnk(cur_lch);
+
+                       next_lch = dma_chan[cur_lch].next_lch;
+                       cur_lch = next_lch;
+               } while (next_lch != -1);
+
+               return;
+       }
+       /* Disable all interrupts on the channel */
+       omap_writew(0, OMAP_DMA_CICR(lch));
+
+       w = omap_readw(OMAP_DMA_CCR(lch));
+       w &= ~OMAP_DMA_CCR_EN;
+       omap_writew(w, OMAP_DMA_CCR(lch));
+       dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
+}
+
+void omap_enable_dma_irq(int lch, u16 bits)
+{
+       dma_chan[lch].enabled_irqs |= bits;
+}
+
+void omap_disable_dma_irq(int lch, u16 bits)
+{
+       dma_chan[lch].enabled_irqs &= ~bits;
+}
+
+static int dma_handle_ch(int ch)
+{
+       u16 csr;
+
+       if (enable_1510_mode && ch >= 6) {
+               csr = dma_chan[ch].saved_csr;
+               dma_chan[ch].saved_csr = 0;
+       } else
+               csr = omap_readw(OMAP_DMA_CSR(ch));
+       if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
+               dma_chan[ch + 6].saved_csr = csr >> 7;
+               csr &= 0x7f;
+       }
+       if (!csr)
+               return 0;
+       if (unlikely(dma_chan[ch].dev_id == -1)) {
+               printk(KERN_WARNING "Spurious interrupt from DMA channel %d 
(CSR %04x)\n",
+                      ch, csr);
+               return 0;
+       }
+       if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
+               printk(KERN_WARNING "DMA timeout with device %d\n", 
dma_chan[ch].dev_id);
+       if (unlikely(csr & OMAP_DMA_DROP_IRQ))
+               printk(KERN_WARNING "DMA synchronization event drop occurred 
with device %d\n",
+                      dma_chan[ch].dev_id);
+       if (likely(csr & OMAP_DMA_BLOCK_IRQ))
+               dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
+       if (likely(dma_chan[ch].callback != NULL))
+               dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
+       return 1;
+}
+
+static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+{
+       int ch = ((int) dev_id) - 1;
+       int handled = 0;
+
+       for (;;) {
+               int handled_now = 0;
+
+               handled_now += dma_handle_ch(ch);
+               if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
+                       handled_now += dma_handle_ch(ch + 6);
+               if (!handled_now)
+                       break;
+               handled += handled_now;
+       }
+
+       return handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+int omap_request_dma(int dev_id, const char *dev_name,
+                    void (* callback)(int lch, u16 ch_status, void *data),
+                    void *data, int *dma_ch_out)
+{
+       int ch, free_ch = -1;
+       unsigned long flags;
+       struct omap_dma_lch *chan;
+
+       spin_lock_irqsave(&dma_chan_lock, flags);
+       for (ch = 0; ch < dma_chan_count; ch++) {
+               if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
+                       free_ch = ch;
+                       if (dev_id == 0)
+                               break;
+               }
+       }
+       if (free_ch == -1) {
+               spin_unlock_irqrestore(&dma_chan_lock, flags);
+               return -EBUSY;
+       }
+       chan = dma_chan + free_ch;
+       chan->dev_id = dev_id;
+       clear_lch_regs(free_ch);
+       spin_unlock_irqrestore(&dma_chan_lock, flags);
+
+       chan->dev_id = dev_id;
+       chan->dev_name = dev_name;
+       chan->callback = callback;
+       chan->data = data;
+       chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ | 
OMAP_DMA_BLOCK_IRQ;
+
+       if (cpu_is_omap16xx()) {
+               /* If the sync device is set, configure it dynamically. */
+               if (dev_id != 0) {
+                       set_gdma_dev(free_ch + 1, dev_id);
+                       dev_id = free_ch + 1;
+               }
+               /* Disable the 1510 compatibility mode and set the sync device
+                * id. */
+               omap_writew(dev_id | (1 << 10), OMAP_DMA_CCR(free_ch));
+       } else {
+               omap_writew(dev_id, OMAP_DMA_CCR(free_ch));
+       }
+       *dma_ch_out = free_ch;
+
+       return 0;
+}
+
+void omap_free_dma(int ch)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&dma_chan_lock, flags);
+       if (dma_chan[ch].dev_id == -1) {
+               printk("omap_dma: trying to free nonallocated DMA channel 
%d\n", ch);
+               spin_unlock_irqrestore(&dma_chan_lock, flags);
+               return;
+       }
+       dma_chan[ch].dev_id = -1;
+       spin_unlock_irqrestore(&dma_chan_lock, flags);
+
+       /* Disable all DMA interrupts for the channel. */
+       omap_writew(0, OMAP_DMA_CICR(ch));
+       /* Make sure the DMA transfer is stopped. */
+       omap_writew(0, OMAP_DMA_CCR(ch));
+}
+
+int omap_dma_in_1510_mode(void)
+{
+       return enable_1510_mode;
+}
+
+/*
+ * lch_queue DMA will start right after lch_head one is finished.
+ * For this DMA link to start, you still need to start (see omap_start_dma)
+ * the first one. That will fire up the entire queue.
+ */
+void omap_dma_link_lch (int lch_head, int lch_queue)
+{
+       if (omap_dma_in_1510_mode()) {
+               printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
+               BUG();
+               return;
+       }
+
+       if ((dma_chan[lch_head].dev_id == -1) ||
+           (dma_chan[lch_queue].dev_id == -1)) {
+               printk(KERN_ERR "omap_dma: trying to link non requested 
channels\n");
+               dump_stack();
+       }
+
+       dma_chan[lch_head].next_lch = lch_queue;
+}
+
+/*
+ * Once the DMA queue is stopped, we can destroy it.
+ */
+void omap_dma_unlink_lch (int lch_head, int lch_queue)
+{
+       if (omap_dma_in_1510_mode()) {
+               printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
+               BUG();
+               return;
+       }
+
+       if (dma_chan[lch_head].next_lch != lch_queue ||
+           dma_chan[lch_head].next_lch == -1) {
+               printk(KERN_ERR "omap_dma: trying to unlink non linked 
channels\n");
+               dump_stack();
+       }
+
+
+       if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
+           (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
+               printk(KERN_ERR "omap_dma: You need to stop the DMA channels 
before unlinking\n");
+               dump_stack();
+       }
+
+       dma_chan[lch_head].next_lch = -1;
+}
+
+
+static struct lcd_dma_info {
+       spinlock_t lock;
+       int reserved;
+       void (* callback)(u16 status, void *data);
+       void *cb_data;
+
+       int active;
+       unsigned long addr, size;
+       int rotate, data_type, xres, yres;
+       int vxres;
+       int mirror;
+       int xscale, yscale;
+       int ext_ctrl;
+       int src_port;
+       int single_transfer;
+} lcd_dma;
+
+void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
+                        int data_type)
+{
+       lcd_dma.addr = addr;
+       lcd_dma.data_type = data_type;
+       lcd_dma.xres = fb_xres;
+       lcd_dma.yres = fb_yres;
+}
+
+void omap_set_lcd_dma_src_port(int port)
+{
+       lcd_dma.src_port = port;
+}
+
+void omap_set_lcd_dma_ext_controller(int external)
+{
+       lcd_dma.ext_ctrl = external;
+}
+
+void omap_set_lcd_dma_single_transfer(int single)
+{
+       lcd_dma.single_transfer = single;
+}
+
+
+void omap_set_lcd_dma_b1_rotation(int rotate)
+{
+       if (omap_dma_in_1510_mode()) {
+               printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
+               BUG();
+               return;
+       }
+       lcd_dma.rotate = rotate;
+}
+
+void omap_set_lcd_dma_b1_mirror(int mirror)
+{
+       if (omap_dma_in_1510_mode()) {
+               printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
+               BUG();
+       }
+       lcd_dma.mirror = mirror;
+}
+
+void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
+{
+       if (omap_dma_in_1510_mode()) {
+               printk(KERN_ERR "DMA virtual resulotion is not supported "
+                               "in 1510 mode\n");
+               BUG();
+       }
+       lcd_dma.vxres = vxres;
+}
+
+void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
+{
+       if (omap_dma_in_1510_mode()) {
+               printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
+               BUG();
+       }
+       lcd_dma.xscale = xscale;
+       lcd_dma.yscale = yscale;
+}
+
+static void set_b1_regs(void)
+{
+       unsigned long top, bottom;
+       int es;
+       u16 w;
+       unsigned long en, fn;
+       long ei, fi;
+       unsigned long vxres;
+       unsigned int xscale, yscale;
+
+       switch (lcd_dma.data_type) {
+       case OMAP_DMA_DATA_TYPE_S8:
+               es = 1;
+               break;
+       case OMAP_DMA_DATA_TYPE_S16:
+               es = 2;
+               break;
+       case OMAP_DMA_DATA_TYPE_S32:
+               es = 4;
+               break;
+       default:
+               BUG();
+               return;
+       }
+
+       vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
+       xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
+       yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
+       BUG_ON(vxres < lcd_dma.xres);
+#define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * 
es)
+#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
+       switch (lcd_dma.rotate) {
+       case 0:
+               if (!lcd_dma.mirror) {
+                       top = PIXADDR(0, 0);
+                       bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
+                       /* 1510 DMA requires the bottom address to be 2 more
+                        * than the actual last memory access location. */
+                       if (omap_dma_in_1510_mode() &&
+                           lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
+                               bottom += 2;
+                       ei = PIXSTEP(0, 0, 1, 0);
+                       fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
+               } else {
+                       top = PIXADDR(lcd_dma.xres - 1, 0);
+                       bottom = PIXADDR(0, lcd_dma.yres - 1);
+                       ei = PIXSTEP(1, 0, 0, 0);
+                       fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
+               }
+               en = lcd_dma.xres;
+               fn = lcd_dma.yres;
+               break;
+       case 90:
+               if (!lcd_dma.mirror) {
+                       top = PIXADDR(0, lcd_dma.yres - 1);
+                       bottom = PIXADDR(lcd_dma.xres - 1, 0);
+                       ei = PIXSTEP(0, 1, 0, 0);
+                       fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
+               } else {
+                       top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
+                       bottom = PIXADDR(0, 0);
+                       ei = PIXSTEP(0, 1, 0, 0);
+                       fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
+               }
+               en = lcd_dma.yres;
+               fn = lcd_dma.xres;
+               break;
+       case 180:
+               if (!lcd_dma.mirror) {
+                       top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
+                       bottom = PIXADDR(0, 0);
+                       ei = PIXSTEP(1, 0, 0, 0);
+                       fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
+               } else {
+                       top = PIXADDR(0, lcd_dma.yres - 1);
+                       bottom = PIXADDR(lcd_dma.xres - 1, 0);
+                       ei = PIXSTEP(0, 0, 1, 0);
+                       fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
+               }
+               en = lcd_dma.xres;
+               fn = lcd_dma.yres;
+               break;
+       case 270:
+               if (!lcd_dma.mirror) {
+                       top = PIXADDR(lcd_dma.xres - 1, 0);
+                       bottom = PIXADDR(0, lcd_dma.yres - 1);
+                       ei = PIXSTEP(0, 0, 0, 1);
+                       fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
+               } else {
+                       top = PIXADDR(0, 0);
+                       bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
+                       ei = PIXSTEP(0, 0, 0, 1);
+                       fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
+               }
+               en = lcd_dma.yres;
+               fn = lcd_dma.xres;
+               break;
+       default:
+               BUG();
+               return; /* Supress warning about uninitialized vars */
+       }
+
+       if (omap_dma_in_1510_mode()) {
+               omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
+               omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
+               omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
+               omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
+
+               return;
+       }
+
+       /* 1610 regs */
+       omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
+       omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
+       omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
+       omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
+
+       omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
+       omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
+
+       w = omap_readw(OMAP1610_DMA_LCD_CSDP);
+       w &= ~0x03;
+       w |= lcd_dma.data_type;
+       omap_writew(w, OMAP1610_DMA_LCD_CSDP);
+
+       w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+       /* Always set the source port as SDRAM for now*/
+       w &= ~(0x03 << 6);
+       if (lcd_dma.callback != NULL)
+               w |= 1 << 1;            /* Block interrupt enable */
+       else
+               w &= ~(1 << 1);
+       omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+
+       if (!(lcd_dma.rotate || lcd_dma.mirror ||
+             lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
+               return;
+
+       w = omap_readw(OMAP1610_DMA_LCD_CCR);
+       /* Set the double-indexed addressing mode */
+       w |= (0x03 << 12);
+       omap_writew(w, OMAP1610_DMA_LCD_CCR);
+
+       omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
+       omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
+       omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
+}
+
+static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id, struct pt_regs 
*regs)
+{
+       u16 w;
+
+       w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+       if (unlikely(!(w & (1 << 3)))) {
+               printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
+               return IRQ_NONE;
+       }
+       /* Ack the IRQ */
+       w |= (1 << 3);
+       omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+       lcd_dma.active = 0;
+       if (lcd_dma.callback != NULL)
+               lcd_dma.callback(w, lcd_dma.cb_data);
+
+       return IRQ_HANDLED;
+}
+
+int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
+                        void *data)
+{
+       spin_lock_irq(&lcd_dma.lock);
+       if (lcd_dma.reserved) {
+               spin_unlock_irq(&lcd_dma.lock);
+               printk(KERN_ERR "LCD DMA channel already reserved\n");
+               BUG();
+               return -EBUSY;
+       }
+       lcd_dma.reserved = 1;
+       spin_unlock_irq(&lcd_dma.lock);
+       lcd_dma.callback = callback;
+       lcd_dma.cb_data = data;
+       lcd_dma.active = 0;
+       lcd_dma.single_transfer = 0;
+       lcd_dma.rotate = 0;
+       lcd_dma.vxres = 0;
+       lcd_dma.mirror = 0;
+       lcd_dma.xscale = 0;
+       lcd_dma.yscale = 0;
+       lcd_dma.ext_ctrl = 0;
+       lcd_dma.src_port = 0;
+
+       return 0;
+}
+
+void omap_free_lcd_dma(void)
+{
+       spin_lock(&lcd_dma.lock);
+       if (!lcd_dma.reserved) {
+               spin_unlock(&lcd_dma.lock);
+               printk(KERN_ERR "LCD DMA is not reserved\n");
+               BUG();
+               return;
+       }
+       if (!enable_1510_mode)
+               omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, 
OMAP1610_DMA_LCD_CCR);
+       lcd_dma.reserved = 0;
+       spin_unlock(&lcd_dma.lock);
+}
+
+void omap_enable_lcd_dma(void)
+{
+       u16 w;
+
+       /* Set the Enable bit only if an external controller is
+        * connected. Otherwise the OMAP internal controller will
+        * start the transfer when it gets enabled.
+        */
+       if (enable_1510_mode || !lcd_dma.ext_ctrl)
+               return;
+
+       w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+       w |= 1 << 8;
+       omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+
+       w = omap_readw(OMAP1610_DMA_LCD_CCR);
+       w |= 1 << 7;
+       omap_writew(w, OMAP1610_DMA_LCD_CCR);
+
+       lcd_dma.active = 1;
+}
+
+void omap_setup_lcd_dma(void)
+{
+       BUG_ON(lcd_dma.active);
+       if (!enable_1510_mode) {
+               /* Set some reasonable defaults */
+               omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
+               omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
+               omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
+       }
+       set_b1_regs();
+       if (!enable_1510_mode) {
+               u16 w;
+
+               w = omap_readw(OMAP1610_DMA_LCD_CCR);
+               /* If DMA was already active set the end_prog bit to have
+                * the programmed register set loaded into the active
+                * register set.
+                */
+               w |= 1 << 11;           /* End_prog */
+               if (!lcd_dma.single_transfer)
+                       w |= (3 << 8);  /* Auto_init, repeat */
+               omap_writew(w, OMAP1610_DMA_LCD_CCR);
+       }
+}
+
+void omap_stop_lcd_dma(void)
+{
+       u16 w;
+
+       lcd_dma.active = 0;
+       if (enable_1510_mode || !lcd_dma.ext_ctrl)
+               return;
+
+       w = omap_readw(OMAP1610_DMA_LCD_CCR);
+       w &= ~(1 << 7);
+       omap_writew(w, OMAP1610_DMA_LCD_CCR);
+
+       w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+       w &= ~(1 << 8);
+       omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+}
+
+/*
+ * Clears any DMA state so the DMA engine is ready to restart with new buffers
+ * through omap_start_dma(). Any buffers in flight are discarded.
+ */
+void omap_clear_dma(int lch)
+{
+       unsigned long flags;
+       int status;
+
+       local_irq_save(flags);
+       omap_writew(omap_readw(OMAP_DMA_CCR(lch)) & ~OMAP_DMA_CCR_EN,
+                   OMAP_DMA_CCR(lch));
+       status = OMAP_DMA_CSR(lch);     /* clear pending interrupts */
+       local_irq_restore(flags);
+}
+
+/*
+ * Returns current physical source address for the given DMA channel.
+ * If the channel is running the caller must disable interrupts prior calling
+ * this function and process the returned value before re-enabling interrupt to
+ * prevent races with the interrupt handler. Note that in continuous mode there
+ * is a chance for CSSA_L register overflow inbetween the two reads resulting
+ * in incorrect return value.
+ */
+dma_addr_t omap_get_dma_src_pos(int lch)
+{
+       return (dma_addr_t) (OMAP_DMA_CSSA_L(lch) |
+                            (OMAP_DMA_CSSA_U(lch) << 16));
+}
+
+/*
+ * Returns current physical destination address for the given DMA channel.
+ * If the channel is running the caller must disable interrupts prior calling
+ * this function and process the returned value before re-enabling interrupt to
+ * prevent races with the interrupt handler. Note that in continuous mode there
+ * is a chance for CDSA_L register overflow inbetween the two reads resulting
+ * in incorrect return value.
+ */
+dma_addr_t omap_get_dma_dst_pos(int lch)
+{
+       return (dma_addr_t) (OMAP_DMA_CDSA_L(lch) |
+                            (OMAP_DMA_CDSA_U(lch) << 16));
+}
+
+int omap_dma_running(void)
+{
+       int lch;
+
+       /* Check if LCD DMA is running */
+       if (cpu_is_omap16xx())
+               if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
+                       return 1;
+
+       for (lch = 0; lch < dma_chan_count; lch++) {
+               u16 w;
+
+               w = omap_readw(OMAP_DMA_CCR(lch));
+               if (w & OMAP_DMA_CCR_EN)
+                       return 1;
+       }
+       return 0;
+}
+
+static int __init omap_init_dma(void)
+{
+       int ch, r;
+
+       if (cpu_is_omap1510()) {
+               printk(KERN_INFO "DMA support for OMAP1510 initialized\n");
+               dma_chan_count = 9;
+               enable_1510_mode = 1;
+       } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
+               printk(KERN_INFO "OMAP DMA hardware version %d\n",
+                      omap_readw(OMAP_DMA_HW_ID));
+               printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
+                      (omap_readw(OMAP_DMA_CAPS_0_U) << 16) | 
omap_readw(OMAP_DMA_CAPS_0_L),
+                      (omap_readw(OMAP_DMA_CAPS_1_U) << 16) | 
omap_readw(OMAP_DMA_CAPS_1_L),
+                      omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
+                      omap_readw(OMAP_DMA_CAPS_4));
+               if (!enable_1510_mode) {
+                       u16 w;
+
+                       /* Disable OMAP 3.0/3.1 compatibility mode. */
+                       w = omap_readw(OMAP_DMA_GSCR);
+                       w |= 1 << 3;
+                       omap_writew(w, OMAP_DMA_GSCR);
+                       dma_chan_count = 16;
+               } else
+                       dma_chan_count = 9;
+       } else {
+               dma_chan_count = 0;
+               return 0;
+       }
+
+       memset(&lcd_dma, 0, sizeof(lcd_dma));
+       spin_lock_init(&lcd_dma.lock);
+       spin_lock_init(&dma_chan_lock);
+       memset(&dma_chan, 0, sizeof(dma_chan));
+
+       for (ch = 0; ch < dma_chan_count; ch++) {
+               dma_chan[ch].dev_id = -1;
+               dma_chan[ch].next_lch = -1;
+
+               if (ch >= 6 && enable_1510_mode)
+                       continue;
+
+               /* request_irq() doesn't like dev_id (ie. ch) being zero,
+                * so we have to kludge around this. */
+               r = request_irq(dma_irq[ch], dma_irq_handler, 0, "DMA",
+                               (void *) (ch + 1));
+               if (r != 0) {
+                       int i;
+
+                       printk(KERN_ERR "unable to request IRQ %d for DMA 
(error %d)\n",
+                              dma_irq[ch], r);
+                       for (i = 0; i < ch; i++)
+                               free_irq(dma_irq[i], (void *) (i + 1));
+                       return r;
+               }
+       }
+       r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, "LCD DMA", NULL);
+       if (r != 0) {
+               int i;
+
+               printk(KERN_ERR "unable to request IRQ for LCD DMA (error 
%d)\n", r);
+               for (i = 0; i < dma_chan_count; i++)
+                       free_irq(dma_irq[i], (void *) (i + 1));
+               return r;
+       }
+       return 0;
+}
+
+arch_initcall(omap_init_dma);
+
+
+EXPORT_SYMBOL(omap_get_dma_src_pos);
+EXPORT_SYMBOL(omap_get_dma_dst_pos);
+EXPORT_SYMBOL(omap_clear_dma);
+EXPORT_SYMBOL(omap_set_dma_priority);
+EXPORT_SYMBOL(omap_request_dma);
+EXPORT_SYMBOL(omap_free_dma);
+EXPORT_SYMBOL(omap_start_dma);
+EXPORT_SYMBOL(omap_stop_dma);
+EXPORT_SYMBOL(omap_enable_dma_irq);
+EXPORT_SYMBOL(omap_disable_dma_irq);
+
+EXPORT_SYMBOL(omap_set_dma_transfer_params);
+EXPORT_SYMBOL(omap_set_dma_color_mode);
+
+EXPORT_SYMBOL(omap_set_dma_src_params);
+EXPORT_SYMBOL(omap_set_dma_src_index);
+EXPORT_SYMBOL(omap_set_dma_src_data_pack);
+EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
+
+EXPORT_SYMBOL(omap_set_dma_dest_params);
+EXPORT_SYMBOL(omap_set_dma_dest_index);
+EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
+EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
+
+EXPORT_SYMBOL(omap_dma_link_lch);
+EXPORT_SYMBOL(omap_dma_unlink_lch);
+
+EXPORT_SYMBOL(omap_request_lcd_dma);
+EXPORT_SYMBOL(omap_free_lcd_dma);
+EXPORT_SYMBOL(omap_enable_lcd_dma);
+EXPORT_SYMBOL(omap_setup_lcd_dma);
+EXPORT_SYMBOL(omap_stop_lcd_dma);
+EXPORT_SYMBOL(omap_set_lcd_dma_b1);
+EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
+EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
+
diff -urN linux/arch/arm/plat-omap/gpio.c linux/arch/arm/plat-omap/gpio.c
--- linux/arch/arm/plat-omap/gpio.c     1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/gpio.c     2005-07-13 12:48:53.947488000 +0100     
1.1
@@ -0,0 +1,762 @@
+/*
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach/irq.h>
+
+#include <asm/io.h>
+
+/*
+ * OMAP1510 GPIO registers
+ */
+#define OMAP1510_GPIO_BASE             0xfffce000
+#define OMAP1510_GPIO_DATA_INPUT       0x00
+#define OMAP1510_GPIO_DATA_OUTPUT      0x04
+#define OMAP1510_GPIO_DIR_CONTROL      0x08
+#define OMAP1510_GPIO_INT_CONTROL      0x0c
+#define OMAP1510_GPIO_INT_MASK         0x10
+#define OMAP1510_GPIO_INT_STATUS       0x14
+#define OMAP1510_GPIO_PIN_CONTROL      0x18
+
+#define OMAP1510_IH_GPIO_BASE          64
+
+/*
+ * OMAP1610 specific GPIO registers
+ */
+#define OMAP1610_GPIO1_BASE            0xfffbe400
+#define OMAP1610_GPIO2_BASE            0xfffbec00
+#define OMAP1610_GPIO3_BASE            0xfffbb400
+#define OMAP1610_GPIO4_BASE            0xfffbbc00
+#define OMAP1610_GPIO_REVISION         0x0000
+#define OMAP1610_GPIO_SYSCONFIG                0x0010
+#define OMAP1610_GPIO_SYSSTATUS                0x0014
+#define OMAP1610_GPIO_IRQSTATUS1       0x0018
+#define OMAP1610_GPIO_IRQENABLE1       0x001c
+#define OMAP1610_GPIO_DATAIN           0x002c
+#define OMAP1610_GPIO_DATAOUT          0x0030
+#define OMAP1610_GPIO_DIRECTION                0x0034
+#define OMAP1610_GPIO_EDGE_CTRL1       0x0038
+#define OMAP1610_GPIO_EDGE_CTRL2       0x003c
+#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
+#define OMAP1610_GPIO_CLEAR_DATAOUT    0x00b0
+#define OMAP1610_GPIO_SET_IRQENABLE1   0x00dc
+#define OMAP1610_GPIO_SET_DATAOUT      0x00f0
+
+/*
+ * OMAP730 specific GPIO registers
+ */
+#define OMAP730_GPIO1_BASE             0xfffbc000
+#define OMAP730_GPIO2_BASE             0xfffbc800
+#define OMAP730_GPIO3_BASE             0xfffbd000
+#define OMAP730_GPIO4_BASE             0xfffbd800
+#define OMAP730_GPIO5_BASE             0xfffbe000
+#define OMAP730_GPIO6_BASE             0xfffbe800
+#define OMAP730_GPIO_DATA_INPUT                0x00
+#define OMAP730_GPIO_DATA_OUTPUT       0x04
+#define OMAP730_GPIO_DIR_CONTROL       0x08
+#define OMAP730_GPIO_INT_CONTROL       0x0c
+#define OMAP730_GPIO_INT_MASK          0x10
+#define OMAP730_GPIO_INT_STATUS                0x14
+
+#define OMAP_MPUIO_MASK                (~OMAP_MAX_GPIO_LINES & 0xff)
+
+struct gpio_bank {
+       u32 base;
+       u16 irq;
+       u16 virtual_irq_start;
+       u8 method;
+       u32 reserved_map;
+       spinlock_t lock;
+};
+
+#define METHOD_MPUIO           0
+#define METHOD_GPIO_1510       1
+#define METHOD_GPIO_1610       2
+#define METHOD_GPIO_730                3
+
+#if defined(CONFIG_ARCH_OMAP16XX)
+static struct gpio_bank gpio_bank_1610[5] = {
+       { OMAP_MPUIO_BASE,     INT_MPUIO,           IH_MPUIO_BASE,     
METHOD_MPUIO},
+       { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,      IH_GPIO_BASE,      
METHOD_GPIO_1610 },
+       { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, 
METHOD_GPIO_1610 },
+       { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, 
METHOD_GPIO_1610 },
+       { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, 
METHOD_GPIO_1610 },
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1510
+static struct gpio_bank gpio_bank_1510[2] = {
+       { OMAP_MPUIO_BASE,    INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
+       { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP730
+static struct gpio_bank gpio_bank_730[7] = {
+       { OMAP_MPUIO_BASE,     INT_730_MPUIO,       IH_MPUIO_BASE,      
METHOD_MPUIO },
+       { OMAP730_GPIO1_BASE,  INT_730_GPIO_BANK1,  IH_GPIO_BASE,       
METHOD_GPIO_730 },
+       { OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,  
METHOD_GPIO_730 },
+       { OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,  
METHOD_GPIO_730 },
+       { OMAP730_GPIO4_BASE,  INT_730_GPIO_BANK4,  IH_GPIO_BASE + 96,  
METHOD_GPIO_730 },
+       { OMAP730_GPIO5_BASE,  INT_730_GPIO_BANK5,  IH_GPIO_BASE + 128, 
METHOD_GPIO_730 },
+       { OMAP730_GPIO6_BASE,  INT_730_GPIO_BANK6,  IH_GPIO_BASE + 160, 
METHOD_GPIO_730 },
+};
+#endif
+
+static struct gpio_bank *gpio_bank;
+static int gpio_bank_count;
+
+static inline struct gpio_bank *get_gpio_bank(int gpio)
+{
+#ifdef CONFIG_ARCH_OMAP1510
+       if (cpu_is_omap1510()) {
+               if (OMAP_GPIO_IS_MPUIO(gpio))
+                       return &gpio_bank[0];
+               return &gpio_bank[1];
+       }
+#endif
+#if defined(CONFIG_ARCH_OMAP16XX)
+       if (cpu_is_omap16xx()) {
+               if (OMAP_GPIO_IS_MPUIO(gpio))
+                       return &gpio_bank[0];
+               return &gpio_bank[1 + (gpio >> 4)];
+       }
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+       if (cpu_is_omap730()) {
+               if (OMAP_GPIO_IS_MPUIO(gpio))
+                       return &gpio_bank[0];
+               return &gpio_bank[1 + (gpio >> 5)];
+       }
+#endif
+}
+
+static inline int get_gpio_index(int gpio)
+{
+       if (cpu_is_omap730())
+               return gpio & 0x1f;
+       else
+               return gpio & 0x0f;
+}
+
+static inline int gpio_valid(int gpio)
+{
+       if (gpio < 0)
+               return -1;
+       if (OMAP_GPIO_IS_MPUIO(gpio)) {
+               if ((gpio & OMAP_MPUIO_MASK) > 16)
+                       return -1;
+               return 0;
+       }
+#ifdef CONFIG_ARCH_OMAP1510
+       if (cpu_is_omap1510() && gpio < 16)
+               return 0;
+#endif
+#if defined(CONFIG_ARCH_OMAP16XX)
+       if ((cpu_is_omap16xx()) && gpio < 64)
+               return 0;
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+       if (cpu_is_omap730() && gpio < 192)
+               return 0;
+#endif
+       return -1;
+}
+
+static int check_gpio(int gpio)
+{
+       if (unlikely(gpio_valid(gpio)) < 0) {
+               printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
+               dump_stack();
+               return -1;
+       }
+       return 0;
+}
+
+static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
+{
+       u32 reg = bank->base;
+       u32 l;
+
+       switch (bank->method) {
+       case METHOD_MPUIO:
+               reg += OMAP_MPUIO_IO_CNTL;
+               break;
+       case METHOD_GPIO_1510:
+               reg += OMAP1510_GPIO_DIR_CONTROL;
+               break;
+       case METHOD_GPIO_1610:
+               reg += OMAP1610_GPIO_DIRECTION;
+               break;
+       case METHOD_GPIO_730:
+               reg += OMAP730_GPIO_DIR_CONTROL;
+               break;
+       }
+       l = __raw_readl(reg);
+       if (is_input)
+               l |= 1 << gpio;
+       else
+               l &= ~(1 << gpio);
+       __raw_writel(l, reg);
+}
+
+void omap_set_gpio_direction(int gpio, int is_input)
+{
+       struct gpio_bank *bank;
+
+       if (check_gpio(gpio) < 0)
+               return;
+       bank = get_gpio_bank(gpio);
+       spin_lock(&bank->lock);
+       _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
+       spin_unlock(&bank->lock);
+}
+
+static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
+{
+       u32 reg = bank->base;
+       u32 l = 0;
+
+       switch (bank->method) {
+       case METHOD_MPUIO:
+               reg += OMAP_MPUIO_OUTPUT;
+               l = __raw_readl(reg);
+               if (enable)
+                       l |= 1 << gpio;
+               else
+                       l &= ~(1 << gpio);
+               break;
+       case METHOD_GPIO_1510:
+               reg += OMAP1510_GPIO_DATA_OUTPUT;
+               l = __raw_readl(reg);
+               if (enable)
+                       l |= 1 << gpio;
+               else
+                       l &= ~(1 << gpio);
+               break;
+       case METHOD_GPIO_1610:
+               if (enable)
+                       reg += OMAP1610_GPIO_SET_DATAOUT;
+               else
+                       reg += OMAP1610_GPIO_CLEAR_DATAOUT;
+               l = 1 << gpio;
+               break;
+       case METHOD_GPIO_730:
+               reg += OMAP730_GPIO_DATA_OUTPUT;
+               l = __raw_readl(reg);
+               if (enable)
+                       l |= 1 << gpio;
+               else
+                       l &= ~(1 << gpio);
+               break;
+       default:
+               BUG();
+               return;
+       }
+       __raw_writel(l, reg);
+}
+
+void omap_set_gpio_dataout(int gpio, int enable)
+{
+       struct gpio_bank *bank;
+
+       if (check_gpio(gpio) < 0)
+               return;
+       bank = get_gpio_bank(gpio);
+       spin_lock(&bank->lock);
+       _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
+       spin_unlock(&bank->lock);
+}
+
+int omap_get_gpio_datain(int gpio)
+{
+       struct gpio_bank *bank;
+       u32 reg;
+
+       if (check_gpio(gpio) < 0)
+               return -1;
+       bank = get_gpio_bank(gpio);
+       reg = bank->base;
+       switch (bank->method) {
+       case METHOD_MPUIO:
+               reg += OMAP_MPUIO_INPUT_LATCH;
+               break;
+       case METHOD_GPIO_1510:
+               reg += OMAP1510_GPIO_DATA_INPUT;
+               break;
+       case METHOD_GPIO_1610:
+               reg += OMAP1610_GPIO_DATAIN;
+               break;
+       case METHOD_GPIO_730:
+               reg += OMAP730_GPIO_DATA_INPUT;
+               break;
+       default:
+               BUG();
+               return -1;
+       }
+       return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
+}
+
+static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge)
+{
+       u32 reg = bank->base;
+       u32 l;
+
+       switch (bank->method) {
+       case METHOD_MPUIO:
+               reg += OMAP_MPUIO_GPIO_INT_EDGE;
+               l = __raw_readl(reg);
+               if (edge == OMAP_GPIO_RISING_EDGE)
+                       l |= 1 << gpio;
+               else
+                       l &= ~(1 << gpio);
+               __raw_writel(l, reg);
+               break;
+       case METHOD_GPIO_1510:
+               reg += OMAP1510_GPIO_INT_CONTROL;
+               l = __raw_readl(reg);
+               if (edge == OMAP_GPIO_RISING_EDGE)
+                       l |= 1 << gpio;
+               else
+                       l &= ~(1 << gpio);
+               __raw_writel(l, reg);
+               break;
+       case METHOD_GPIO_1610:
+               edge &= 0x03;
+               if (gpio & 0x08)
+                       reg += OMAP1610_GPIO_EDGE_CTRL2;
+               else
+                       reg += OMAP1610_GPIO_EDGE_CTRL1;
+               gpio &= 0x07;
+               l = __raw_readl(reg);
+               l &= ~(3 << (gpio << 1));
+               l |= edge << (gpio << 1);
+               __raw_writel(l, reg);
+               break;
+       case METHOD_GPIO_730:
+               reg += OMAP730_GPIO_INT_CONTROL;
+               l = __raw_readl(reg);
+               if (edge == OMAP_GPIO_RISING_EDGE)
+                       l |= 1 << gpio;
+               else
+                       l &= ~(1 << gpio);
+               __raw_writel(l, reg);
+               break;
+       default:
+               BUG();
+               return;
+       }
+}
+
+void omap_set_gpio_edge_ctrl(int gpio, int edge)
+{
+       struct gpio_bank *bank;
+
+       if (check_gpio(gpio) < 0)
+               return;
+       bank = get_gpio_bank(gpio);
+       spin_lock(&bank->lock);
+       _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), edge);
+       spin_unlock(&bank->lock);
+}
+
+
+static int _get_gpio_edge_ctrl(struct gpio_bank *bank, int gpio)
+{
+       u32 reg = bank->base, l;
+
+       switch (bank->method) {
+       case METHOD_MPUIO:
+               l = __raw_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE);
+               return (l & (1 << gpio)) ?
+                       OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
+       case METHOD_GPIO_1510:
+               l = __raw_readl(reg + OMAP1510_GPIO_INT_CONTROL);
+               return (l & (1 << gpio)) ?
+                       OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
+       case METHOD_GPIO_1610:
+               if (gpio & 0x08)
+                       reg += OMAP1610_GPIO_EDGE_CTRL2;
+               else
+                       reg += OMAP1610_GPIO_EDGE_CTRL1;
+               return (__raw_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03;
+       case METHOD_GPIO_730:
+               l = __raw_readl(reg + OMAP730_GPIO_INT_CONTROL);
+               return (l & (1 << gpio)) ?
+                       OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
+       default:
+               BUG();
+               return -1;
+       }
+}
+
+static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
+{
+       u32 reg = bank->base;
+
+       switch (bank->method) {
+       case METHOD_MPUIO:
+               /* MPUIO irqstatus is reset by reading the status register,
+                * so do nothing here */
+               return;
+       case METHOD_GPIO_1510:
+               reg += OMAP1510_GPIO_INT_STATUS;
+               break;
+       case METHOD_GPIO_1610:
+               reg += OMAP1610_GPIO_IRQSTATUS1;
+               break;
+       case METHOD_GPIO_730:
+               reg += OMAP730_GPIO_INT_STATUS;
+               break;
+       default:
+               BUG();
+               return;
+       }
+       __raw_writel(gpio_mask, reg);
+}
+
+static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
+{
+       _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
+}
+
+static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int 
enable)
+{
+       u32 reg = bank->base;
+       u32 l;
+
+       switch (bank->method) {
+       case METHOD_MPUIO:
+               reg += OMAP_MPUIO_GPIO_MASKIT;
+               l = __raw_readl(reg);
+               if (enable)
+                       l &= ~(gpio_mask);
+               else
+                       l |= gpio_mask;
+               break;
+       case METHOD_GPIO_1510:
+               reg += OMAP1510_GPIO_INT_MASK;
+               l = __raw_readl(reg);
+               if (enable)
+                       l &= ~(gpio_mask);
+               else
+                       l |= gpio_mask;
+               break;
+       case METHOD_GPIO_1610:
+               if (enable)
+                       reg += OMAP1610_GPIO_SET_IRQENABLE1;
+               else
+                       reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
+               l = gpio_mask;
+               break;
+       case METHOD_GPIO_730:
+               reg += OMAP730_GPIO_INT_MASK;
+               l = __raw_readl(reg);
+               if (enable)
+                       l &= ~(gpio_mask);
+               else
+                       l |= gpio_mask;
+               break;
+       default:
+               BUG();
+               return;
+       }
+       __raw_writel(l, reg);
+}
+
+static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int 
enable)
+{
+       _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
+}
+
+int omap_request_gpio(int gpio)
+{
+       struct gpio_bank *bank;
+
+       if (check_gpio(gpio) < 0)
+               return -EINVAL;
+
+       bank = get_gpio_bank(gpio);
+       spin_lock(&bank->lock);
+       if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
+               printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", 
gpio);
+               dump_stack();
+               spin_unlock(&bank->lock);
+               return -1;
+       }
+       bank->reserved_map |= (1 << get_gpio_index(gpio));
+#ifdef CONFIG_ARCH_OMAP1510
+       if (bank->method == METHOD_GPIO_1510) {
+               u32 reg;
+
+               /* Claim the pin for the ARM */
+               reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
+               __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), 
reg);
+       }
+#endif
+       spin_unlock(&bank->lock);
+
+       return 0;
+}
+
+void omap_free_gpio(int gpio)
+{
+       struct gpio_bank *bank;
+
+       if (check_gpio(gpio) < 0)
+               return;
+       bank = get_gpio_bank(gpio);
+       spin_lock(&bank->lock);
+       if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
+               printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
+               dump_stack();
+               spin_unlock(&bank->lock);
+               return;
+       }
+       bank->reserved_map &= ~(1 << get_gpio_index(gpio));
+       _set_gpio_direction(bank, get_gpio_index(gpio), 1);
+       _set_gpio_irqenable(bank, gpio, 0);
+       _clear_gpio_irqstatus(bank, gpio);
+       spin_unlock(&bank->lock);
+}
+
+/*
+ * We need to unmask the GPIO bank interrupt as soon as possible to
+ * avoid missing GPIO interrupts for other lines in the bank.
+ * Then we need to mask-read-clear-unmask the triggered GPIO lines
+ * in the bank to avoid missing nested interrupts for a GPIO line.
+ * If we wait to unmask individual GPIO lines in the bank after the
+ * line's interrupt handler has been run, we may miss some nested
+ * interrupts.
+ */
+static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
+                            struct pt_regs *regs)
+{
+       u32 isr_reg = 0;
+       u32 isr;
+       unsigned int gpio_irq;
+       struct gpio_bank *bank;
+
+       desc->chip->ack(irq);
+
+       bank = (struct gpio_bank *) desc->data;
+       if (bank->method == METHOD_MPUIO)
+               isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
+#ifdef CONFIG_ARCH_OMAP1510
+       if (bank->method == METHOD_GPIO_1510)
+               isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
+#endif
+#if defined(CONFIG_ARCH_OMAP16XX)
+       if (bank->method == METHOD_GPIO_1610)
+               isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+       if (bank->method == METHOD_GPIO_730)
+               isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
+#endif
+
+       isr = __raw_readl(isr_reg);
+       _enable_gpio_irqbank(bank, isr, 0);
+       _clear_gpio_irqbank(bank, isr);
+       _enable_gpio_irqbank(bank, isr, 1);
+       desc->chip->unmask(irq);
+
+       if (unlikely(!isr))
+               return;
+
+       gpio_irq = bank->virtual_irq_start;
+       for (; isr != 0; isr >>= 1, gpio_irq++) {
+               struct irqdesc *d;
+               if (!(isr & 1))
+                       continue;
+               d = irq_desc + gpio_irq;
+               d->handle(gpio_irq, d, regs);
+       }
+}
+
+static void gpio_ack_irq(unsigned int irq)
+{
+       unsigned int gpio = irq - IH_GPIO_BASE;
+       struct gpio_bank *bank = get_gpio_bank(gpio);
+
+       _clear_gpio_irqstatus(bank, gpio);
+}
+
+static void gpio_mask_irq(unsigned int irq)
+{
+       unsigned int gpio = irq - IH_GPIO_BASE;
+       struct gpio_bank *bank = get_gpio_bank(gpio);
+
+       _set_gpio_irqenable(bank, gpio, 0);
+}
+
+static void gpio_unmask_irq(unsigned int irq)
+{
+       unsigned int gpio = irq - IH_GPIO_BASE;
+       struct gpio_bank *bank = get_gpio_bank(gpio);
+
+       if (_get_gpio_edge_ctrl(bank, get_gpio_index(gpio)) == 
OMAP_GPIO_NO_EDGE) {
+               printk(KERN_ERR "OMAP GPIO %d: trying to enable GPIO IRQ while 
no edge is set\n",
+                      gpio);
+               _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), 
OMAP_GPIO_RISING_EDGE);
+       }
+       _set_gpio_irqenable(bank, gpio, 1);
+}
+
+static void mpuio_ack_irq(unsigned int irq)
+{
+       /* The ISR is reset automatically, so do nothing here. */
+}
+
+static void mpuio_mask_irq(unsigned int irq)
+{
+       unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
+       struct gpio_bank *bank = get_gpio_bank(gpio);
+
+       _set_gpio_irqenable(bank, gpio, 0);
+}
+
+static void mpuio_unmask_irq(unsigned int irq)
+{
+       unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
+       struct gpio_bank *bank = get_gpio_bank(gpio);
+
+       _set_gpio_irqenable(bank, gpio, 1);
+}
+
+static struct irqchip gpio_irq_chip = {
+       .ack    = gpio_ack_irq,
+       .mask   = gpio_mask_irq,
+       .unmask = gpio_unmask_irq,
+};
+
+static struct irqchip mpuio_irq_chip = {
+       .ack    = mpuio_ack_irq,
+       .mask   = mpuio_mask_irq,
+       .unmask = mpuio_unmask_irq
+};
+
+static int initialized = 0;
+
+static int __init _omap_gpio_init(void)
+{
+       int i;
+       struct gpio_bank *bank;
+
+       initialized = 1;
+
+#ifdef CONFIG_ARCH_OMAP1510
+       if (cpu_is_omap1510()) {
+               printk(KERN_INFO "OMAP1510 GPIO hardware\n");
+               gpio_bank_count = 2;
+               gpio_bank = gpio_bank_1510;
+       }
+#endif
+#if defined(CONFIG_ARCH_OMAP16XX)
+       if (cpu_is_omap16xx()) {
+               int rev;
+
+               gpio_bank_count = 5;
+               gpio_bank = gpio_bank_1610;
+               rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
+               printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
+                      (rev >> 4) & 0x0f, rev & 0x0f);
+       }
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+       if (cpu_is_omap730()) {
+               printk(KERN_INFO "OMAP730 GPIO hardware\n");
+               gpio_bank_count = 7;
+               gpio_bank = gpio_bank_730;
+       }
+#endif
+       for (i = 0; i < gpio_bank_count; i++) {
+               int j, gpio_count = 16;
+
+               bank = &gpio_bank[i];
+               bank->reserved_map = 0;
+               bank->base = IO_ADDRESS(bank->base);
+               spin_lock_init(&bank->lock);
+               if (bank->method == METHOD_MPUIO) {
+                       omap_writew(0xFFFF, OMAP_MPUIO_BASE + 
OMAP_MPUIO_GPIO_MASKIT);
+               }
+#ifdef CONFIG_ARCH_OMAP1510
+               if (bank->method == METHOD_GPIO_1510) {
+                       __raw_writew(0xffff, bank->base + 
OMAP1510_GPIO_INT_MASK);
+                       __raw_writew(0x0000, bank->base + 
OMAP1510_GPIO_INT_STATUS);
+               }
+#endif
+#if defined(CONFIG_ARCH_OMAP16XX)
+               if (bank->method == METHOD_GPIO_1610) {
+                       __raw_writew(0x0000, bank->base + 
OMAP1610_GPIO_IRQENABLE1);
+                       __raw_writew(0xffff, bank->base + 
OMAP1610_GPIO_IRQSTATUS1);
+               }
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+               if (bank->method == METHOD_GPIO_730) {
+                       __raw_writel(0xffffffff, bank->base + 
OMAP730_GPIO_INT_MASK);
+                       __raw_writel(0x00000000, bank->base + 
OMAP730_GPIO_INT_STATUS);
+
+                       gpio_count = 32; /* 730 has 32-bit GPIOs */
+               }
+#endif
+               for (j = bank->virtual_irq_start;
+                    j < bank->virtual_irq_start + gpio_count; j++) {
+                       if (bank->method == METHOD_MPUIO)
+                               set_irq_chip(j, &mpuio_irq_chip);
+                       else
+                               set_irq_chip(j, &gpio_irq_chip);
+                       set_irq_handler(j, do_simple_IRQ);
+                       set_irq_flags(j, IRQF_VALID);
+               }
+               set_irq_chained_handler(bank->irq, gpio_irq_handler);
+               set_irq_data(bank->irq, bank);
+       }
+
+       /* Enable system clock for GPIO module.
+        * The CAM_CLK_CTRL *is* really the right place. */
+       if (cpu_is_omap1610() || cpu_is_omap1710())
+               omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, 
ULPD_CAM_CLK_CTRL);
+
+       return 0;
+}
+
+/*
+ * This may get called early from board specific init
+ */
+int omap_gpio_init(void)
+{
+       if (!initialized)
+               return _omap_gpio_init();
+       else
+               return 0;
+}
+
+EXPORT_SYMBOL(omap_request_gpio);
+EXPORT_SYMBOL(omap_free_gpio);
+EXPORT_SYMBOL(omap_set_gpio_direction);
+EXPORT_SYMBOL(omap_set_gpio_dataout);
+EXPORT_SYMBOL(omap_get_gpio_datain);
+EXPORT_SYMBOL(omap_set_gpio_edge_ctrl);
+
+arch_initcall(omap_gpio_init);
diff -urN linux/arch/arm/plat-omap/mcbsp.c linux/arch/arm/plat-omap/mcbsp.c
--- linux/arch/arm/plat-omap/mcbsp.c    1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/mcbsp.c    2005-07-13 12:48:53.975687000 +0100     
1.1
@@ -0,0 +1,758 @@
+/*
+ * linux/arch/arm/plat-omap/mcbsp.c
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Multichannel mode not supported.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/wait.h>
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <asm/arch/dma.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/mcbsp.h>
+
+#include <asm/hardware/clock.h>
+
+#ifdef CONFIG_MCBSP_DEBUG
+#define DBG(x...)      printk(x)
+#else
+#define DBG(x...)      do { } while (0)
+#endif
+
+struct omap_mcbsp {
+       u32                          io_base;
+       u8                           id;
+       u8                           free;
+       omap_mcbsp_word_length       rx_word_length;
+       omap_mcbsp_word_length       tx_word_length;
+
+       /* IRQ based TX/RX */
+       int                          rx_irq;
+       int                          tx_irq;
+
+       /* DMA stuff */
+       u8                           dma_rx_sync;
+       short                        dma_rx_lch;
+       u8                           dma_tx_sync;
+       short                        dma_tx_lch;
+
+       /* Completion queues */
+       struct completion            tx_irq_completion;
+       struct completion            rx_irq_completion;
+       struct completion            tx_dma_completion;
+       struct completion            rx_dma_completion;
+
+       spinlock_t                   lock;
+};
+
+static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
+static struct clk *mcbsp_dsp_ck = 0;
+static struct clk *mcbsp_api_ck = 0;
+static struct clk *mcbsp_dspxor_ck = 0;
+
+
+static void omap_mcbsp_dump_reg(u8 id)
+{
+       DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
+       DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
+       DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
+       DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
+       DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
+       DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
+       DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
+       DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
+       DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
+       DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
+       DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
+       DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
+       DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
+       DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
+       DBG("***********************\n");
+}
+
+
+static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id, struct 
pt_regs *regs)
+{
+       struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id);
+
+       DBG("TX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_tx->io_base, 
SPCR2));
+
+       complete(&mcbsp_tx->tx_irq_completion);
+       return IRQ_HANDLED;
+}
+
+static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id, struct 
pt_regs *regs)
+{
+       struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id);
+
+       DBG("RX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_rx->io_base, 
SPCR2));
+
+       complete(&mcbsp_rx->rx_irq_completion);
+       return IRQ_HANDLED;
+}
+
+
+static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
+{
+       struct omap_mcbsp * mcbsp_dma_tx = (struct omap_mcbsp *)(data);
+
+       DBG("TX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, 
SPCR2));
+
+       /* We can free the channels */
+       omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
+       mcbsp_dma_tx->dma_tx_lch = -1;
+
+       complete(&mcbsp_dma_tx->tx_dma_completion);
+}
+
+static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
+{
+       struct omap_mcbsp * mcbsp_dma_rx = (struct omap_mcbsp *)(data);
+
+       DBG("RX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, 
SPCR2));
+
+       /* We can free the channels */
+       omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
+       mcbsp_dma_rx->dma_rx_lch = -1;
+
+       complete(&mcbsp_dma_rx->rx_dma_completion);
+}
+
+
+/*
+ * omap_mcbsp_config simply write a config to the
+ * appropriate McBSP.
+ * You either call this function or set the McBSP registers
+ * by yourself before calling omap_mcbsp_start().
+ */
+
+void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * 
config)
+{
+       u32 io_base = mcbsp[id].io_base;
+
+       DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id+1, io_base);
+
+       /* We write the given config */
+       OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
+       OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
+       OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
+       OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
+       OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
+       OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
+       OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
+       OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
+       OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
+       OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
+       OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
+}
+
+
+
+static int omap_mcbsp_check(unsigned int id)
+{
+       if (cpu_is_omap730()) {
+               if (id > OMAP_MAX_MCBSP_COUNT - 1) {
+                      printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", 
id + 1);
+                      return -1;
+               }
+               return 0;
+       }
+
+       if (cpu_is_omap1510() || cpu_is_omap16xx()) {
+               if (id > OMAP_MAX_MCBSP_COUNT) {
+                       printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", 
id + 1);
+                       return -1;
+               }
+               return 0;
+       }
+
+       return -1;
+}
+
+#define EN_XORPCK              1
+#define DSP_RSTCT2              0xe1008014
+
+static void omap_mcbsp_dsp_request(void)
+{
+       if (cpu_is_omap1510() || cpu_is_omap16xx()) {
+               clk_use(mcbsp_dsp_ck);
+               clk_use(mcbsp_api_ck);
+
+               /* enable 12MHz clock to mcbsp 1 & 3 */
+               clk_use(mcbsp_dspxor_ck);
+               __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
+                            DSP_RSTCT2);
+       }
+}
+
+static void omap_mcbsp_dsp_free(void)
+{
+       if (cpu_is_omap1510() || cpu_is_omap16xx()) {
+               clk_unuse(mcbsp_dspxor_ck);
+               clk_unuse(mcbsp_dsp_ck);
+               clk_unuse(mcbsp_api_ck);
+       }
+}
+
+int omap_mcbsp_request(unsigned int id)
+{
+       int err;
+
+       if (omap_mcbsp_check(id) < 0)
+               return -EINVAL;
+
+       /*
+        * On 1510, 1610 and 1710, McBSP1 and McBSP3
+        * are DSP public peripherals.
+        */
+       if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
+               omap_mcbsp_dsp_request();
+
+       spin_lock(&mcbsp[id].lock);
+       if (!mcbsp[id].free) {
+               printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", 
id + 1);
+               spin_unlock(&mcbsp[id].lock);
+               return -1;
+       }
+
+       mcbsp[id].free = 0;
+       spin_unlock(&mcbsp[id].lock);
+
+       /* We need to get IRQs here */
+       err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
+                         "McBSP",
+                         (void *) (&mcbsp[id]));
+       if (err != 0) {
+               printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for 
McBSP%d\n",
+                      mcbsp[id].tx_irq, mcbsp[id].id);
+               return err;
+       }
+
+       init_completion(&(mcbsp[id].tx_irq_completion));
+
+
+       err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
+                         "McBSP",
+                         (void *) (&mcbsp[id]));
+       if (err != 0) {
+               printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for 
McBSP%d\n",
+                      mcbsp[id].rx_irq, mcbsp[id].id);
+               free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
+               return err;
+       }
+
+       init_completion(&(mcbsp[id].rx_irq_completion));
+       return 0;
+
+}
+
+void omap_mcbsp_free(unsigned int id)
+{
+       if (omap_mcbsp_check(id) < 0)
+               return;
+
+       if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
+               omap_mcbsp_dsp_free();
+
+       spin_lock(&mcbsp[id].lock);
+       if (mcbsp[id].free) {
+               printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 
1);
+               spin_unlock(&mcbsp[id].lock);
+               return;
+       }
+
+       mcbsp[id].free = 1;
+       spin_unlock(&mcbsp[id].lock);
+
+       /* Free IRQs */
+       free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
+       free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
+}
+
+/*
+ * Here we start the McBSP, by enabling the sample
+ * generator, both transmitter and receivers,
+ * and the frame sync.
+ */
+void omap_mcbsp_start(unsigned int id)
+{
+       u32 io_base;
+       u16 w;
+
+       if (omap_mcbsp_check(id) < 0)
+               return;
+
+       io_base = mcbsp[id].io_base;
+
+       mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 
0x7);
+       mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 
0x7);
+
+       /* Start the sample generator */
+       w = OMAP_MCBSP_READ(io_base, SPCR2);
+       OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
+
+       /* Enable transmitter and receiver */
+       w = OMAP_MCBSP_READ(io_base, SPCR2);
+       OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
+
+       w = OMAP_MCBSP_READ(io_base, SPCR1);
+       OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
+
+       udelay(100);
+
+       /* Start frame sync */
+       w = OMAP_MCBSP_READ(io_base, SPCR2);
+       OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
+
+       /* Dump McBSP Regs */
+       omap_mcbsp_dump_reg(id);
+
+}
+
+void omap_mcbsp_stop(unsigned int id)
+{
+       u32 io_base;
+       u16 w;
+
+       if (omap_mcbsp_check(id) < 0)
+               return;
+
+       io_base = mcbsp[id].io_base;
+
+        /* Reset transmitter */
+       w = OMAP_MCBSP_READ(io_base, SPCR2);
+       OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
+
+       /* Reset receiver */
+       w = OMAP_MCBSP_READ(io_base, SPCR1);
+       OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
+
+       /* Reset the sample rate generator */
+       w = OMAP_MCBSP_READ(io_base, SPCR2);
+       OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
+}
+
+
+/* polled mcbsp i/o operations */
+int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
+{
+       u32 base = mcbsp[id].io_base;
+       writew(buf, base + OMAP_MCBSP_REG_DXR1);
+       /* if frame sync error - clear the error */
+       if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
+               /* clear error */
+               writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
+                      base + OMAP_MCBSP_REG_SPCR2);
+               /* resend */
+               return -1;
+       } else {
+               /* wait for transmit confirmation */
+               int attemps = 0;
+               while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
+                       if (attemps++ > 1000) {
+                               writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
+                                      (~XRST),
+                                      base + OMAP_MCBSP_REG_SPCR2);
+                               udelay(10);
+                               writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
+                                      (XRST),
+                                      base + OMAP_MCBSP_REG_SPCR2);
+                               udelay(10);
+                               printk(KERN_ERR
+                                      " Could not write to McBSP Register\n");
+                               return -2;
+                       }
+               }
+       }
+       return 0;
+}
+
+int omap_mcbsp_pollread(unsigned int id, u16 * buf)
+{
+       u32 base = mcbsp[id].io_base;
+       /* if frame sync error - clear the error */
+       if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
+               /* clear error */
+               writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
+                      base + OMAP_MCBSP_REG_SPCR1);
+               /* resend */
+               return -1;
+       } else {
+               /* wait for recieve confirmation */
+               int attemps = 0;
+               while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
+                       if (attemps++ > 1000) {
+                               writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
+                                      (~RRST),
+                                      base + OMAP_MCBSP_REG_SPCR1);
+                               udelay(10);
+                               writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
+                                      (RRST),
+                                      base + OMAP_MCBSP_REG_SPCR1);
+                               udelay(10);
+                               printk(KERN_ERR
+                                      " Could not read from McBSP Register\n");
+                               return -2;
+                       }
+               }
+       }
+       *buf = readw(base + OMAP_MCBSP_REG_DRR1);
+       return 0;
+}
+
+/*
+ * IRQ based word transmission.
+ */
+void omap_mcbsp_xmit_word(unsigned int id, u32 word)
+{
+       u32 io_base;
+       omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
+
+       if (omap_mcbsp_check(id) < 0)
+               return;
+
+       io_base = mcbsp[id].io_base;
+
+       wait_for_completion(&(mcbsp[id].tx_irq_completion));
+
+       if (word_length > OMAP_MCBSP_WORD_16)
+               OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
+       OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
+}
+
+u32 omap_mcbsp_recv_word(unsigned int id)
+{
+       u32 io_base;
+       u16 word_lsb, word_msb = 0;
+       omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
+
+       if (omap_mcbsp_check(id) < 0)
+               return -EINVAL;
+
+       io_base = mcbsp[id].io_base;
+
+       wait_for_completion(&(mcbsp[id].rx_irq_completion));
+
+       if (word_length > OMAP_MCBSP_WORD_16)
+               word_msb = OMAP_MCBSP_READ(io_base, DRR2);
+       word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
+
+       return (word_lsb | (word_msb << 16));
+}
+
+
+/*
+ * Simple DMA based buffer rx/tx routines.
+ * Nothing fancy, just a single buffer tx/rx through DMA.
+ * The DMA resources are released once the transfer is done.
+ * For anything fancier, you should use your own customized DMA
+ * routines and callbacks.
+ */
+int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int 
length)
+{
+       int dma_tx_ch;
+
+       if (omap_mcbsp_check(id) < 0)
+               return -EINVAL;
+
+       if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", 
omap_mcbsp_tx_dma_callback,
+                            &mcbsp[id],
+                            &dma_tx_ch)) {
+               printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d 
TX. Trying IRQ based TX\n", id+1);
+               return -EAGAIN;
+       }
+       mcbsp[id].dma_tx_lch = dma_tx_ch;
+
+       DBG("TX DMA on channel %d\n", dma_tx_ch);
+
+       init_completion(&(mcbsp[id].tx_dma_completion));
+
+       omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
+                                    OMAP_DMA_DATA_TYPE_S16,
+                                    length >> 1, 1,
+                                    OMAP_DMA_SYNC_ELEMENT);
+
+       omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
+                                OMAP_DMA_PORT_TIPB,
+                                OMAP_DMA_AMODE_CONSTANT,
+                                mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1);
+
+       omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
+                               OMAP_DMA_PORT_EMIFF,
+                               OMAP_DMA_AMODE_POST_INC,
+                               buffer);
+
+       omap_start_dma(mcbsp[id].dma_tx_lch);
+       wait_for_completion(&(mcbsp[id].tx_dma_completion));
+       return 0;
+}
+
+
+int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int 
length)
+{
+       int dma_rx_ch;
+
+       if (omap_mcbsp_check(id) < 0)
+               return -EINVAL;
+
+       if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", 
omap_mcbsp_rx_dma_callback,
+                            &mcbsp[id],
+                            &dma_rx_ch)) {
+               printk("Unable to request DMA channel for McBSP%d RX. Trying 
IRQ based RX\n", id+1);
+               return -EAGAIN;
+       }
+       mcbsp[id].dma_rx_lch = dma_rx_ch;
+
+       DBG("RX DMA on channel %d\n", dma_rx_ch);
+
+       init_completion(&(mcbsp[id].rx_dma_completion));
+
+       omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
+                                    OMAP_DMA_DATA_TYPE_S16,
+                                    length >> 1, 1,
+                                    OMAP_DMA_SYNC_ELEMENT);
+
+       omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
+                               OMAP_DMA_PORT_TIPB,
+                               OMAP_DMA_AMODE_CONSTANT,
+                               mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1);
+
+       omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
+                                OMAP_DMA_PORT_EMIFF,
+                                OMAP_DMA_AMODE_POST_INC,
+                                buffer);
+
+       omap_start_dma(mcbsp[id].dma_rx_lch);
+       wait_for_completion(&(mcbsp[id].rx_dma_completion));
+       return 0;
+}
+
+
+/*
+ * SPI wrapper.
+ * Since SPI setup is much simpler than the generic McBSP one,
+ * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
+ * Once this is done, you can call omap_mcbsp_start().
+ */
+void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg 
* spi_cfg)
+{
+       struct omap_mcbsp_reg_cfg mcbsp_cfg;
+
+       if (omap_mcbsp_check(id) < 0)
+               return;
+
+       memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
+
+       /* SPI has only one frame */
+       mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
+       mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
+
+        /* Clock stop mode */
+       if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
+               mcbsp_cfg.spcr1 |= (1 << 12);
+       else
+               mcbsp_cfg.spcr1 |= (3 << 11);
+
+       /* Set clock parities */
+       if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
+               mcbsp_cfg.pcr0 |= CLKRP;
+       else
+               mcbsp_cfg.pcr0 &= ~CLKRP;
+
+       if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
+               mcbsp_cfg.pcr0 &= ~CLKXP;
+       else
+               mcbsp_cfg.pcr0 |= CLKXP;
+
+       /* Set SCLKME to 0 and CLKSM to 1 */
+       mcbsp_cfg.pcr0 &= ~SCLKME;
+       mcbsp_cfg.srgr2 |= CLKSM;
+
+       /* Set FSXP */
+       if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
+               mcbsp_cfg.pcr0 &= ~FSXP;
+       else
+               mcbsp_cfg.pcr0 |= FSXP;
+
+       if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
+               mcbsp_cfg.pcr0 |= CLKXM;
+               mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
+               mcbsp_cfg.pcr0 |= FSXM;
+               mcbsp_cfg.srgr2 &= ~FSGM;
+               mcbsp_cfg.xcr2 |= XDATDLY(1);
+               mcbsp_cfg.rcr2 |= RDATDLY(1);
+       }
+       else {
+               mcbsp_cfg.pcr0 &= ~CLKXM;
+               mcbsp_cfg.srgr1 |= CLKGDV(1);
+               mcbsp_cfg.pcr0 &= ~FSXM;
+               mcbsp_cfg.xcr2 &= ~XDATDLY(3);
+               mcbsp_cfg.rcr2 &= ~RDATDLY(3);
+       }
+
+       mcbsp_cfg.xcr2 &= ~XPHASE;
+       mcbsp_cfg.rcr2 &= ~RPHASE;
+
+       omap_mcbsp_config(id, &mcbsp_cfg);
+}
+
+
+/*
+ * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
+ * 730 has only 2 McBSP, and both of them are MPU peripherals.
+ */
+struct omap_mcbsp_info {
+       u32 virt_base;
+       u8 dma_rx_sync, dma_tx_sync;
+       u16 rx_irq, tx_irq;
+};
+
+#ifdef CONFIG_ARCH_OMAP730
+static const struct omap_mcbsp_info mcbsp_730[] = {
+       [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
+               .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+               .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+               .rx_irq = INT_730_McBSP1RX,
+               .tx_irq = INT_730_McBSP1TX },
+       [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
+               .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+               .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+               .rx_irq = INT_730_McBSP2RX,
+               .tx_irq = INT_730_McBSP2TX },
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1510
+static const struct omap_mcbsp_info mcbsp_1510[] = {
+       [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
+               .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+               .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+               .rx_irq = INT_McBSP1RX,
+               .tx_irq = INT_McBSP1TX },
+       [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
+               .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
+               .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
+               .rx_irq = INT_1510_SPI_RX,
+               .tx_irq = INT_1510_SPI_TX },
+       [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
+               .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+               .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+               .rx_irq = INT_McBSP3RX,
+               .tx_irq = INT_McBSP3TX },
+};
+#endif
+
+#if defined(CONFIG_ARCH_OMAP16XX)
+static const struct omap_mcbsp_info mcbsp_1610[] = {
+       [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
+               .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+               .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+               .rx_irq = INT_McBSP1RX,
+               .tx_irq = INT_McBSP1TX },
+       [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
+               .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
+               .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
+               .rx_irq = INT_1610_McBSP2_RX,
+               .tx_irq = INT_1610_McBSP2_TX },
+       [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
+               .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+               .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+               .rx_irq = INT_McBSP3RX,
+               .tx_irq = INT_McBSP3TX },
+};
+#endif
+
+static int __init omap_mcbsp_init(void)
+{
+       int mcbsp_count = 0, i;
+       static const struct omap_mcbsp_info *mcbsp_info;
+
+       printk("Initializing OMAP McBSP system\n");
+
+       mcbsp_dsp_ck = clk_get(0, "dsp_ck");
+       if (IS_ERR(mcbsp_dsp_ck)) {
+               printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
+               return PTR_ERR(mcbsp_dsp_ck);
+       }
+       mcbsp_api_ck = clk_get(0, "api_ck");
+       if (IS_ERR(mcbsp_api_ck)) {
+               printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
+               return PTR_ERR(mcbsp_api_ck);
+       }
+       mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
+       if (IS_ERR(mcbsp_dspxor_ck)) {
+               printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
+               return PTR_ERR(mcbsp_dspxor_ck);
+       }
+
+#ifdef CONFIG_ARCH_OMAP730
+       if (cpu_is_omap730()) {
+               mcbsp_info = mcbsp_730;
+               mcbsp_count = ARRAY_SIZE(mcbsp_730);
+       }
+#endif
+#ifdef CONFIG_ARCH_OMAP1510
+       if (cpu_is_omap1510()) {
+               mcbsp_info = mcbsp_1510;
+               mcbsp_count = ARRAY_SIZE(mcbsp_1510);
+       }
+#endif
+#if defined(CONFIG_ARCH_OMAP16XX)
+       if (cpu_is_omap16xx()) {
+               mcbsp_info = mcbsp_1610;
+               mcbsp_count = ARRAY_SIZE(mcbsp_1610);
+       }
+#endif
+       for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
+               if (i >= mcbsp_count) {
+                       mcbsp[i].io_base = 0;
+                       mcbsp[i].free = 0;
+                        continue;
+               }
+               mcbsp[i].id = i + 1;
+               mcbsp[i].free = 1;
+               mcbsp[i].dma_tx_lch = -1;
+               mcbsp[i].dma_rx_lch = -1;
+
+               mcbsp[i].io_base = mcbsp_info[i].virt_base;
+               mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
+               mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
+               mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
+               mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
+               spin_lock_init(&mcbsp[i].lock);
+       }
+
+       return 0;
+}
+
+
+arch_initcall(omap_mcbsp_init);
+
+EXPORT_SYMBOL(omap_mcbsp_config);
+EXPORT_SYMBOL(omap_mcbsp_request);
+EXPORT_SYMBOL(omap_mcbsp_free);
+EXPORT_SYMBOL(omap_mcbsp_start);
+EXPORT_SYMBOL(omap_mcbsp_stop);
+EXPORT_SYMBOL(omap_mcbsp_xmit_word);
+EXPORT_SYMBOL(omap_mcbsp_recv_word);
+EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
+EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
+EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
diff -urN linux/arch/arm/plat-omap/mux.c linux/arch/arm/plat-omap/mux.c
--- linux/arch/arm/plat-omap/mux.c      1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/mux.c      2005-07-13 12:48:54.007226000 +0100     
1.1
@@ -0,0 +1,160 @@
+/*
+ * linux/arch/arm/plat-omap/mux.c
+ *
+ * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
+ *
+ * Copyright (C) 2003 Nokia Corporation
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <linux/spinlock.h>
+
+#define __MUX_C__
+#include <asm/arch/mux.h>
+
+#ifdef CONFIG_OMAP_MUX
+
+/*
+ * Sets the Omap MUX and PULL_DWN registers based on the table
+ */
+int __init_or_module
+omap_cfg_reg(const reg_cfg_t reg_cfg)
+{
+       static DEFINE_SPINLOCK(mux_spin_lock);
+
+       unsigned long flags;
+       reg_cfg_set *cfg;
+       unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
+               pull_orig = 0, pull = 0;
+       unsigned int mask, warn = 0;
+
+       if (reg_cfg > ARRAY_SIZE(reg_cfg_table)) {
+               printk(KERN_ERR "MUX: reg_cfg %d\n", reg_cfg);
+               return -EINVAL;
+       }
+
+       cfg = (reg_cfg_set *)&reg_cfg_table[reg_cfg];
+
+       /* Check the mux register in question */
+       if (cfg->mux_reg) {
+               unsigned        tmp1, tmp2;
+
+               spin_lock_irqsave(&mux_spin_lock, flags);
+               reg_orig = omap_readl(cfg->mux_reg);
+
+               /* The mux registers always seem to be 3 bits long */
+               mask = (0x7 << cfg->mask_offset);
+               tmp1 = reg_orig & mask;
+               reg = reg_orig & ~mask;
+
+               tmp2 = (cfg->mask << cfg->mask_offset);
+               reg |= tmp2;
+
+               if (tmp1 != tmp2)
+                       warn = 1;
+
+               omap_writel(reg, cfg->mux_reg);
+               spin_unlock_irqrestore(&mux_spin_lock, flags);
+       }
+
+       /* Check for pull up or pull down selection on 1610 */
+       if (!cpu_is_omap1510()) {
+               if (cfg->pu_pd_reg && cfg->pull_val) {
+                       spin_lock_irqsave(&mux_spin_lock, flags);
+                       pu_pd_orig = omap_readl(cfg->pu_pd_reg);
+                       mask = 1 << cfg->pull_bit;
+
+                       if (cfg->pu_pd_val) {
+                               if (!(pu_pd_orig & mask))
+                                       warn = 1;
+                               /* Use pull up */
+                               pu_pd = pu_pd_orig | mask;
+                       } else {
+                               if (pu_pd_orig & mask)
+                                       warn = 1;
+                               /* Use pull down */
+                               pu_pd = pu_pd_orig & ~mask;
+                       }
+                       omap_writel(pu_pd, cfg->pu_pd_reg);
+                       spin_unlock_irqrestore(&mux_spin_lock, flags);
+               }
+       }
+
+       /* Check for an associated pull down register */
+       if (cfg->pull_reg) {
+               spin_lock_irqsave(&mux_spin_lock, flags);
+               pull_orig = omap_readl(cfg->pull_reg);
+               mask = 1 << cfg->pull_bit;
+
+               if (cfg->pull_val) {
+                       if (pull_orig & mask)
+                               warn = 1;
+                       /* Low bit = pull enabled */
+                       pull = pull_orig & ~mask;
+               } else {
+                       if (!(pull_orig & mask))
+                               warn = 1;
+                       /* High bit = pull disabled */
+                       pull = pull_orig | mask;
+               }
+
+               omap_writel(pull, cfg->pull_reg);
+               spin_unlock_irqrestore(&mux_spin_lock, flags);
+       }
+
+       if (warn) {
+#ifdef CONFIG_OMAP_MUX_WARNINGS
+               printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
+#endif
+       }
+
+#ifdef CONFIG_OMAP_MUX_DEBUG
+       if (cfg->debug || warn) {
+               printk("MUX: Setting register %s\n", cfg->name);
+               printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+                      cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
+
+               if (!cpu_is_omap1510()) {
+                       if (cfg->pu_pd_reg && cfg->pull_val) {
+                               printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+                                      cfg->pu_pd_name, cfg->pu_pd_reg,
+                                      pu_pd_orig, pu_pd);
+                       }
+               }
+
+               if (cfg->pull_reg)
+                       printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+                              cfg->pull_name, cfg->pull_reg, pull_orig, pull);
+       }
+#endif
+
+#ifdef CONFIG_OMAP_MUX_ERRORS
+       return warn ? -ETXTBSY : 0;
+#else
+       return 0;
+#endif
+}
+
+EXPORT_SYMBOL(omap_cfg_reg);
+
+#endif /* CONFIG_OMAP_MUX */
diff -urN linux/arch/arm/plat-omap/ocpi.c linux/arch/arm/plat-omap/ocpi.c
--- linux/arch/arm/plat-omap/ocpi.c     1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/ocpi.c     2005-07-13 12:48:54.029114000 +0100     
1.1
@@ -0,0 +1,114 @@
+/*
+ * linux/arch/arm/plat-omap/ocpi.c
+ *
+ * Minimal OCP bus support for omap16xx
+ *
+ * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ *
+ * Modified for clock framework by Paul Mundt <paul.mundt@nokia.com>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/err.h>
+
+#include <asm/io.h>
+#include <asm/hardware/clock.h>
+#include <asm/arch/hardware.h>
+
+#define OCPI_BASE              0xfffec320
+#define OCPI_FAULT             (OCPI_BASE + 0x00)
+#define OCPI_CMD_FAULT         (OCPI_BASE + 0x04)
+#define OCPI_SINT0             (OCPI_BASE + 0x08)
+#define OCPI_TABORT            (OCPI_BASE + 0x0c)
+#define OCPI_SINT1             (OCPI_BASE + 0x10)
+#define OCPI_PROT              (OCPI_BASE + 0x14)
+#define OCPI_SEC               (OCPI_BASE + 0x18)
+
+/* USB OHCI OCPI access error registers */
+#define HOSTUEADDR     0xfffba0e0
+#define HOSTUESTATUS   0xfffba0e4
+
+static struct clk *ocpi_ck;
+
+/*
+ * Enables device access to OMAP buses via the OCPI bridge
+ * FIXME: Add locking
+ */
+int ocpi_enable(void)
+{
+       unsigned int val;
+
+       if (!cpu_is_omap16xx())
+               return -ENODEV;
+
+       /* Make sure there's clock for OCPI */
+       clk_enable(ocpi_ck);
+
+       /* Enable access for OHCI in OCPI */
+       val = omap_readl(OCPI_PROT);
+       val &= ~0xff;
+       //val &= (1 << 0);      /* Allow access only to EMIFS */
+       omap_writel(val, OCPI_PROT);
+
+       val = omap_readl(OCPI_SEC);
+       val &= ~0xff;
+       omap_writel(val, OCPI_SEC);
+
+       return 0;
+}
+EXPORT_SYMBOL(ocpi_enable);
+
+static int __init omap_ocpi_init(void)
+{
+       if (!cpu_is_omap16xx())
+               return -ENODEV;
+
+       ocpi_ck = clk_get(NULL, "l3_ocpi_ck");
+       if (IS_ERR(ocpi_ck))
+               return PTR_ERR(ocpi_ck);
+
+       clk_use(ocpi_ck);
+       ocpi_enable();
+       printk("OMAP OCPI interconnect driver loaded\n");
+
+       return 0;
+}
+
+static void __exit omap_ocpi_exit(void)
+{
+       /* REVISIT: Disable OCPI */
+
+       if (!cpu_is_omap16xx())
+               return;
+
+       clk_unuse(ocpi_ck);
+       clk_put(ocpi_ck);
+}
+
+MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
+MODULE_DESCRIPTION("OMAP OCPI bus controller module");
+MODULE_LICENSE("GPL");
+module_init(omap_ocpi_init);
+module_exit(omap_ocpi_exit);
diff -urN linux/arch/arm/plat-omap/pm.c linux/arch/arm/plat-omap/pm.c
--- linux/arch/arm/plat-omap/pm.c       1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/pm.c       2005-07-13 12:48:54.052986000 +0100     
1.1
@@ -0,0 +1,632 @@
+/*
+ * linux/arch/arm/plat-omap/pm.c
+ *
+ * OMAP Power Management Routines
+ *
+ * Original code for the SA11x0:
+ * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
+ *
+ * Modified for the PXA250 by Nicolas Pitre:
+ * Copyright (c) 2002 Monta Vista Software, Inc.
+ *
+ * Modified for the OMAP1510 by David Singleton:
+ * Copyright (c) 2002 Monta Vista Software, Inc.
+ *
+ * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/pm.h>
+#include <linux/sched.h>
+#include <linux/proc_fs.h>
+#include <linux/pm.h>
+
+#include <asm/io.h>
+#include <asm/mach/time.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/omap16xx.h>
+#include <asm/arch/pm.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/tc.h>
+#include <asm/arch/tps65010.h>
+
+#include "clock.h"
+
+static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
+static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
+static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
+static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
+
+/*
+ * Let's power down on idle, but only if we are really
+ * idle, because once we start down the path of
+ * going idle we continue to do idle even if we get
+ * a clock tick interrupt . .
+ */
+void omap_pm_idle(void)
+{
+       int (*func_ptr)(void) = 0;
+       unsigned int mask32 = 0;
+
+       /*
+        * If the DSP is being used let's just idle the CPU, the overhead
+        * to wake up from Big Sleep is big, milliseconds versus micro
+        * seconds for wait for interrupt.
+        */
+
+       local_irq_disable();
+       local_fiq_disable();
+       if (need_resched()) {
+               local_fiq_enable();
+               local_irq_enable();
+               return;
+       }
+       mask32 = omap_readl(ARM_SYSST);
+
+       /*
+        * Since an interrupt may set up a timer, we don't want to
+        * reprogram the hardware timer with interrupts enabled.
+        * Re-enable interrupts only after returning from idle.
+        */
+       timer_dyn_reprogram();
+
+       if ((mask32 & DSP_IDLE) == 0) {
+               __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
+       } else {
+
+               if (cpu_is_omap1510()) {
+                       func_ptr = (void *)(OMAP1510_SRAM_IDLE_SUSPEND);
+               } else if (cpu_is_omap1610() || cpu_is_omap1710()) {
+                       func_ptr = (void *)(OMAP1610_SRAM_IDLE_SUSPEND);
+               } else if (cpu_is_omap5912()) {
+                       func_ptr = (void *)(OMAP5912_SRAM_IDLE_SUSPEND);
+               }
+
+               func_ptr();
+       }
+       local_fiq_enable();
+       local_irq_enable();
+}
+
+/*
+ * Configuration of the wakeup event is board specific. For the
+ * moment we put it into this helper function. Later it may move
+ * to board specific files.
+ */
+static void omap_pm_wakeup_setup(void)
+{
+       /*
+        * Enable ARM XOR clock and release peripheral from reset by
+        * writing 1 to PER_EN bit in ARM_RSTCT2, this is required
+        * for UART configuration to use UART2 to wake up.
+        */
+
+       omap_writel(omap_readl(ARM_IDLECT2) | ENABLE_XORCLK, ARM_IDLECT2);
+       omap_writel(omap_readl(ARM_RSTCT2) | PER_EN, ARM_RSTCT2);
+       omap_writew(MODEM_32K_EN, ULPD_CLOCK_CTRL);
+
+       /*
+        * Turn off all interrupts except L1-2nd level cascade,
+        * and the L2 wakeup interrupts: keypad and UART2.
+        */
+
+       omap_writel(~IRQ_LEVEL2, OMAP_IH1_MIR);
+
+       if (cpu_is_omap1510()) {
+               omap_writel(~(IRQ_UART2 | IRQ_KEYBOARD),  OMAP_IH2_MIR);
+       }
+
+       if (cpu_is_omap16xx()) {
+               omap_writel(~(IRQ_UART2 | IRQ_KEYBOARD), OMAP_IH2_0_MIR);
+
+               omap_writel(~0x0, OMAP_IH2_1_MIR);
+               omap_writel(~0x0, OMAP_IH2_2_MIR);
+               omap_writel(~0x0, OMAP_IH2_3_MIR);
+       }
+
+       /*  New IRQ agreement */
+       omap_writel(1, OMAP_IH1_CONTROL);
+
+       /* external PULL to down, bit 22 = 0 */
+       omap_writel(omap_readl(PULL_DWN_CTRL_2) & ~(1<<22), PULL_DWN_CTRL_2);
+}
+
+void omap_pm_suspend(void)
+{
+       unsigned int mask32 = 0;
+       unsigned long arg0 = 0, arg1 = 0;
+       int (*func_ptr)(unsigned short, unsigned short) = 0;
+       unsigned short save_dsp_idlect2;
+
+       printk("PM: OMAP%x is entering deep sleep now ...\n", system_rev);
+
+       if (machine_is_omap_osk()) {
+               /* Stop LED1 (D9) blink */
+               tps65010_set_led(LED1, OFF);
+       }
+
+       /*
+        * Step 1: turn off interrupts
+        */
+
+       local_irq_disable();
+       local_fiq_disable();
+
+       /*
+        * Step 2: save registers
+        *
+        * The omap is a strange/beautiful device. The caches, memory
+        * and register state are preserved across power saves.
+        * We have to save and restore very little register state to
+        * idle the omap.
+         *
+        * Save interrupt, MPUI, ARM and UPLD control registers.
+        */
+
+       if (cpu_is_omap1510()) {
+               MPUI1510_SAVE(OMAP_IH1_MIR);
+               MPUI1510_SAVE(OMAP_IH2_MIR);
+               MPUI1510_SAVE(MPUI_CTRL);
+               MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
+               MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
+               MPUI1510_SAVE(EMIFS_CONFIG);
+               MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
+       } else if (cpu_is_omap16xx()) {
+               MPUI1610_SAVE(OMAP_IH1_MIR);
+               MPUI1610_SAVE(OMAP_IH2_0_MIR);
+               MPUI1610_SAVE(OMAP_IH2_1_MIR);
+               MPUI1610_SAVE(OMAP_IH2_2_MIR);
+               MPUI1610_SAVE(OMAP_IH2_3_MIR);
+               MPUI1610_SAVE(MPUI_CTRL);
+               MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
+               MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
+               MPUI1610_SAVE(EMIFS_CONFIG);
+               MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
+       }
+
+       ARM_SAVE(ARM_CKCTL);
+       ARM_SAVE(ARM_IDLECT1);
+       ARM_SAVE(ARM_IDLECT2);
+       ARM_SAVE(ARM_EWUPCT);
+       ARM_SAVE(ARM_RSTCT1);
+       ARM_SAVE(ARM_RSTCT2);
+       ARM_SAVE(ARM_SYSST);
+       ULPD_SAVE(ULPD_CLOCK_CTRL);
+       ULPD_SAVE(ULPD_STATUS_REQ);
+
+       /*
+        * Step 3: LOW_PWR signal enabling
+        *
+        * Allow the LOW_PWR signal to be visible on MPUIO5 ball.
+        */
+       if (cpu_is_omap1510()) {
+               /* POWER_CTRL_REG = 0x1 (LOW_POWER is available) */
+               omap_writew(omap_readw(ULPD_POWER_CTRL) |
+                           OMAP1510_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL);
+       } else if (cpu_is_omap16xx()) {
+               /* POWER_CTRL_REG = 0x1 (LOW_POWER is available) */
+               omap_writew(omap_readw(ULPD_POWER_CTRL) |
+                           OMAP1610_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL);
+       }
+
+       /* configure LOW_PWR pin */
+       omap_cfg_reg(T20_1610_LOW_PWR);
+
+       /*
+        * Step 4: OMAP DSP Shutdown
+        */
+
+       /* Set DSP_RST = 1 and DSP_EN = 0, put DSP block into reset */
+       omap_writel((omap_readl(ARM_RSTCT1) | DSP_RST) & ~DSP_ENABLE,
+                   ARM_RSTCT1);
+
+       /* Set DSP boot mode to DSP-IDLE, DSP_BOOT_MODE = 0x2 */
+        omap_writel(DSP_IDLE_MODE, MPUI_DSP_BOOT_CONFIG);
+
+       /* Set EN_DSPCK = 0, stop DSP block clock */
+       omap_writel(omap_readl(ARM_CKCTL) & ~DSP_CLOCK_ENABLE, ARM_CKCTL);
+
+       /* Stop any DSP domain clocks */
+       omap_writel(omap_readl(ARM_IDLECT2) | (1<<EN_APICK), ARM_IDLECT2);
+       save_dsp_idlect2 = __raw_readw(DSP_IDLECT2);
+       __raw_writew(0, DSP_IDLECT2);
+
+       /*
+        * Step 5: Wakeup Event Setup
+        */
+
+       omap_pm_wakeup_setup();
+
+       /*
+        * Step 6a: ARM and Traffic controller shutdown
+        *
+        * Step 6 starts here with clock and watchdog disable
+        */
+
+       /* stop clocks */
+       mask32 = omap_readl(ARM_IDLECT2);
+       mask32 &= ~(1<<EN_WDTCK);  /* bit 0 -> 0 (WDT clock) */
+       mask32 |=  (1<<EN_XORPCK); /* bit 1 -> 1 (XORPCK clock) */
+       mask32 &= ~(1<<EN_PERCK);  /* bit 2 -> 0 (MPUPER_CK clock) */
+       mask32 &= ~(1<<EN_LCDCK);  /* bit 3 -> 0 (LCDC clock) */
+       mask32 &= ~(1<<EN_LBCK);   /* bit 4 -> 0 (local bus clock) */
+       mask32 |=  (1<<EN_APICK);  /* bit 6 -> 1 (MPUI clock) */
+       mask32 &= ~(1<<EN_TIMCK);  /* bit 7 -> 0 (MPU timer clock) */
+       mask32 &= ~(1<<DMACK_REQ); /* bit 8 -> 0 (DMAC clock) */
+       mask32 &= ~(1<<EN_GPIOCK); /* bit 9 -> 0 (GPIO clock) */
+       omap_writel(mask32, ARM_IDLECT2);
+
+       /* disable ARM watchdog */
+       omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
+       omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
+
+       /*
+        * Step 6b: ARM and Traffic controller shutdown
+        *
+        * Step 6 continues here. Prepare jump to power management
+        * assembly code in internal SRAM.
+        *
+        * Since the omap_cpu_suspend routine has been copied to
+        * SRAM, we'll do an indirect procedure call to it and pass the
+        * contents of arm_idlect1 and arm_idlect2 so it can restore
+        * them when it wakes up and it will return.
+        */
+
+       arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
+       arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
+
+       if (cpu_is_omap1510()) {
+               func_ptr = (void *)(OMAP1510_SRAM_API_SUSPEND);
+       } else if (cpu_is_omap1610() || cpu_is_omap1710()) {
+               func_ptr = (void *)(OMAP1610_SRAM_API_SUSPEND);
+       } else if (cpu_is_omap5912()) {
+               func_ptr = (void *)(OMAP5912_SRAM_API_SUSPEND);
+       }
+
+       /*
+        * Step 6c: ARM and Traffic controller shutdown
+        *
+        * Jump to assembly code. The processor will stay there
+        * until wake up.
+        */
+
+        func_ptr(arg0, arg1);
+
+       /*
+        * If we are here, processor is woken up!
+        */
+
+       if (cpu_is_omap1510()) {
+               /* POWER_CTRL_REG = 0x0 (LOW_POWER is disabled) */
+               omap_writew(omap_readw(ULPD_POWER_CTRL) &
+                           ~OMAP1510_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL);
+       } else if (cpu_is_omap16xx()) {
+               /* POWER_CTRL_REG = 0x0 (LOW_POWER is disabled) */
+               omap_writew(omap_readw(ULPD_POWER_CTRL) &
+                           ~OMAP1610_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL);
+       }
+
+
+       /* Restore DSP clocks */
+       omap_writel(omap_readl(ARM_IDLECT2) | (1<<EN_APICK), ARM_IDLECT2);
+       __raw_writew(save_dsp_idlect2, DSP_IDLECT2);
+       ARM_RESTORE(ARM_IDLECT2);
+
+       /*
+        * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
+        */
+
+       ARM_RESTORE(ARM_CKCTL);
+       ARM_RESTORE(ARM_EWUPCT);
+       ARM_RESTORE(ARM_RSTCT1);
+       ARM_RESTORE(ARM_RSTCT2);
+       ARM_RESTORE(ARM_SYSST);
+       ULPD_RESTORE(ULPD_CLOCK_CTRL);
+       ULPD_RESTORE(ULPD_STATUS_REQ);
+
+       if (cpu_is_omap1510()) {
+               MPUI1510_RESTORE(MPUI_CTRL);
+               MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
+               MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
+               MPUI1510_RESTORE(EMIFS_CONFIG);
+               MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
+               MPUI1510_RESTORE(OMAP_IH1_MIR);
+               MPUI1510_RESTORE(OMAP_IH2_MIR);
+       } else if (cpu_is_omap16xx()) {
+               MPUI1610_RESTORE(MPUI_CTRL);
+               MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
+               MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
+               MPUI1610_RESTORE(EMIFS_CONFIG);
+               MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
+
+               MPUI1610_RESTORE(OMAP_IH1_MIR);
+               MPUI1610_RESTORE(OMAP_IH2_0_MIR);
+               MPUI1610_RESTORE(OMAP_IH2_1_MIR);
+               MPUI1610_RESTORE(OMAP_IH2_2_MIR);
+               MPUI1610_RESTORE(OMAP_IH2_3_MIR);
+       }
+
+       /*
+        * Reenable interrupts
+        */
+
+       local_irq_enable();
+       local_fiq_enable();
+
+       printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
+
+       if (machine_is_omap_osk()) {
+               /* Let LED1 (D9) blink again */
+               tps65010_set_led(LED1, BLINK);
+       }
+}
+
+#if defined(DEBUG) && defined(CONFIG_PROC_FS)
+static int g_read_completed;
+
+/*
+ * Read system PM registers for debugging
+ */
+static int omap_pm_read_proc(
+       char *page_buffer,
+       char **my_first_byte,
+       off_t virtual_start,
+       int length,
+       int *eof,
+       void *data)
+{
+       int my_buffer_offset = 0;
+       char * const my_base = page_buffer;
+
+       ARM_SAVE(ARM_CKCTL);
+       ARM_SAVE(ARM_IDLECT1);
+       ARM_SAVE(ARM_IDLECT2);
+       ARM_SAVE(ARM_EWUPCT);
+       ARM_SAVE(ARM_RSTCT1);
+       ARM_SAVE(ARM_RSTCT2);
+       ARM_SAVE(ARM_SYSST);
+
+       ULPD_SAVE(ULPD_IT_STATUS);
+       ULPD_SAVE(ULPD_CLOCK_CTRL);
+       ULPD_SAVE(ULPD_SOFT_REQ);
+       ULPD_SAVE(ULPD_STATUS_REQ);
+       ULPD_SAVE(ULPD_DPLL_CTRL);
+       ULPD_SAVE(ULPD_POWER_CTRL);
+
+       if (cpu_is_omap1510()) {
+               MPUI1510_SAVE(MPUI_CTRL);
+               MPUI1510_SAVE(MPUI_DSP_STATUS);
+               MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
+               MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
+               MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
+               MPUI1510_SAVE(EMIFS_CONFIG);
+       } else if (cpu_is_omap16xx()) {
+               MPUI1610_SAVE(MPUI_CTRL);
+               MPUI1610_SAVE(MPUI_DSP_STATUS);
+               MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
+               MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
+               MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
+               MPUI1610_SAVE(EMIFS_CONFIG);
+       }
+
+       if (virtual_start == 0) {
+               g_read_completed = 0;
+
+               my_buffer_offset += sprintf(my_base + my_buffer_offset,
+                  "ARM_CKCTL_REG:            0x%-8x     \n"
+                  "ARM_IDLECT1_REG:          0x%-8x     \n"
+                  "ARM_IDLECT2_REG:          0x%-8x     \n"
+                  "ARM_EWUPCT_REG:           0x%-8x     \n"
+                  "ARM_RSTCT1_REG:           0x%-8x     \n"
+                  "ARM_RSTCT2_REG:           0x%-8x     \n"
+                  "ARM_SYSST_REG:            0x%-8x     \n"
+                  "ULPD_IT_STATUS_REG:       0x%-4x     \n"
+                  "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
+                  "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
+                  "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
+                  "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
+                  "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
+                  ARM_SHOW(ARM_CKCTL),
+                  ARM_SHOW(ARM_IDLECT1),
+                  ARM_SHOW(ARM_IDLECT2),
+                  ARM_SHOW(ARM_EWUPCT),
+                  ARM_SHOW(ARM_RSTCT1),
+                  ARM_SHOW(ARM_RSTCT2),
+                  ARM_SHOW(ARM_SYSST),
+                  ULPD_SHOW(ULPD_IT_STATUS),
+                  ULPD_SHOW(ULPD_CLOCK_CTRL),
+                  ULPD_SHOW(ULPD_SOFT_REQ),
+                  ULPD_SHOW(ULPD_DPLL_CTRL),
+                  ULPD_SHOW(ULPD_STATUS_REQ),
+                  ULPD_SHOW(ULPD_POWER_CTRL));
+
+               if (cpu_is_omap1510()) {
+                       my_buffer_offset += sprintf(my_base + my_buffer_offset,
+                          "MPUI1510_CTRL_REG             0x%-8x \n"
+                          "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
+                          "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
+                          "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
+                          "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
+                          "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
+                          MPUI1510_SHOW(MPUI_CTRL),
+                          MPUI1510_SHOW(MPUI_DSP_STATUS),
+                          MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
+                          MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
+                          MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
+                          MPUI1510_SHOW(EMIFS_CONFIG));
+               } else if (cpu_is_omap16xx()) {
+                       my_buffer_offset += sprintf(my_base + my_buffer_offset,
+                          "MPUI1610_CTRL_REG             0x%-8x \n"
+                          "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
+                          "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
+                          "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
+                          "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
+                          "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
+                          MPUI1610_SHOW(MPUI_CTRL),
+                          MPUI1610_SHOW(MPUI_DSP_STATUS),
+                          MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
+                          MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
+                          MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
+                          MPUI1610_SHOW(EMIFS_CONFIG));
+               }
+
+               g_read_completed++;
+       } else if (g_read_completed >= 1) {
+                *eof = 1;
+                return 0;
+       }
+       g_read_completed++;
+
+       *my_first_byte = page_buffer;
+       return  my_buffer_offset;
+}
+
+static void omap_pm_init_proc(void)
+{
+       struct proc_dir_entry *entry;
+
+       entry = create_proc_read_entry("driver/omap_pm",
+                                      S_IWUSR | S_IRUGO, NULL,
+                                      omap_pm_read_proc, 0);
+}
+
+#endif /* DEBUG && CONFIG_PROC_FS */
+
+/*
+ *     omap_pm_prepare - Do preliminary suspend work.
+ *     @state:         suspend state we're entering.
+ *
+ */
+//#include <asm/arch/hardware.h>
+
+static int omap_pm_prepare(suspend_state_t state)
+{
+       int error = 0;
+
+       switch (state)
+       {
+       case PM_SUSPEND_STANDBY:
+       case PM_SUSPEND_MEM:
+               break;
+
+       case PM_SUSPEND_DISK:
+               return -ENOTSUPP;
+
+       default:
+               return -EINVAL;
+       }
+
+       return error;
+}
+
+
+/*
+ *     omap_pm_enter - Actually enter a sleep state.
+ *     @state:         State we're entering.
+ *
+ */
+
+static int omap_pm_enter(suspend_state_t state)
+{
+       switch (state)
+       {
+       case PM_SUSPEND_STANDBY:
+       case PM_SUSPEND_MEM:
+               omap_pm_suspend();
+               break;
+
+       case PM_SUSPEND_DISK:
+               return -ENOTSUPP;
+
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+
+/**
+ *     omap_pm_finish - Finish up suspend sequence.
+ *     @state:         State we're coming out of.
+ *
+ *     This is called after we wake back up (or if entering the sleep state
+ *     failed).
+ */
+
+static int omap_pm_finish(suspend_state_t state)
+{
+       return 0;
+}
+
+
+struct pm_ops omap_pm_ops ={
+       .pm_disk_mode = 0,
+        .prepare        = omap_pm_prepare,
+        .enter          = omap_pm_enter,
+        .finish         = omap_pm_finish,
+};
+
+static int __init omap_pm_init(void)
+{
+       printk("Power Management for TI OMAP.\n");
+       pm_idle = omap_pm_idle;
+       /*
+        * We copy the assembler sleep/wakeup routines to SRAM.
+        * These routines need to be in SRAM as that's the only
+        * memory the MPU can see when it wakes up.
+        */
+
+#ifdef CONFIG_ARCH_OMAP1510
+       if (cpu_is_omap1510()) {
+               memcpy((void *)OMAP1510_SRAM_IDLE_SUSPEND,
+                      omap1510_idle_loop_suspend,
+                      omap1510_idle_loop_suspend_sz);
+               memcpy((void *)OMAP1510_SRAM_API_SUSPEND, omap1510_cpu_suspend,
+                      omap1510_cpu_suspend_sz);
+       } else
+#endif
+       if (cpu_is_omap1610() || cpu_is_omap1710()) {
+               memcpy((void *)OMAP1610_SRAM_IDLE_SUSPEND,
+                      omap1610_idle_loop_suspend,
+                      omap1610_idle_loop_suspend_sz);
+               memcpy((void *)OMAP1610_SRAM_API_SUSPEND, omap1610_cpu_suspend,
+                      omap1610_cpu_suspend_sz);
+       } else if (cpu_is_omap5912()) {
+               memcpy((void *)OMAP5912_SRAM_IDLE_SUSPEND,
+                      omap1610_idle_loop_suspend,
+                      omap1610_idle_loop_suspend_sz);
+               memcpy((void *)OMAP5912_SRAM_API_SUSPEND, omap1610_cpu_suspend,
+                      omap1610_cpu_suspend_sz);
+       }
+
+       pm_set_ops(&omap_pm_ops);
+
+#if defined(DEBUG) && defined(CONFIG_PROC_FS)
+       omap_pm_init_proc();
+#endif
+
+       return 0;
+}
+__initcall(omap_pm_init);
+
diff -urN linux/arch/arm/plat-omap/sleep.S linux/arch/arm/plat-omap/sleep.S
--- linux/arch/arm/plat-omap/sleep.S    1970/01/01 00:00:00
+++ linux/arch/arm/plat-omap/sleep.S    2005-07-13 12:48:54.080389000 +0100     
1.1
@@ -0,0 +1,314 @@
+/*
+ * linux/arch/arm/plat-omap/sleep.S
+ *
+ * Low-level OMAP1510/1610 sleep/wakeUp support
+ *
+ * Initial SA1110 code:
+ * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
+ *
+ * Adapted for PXA by Nicolas Pitre:
+ * Copyright (c) 2002 Monta Vista Software, Inc.
+ *
+ * Support for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/arch/io.h>
+#include <asm/arch/pm.h>
+
+               .text
+
+/*
+ * Forces OMAP into idle state
+ *
+ * omapXXXX_idle_loop_suspend()
+ *
+ * Note: This code get's copied to internal SRAM at boot. When the OMAP
+ *      wakes up it continues execution at the point it went to sleep.
+ *
+ * Note: Because of slightly different configuration values we have
+ *       processor specific functions here.
+ */
+
+#ifdef CONFIG_ARCH_OMAP1510
+ENTRY(omap1510_idle_loop_suspend)
+
+       stmfd   sp!, {r0 - r12, lr}             @ save registers on stack
+
+       @ load base address of ARM_IDLECT1 and ARM_IDLECT2
+       mov     r4, #CLKGEN_REG_ASM_BASE & 0xff000000
+       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
+       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
+
+       @ turn off clock domains
+       @ get ARM_IDLECT2 into r2
+       ldrh    r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
+       mov     r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
+       orr     r5,r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
+       strh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
+
+       @ request ARM idle
+       @ get ARM_IDLECT1 into r1
+       ldrh    r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
+       orr     r3, r1, #OMAP1510_IDLE_LOOP_REQUEST & 0xffff
+       strh    r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
+
+       mov     r5, #IDLE_WAIT_CYCLES & 0xff
+       orr     r5, r5, #IDLE_WAIT_CYCLES & 0xff00
+l_1510:        subs    r5, r5, #1
+       bne     l_1510
+/*
+ * Let's wait for the next clock tick to wake us up.
+ */
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c0, 4           @ wait for interrupt
+/*
+ * omap1510_idle_loop_suspend()'s resume point.
+ *
+ * It will just start executing here, so we'll restore stuff from the
+ * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
+ */
+
+       @ restore ARM_IDLECT1 and ARM_IDLECT2 and return
+       @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
+       strh    r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
+       strh    r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
+
+       ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
+
+ENTRY(omap1510_idle_loop_suspend_sz)
+       .word   . - omap1510_idle_loop_suspend
+#endif /* CONFIG_ARCH_OMAP1510 */
+
+#if defined(CONFIG_ARCH_OMAP16XX)
+ENTRY(omap1610_idle_loop_suspend)
+
+       stmfd   sp!, {r0 - r12, lr}             @ save registers on stack
+
+       @ load base address of ARM_IDLECT1 and ARM_IDLECT2
+       mov     r4, #CLKGEN_REG_ASM_BASE & 0xff000000
+       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
+       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
+
+       @ turn off clock domains
+       @ get ARM_IDLECT2 into r2
+       ldrh    r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
+       mov     r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff
+       orr     r5,r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff00
+       strh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
+
+       @ request ARM idle
+       @ get ARM_IDLECT1 into r1
+       ldrh    r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
+       orr     r3, r1, #OMAP1610_IDLE_LOOP_REQUEST & 0xffff
+       strh    r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
+
+       mov     r5, #IDLE_WAIT_CYCLES & 0xff
+       orr     r5, r5, #IDLE_WAIT_CYCLES & 0xff00
+l_1610:        subs    r5, r5, #1
+       bne     l_1610
+/*
+ * Let's wait for the next clock tick to wake us up.
+ */
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c0, 4           @ wait for interrupt
+/*
+ * omap1610_idle_loop_suspend()'s resume point.
+ *
+ * It will just start executing here, so we'll restore stuff from the
+ * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
+ */
+
+       @ restore ARM_IDLECT1 and ARM_IDLECT2 and return
+       @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
+       strh    r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
+       strh    r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
+
+       ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
+
+ENTRY(omap1610_idle_loop_suspend_sz)
+       .word   . - omap1610_idle_loop_suspend
+#endif /* CONFIG_ARCH_OMAP16XX */
+
+/*
+ * Forces OMAP into deep sleep state
+ *
+ * omapXXXX_cpu_suspend()
+ *
+ * The values of the registers ARM_IDLECT1 and ARM_IDLECT2 are passed
+ * as arg0 and arg1 from caller. arg0 is stored in register r0 and arg1
+ * in register r1.
+ *
+ * Note: This code get's copied to internal SRAM at boot. When the OMAP
+ *      wakes up it continues execution at the point it went to sleep.
+ *
+ * Note: Because of errata work arounds we have processor specific functions
+ *       here. They are mostly the same, but slightly different.
+ *
+ */
+
+#ifdef CONFIG_ARCH_OMAP1510
+ENTRY(omap1510_cpu_suspend)
+
+       @ save registers on stack
+       stmfd   sp!, {r0 - r12, lr}
+
+       @ load base address of Traffic Controller
+       mov     r4, #TCMIF_ASM_BASE & 0xff000000
+       orr     r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
+       orr     r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
+
+       @ work around errata of OMAP1510 PDE bit for TC shut down
+       @ clear PDE bit
+       ldr     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
+       bic     r5, r5, #PDE_BIT & 0xff
+       str     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
+
+       @ set PWD_EN bit
+       and     r5, r5, #PWD_EN_BIT & 0xff
+       str     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
+
+       @ prepare to put SDRAM into self-refresh manually
+       ldr     r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
+       orr     r5, r5, #SELF_REFRESH_MODE & 0xff000000
+       orr     r5, r5, #SELF_REFRESH_MODE & 0x000000ff
+       str     r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
+
+       @ prepare to put EMIFS to Sleep
+       ldr     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
+       orr     r5, r5, #IDLE_EMIFS_REQUEST & 0xff
+       str     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
+
+       @ load base address of ARM_IDLECT1 and ARM_IDLECT2
+       mov     r4, #CLKGEN_REG_ASM_BASE & 0xff000000
+       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
+       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
+
+       @ turn off clock domains
+       mov     r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
+       orr     r5,r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
+       strh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
+
+       @ request ARM idle
+       mov     r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff
+       orr     r3, r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff00
+       strh    r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
+
+       mov     r5, #IDLE_WAIT_CYCLES & 0xff
+       orr     r5, r5, #IDLE_WAIT_CYCLES & 0xff00
+l_1510_2:
+       subs    r5, r5, #1
+       bne     l_1510_2
+/*
+ * Let's wait for the next wake up event to wake us up. r0 can't be
+ * used here because r0 holds ARM_IDLECT1
+ */
+       mov     r2, #0
+       mcr     p15, 0, r2, c7, c0, 4           @ wait for interrupt
+/*
+ * omap1510_cpu_suspend()'s resume point.
+ *
+ * It will just start executing here, so we'll restore stuff from the
+ * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
+ */
+       strh    r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
+       strh    r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
+
+       @ restore regs and return
+       ldmfd   sp!, {r0 - r12, pc}
+
+ENTRY(omap1510_cpu_suspend_sz)
+       .word   . - omap1510_cpu_suspend
+#endif /* CONFIG_ARCH_OMAP1510 */
+
+#if defined(CONFIG_ARCH_OMAP16XX)
+ENTRY(omap1610_cpu_suspend)
+
+       @ save registers on stack
+       stmfd   sp!, {r0 - r12, lr}
+
+       @ load base address of Traffic Controller
+       mov     r4, #TCMIF_ASM_BASE & 0xff000000
+       orr     r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
+       orr     r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
+
+       @ prepare to put SDRAM into self-refresh manually
+       ldr     r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
+       orr     r5, r5, #SELF_REFRESH_MODE & 0xff000000
+       orr     r5, r5, #SELF_REFRESH_MODE & 0x000000ff
+       str     r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
+
+       @ prepare to put EMIFS to Sleep
+       ldr     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
+       orr     r5, r5, #IDLE_EMIFS_REQUEST & 0xff
+       str     r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
+
+       @ load base address of ARM_IDLECT1 and ARM_IDLECT2
+       mov     r4, #CLKGEN_REG_ASM_BASE & 0xff000000
+       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
+       orr     r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
+
+       @ turn off clock domains
+       mov     r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff
+       orr     r5,r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff00
+       strh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
+
+       @ work around errata of OMAP1610/5912. Enable (!) peripheral
+       @ clock to let the chip go into deep sleep
+       ldrh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
+       orr     r5,r5, #EN_PERCK_BIT & 0xff
+       strh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
+
+       @ request ARM idle
+       mov     r3, #OMAP1610_DEEP_SLEEP_REQUEST & 0xff
+       orr     r3, r3, #OMAP1610_DEEP_SLEEP_REQUEST & 0xff00
+       strh    r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
+
+       mov     r5, #IDLE_WAIT_CYCLES & 0xff
+       orr     r5, r5, #IDLE_WAIT_CYCLES & 0xff00
+l_1610_2:
+       subs    r5, r5, #1
+       bne     l_1610_2
+/*
+ * Let's wait for the next wake up event to wake us up. r0 can't be
+ * used here because r0 holds ARM_IDLECT1
+ */
+       mov     r2, #0
+       mcr     p15, 0, r2, c7, c0, 4           @ wait for interrupt
+/*
+ * omap1610_cpu_suspend()'s resume point.
+ *
+ * It will just start executing here, so we'll restore stuff from the
+ * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
+ */
+       strh    r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
+       strh    r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
+
+       @ restore regs and return
+       ldmfd   sp!, {r0 - r12, pc}
+
+ENTRY(omap1610_cpu_suspend_sz)
+       .word   . - omap1610_cpu_suspend
+#endif /* CONFIG_ARCH_OMAP16XX */
diff -urN linux/arch/arm/plat-omap/usb.c linux/arch/