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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: ralf@linux-mips.org
Date: Tue, 12 Jul 2005 19:35:45 +0100
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 05/07/12 19:35:38

Modified files:
        arch/mips/mm   : c-r4k.c 
        include/asm-mips: hazards.h 

Log message:
        MIPS R2 instruction hazard handling.

diff -urN linux/arch/mips/mm/c-r4k.c linux/arch/mips/mm/c-r4k.c
--- linux/arch/mips/mm/c-r4k.c  2005/07/11 10:03:28     1.109
+++ linux/arch/mips/mm/c-r4k.c  2005/07/12 18:35:38     1.110
@@ -529,6 +529,7 @@
        args.end = end;
 
        on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
+       instruction_hazard();
 }
 
 /*
diff -urN linux/include/asm-mips/hazards.h linux/include/asm-mips/hazards.h
--- linux/include/asm-mips/hazards.h    2005/03/02 19:18:46     1.9
+++ linux/include/asm-mips/hazards.h    2005/07/12 18:35:38     1.10
@@ -228,6 +228,22 @@
 
 #endif
 
+#if defined(CONFIG_CPU_MIPS32_R2) || defined (CONFIG_CPU_MIPS64_R2)
+#define instruction_hazard()                                           \
+do {                                                                   \
+__label__ __next;                                                      \
+       __asm__ __volatile__(                                           \
+       "       jr.hb   %0                                      \n"     \
+       :                                                               \
+       : "r" (&&__next));                                              \
+__next:                                                                        
\
+       ;                                                               \
+} while (0)
+
+#else
+#define instruction_hazard() do { } while (0)
+#endif
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_HAZARDS_H */

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