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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: macro@linux-mips.org
Date: Mon, 20 Jun 2005 14:09:58 +0100
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     macro@ftp.linux-mips.org        05/06/20 14:09:52

Modified files:
        arch/mips/mm   : sc-rm7k.c 
        include/asm-mips: mipsregs.h 

Log message:
        Use macros for the RM7k cp0.config bits instead of magic numbers.
        Minor clean-ups.

diff -urN linux/arch/mips/mm/sc-rm7k.c linux/arch/mips/mm/sc-rm7k.c
--- linux/arch/mips/mm/sc-rm7k.c        2005/04/25 16:36:23     1.8
+++ linux/arch/mips/mm/sc-rm7k.c        2005/06/20 13:09:49     1.9
@@ -103,7 +103,7 @@
 {
        int i;
 
-       set_c0_config(R7K_CONF_SE);
+       set_c0_config(RM7K_CONF_SE);
 
        write_c0_taglo(0);
        write_c0_taghi(0);
@@ -122,16 +122,16 @@
 
 static __init void rm7k_sc_enable(void)
 {
-       if (read_c0_config() & R7K_CONF_SE)
+       if (read_c0_config() & RM7K_CONF_SE)
                return;
 
-       printk(KERN_INFO "Enabling secondary cache...");
+       printk(KERN_INFO "Enabling secondary cache...\n");
        run_uncached(__rm7k_sc_enable);
 }
 
 static void rm7k_sc_disable(void)
 {
-       clear_c0_config(R7K_CONF_SE);
+       clear_c0_config(RM7K_CONF_SE);
 }
 
 struct bcache_ops rm7k_sc_ops = {
@@ -145,19 +145,19 @@
 {
        unsigned int config = read_c0_config();
 
-       if ((config >> 31) & 1)         /* Bit 31 set -> no S-Cache */
+       if ((config & RM7K_CONF_SC))
                return;
 
        printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
               (scache_size >> 10), sc_lsize);
 
-       if (!(config & R7K_CONF_SE))
+       if (!(config & RM7K_CONF_SE))
                rm7k_sc_enable();
 
        /*
         * While we're at it let's deal with the tertiary cache.
         */
-       if (!((config >> 17) & 1)) {
+       if (!(config & RM7K_CONF_TC)) {
 
                /*
                 * We can't enable the L3 cache yet. There may be board-specific
@@ -170,9 +170,9 @@
                 * to probe it.
                 */
                printk(KERN_INFO "Tertiary cache present, %s enabled\n",
-                      config&(1<<12) ? "already" : "not (yet)");
+                      (config & RM7K_CONF_TE) ? "already" : "not (yet)");
 
-               if ((config >> 12) & 1)
+               if ((config & RM7K_CONF_TE))
                        rm7k_tcache_enabled = 1;
        }
 
diff -urN linux/include/asm-mips/mipsregs.h linux/include/asm-mips/mipsregs.h
--- linux/include/asm-mips/mipsregs.h   2005/06/07 11:39:57     1.74
+++ linux/include/asm-mips/mipsregs.h   2005/06/20 13:09:52     1.75
@@ -425,6 +425,7 @@
 #define CONF_SM                        (_ULCAST_(1) << 16)
 #define CONF_SC                        (_ULCAST_(1) << 17)
 #define CONF_EW                        (_ULCAST_(3) << 18)
+#define CONF_SB                        (_ULCAST_(3) << 22)
 #define CONF_EP                        (_ULCAST_(15)<< 24)
 #define CONF_EC                        (_ULCAST_(7) << 28)
 #define CONF_CM                        (_ULCAST_(1) << 31)
@@ -432,14 +433,18 @@
 /* Bits specific to the R4xx0.  */
 #define R4K_CONF_SW            (_ULCAST_(1) << 20)
 #define R4K_CONF_SS            (_ULCAST_(1) << 21)
-#define R4K_CONF_SB            (_ULCAST_(3) << 22)
 
 /* Bits specific to the R5000.  */
 #define R5K_CONF_SE            (_ULCAST_(1) << 12)
 #define R5K_CONF_SS            (_ULCAST_(3) << 20)
 
 /* Bits specific to the RM7000.  */
-#define R7K_CONF_SE            (_ULCAST_(1) << 3)
+#define RM7K_CONF_SE           (_ULCAST_(1) <<  3)
+#define RM7K_CONF_TE           (_ULCAST_(1) << 12)
+#define RM7K_CONF_CLK          (_ULCAST_(1) << 16)
+#define RM7K_CONF_TC           (_ULCAST_(1) << 17)
+#define RM7K_CONF_SI           (_ULCAST_(3) << 20)
+#define RM7K_CONF_SC           (_ULCAST_(1) << 31)
 
 /* Bits specific to the R10000.  */
 #define R10K_CONF_DN           (_ULCAST_(3) <<  3)

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