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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: ralf@linux-mips.org
Date: Tue, 07 Jun 2005 14:45:50 +0100
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 05/06/07 14:45:43

Modified files:
        .              : MAINTAINERS Makefile 
        Documentation/DocBook: libata.tmpl 
        arch/h8300/kernel: process.c 
        arch/i386      : Kconfig 
        arch/i386/kernel: setup.c smpboot.c 
        arch/i386/kernel/cpu: intel_cacheinfo.c 
        arch/i386/kernel/cpu/cpufreq: Kconfig Makefile longhaul.c 
                                      powernow-k7.c powernow-k8.c 
                                      powernow-k8.h speedstep-centrino.c 
                                      speedstep-lib.c speedstep-smi.c 
        arch/i386/kernel/timers: common.c timer_tsc.c 
        arch/i386/pci  : irq.c 
        arch/ia64/ia32 : sys_ia32.c 
        arch/ia64/kernel: entry.S mca.c minstate.h perfmon.c ptrace.c 
                          smpboot.c sys_ia64.c 
        arch/ia64/sn/kernel: setup.c 
        arch/m68knommu/kernel: process.c 
        arch/mips      : defconfig 
        arch/mips/configs: atlas_defconfig capcella_defconfig 
                           cobalt_defconfig db1000_defconfig 
                           db1100_defconfig db1500_defconfig 
                           db1550_defconfig ddb5476_defconfig 
                           ddb5477_defconfig decstation_defconfig 
                           e55_defconfig ev64120_defconfig 
                           ev96100_defconfig ip22_defconfig 
                           ip27_defconfig ip32_defconfig 
                           it8172_defconfig ivr_defconfig 
                           jaguar-atx_defconfig jmr3927_defconfig 
                           lasat200_defconfig malta_defconfig 
                           mpc30x_defconfig ocelot_3_defconfig 
                           ocelot_c_defconfig ocelot_defconfig 
                           ocelot_g_defconfig pb1100_defconfig 
                           pb1500_defconfig pb1550_defconfig 
                           rm200_defconfig sb1250-swarm_defconfig 
                           sead_defconfig tb0226_defconfig 
                           tb0229_defconfig workpad_defconfig 
                           yosemite_defconfig 
        arch/ppc       : Kconfig 
        arch/ppc/boot/images: Makefile 
        arch/ppc/configs: mpc8555_cds_defconfig 
        arch/ppc/kernel: head_fsl_booke.S traps.c 
        arch/ppc/platforms: pmac_cpufreq.c pq2ads.h 
        arch/ppc/platforms/83xx: mpc834x_sys.c mpc834x_sys.h 
        arch/ppc/platforms/85xx: mpc8540_ads.c mpc85xx_cds_common.c 
                                 mpc85xx_cds_common.h sbc8560.c 
        arch/ppc/syslib: Makefile m8260_pci_erratum9.c m8260_setup.c 
                         open_pic.c ppc83xx_setup.c ppc85xx_setup.c 
                         prom_init.c 
        arch/ppc64/kernel: entry.S head.S iSeries_setup.c idle.c mf.c 
                           pSeries_reconfig.c process.c prom_init.c 
                           rtc.c setup.c smp.c sysfs.c time.c 
        arch/s390/appldata: appldata_base.c appldata_mem.c 
                            appldata_net_sum.c appldata_os.c 
        arch/s390/kernel: ptrace.c 
        arch/s390/mm   : fault.c 
        arch/sparc64/kernel: pci_iommu.c pci_psycho.c pci_sabre.c 
                             pci_schizo.c sbus.c setup.c smp.c traps.c 
        arch/um        : Kconfig.debug 
        arch/um/drivers: random.c ssl.c stdio_console.c ubd_kern.c 
        arch/um/include: sysrq.h 
        arch/um/kernel : exec_kern.c main.c process_kern.c ptrace.c 
                         sysrq.c trap_kern.c um_arch.c 
        arch/um/kernel/tt: process_kern.c 
        arch/um/sys-i386: sysrq.c 
        arch/um/sys-ppc: sysrq.c 
        arch/um/sys-x86_64: syscalls.c sysrq.c 
        arch/x86_64    : Kconfig 
        arch/x86_64/kernel: io_apic.c mpparse.c signal.c time.c traps.c 
                            x8664_ksyms.c 
        drivers/acpi   : Kconfig pci_irq.c 
        drivers/atm    : Makefile fore200e.c he.c nicstar.c zatm.c 
        drivers/block  : ub.c 
        drivers/cdrom  : viocd.c 
        drivers/char/ipmi: ipmi_devintf.c 
        drivers/cpufreq: Kconfig Makefile cpufreq.c cpufreq_ondemand.c 
                         cpufreq_stats.c 
        drivers/firmware: pcdp.c 
        drivers/i2c/busses: i2c-ali1563.c 
        drivers/ide    : ide-cd.c ide-disk.c ide-floppy.c ide-probe.c 
                         ide-proc.c ide-tape.c ide.c 
        drivers/ide/pci: amd74xx.c 
        drivers/infiniband/core: sa_query.c user_mad.c 
        drivers/infiniband/include: ib_sa.h 
        drivers/input  : joydev.c mousedev.c 
        drivers/input/gameport: Kconfig 
        drivers/input/keyboard: atkbd.c 
        drivers/input/mouse: psmouse-base.c synaptics.c 
        drivers/input/serio: i8042-x86ia64io.h i8042.c 
        drivers/input/touchscreen: gunze.c 
        drivers/macintosh: therm_adt746x.c via-pmu.c 
        drivers/media/dvb/bt8xx: dst.c 
        drivers/media/video: bttv-i2c.c 
        drivers/net    : Kconfig Makefile amd8111e.c e100.c forcedeth.c 
                         iseries_veth.c natsemi.c ns83820.c pcnet32.c 
                         r8169.c shaper.c sis900.c tg3.c tlan.c 
        drivers/net/bonding: bond_main.c 
        drivers/net/e1000: e1000.h e1000_ethtool.c e1000_hw.c e1000_hw.h 
                           e1000_main.c e1000_osdep.h e1000_param.c 
        drivers/net/hamradio: baycom_epp.c 
        drivers/net/ixgb: ixgb.h ixgb_ee.c ixgb_ethtool.c ixgb_main.c 
                          ixgb_osdep.h 
        drivers/net/pcmcia: 3c574_cs.c 
        drivers/net/tulip: media.c 
        drivers/net/wireless: airo.c atmel_cs.c 
        drivers/pci    : quirks.c 
        drivers/pci/hotplug: cpci_hotplug_core.c cpci_hotplug_pci.c 
                             shpchprm_acpi.c 
        drivers/s390/net: Makefile ctcdbug.h ctcmain.c ctctty.c cu3088.c 
                          cu3088.h iucv.c lcs.c qeth.h qeth_eddp.c 
                          qeth_main.c qeth_tso.h 
        drivers/scsi   : ahci.c ata_piix.c ide-scsi.c libata-core.c 
                         libata-scsi.c libata.h sata_nv.c sata_promise.c 
                         sata_qstor.c sata_sil.c sata_sis.c sata_svw.c 
                         sata_sx4.c sata_uli.c sata_via.c sata_vsc.c 
                         scsi_scan.c 
        drivers/scsi/aic7xxx: aic79xx_osm.c 
        drivers/scsi/qla2xxx: qla_os.c 
        drivers/usb/atm: speedtch.c 
        drivers/usb/core: sysfs.c 
        drivers/usb/host: Kconfig Makefile sl811-hcd.c 
        drivers/usb/input: hid-core.c 
        drivers/usb/media/pwc: Makefile pwc-ctrl.c pwc-if.c pwc-kiara.c 
                               pwc-timon.c pwc-uncompress.c 
        drivers/usb/net: usbnet.c 
        drivers/usb/serial: Kconfig Makefile cp2101.c ftdi_sio.c 
                            ftdi_sio.h usb-serial.c 
        drivers/usb/storage: unusual_devs.h 
        drivers/video/intelfb: intelfbdrv.c 
        fs             : mpage.c 
        fs/cifs        : README cifsproto.h cifssmb.c dir.c inode.c 
                         misc.c 
        fs/hostfs      : hostfs_kern.c 
        fs/jbd         : checkpoint.c 
        fs/proc        : proc_devtree.c 
        fs/udf         : udftime.c 
        fs/xfs         : xfs_iomap.c 
        fs/xfs/linux-2.6: xfs_aops.c xfs_file.c xfs_ioctl32.c 
                          xfs_ioctl32.h xfs_super.c 
        include/asm-i386: linkage.h timer.h 
        include/asm-ia64: perfmon.h 
        include/asm-ia64/sn: sn_sal.h 
        include/asm-ppc: cpm2.h m8260_pci.h mpc8260.h 
        include/asm-ppc64: processor.h prom.h thread_info.h 
        include/asm-ppc64/iSeries: mf.h 
        include/asm-s390: user.h 
        include/asm-sh : thread_info.h 
        include/asm-sh64: thread_info.h 
        include/asm-sparc64: iommu.h pbm.h spitfire.h 
        include/asm-um : page.h pgtable.h thread_info.h 
        include/asm-x86_64: bug.h 
        include/linux  : acpi.h cpufreq.h etherdevice.h ethtool.h 
                         gameport.h hardirq.h ide.h if_shaper.h if_tr.h 
                         inetdevice.h libata.h mii.h netdevice.h 
                         notifier.h pci_ids.h pkt_sched.h sysctl.h usb.h 
        include/net    : route.h xfrm.h 
        init           : Kconfig 
        kernel         : cpuset.c module.c 
        kernel/irq     : handle.c 
        lib            : Kconfig.debug 
        net/802        : tr.c 
        net/bridge     : br_device.c br_if.c br_input.c br_notify.c 
                         br_private.h br_stp_bpdu.c 
        net/core       : dev.c ethtool.c net-sysfs.c 
        net/ipv4       : devinet.c esp4.c multipath_drr.c multipath_rr.c 
                         udp.c 
        net/ipv4/ipvs  : Makefile ip_vs_proto.c 
        net/ipv4/netfilter: ip_queue.c 
        net/ipv6       : ip6_flowlabel.c ipv6_syms.c xfrm6_policy.c 
        net/sched      : sch_dsmark.c sch_netem.c 
        net/xfrm       : xfrm_policy.c 
        sound/oss      : Kconfig 
        sound/ppc      : pmac.c 
Added files:
        Documentation/cpu-freq: cpufreq-stats.txt 
        arch/i386/kernel/cpu/cpufreq: sc520_freq.c 
        arch/ppc/syslib: m82xx_pci.c m82xx_pci.h 
        drivers/cpufreq: cpufreq_conservative.c 
        drivers/net    : bnx2.c bnx2.h bnx2_fw.h 
        drivers/s390/net: ctcmain.h 
        drivers/usb/host: sl811_cs.c 
        drivers/usb/serial: option.c 
Removed files:
        arch/ppc/syslib: m8260_pci.c m8260_pci.h 
        arch/um/include: 2_5compat.h 
        arch/um/kernel : initrd_kern.c initrd_user.c 
        drivers/s390/net: qeth_tso.c 
        drivers/usb/media/pwc: ChangeLog pwc-dec1.c pwc-dec1.h 
                               pwc-dec23.c pwc-dec23.h 
        net/ipv4/ipvs  : ip_vs_proto_icmp.c 

Log message:
        Merge with Linux 2.6.12-rc6.

diff -urN linux/MAINTAINERS linux/MAINTAINERS
--- linux/MAINTAINERS   2005/05/19 12:08:04     1.180
+++ linux/MAINTAINERS   2005/06/07 13:45:25     1.181
@@ -239,6 +239,12 @@
 W:     http://www.linux-usb.org/SpeedTouch/
 S:     Maintained
 
+ALI1563 I2C DRIVER
+P:     Rudolf Marek
+M:     r.marek@sh.cvut.cz
+L:     sensors@stimpy.netroedge.com
+S:     Maintained
+
 ALPHA PORT
 P:     Richard Henderson
 M:     rth@twiddle.net
@@ -1023,8 +1029,8 @@
 S:     Maintained
 
 SN-IA64 (Itanium) SUB-PLATFORM
-P:     Jesse Barnes
-M:     jbarnes@sgi.com
+P:     Greg Edwards
+M:     edwardsg@sgi.com
 L:     linux-altix@sgi.com
 L:     linux-ia64@vger.kernel.org
 W:     http://www.sgi.com/altix
diff -urN linux/Makefile linux/Makefile
--- linux/Makefile      2005/05/26 09:12:35     1.252
+++ linux/Makefile      2005/06/07 13:45:25     1.253
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
 SUBLEVEL = 12
-EXTRAVERSION =-rc5
+EXTRAVERSION =-rc6
 NAME=Woozy Numbat
 
 # *DOCUMENTATION*
diff -urN linux/Documentation/DocBook/libata.tmpl 
linux/Documentation/DocBook/libata.tmpl
--- linux/Documentation/DocBook/libata.tmpl     2005/03/18 17:36:43     1.4
+++ linux/Documentation/DocBook/libata.tmpl     2005/06/07 13:45:25     1.5
@@ -14,7 +14,7 @@
   </authorgroup>
 
   <copyright>
-   <year>2003</year>
+   <year>2003-2005</year>
    <holder>Jeff Garzik</holder>
   </copyright>
 
@@ -44,30 +44,38 @@
 
 <toc></toc>
 
-  <chapter id="libataThanks">
-     <title>Thanks</title>
+  <chapter id="libataIntroduction">
+     <title>Introduction</title>
   <para>
-  The bulk of the ATA knowledge comes thanks to long conversations with
-  Andre Hedrick (www.linux-ide.org).
+  libATA is a library used inside the Linux kernel to support ATA host
+  controllers and devices.  libATA provides an ATA driver API, class
+  transports for ATA and ATAPI devices, and SCSI&lt;-&gt;ATA translation
+  for ATA devices according to the T10 SAT specification.
   </para>
   <para>
-  Thanks to Alan Cox for pointing out similarities 
-  between SATA and SCSI, and in general for motivation to hack on
-  libata.
-  </para>
-  <para>
-  libata's device detection
-  method, ata_pio_devchk, and in general all the early probing was
-  based on extensive study of Hale Landis's probe/reset code in his
-  ATADRVR driver (www.ata-atapi.com).
+  This Guide documents the libATA driver API, library functions, library
+  internals, and a couple sample ATA low-level drivers.
   </para>
   </chapter>
 
   <chapter id="libataDriverApi">
      <title>libata Driver API</title>
+     <para>
+     struct ata_port_operations is defined for every low-level libata
+     hardware driver, and it controls how the low-level driver
+     interfaces with the ATA and SCSI layers.
+     </para>
+     <para>
+     FIS-based drivers will hook into the system with ->qc_prep() and
+     ->qc_issue() high-level hooks.  Hardware which behaves in a manner
+     similar to PCI IDE hardware may utilize several generic helpers,
+     defining at a bare minimum the bus I/O addresses of the ATA shadow
+     register blocks.
+     </para>
      <sect1>
         <title>struct ata_port_operations</title>
 
+       <sect2><title>Disable ATA port</title>
        <programlisting>
 void (*port_disable) (struct ata_port *);
        </programlisting>
@@ -78,6 +86,9 @@
        unplug).
        </para>
 
+       </sect2>
+
+       <sect2><title>Post-IDENTIFY device configuration</title>
        <programlisting>
 void (*dev_config) (struct ata_port *, struct ata_device *);
        </programlisting>
@@ -88,6 +99,9 @@
        issue of SET FEATURES - XFER MODE, and prior to operation.
        </para>
 
+       </sect2>
+
+       <sect2><title>Set PIO/DMA mode</title>
        <programlisting>
 void (*set_piomode) (struct ata_port *, struct ata_device *);
 void (*set_dmamode) (struct ata_port *, struct ata_device *);
@@ -108,6 +122,9 @@
        ->set_dma_mode() is only called if DMA is possible.
        </para>
 
+       </sect2>
+
+       <sect2><title>Taskfile read/write</title>
        <programlisting>
 void (*tf_load) (struct ata_port *ap, struct ata_taskfile *tf);
 void (*tf_read) (struct ata_port *ap, struct ata_taskfile *tf);
@@ -120,6 +137,9 @@
        taskfile register values.
        </para>
 
+       </sect2>
+
+       <sect2><title>ATA command execute</title>
        <programlisting>
 void (*exec_command)(struct ata_port *ap, struct ata_taskfile *tf);
        </programlisting>
@@ -129,17 +149,37 @@
        ->tf_load(), to be initiated in hardware.
        </para>
 
+       </sect2>
+
+       <sect2><title>Per-cmd ATAPI DMA capabilities filter</title>
+       <programlisting>
+int (*check_atapi_dma) (struct ata_queued_cmd *qc);
+       </programlisting>
+
+       <para>
+Allow low-level driver to filter ATA PACKET commands, returning a status
+indicating whether or not it is OK to use DMA for the supplied PACKET
+command.
+       </para>
+
+       </sect2>
+
+       <sect2><title>Read specific ATA shadow registers</title>
        <programlisting>
 u8   (*check_status)(struct ata_port *ap);
-void (*dev_select)(struct ata_port *ap, unsigned int device);
+u8   (*check_altstatus)(struct ata_port *ap);
+u8   (*check_err)(struct ata_port *ap);
        </programlisting>
 
        <para>
-       Reads the Status ATA shadow register from hardware.  On some
-       hardware, this has the side effect of clearing the interrupt
-       condition.
+       Reads the Status/AltStatus/Error ATA shadow register from
+       hardware.  On some hardware, reading the Status register has
+       the side effect of clearing the interrupt condition.
        </para>
 
+       </sect2>
+
+       <sect2><title>Select ATA device on bus</title>
        <programlisting>
 void (*dev_select)(struct ata_port *ap, unsigned int device);
        </programlisting>
@@ -147,9 +187,13 @@
        <para>
        Issues the low-level hardware command(s) that causes one of N
        hardware devices to be considered 'selected' (active and
-       available for use) on the ATA bus.
+       available for use) on the ATA bus.  This generally has no
+meaning on FIS-based devices.
        </para>
 
+       </sect2>
+
+       <sect2><title>Reset ATA bus</title>
        <programlisting>
 void (*phy_reset) (struct ata_port *ap);
        </programlisting>
@@ -162,17 +206,31 @@
        functions ata_bus_reset() or sata_phy_reset() for this hook.
        </para>
 
+       </sect2>
+
+       <sect2><title>Control PCI IDE BMDMA engine</title>
        <programlisting>
 void (*bmdma_setup) (struct ata_queued_cmd *qc);
 void (*bmdma_start) (struct ata_queued_cmd *qc);
+void (*bmdma_stop) (struct ata_port *ap);
+u8   (*bmdma_status) (struct ata_port *ap);
        </programlisting>
 
        <para>
-       When setting up an IDE BMDMA transaction, these hooks arm
-       (->bmdma_setup) and fire (->bmdma_start) the hardware's DMA
-       engine.
+When setting up an IDE BMDMA transaction, these hooks arm
+(->bmdma_setup), fire (->bmdma_start), and halt (->bmdma_stop)
+the hardware's DMA engine.  ->bmdma_status is used to read the standard
+PCI IDE DMA Status register.
        </para>
 
+       <para>
+These hooks are typically either no-ops, or simply not implemented, in
+FIS-based drivers.
+       </para>
+
+       </sect2>
+
+       <sect2><title>High-level taskfile hooks</title>
        <programlisting>
 void (*qc_prep) (struct ata_queued_cmd *qc);
 int (*qc_issue) (struct ata_queued_cmd *qc);
@@ -190,20 +248,26 @@
        ->qc_issue is used to make a command active, once the hardware
        and S/G tables have been prepared.  IDE BMDMA drivers use the
        helper function ata_qc_issue_prot() for taskfile protocol-based
-       dispatch.  More advanced drivers roll their own ->qc_issue
-       implementation, using this as the "issue new ATA command to
-       hardware" hook.
+       dispatch.  More advanced drivers implement their own ->qc_issue.
        </para>
 
+       </sect2>
+
+       <sect2><title>Timeout (error) handling</title>
        <programlisting>
 void (*eng_timeout) (struct ata_port *ap);
        </programlisting>
 
        <para>
-       This is a high level error handling function, called from the
-       error handling thread, when a command times out.
+This is a high level error handling function, called from the
+error handling thread, when a command times out.  Most newer
+hardware will implement its own error handling code here.  IDE BMDMA
+drivers may use the helper function ata_eng_timeout().
        </para>
 
+       </sect2>
+
+       <sect2><title>Hardware interrupt handling</title>
        <programlisting>
 irqreturn_t (*irq_handler)(int, void *, struct pt_regs *);
 void (*irq_clear) (struct ata_port *);
@@ -216,6 +280,9 @@
        is quiet.
        </para>
 
+       </sect2>
+
+       <sect2><title>SATA phy read/write</title>
        <programlisting>
 u32 (*scr_read) (struct ata_port *ap, unsigned int sc_reg);
 void (*scr_write) (struct ata_port *ap, unsigned int sc_reg,
@@ -227,6 +294,9 @@
        if ->phy_reset hook called the sata_phy_reset() helper function.
        </para>
 
+       </sect2>
+
+       <sect2><title>Init and shutdown</title>
        <programlisting>
 int (*port_start) (struct ata_port *ap);
 void (*port_stop) (struct ata_port *ap);
@@ -240,15 +310,17 @@
        tasks.  
        </para>
        <para>
-       ->host_stop() is called when the rmmod or hot unplug process
-       begins.  The hook must stop all hardware interrupts, DMA
-       engines, etc.
-       </para>
-       <para>
        ->port_stop() is called after ->host_stop().  It's sole function
        is to release DMA/memory resources, now that they are no longer
        actively being used.
        </para>
+       <para>
+       ->host_stop() is called after all ->port_stop() calls
+have completed.  The hook must finalize hardware shutdown, release DMA
+and other resources, etc.
+       </para>
+
+       </sect2>
 
      </sect1>
   </chapter>
@@ -279,4 +351,24 @@
 !Idrivers/scsi/sata_sil.c
   </chapter>
 
+  <chapter id="libataThanks">
+     <title>Thanks</title>
+  <para>
+  The bulk of the ATA knowledge comes thanks to long conversations with
+  Andre Hedrick (www.linux-ide.org), and long hours pondering the ATA
+  and SCSI specifications.
+  </para>
+  <para>
+  Thanks to Alan Cox for pointing out similarities 
+  between SATA and SCSI, and in general for motivation to hack on
+  libata.
+  </para>
+  <para>
+  libata's device detection
+  method, ata_pio_devchk, and in general all the early probing was
+  based on extensive study of Hale Landis's probe/reset code in his
+  ATADRVR driver (www.ata-atapi.com).
+  </para>
+  </chapter>
+
 </book>
diff -urN linux/Documentation/cpu-freq/cpufreq-stats.txt 
linux/Documentation/cpu-freq/cpufreq-stats.txt
--- linux/Documentation/cpu-freq/cpufreq-stats.txt      1970/01/01 00:00:00
+++ linux/Documentation/cpu-freq/cpufreq-stats.txt      2005-06-07 
14:45:26.089252000 +0100     1.1
@@ -0,0 +1,128 @@
+
+     CPU frequency and voltage scaling statictics in the Linux(TM) kernel
+
+
+             L i n u x    c p u f r e q - s t a t s   d r i v e r
+
+                       - information for users -
+
+
+             Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
+
+Contents
+1. Introduction
+2. Statistics Provided (with example)
+3. Configuring cpufreq-stats
+
+
+1. Introduction
+
+cpufreq-stats is a driver that provices CPU frequency statistics for each CPU.
+This statistics is provided in /sysfs as a bunch of read_only interfaces. This
+interface (when configured) will appear in a seperate directory under cpufreq
+in /sysfs (<sysfs root>/devices/system/cpu/cpuX/cpufreq/stats/) for each CPU.
+Various statistics will form read_only files under this directory.
+
+This driver is designed to be independent of any particular cpufreq_driver
+that may be running on your CPU. So, it will work with any cpufreq_driver.
+
+
+2. Statistics Provided (with example)
+
+cpufreq stats provides following statistics (explained in detail below).
+-  time_in_state
+-  total_trans
+-  trans_table
+
+All the statistics will be from the time the stats driver has been inserted 
+to the time when a read of a particular statistic is done. Obviously, stats 
+driver will not have any information about the the frequcny transitions before
+the stats driver insertion.
+
+--------------------------------------------------------------------------------
+<mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # ls -l
+total 0
+drwxr-xr-x  2 root root    0 May 14 16:06 .
+drwxr-xr-x  3 root root    0 May 14 15:58 ..
+-r--r--r--  1 root root 4096 May 14 16:06 time_in_state
+-r--r--r--  1 root root 4096 May 14 16:06 total_trans
+-r--r--r--  1 root root 4096 May 14 16:06 trans_table
+--------------------------------------------------------------------------------
+
+-  time_in_state
+This gives the amount of time spent in each of the frequencies supported by
+this CPU. The cat output will have "<frequency> <time>" pair in each line, 
which
+will mean this CPU spent <time> usertime units of time at <frequency>. Output
+will have one line for each of the supported freuencies. usertime units here 
+is 10mS (similar to other time exported in /proc).
+
+--------------------------------------------------------------------------------
+<mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat time_in_state 
+3600000 2089
+3400000 136
+3200000 34
+3000000 67
+2800000 172488
+--------------------------------------------------------------------------------
+
+
+-  total_trans
+This gives the total number of frequency transitions on this CPU. The cat 
+output will have a single count which is the total number of frequency
+transitions.
+
+--------------------------------------------------------------------------------
+<mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat total_trans
+20
+--------------------------------------------------------------------------------
+
+-  trans_table
+This will give a fine grained information about all the CPU frequency
+transitions. The cat output here is a two dimensional matrix, where an entry
+<i,j> (row i, column j) represents the count of number of transitions from 
+Freq_i to Freq_j. Freq_i is in descending order with increasing rows and 
+Freq_j is in descending order with increasing columns. The output here also 
+contains the actual freq values for each row and column for better readability.
+
+--------------------------------------------------------------------------------
+<mysystem>:/sys/devices/system/cpu/cpu0/cpufreq/stats # cat trans_table
+   From  :    To
+         :   3600000   3400000   3200000   3000000   2800000 
+  3600000:         0         5         0         0         0 
+  3400000:         4         0         2         0         0 
+  3200000:         0         1         0         2         0 
+  3000000:         0         0         1         0         3 
+  2800000:         0         0         0         2         0 
+--------------------------------------------------------------------------------
+
+
+3. Configuring cpufreq-stats
+
+To configure cpufreq-stats in your kernel
+Config Main Menu
+       Power management options (ACPI, APM)  --->
+               CPU Frequency scaling  --->
+                       [*] CPU Frequency scaling
+                       <*>   CPU frequency translation statistics 
+                       [*]     CPU frequency translation statistics details
+
+
+"CPU Frequency scaling" (CONFIG_CPU_FREQ) should be enabled to configure
+cpufreq-stats.
+
+"CPU frequency translation statistics" (CONFIG_CPU_FREQ_STAT) provides the
+basic statistics which includes time_in_state and total_trans.
+
+"CPU frequency translation statistics details" (CONFIG_CPU_FREQ_STAT_DETAILS)
+provides fine grained cpufreq stats by trans_table. The reason for having a
+seperate config option for trans_table is:
+- trans_table goes against the traditional /sysfs rule of one value per
+  interface. It provides a whole bunch of value in a 2 dimensional matrix
+  form.
+
+Once these two options are enabled and your CPU supports cpufrequency, you
+will be able to see the CPU frequency statistics in /sysfs.
+
+
+
+
diff -urN linux/arch/h8300/kernel/process.c linux/arch/h8300/kernel/process.c
--- linux/arch/h8300/kernel/process.c   2004/09/19 12:30:02     1.6
+++ linux/arch/h8300/kernel/process.c   2005/06/07 13:45:26     1.7
@@ -54,7 +54,7 @@
 void default_idle(void)
 {
        while(1) {
-               if (need_resched()) {
+               if (!need_resched()) {
                        local_irq_enable();
                        __asm__("sleep");
                        local_irq_disable();
diff -urN linux/arch/i386/Kconfig linux/arch/i386/Kconfig
--- linux/arch/i386/Kconfig     2005/05/19 12:08:08     1.54
+++ linux/arch/i386/Kconfig     2005/06/07 13:45:26     1.55
@@ -1163,7 +1163,7 @@
 
 config PCI_MMCONFIG
        bool
-       depends on PCI && (PCI_GOMMCONFIG || (PCI_GOANY && ACPI))
+       depends on PCI && ACPI && (PCI_GOMMCONFIG || PCI_GOANY)
        select ACPI_BOOT
        default y
 
diff -urN linux/arch/i386/kernel/setup.c linux/arch/i386/kernel/setup.c
--- linux/arch/i386/kernel/setup.c      2005/03/18 17:36:48     1.109
+++ linux/arch/i386/kernel/setup.c      2005/06/07 13:45:26     1.110
@@ -1502,11 +1502,13 @@
        if (efi_enabled)
                efi_map_memmap();
 
+#ifdef CONFIG_ACPI_BOOT
        /*
         * Parse the ACPI tables for possible boot-time SMP configuration.
         */
        acpi_boot_table_init();
        acpi_boot_init();
+#endif
 
 #ifdef CONFIG_X86_LOCAL_APIC
        if (smp_found_config)
diff -urN linux/arch/i386/kernel/smpboot.c linux/arch/i386/kernel/smpboot.c
--- linux/arch/i386/kernel/smpboot.c    2005/05/26 09:12:36     1.70
+++ linux/arch/i386/kernel/smpboot.c    2005/06/07 13:45:26     1.71
@@ -1074,8 +1074,10 @@
                        cpu_set(cpu, cpu_sibling_map[cpu]);
                }
 
-               if (siblings != smp_num_siblings)
+               if (siblings != smp_num_siblings) {
                        printk(KERN_WARNING "WARNING: %d siblings found for 
CPU%d, should be %d\n", siblings, cpu, smp_num_siblings);
+                       smp_num_siblings = siblings;
+               }
 
                if (c->x86_num_cores > 1) {
                        for (i = 0; i < NR_CPUS; i++) {
diff -urN linux/arch/i386/kernel/cpu/intel_cacheinfo.c 
linux/arch/i386/kernel/cpu/intel_cacheinfo.c
--- linux/arch/i386/kernel/cpu/intel_cacheinfo.c        2005/04/08 18:57:53     
1.3
+++ linux/arch/i386/kernel/cpu/intel_cacheinfo.c        2005/06/07 13:45:26     
1.4
@@ -118,7 +118,7 @@
 };
 
 #define MAX_CACHE_LEAVES               4
-static unsigned short __devinitdata    num_cache_leaves;
+static unsigned short                  num_cache_leaves;
 
 static int __devinit cpuid4_cache_lookup(int index, struct _cpuid4_info 
*this_leaf)
 {
diff -urN linux/arch/i386/kernel/cpu/cpufreq/sc520_freq.c 
linux/arch/i386/kernel/cpu/cpufreq/sc520_freq.c
--- linux/arch/i386/kernel/cpu/cpufreq/sc520_freq.c     1970/01/01 00:00:00
+++ linux/arch/i386/kernel/cpu/cpufreq/sc520_freq.c     2005-06-07 
14:45:26.501483000 +0100     1.1
@@ -0,0 +1,186 @@
+/*
+ *     sc520_freq.c: cpufreq driver for the AMD Elan sc520
+ *
+ *     Copyright (C) 2005 Sean Young <sean@mess.org>
+ *
+ *     This program is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     as published by the Free Software Foundation; either version
+ *     2 of the License, or (at your option) any later version.
+ *
+ *     Based on elanfreq.c
+ *
+ *     2005-03-30: - initial revision
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/delay.h>
+#include <linux/cpufreq.h>
+
+#include <asm/msr.h>
+#include <asm/timex.h>
+#include <asm/io.h>
+
+#define MMCR_BASE      0xfffef000      /* The default base address */
+#define OFFS_CPUCTL    0x2   /* CPU Control Register */
+
+static __u8 __iomem *cpuctl;
+
+#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, 
"sc520_freq", msg)
+
+static struct cpufreq_frequency_table sc520_freq_table[] = {
+       {0x01,  100000},
+       {0x02,  133000},
+       {0,     CPUFREQ_TABLE_END},
+};
+
+static unsigned int sc520_freq_get_cpu_frequency(unsigned int cpu)
+{
+       u8 clockspeed_reg = *cpuctl;
+
+       switch (clockspeed_reg & 0x03) {
+       default:
+               printk(KERN_ERR "sc520_freq: error: cpuctl register has 
unexpected value %02x\n", clockspeed_reg);
+       case 0x01:
+               return 100000;
+       case 0x02:
+               return 133000;
+       }
+}
+
+static void sc520_freq_set_cpu_state (unsigned int state)
+{
+
+       struct cpufreq_freqs    freqs;
+       u8 clockspeed_reg;
+
+       freqs.old = sc520_freq_get_cpu_frequency(0);
+       freqs.new = sc520_freq_table[state].frequency;
+       freqs.cpu = 0; /* AMD Elan is UP */
+
+       cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+       dprintk("attempting to set frequency to %i kHz\n",
+                       sc520_freq_table[state].frequency);
+
+       local_irq_disable();
+
+       clockspeed_reg = *cpuctl & ~0x03;
+       *cpuctl = clockspeed_reg | sc520_freq_table[state].index;
+
+       local_irq_enable();
+
+       cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+};
+
+static int sc520_freq_verify (struct cpufreq_policy *policy)
+{
+       return cpufreq_frequency_table_verify(policy, &sc520_freq_table[0]);
+}
+
+static int sc520_freq_target (struct cpufreq_policy *policy,
+                           unsigned int target_freq,
+                           unsigned int relation)
+{
+       unsigned int newstate = 0;
+
+       if (cpufreq_frequency_table_target(policy, sc520_freq_table, 
target_freq, relation, &newstate))
+               return -EINVAL;
+
+       sc520_freq_set_cpu_state(newstate);
+
+       return 0;
+}
+
+
+/*
+ *     Module init and exit code
+ */
+
+static int sc520_freq_cpu_init(struct cpufreq_policy *policy)
+{
+       struct cpuinfo_x86 *c = cpu_data;
+       int result;
+
+       /* capability check */
+       if (c->x86_vendor != X86_VENDOR_AMD ||
+           c->x86 != 4 || c->x86_model != 9)
+               return -ENODEV;
+
+       /* cpuinfo and default policy values */
+       policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+       policy->cpuinfo.transition_latency = 1000000; /* 1ms */
+       policy->cur = sc520_freq_get_cpu_frequency(0);
+
+       result = cpufreq_frequency_table_cpuinfo(policy, sc520_freq_table);
+       if (result)
+               return (result);
+
+       cpufreq_frequency_table_get_attr(sc520_freq_table, policy->cpu);
+
+       return 0;
+}
+
+
+static int sc520_freq_cpu_exit(struct cpufreq_policy *policy)
+{
+       cpufreq_frequency_table_put_attr(policy->cpu);
+       return 0;
+}
+
+
+static struct freq_attr* sc520_freq_attr[] = {
+       &cpufreq_freq_attr_scaling_available_freqs,
+       NULL,
+};
+
+
+static struct cpufreq_driver sc520_freq_driver = {
+       .get    = sc520_freq_get_cpu_frequency,
+       .verify = sc520_freq_verify,
+       .target = sc520_freq_target,
+       .init   = sc520_freq_cpu_init,
+       .exit   = sc520_freq_cpu_exit,
+       .name   = "sc520_freq",
+       .owner  = THIS_MODULE,
+       .attr   = sc520_freq_attr,
+};
+
+
+static int __init sc520_freq_init(void)
+{
+       struct cpuinfo_x86 *c = cpu_data;
+
+       /* Test if we have the right hardware */
+       if(c->x86_vendor != X86_VENDOR_AMD ||
+                               c->x86 != 4 || c->x86_model != 9) {
+               dprintk("no Elan SC520 processor found!\n");
+               return -ENODEV;
+       }
+       cpuctl = ioremap((unsigned long)(MMCR_BASE + OFFS_CPUCTL), 1);
+       if(!cpuctl) {
+               printk(KERN_ERR "sc520_freq: error: failed to remap memory\n");
+               return -ENOMEM;
+       }
+
+       return cpufreq_register_driver(&sc520_freq_driver);
+}
+
+
+static void __exit sc520_freq_exit(void)
+{
+       cpufreq_unregister_driver(&sc520_freq_driver);
+       iounmap(cpuctl);
+}
+
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Sean Young <sean@mess.org>");
+MODULE_DESCRIPTION("cpufreq driver for AMD's Elan sc520 CPU");
+
+module_init(sc520_freq_init);
+module_exit(sc520_freq_exit);
+
diff -urN linux/arch/i386/kernel/cpu/cpufreq/Kconfig 
linux/arch/i386/kernel/cpu/cpufreq/Kconfig
--- linux/arch/i386/kernel/cpu/cpufreq/Kconfig  2005/03/18 17:36:49     1.14
+++ linux/arch/i386/kernel/cpu/cpufreq/Kconfig  2005/06/07 13:45:26     1.15
@@ -23,7 +23,7 @@
          If in doubt, say N.
 
 config ELAN_CPUFREQ
-       tristate "AMD Elan"
+       tristate "AMD Elan SC400 and SC410"
        select CPU_FREQ_TABLE
        depends on X86_ELAN
        ---help---
@@ -38,6 +38,18 @@
 
          If in doubt, say N.
 
+config SC520_CPUFREQ
+       tristate "AMD Elan SC520"
+       select CPU_FREQ_TABLE
+       depends on X86_ELAN
+       ---help---
+         This adds the CPUFreq driver for AMD Elan SC520 processor.
+
+         For details, take a look at <file:Documentation/cpu-freq/>.
+
+         If in doubt, say N.
+
+
 config X86_POWERNOW_K6
        tristate "AMD Mobile K6-2/K6-3 PowerNow!"
        select CPU_FREQ_TABLE
diff -urN linux/arch/i386/kernel/cpu/cpufreq/Makefile 
linux/arch/i386/kernel/cpu/cpufreq/Makefile
--- linux/arch/i386/kernel/cpu/cpufreq/Makefile 2004/11/15 11:49:16     1.11
+++ linux/arch/i386/kernel/cpu/cpufreq/Makefile 2005/06/07 13:45:26     1.12
@@ -3,6 +3,7 @@
 obj-$(CONFIG_X86_POWERNOW_K8)          += powernow-k8.o
 obj-$(CONFIG_X86_LONGHAUL)             += longhaul.o
 obj-$(CONFIG_ELAN_CPUFREQ)             += elanfreq.o
+obj-$(CONFIG_SC520_CPUFREQ)            += sc520_freq.o
 obj-$(CONFIG_X86_LONGRUN)              += longrun.o  
 obj-$(CONFIG_X86_GX_SUSPMOD)           += gx-suspmod.o
 obj-$(CONFIG_X86_SPEEDSTEP_ICH)                += speedstep-ich.o
diff -urN linux/arch/i386/kernel/cpu/cpufreq/longhaul.c 
linux/arch/i386/kernel/cpu/cpufreq/longhaul.c
--- linux/arch/i386/kernel/cpu/cpufreq/longhaul.c       2004/11/15 11:49:16     
1.26
+++ linux/arch/i386/kernel/cpu/cpufreq/longhaul.c       2005/06/07 13:45:26     
1.27
@@ -29,6 +29,7 @@
 #include <linux/cpufreq.h>
 #include <linux/slab.h>
 #include <linux/string.h>
+#include <linux/pci.h>
 
 #include <asm/msr.h>
 #include <asm/timex.h>
@@ -119,7 +120,13 @@
 static void do_powersaver(union msr_longhaul *longhaul,
                        unsigned int clock_ratio_index)
 {
+       struct pci_dev *dev;
+       unsigned long flags;
+       unsigned int tmp_mask;
        int version;
+       int i;
+       u16 pci_cmd;
+       u16 cmd_state[64];
 
        switch (cpu_model) {
        case CPU_EZRA_T:
@@ -137,17 +144,58 @@
        longhaul->bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
        longhaul->bits.EnableSoftBusRatio = 1;
        longhaul->bits.RevisionKey = 0;
-       local_irq_disable();
-       wrmsrl(MSR_VIA_LONGHAUL, longhaul->val);
+
+       preempt_disable();
+       local_irq_save(flags);
+
+       /*
+        * get current pci bus master state for all devices
+        * and clear bus master bit
+        */
+       dev = NULL;
+       i = 0;
+       do {
+               dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
+               if (dev != NULL) {
+                       pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
+                       cmd_state[i++] = pci_cmd;
+                       pci_cmd &= ~PCI_COMMAND_MASTER;
+                       pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
+               }
+       } while (dev != NULL);
+
+       tmp_mask=inb(0x21);     /* works on C3. save mask. */
+       outb(0xFE,0x21);        /* TMR0 only */
+       outb(0xFF,0x80);        /* delay */
+
        local_irq_enable();
+
+       __hlt();
+       wrmsrl(MSR_VIA_LONGHAUL, longhaul->val);
        __hlt();
 
+       local_irq_disable();
+
+       outb(tmp_mask,0x21);    /* restore mask */
+
+       /* restore pci bus master state for all devices */
+       dev = NULL;
+       i = 0;
+       do {
+               dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
+               if (dev != NULL) {
+                       pci_cmd = cmd_state[i++];
+                       pci_write_config_byte(dev, PCI_COMMAND, pci_cmd);
+               }
+       } while (dev != NULL);
+       local_irq_restore(flags);
+       preempt_enable();
+
+       /* disable bus ratio bit */
        rdmsrl(MSR_VIA_LONGHAUL, longhaul->val);
        longhaul->bits.EnableSoftBusRatio = 0;
        longhaul->bits.RevisionKey = version;
-       local_irq_disable();
        wrmsrl(MSR_VIA_LONGHAUL, longhaul->val);
-       local_irq_enable();
 }
 
 /**
@@ -578,7 +626,7 @@
                longhaul_setup_voltagescaling();
 
        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
-       policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+       policy->cpuinfo.transition_latency = 200000;    /* nsec */
        policy->cur = calc_speed(longhaul_get_cpu_mult());
 
        ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
diff -urN linux/arch/i386/kernel/cpu/cpufreq/powernow-k7.c 
linux/arch/i386/kernel/cpu/cpufreq/powernow-k7.c
--- linux/arch/i386/kernel/cpu/cpufreq/powernow-k7.c    2005/01/25 04:27:55     
1.23
+++ linux/arch/i386/kernel/cpu/cpufreq/powernow-k7.c    2005/06/07 13:45:26     
1.24
@@ -23,6 +23,7 @@
 #include <linux/dmi.h>
 
 #include <asm/msr.h>
+#include <asm/timer.h>
 #include <asm/timex.h>
 #include <asm/io.h>
 #include <asm/system.h>
@@ -586,13 +587,17 @@
 
        rdmsrl (MSR_K7_FID_VID_STATUS, fidvidstatus.val);
 
-       /* A K7 with powernow technology is set to max frequency by BIOS */
-       fsb = (10 * cpu_khz) / fid_codes[fidvidstatus.bits.MFID];
+       /* recalibrate cpu_khz */
+       result = recalibrate_cpu_khz();
+       if (result)
+               return result;
+
+       fsb = (10 * cpu_khz) / fid_codes[fidvidstatus.bits.CFID];
        if (!fsb) {
                printk(KERN_WARNING PFX "can not determine bus frequency\n");
                return -EINVAL;
        }
-       dprintk("FSB: %3d.%03d MHz\n", fsb/1000, fsb%1000);
+       dprintk("FSB: %3dMHz\n", fsb/1000);
 
        if (dmi_check_system(powernow_dmi_table) || acpi_force) {
                printk (KERN_INFO PFX "PSB/PST known to be broken.  Trying ACPI 
instead\n");
diff -urN linux/arch/i386/kernel/cpu/cpufreq/powernow-k8.c 
linux/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
--- linux/arch/i386/kernel/cpu/cpufreq/powernow-k8.c    2005/01/25 04:27:55     
1.14
+++ linux/arch/i386/kernel/cpu/cpufreq/powernow-k8.c    2005/06/07 13:45:26     
1.15
@@ -4,7 +4,7 @@
  *  GNU general public license version 2. See "COPYING" or
  *  http://www.gnu.org/licenses/gpl.html
  *
- *  Support : paul.devriendt@amd.com
+ *  Support : mark.langsdorf@amd.com
  *
  *  Based on the powernow-k7.c module written by Dave Jones.
  *  (C) 2003 Dave Jones <davej@codemonkey.org.uk> on behalf of SuSE Labs
@@ -15,12 +15,13 @@
  *
  *  Valuable input gratefully received from Dave Jones, Pavel Machek,
  *  Dominik Brodowski, and others.
+ *  Originally developed by Paul Devriendt.
  *  Processor information obtained from Chapter 9 (Power and Thermal 
Management)
  *  of the "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
  *  Opteron Processors" available for download from www.amd.com
  *
  *  Tables for specific CPUs can be infrerred from
- *     
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30430.pdf
+ *     
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30430.pdf
  */
 
 #include <linux/kernel.h>
@@ -30,6 +31,7 @@
 #include <linux/cpufreq.h>
 #include <linux/slab.h>
 #include <linux/string.h>
+#include <linux/cpumask.h>
 
 #include <asm/msr.h>
 #include <asm/io.h>
@@ -42,7 +44,7 @@
 
 #define PFX "powernow-k8: "
 #define BFX PFX "BIOS error: "
-#define VERSION "version 1.00.09e"
+#define VERSION "version 1.40.2"
 #include "powernow-k8.h"
 
 /* serialize freq changes  */
@@ -50,6 +52,10 @@
 
 static struct powernow_k8_data *powernow_data[NR_CPUS];
 
+#ifndef CONFIG_SMP
+static cpumask_t cpu_core_map[1];
+#endif
+
 /* Return a frequency in MHz, given an input fid */
 static u32 find_freq_from_fid(u32 fid)
 {
@@ -274,11 +280,18 @@
 {
        u32 rvosteps = data->rvo;
        u32 savefid = data->currfid;
+       u32 maxvid, lo;
 
        dprintk("ph1 (cpu%d): start, currfid 0x%x, currvid 0x%x, reqvid 0x%x, 
rvo 0x%x\n",
                smp_processor_id(),
                data->currfid, data->currvid, reqvid, data->rvo);
 
+       rdmsr(MSR_FIDVID_STATUS, lo, maxvid);
+       maxvid = 0x1f & (maxvid >> 16);
+       dprintk("ph1 maxvid=0x%x\n", maxvid);
+       if (reqvid < maxvid) /* lower numbers are higher voltages */
+               reqvid = maxvid;
+
        while (data->currvid > reqvid) {
                dprintk("ph1: curr 0x%x, req vid 0x%x\n",
                        data->currvid, reqvid);
@@ -286,8 +299,8 @@
                        return 1;
        }
 
-       while ((rvosteps > 0)  && ((data->rvo + data->currvid) > reqvid)) {
-               if (data->currvid == 0) {
+       while ((rvosteps > 0) && ((data->rvo + data->currvid) > reqvid)) {
+               if (data->currvid == maxvid) {
                        rvosteps = 0;
                } else {
                        dprintk("ph1: changing vid for rvo, req 0x%x\n",
@@ -671,7 +684,7 @@
         * BIOS and Kernel Developer's Guide, which is available on
         * www.amd.com
         */
-       printk(KERN_ERR PFX "BIOS error - no PSB\n");
+       printk(KERN_INFO PFX "BIOS error - no PSB or ACPI _PSS objects\n");
        return -ENODEV;
 }
 
@@ -695,7 +708,7 @@
        struct cpufreq_frequency_table *powernow_table;
 
        if (acpi_processor_register_performance(&data->acpi_data, data->cpu)) {
-               dprintk("register performance failed\n");
+               dprintk("register performance failed: bad ACPI data\n");
                return -EIO;
        }
 
@@ -746,22 +759,23 @@
                        continue;
                }
 
-               if (fid < HI_FID_TABLE_BOTTOM) {
-                       if (cntlofreq) {
-                               /* if both entries are the same, ignore this
-                                * one... 
-                                */
-                               if ((powernow_table[i].frequency != 
powernow_table[cntlofreq].frequency) ||
-                                   (powernow_table[i].index != 
powernow_table[cntlofreq].index)) {
-                                       printk(KERN_ERR PFX "Too many lo freq 
table entries\n");
-                                       goto err_out_mem;
-                               }
-                               
-                               dprintk("double low frequency table entry, 
ignoring it.\n");
-                               powernow_table[i].frequency = 
CPUFREQ_ENTRY_INVALID;
-                               continue;
-                       } else
-                               cntlofreq = i;
+               /* verify only 1 entry from the lo frequency table */
+               if (fid < HI_FID_TABLE_BOTTOM) {
+                       if (cntlofreq) {
+                               /* if both entries are the same, ignore this
+                                * one... 
+                                */
+                               if ((powernow_table[i].frequency != 
powernow_table[cntlofreq].frequency) ||
+                                   (powernow_table[i].index != 
powernow_table[cntlofreq].index)) {
+                                       printk(KERN_ERR PFX "Too many lo freq 
table entries\n");
+                                       goto err_out_mem;
+                               }
+
+                               dprintk("double low frequency table entry, 
ignoring it.\n");
+                               powernow_table[i].frequency = 
CPUFREQ_ENTRY_INVALID;
+                               continue;
+                       } else
+                               cntlofreq = i;
                }
 
                if (powernow_table[i].frequency != 
(data->acpi_data.states[i].core_frequency * 1000)) {
@@ -816,7 +830,7 @@
 {
        u32 fid;
        u32 vid;
-       int res;
+       int res, i;
        struct cpufreq_freqs freqs;
 
        dprintk("cpu %d transition to index %u\n", smp_processor_id(), index);
@@ -841,7 +855,8 @@
        }
 
        if ((fid < HI_FID_TABLE_BOTTOM) && (data->currfid < 
HI_FID_TABLE_BOTTOM)) {
-               printk("ignoring illegal change in lo freq table-%x to 0x%x\n",
+               printk(KERN_ERR PFX
+                      "ignoring illegal change in lo freq table-%x to 0x%x\n",
                       data->currfid, fid);
                return 1;
        }
@@ -850,18 +865,20 @@
                smp_processor_id(), fid, vid);
 
        freqs.cpu = data->cpu;
-
        freqs.old = find_khz_freq_from_fid(data->currfid);
        freqs.new = find_khz_freq_from_fid(fid);
-       cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+       for_each_cpu_mask(i, cpu_core_map[data->cpu]) {
+               freqs.cpu = i;
+               cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+       }
 
-       down(&fidvid_sem);
        res = transition_fid_vid(data, fid, vid);
-       up(&fidvid_sem);
 
        freqs.new = find_khz_freq_from_fid(data->currfid);
-       cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
+       for_each_cpu_mask(i, cpu_core_map[data->cpu]) {
+               freqs.cpu = i;
+               cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+        }
        return res;
 }
 
@@ -874,6 +891,7 @@
        u32 checkvid = data->currvid;
        unsigned int newstate;
        int ret = -EIO;
+       int i;
 
        /* only run on specific CPU from here on */
        oldmask = current->cpus_allowed;
@@ -902,22 +920,41 @@
                data->currfid, data->currvid);
 
        if ((checkvid != data->currvid) || (checkfid != data->currfid)) {
-               printk(KERN_ERR PFX
-                      "error - out of sync, fid 0x%x 0x%x, vid 0x%x 0x%x\n",
-                      checkfid, data->currfid, checkvid, data->currvid);
+               printk(KERN_INFO PFX
+                       "error - out of sync, fix 0x%x 0x%x, vid 0x%x 0x%x\n",
+                       checkfid, data->currfid, checkvid, data->currvid);
        }
 
        if (cpufreq_frequency_table_target(pol, data->powernow_table, targfreq, 
relation, &newstate))
                goto err_out;
 
+       down(&fidvid_sem);
+
+       for_each_cpu_mask(i, cpu_core_map[pol->cpu]) {
+               /* make sure the sibling is initialized */
+               if (!powernow_data[i]) {
+                        ret = 0;
+                        up(&fidvid_sem);
+                        goto err_out;
+                }
+       }
+
        powernow_k8_acpi_pst_values(data, newstate);
 
        if (transition_frequency(data, newstate)) {
                printk(KERN_ERR PFX "transition frequency failed\n");
                ret = 1;
+               up(&fidvid_sem);
                goto err_out;
        }
 
+       /* Update all the fid/vids of our siblings */
+       for_each_cpu_mask(i, cpu_core_map[pol->cpu]) {
+               powernow_data[i]->currvid = data->currvid;
+               powernow_data[i]->currfid = data->currfid;
+       }       
+       up(&fidvid_sem);
+
        pol->cur = find_khz_freq_from_fid(data->currfid);
        ret = 0;
 
@@ -962,7 +999,7 @@
                 */
 
                if ((num_online_cpus() != 1) || (num_possible_cpus() != 1)) {
-                       printk(KERN_INFO PFX "MP systems not supported by PSB 
BIOS structure\n");
+                       printk(KERN_ERR PFX "MP systems not supported by PSB 
BIOS structure\n");
                        kfree(data);
                        return -ENODEV;
                }
@@ -1003,6 +1040,7 @@
        schedule();
 
        pol->governor = CPUFREQ_DEFAULT_GOVERNOR;
+       pol->cpus = cpu_core_map[pol->cpu];
 
        /* Take a crude guess here. 
         * That guess was in microseconds, so multiply with 1000 */
@@ -1069,7 +1107,7 @@
                return 0;
        }
        preempt_disable();
-
+       
        if (query_current_values_with_pending_wait(data))
                goto out;
 
@@ -1127,9 +1165,10 @@
        cpufreq_unregister_driver(&cpufreq_amd64_driver);
 }
 
-MODULE_AUTHOR("Paul Devriendt <paul.devriendt@amd.com>");
+MODULE_AUTHOR("Paul Devriendt <paul.devriendt@amd.com> and Mark Langsdorf 
<mark.langsdorf@amd.com.");
 MODULE_DESCRIPTION("AMD Athlon 64 and Opteron processor frequency driver.");
 MODULE_LICENSE("GPL");
 
 late_initcall(powernowk8_init);
 module_exit(powernowk8_exit);
+
diff -urN linux/arch/i386/kernel/cpu/cpufreq/powernow-k8.h 
linux/arch/i386/kernel/cpu/cpufreq/powernow-k8.h
--- linux/arch/i386/kernel/cpu/cpufreq/powernow-k8.h    2005/01/25 04:27:55     
1.8
+++ linux/arch/i386/kernel/cpu/cpufreq/powernow-k8.h    2005/06/07 13:45:26     
1.9
@@ -174,3 +174,18 @@
 static int core_frequency_transition(struct powernow_k8_data *data, u32 
reqfid);
 
 static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, 
unsigned int index);
+
+#ifndef for_each_cpu_mask
+#define for_each_cpu_mask(i,mask) for (i=0;i<1;i++)
+#endif
+                                                                               
 
+#ifdef CONFIG_SMP
+static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[])
+{
+}
+#else
+static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[])
+{
+       cpu_set(0, cpu_sharedcore_mask[0]);
+}
+#endif
diff -urN linux/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c 
linux/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
--- linux/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c     2005/01/25 
04:27:55     1.14
+++ linux/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c     2005/06/07 
13:45:26     1.15
@@ -54,6 +54,8 @@
        CPU_DOTHAN_A1,
        CPU_DOTHAN_A2,
        CPU_DOTHAN_B0,
+       CPU_MP4HT_D0,
+       CPU_MP4HT_E0,
 };
 
 static const struct cpu_id cpu_ids[] = {
@@ -61,6 +63,8 @@
        [CPU_DOTHAN_A1] = { 6, 13, 1 },
        [CPU_DOTHAN_A2] = { 6, 13, 2 },
        [CPU_DOTHAN_B0] = { 6, 13, 6 },
+       [CPU_MP4HT_D0]  = {15,  3, 4 },
+       [CPU_MP4HT_E0]  = {15,  4, 1 },
 };
 #define N_IDS  (sizeof(cpu_ids)/sizeof(cpu_ids[0]))
 
@@ -226,6 +230,8 @@
        { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
        { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
        { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
+       { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
+       { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
 
        { NULL, }
 };
diff -urN linux/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c 
linux/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c
--- linux/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c  2005/02/13 20:16:15     
1.9
+++ linux/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c  2005/06/07 13:45:26     
1.10
@@ -336,7 +336,7 @@
        if (!prev_speed)
                return -EIO;
 
-       dprintk("previous seped is %u\n", prev_speed);
+       dprintk("previous speed is %u\n", prev_speed);
        
        local_irq_save(flags);
 
@@ -348,7 +348,7 @@
                goto out;
        }
 
-       dprintk("low seped is %u\n", *low_speed);
+       dprintk("low speed is %u\n", *low_speed);
 
        /* switch to high state */
        set_state(SPEEDSTEP_HIGH);
@@ -358,7 +358,7 @@
                goto out;
        }
 
-       dprintk("high seped is %u\n", *high_speed);
+       dprintk("high speed is %u\n", *high_speed);
 
        if (*low_speed == *high_speed) {
                ret = -ENODEV;
diff -urN linux/arch/i386/kernel/cpu/cpufreq/speedstep-smi.c 
linux/arch/i386/kernel/cpu/cpufreq/speedstep-smi.c
--- linux/arch/i386/kernel/cpu/cpufreq/speedstep-smi.c  2004/11/15 11:49:16     
1.9
+++ linux/arch/i386/kernel/cpu/cpufreq/speedstep-smi.c  2005/06/07 13:45:26     
1.10
@@ -357,6 +357,9 @@
        case SPEEDSTEP_PROCESSOR_PIII_C:
        case SPEEDSTEP_PROCESSOR_PIII_C_EARLY:
                break;
+       case SPEEDSTEP_PROCESSOR_P4M:
+               printk(KERN_INFO "speedstep-smi: you're trying to use this 
cpufreq driver on a Pentium 4-based CPU. Most likely it will not work.\n");
+               break;
        default:
                speedstep_processor = 0;
        }
diff -urN linux/arch/i386/kernel/timers/common.c 
linux/arch/i386/kernel/timers/common.c
--- linux/arch/i386/kernel/timers/common.c      2004/10/25 20:44:13     1.3
+++ linux/arch/i386/kernel/timers/common.c      2005/06/07 13:45:26     1.4
@@ -6,6 +6,7 @@
 #include <linux/timex.h>
 #include <linux/errno.h>
 #include <linux/jiffies.h>
+#include <linux/module.h>
 
 #include <asm/io.h>
 #include <asm/timer.h>
@@ -24,7 +25,7 @@
 
 #define CALIBRATE_TIME (5 * 1000020/HZ)
 
-unsigned long __init calibrate_tsc(void)
+unsigned long calibrate_tsc(void)
 {
        mach_prepare_counter();
 
@@ -139,7 +140,7 @@
 #endif
 
 /* calculate cpu_khz */
-void __init init_cpu_khz(void)
+void init_cpu_khz(void)
 {
        if (cpu_has_tsc) {
                unsigned long tsc_quotient = calibrate_tsc();
@@ -158,3 +159,4 @@
                }
        }
 }
+
diff -urN linux/arch/i386/kernel/timers/timer_tsc.c 
linux/arch/i386/kernel/timers/timer_tsc.c
--- linux/arch/i386/kernel/timers/timer_tsc.c   2005/05/19 12:08:09     1.28
+++ linux/arch/i386/kernel/timers/timer_tsc.c   2005/06/07 13:45:26     1.29
@@ -320,6 +320,26 @@
 static inline void cpufreq_delayed_get(void) { return; }
 #endif 
 
+int recalibrate_cpu_khz(void)
+{
+#ifndef CONFIG_SMP
+       unsigned long cpu_khz_old = cpu_khz;
+
+       if (cpu_has_tsc) {
+               init_cpu_khz();
+               cpu_data[0].loops_per_jiffy =
+                   cpufreq_scale(cpu_data[0].loops_per_jiffy,
+                                 cpu_khz_old,
+                                 cpu_khz);
+               return 0;
+       } else
+               return -ENODEV;
+#else
+       return -ENODEV;
+#endif
+}
+EXPORT_SYMBOL(recalibrate_cpu_khz);
+
 static void mark_offset_tsc(void)
 {
        unsigned long lost,delay;
diff -urN linux/arch/i386/pci/irq.c linux/arch/i386/pci/irq.c
--- linux/arch/i386/pci/irq.c   2005/05/19 12:08:09     1.25
+++ linux/arch/i386/pci/irq.c   2005/06/07 13:45:26     1.26
@@ -1029,7 +1029,6 @@
 static int pirq_enable_irq(struct pci_dev *dev)
 {
        u8 pin;
-       extern int via_interrupt_line_quirk;
        struct pci_dev *temp_dev;
 
        pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
@@ -1084,10 +1083,6 @@
                printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of 
device %s.%s\n",
                       'A' + pin, pci_name(dev), msg);
        }
-       /* VIA bridges use interrupt line for apic/pci steering across
-          the V-Link */
-       else if (via_interrupt_line_quirk)
-               pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq & 15);
        return 0;
 }
 
diff -urN linux/arch/ia64/ia32/sys_ia32.c linux/arch/ia64/ia32/sys_ia32.c
--- linux/arch/ia64/ia32/sys_ia32.c     2005/03/18 17:36:51     1.73
+++ linux/arch/ia64/ia32/sys_ia32.c     2005/06/07 13:45:26     1.74
@@ -2427,7 +2427,7 @@
 {
        struct epoll_event *events64 = NULL;
        mm_segment_t old_fs = get_fs();
-       int error, numevents, size;
+       int numevents, size;
        int evt_idx;
        int do_free_pages = 0;
 
diff -urN linux/arch/ia64/kernel/entry.S linux/arch/ia64/kernel/entry.S
--- linux/arch/ia64/kernel/entry.S      2005/05/19 12:08:09     1.56
+++ linux/arch/ia64/kernel/entry.S      2005/06/07 13:45:26     1.57
@@ -1182,7 +1182,7 @@
        ;;
 (pNonSys) mov out2=0                           // out2==0 => not a syscall
        .fframe 16
-       .spillpsp ar.unat, 16                   // (note that offset is 
relative to psp+0x10!)
+       .spillsp ar.unat, 16
        st8 [sp]=r9,-16                         // allocate space for ar.unat 
and save it
        st8 [out1]=loc1,-8                      // save ar.pfs, out1=&sigscratch
        .body
@@ -1208,7 +1208,7 @@
        adds out2=8,sp                          // out2=&sigscratch->ar_pfs
        ;;
        .fframe 16
-       .spillpsp ar.unat, 16                   // (note that offset is 
relative to psp+0x10!)
+       .spillsp ar.unat, 16
        st8 [sp]=r9,-16                         // allocate space for ar.unat 
and save it
        st8 [out2]=loc1,-8                      // save ar.pfs, out2=&sigscratch
        .body
diff -urN linux/arch/ia64/kernel/mca.c linux/arch/ia64/kernel/mca.c
--- linux/arch/ia64/kernel/mca.c        2005/02/13 20:16:16     1.42
+++ linux/arch/ia64/kernel/mca.c        2005/06/07 13:45:26     1.43
@@ -1103,8 +1103,6 @@
        return IRQ_HANDLED;
 }
 
-#endif /* CONFIG_ACPI */
-
 /*
  *  ia64_mca_cpe_poll
  *
@@ -1122,6 +1120,8 @@
        platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, 
IA64_IPI_DM_INT, 0);
 }
 
+#endif /* CONFIG_ACPI */
+
 /*
  * C portion of the OS INIT handler
  *
@@ -1390,8 +1390,7 @@
        register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
 
 #ifdef CONFIG_ACPI
-       /* Setup the CPEI/P vector and handler */
-       cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
+       /* Setup the CPEI/P handler */
        register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
 #endif
 
@@ -1436,6 +1435,7 @@
 
 #ifdef CONFIG_ACPI
        /* Setup the CPEI/P vector and handler */
+       cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
        init_timer(&cpe_poll_timer);
        cpe_poll_timer.function = ia64_mca_cpe_poll;
 
diff -urN linux/arch/ia64/kernel/minstate.h linux/arch/ia64/kernel/minstate.h
--- linux/arch/ia64/kernel/minstate.h   2005/04/08 18:57:54     1.15
+++ linux/arch/ia64/kernel/minstate.h   2005/06/07 13:45:26     1.16
@@ -41,7 +41,7 @@
 (pKStk) addl r3=THIS_CPU(ia64_mca_data),r3;;                                   
                \
 (pKStk) ld8 r3 = [r3];;                                                        
                        \
 (pKStk) addl r3=IA64_MCA_CPU_INIT_STACK_OFFSET,r3;;                            
                \
-(pKStk) addl sp=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r3;                          
                \
+(pKStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r3;                          
                \
 (pUStk)        mov ar.rsc=0;           /* set enforced lazy mode, pl 0, 
little-endian, loadrs=0 */     \
 (pUStk)        addl r22=IA64_RBS_OFFSET,r1;            /* compute base of 
register backing store */    \
        ;;                                                                      
                \
@@ -50,7 +50,6 @@
 (pUStk)        mov r23=ar.bspstore;                            /* save 
ar.bspstore */                  \
 (pUStk)        dep r22=-1,r22,61,3;                    /* compute kernel 
virtual addr of RBS */        \
        ;;                                                                      
                \
-(pKStk) addl r1=-IA64_PT_REGS_SIZE,r1;         /* if in kernel mode, use sp 
(r12) */           \
 (pUStk)        mov ar.bspstore=r22;                    /* switch to kernel RBS 
*/                      \
        ;;                                                                      
                \
 (pUStk)        mov r18=ar.bsp;                                                 
                        \
diff -urN linux/arch/ia64/kernel/perfmon.c linux/arch/ia64/kernel/perfmon.c
--- linux/arch/ia64/kernel/perfmon.c    2005/05/19 12:08:09     1.51
+++ linux/arch/ia64/kernel/perfmon.c    2005/06/07 13:45:26     1.52
@@ -11,7 +11,7 @@
  * Version Perfmon-2.x is a rewrite of perfmon-1.x
  * by Stephane Eranian, Hewlett Packard Co.
  *
- * Copyright (C) 1999-2003, 2005  Hewlett Packard Co
+ * Copyright (C) 1999-2005  Hewlett Packard Co
  *               Stephane Eranian <eranian@hpl.hp.com>
  *               David Mosberger-Tang <davidm@hpl.hp.com>
  *
@@ -497,6 +497,9 @@
 static pfm_stats_t             pfm_stats[NR_CPUS];
 static pfm_session_t           pfm_sessions;   /* global sessions information 
*/
 
+static spinlock_t pfm_alt_install_check = SPIN_LOCK_UNLOCKED;
+static pfm_intr_handler_desc_t  *pfm_alt_intr_handler;
+
 static struct proc_dir_entry   *perfmon_dir;
 static pfm_uuid_t              pfm_null_uuid = {0,};
 
@@ -606,6 +609,7 @@
 DEFINE_PER_CPU(struct task_struct *, pmu_owner);
 DEFINE_PER_CPU(pfm_context_t  *, pmu_ctx);
 DEFINE_PER_CPU(unsigned long, pmu_activation_number);
+EXPORT_PER_CPU_SYMBOL_GPL(pfm_syst_info);
 
 
 /* forward declaration */
@@ -1325,7 +1329,7 @@
 error_conflict:
        DPRINT(("system wide not possible, conflicting session [%d] on CPU%d\n",
                pfm_sessions.pfs_sys_session[cpu]->pid,
-               smp_processor_id()));
+               cpu));
 abort:
        UNLOCK_PFS(flags);
 
@@ -5555,26 +5559,32 @@
        int ret;
 
        this_cpu = get_cpu();
-       min      = pfm_stats[this_cpu].pfm_ovfl_intr_cycles_min;
-       max      = pfm_stats[this_cpu].pfm_ovfl_intr_cycles_max;
+       if (likely(!pfm_alt_intr_handler)) {
+               min = pfm_stats[this_cpu].pfm_ovfl_intr_cycles_min;
+               max = pfm_stats[this_cpu].pfm_ovfl_intr_cycles_max;
 
-       start_cycles = ia64_get_itc();
+               start_cycles = ia64_get_itc();
 
-       ret = pfm_do_interrupt_handler(irq, arg, regs);
+               ret = pfm_do_interrupt_handler(irq, arg, regs);
 
-       total_cycles = ia64_get_itc();
+               total_cycles = ia64_get_itc();
 
-       /*
-        * don't measure spurious interrupts
-        */
-       if (likely(ret == 0)) {
-               total_cycles -= start_cycles;
+               /*
+                * don't measure spurious interrupts
+                */
+               if (likely(ret == 0)) {
+                       total_cycles -= start_cycles;
 
-               if (total_cycles < min) 
pfm_stats[this_cpu].pfm_ovfl_intr_cycles_min = total_cycles;
-               if (total_cycles > max) 
pfm_stats[this_cpu].pfm_ovfl_intr_cycles_max = total_cycles;
+                       if (total_cycles < min) 
pfm_stats[this_cpu].pfm_ovfl_intr_cycles_min = total_cycles;
+                       if (total_cycles > max) 
pfm_stats[this_cpu].pfm_ovfl_intr_cycles_max = total_cycles;
 
-               pfm_stats[this_cpu].pfm_ovfl_intr_cycles += total_cycles;
+                       pfm_stats[this_cpu].pfm_ovfl_intr_cycles += 
total_cycles;
+               }
+       }
+       else {
+               (*pfm_alt_intr_handler->handler)(irq, arg, regs);
        }
+
        put_cpu_no_resched();
        return IRQ_HANDLED;
 }
@@ -6425,6 +6435,141 @@
        .name    = "perfmon"
 };
 
+static void
+pfm_alt_save_pmu_state(void *data)
+{
+       struct pt_regs *regs;
+
+       regs = ia64_task_regs(current);
+
+       DPRINT(("called\n"));
+
+       /*
+        * should not be necessary but
+        * let's take not risk
+        */
+       pfm_clear_psr_up();
+       pfm_clear_psr_pp();
+       ia64_psr(regs)->pp = 0;
+
+       /*
+        * This call is required
+        * May cause a spurious interrupt on some processors
+        */
+       pfm_freeze_pmu();
+
+       ia64_srlz_d();
+}
+
+void
+pfm_alt_restore_pmu_state(void *data)
+{
+       struct pt_regs *regs;
+
+       regs = ia64_task_regs(current);
+
+       DPRINT(("called\n"));
+
+       /*
+        * put PMU back in state expected
+        * by perfmon
+        */
+       pfm_clear_psr_up();
+       pfm_clear_psr_pp();
+       ia64_psr(regs)->pp = 0;
+
+       /*
+        * perfmon runs with PMU unfrozen at all times
+        */
+       pfm_unfreeze_pmu();
+
+       ia64_srlz_d();
+}
+
+int
+pfm_install_alt_pmu_interrupt(pfm_intr_handler_desc_t *hdl)
+{
+       int ret, i;
+       int reserve_cpu;
+
+       /* some sanity checks */
+       if (hdl == NULL || hdl->handler == NULL) return -EINVAL;
+
+       /* do the easy test first */
+       if (pfm_alt_intr_handler) return -EBUSY;
+
+       /* one at a time in the install or remove, just fail the others */
+       if (!spin_trylock(&pfm_alt_install_check)) {
+               return -EBUSY;
+       }
+
+       /* reserve our session */
+       for_each_online_cpu(reserve_cpu) {
+               ret = pfm_reserve_session(NULL, 1, reserve_cpu);
+               if (ret) goto cleanup_reserve;
+       }
+
+       /* save the current system wide pmu states */
+       ret = on_each_cpu(pfm_alt_save_pmu_state, NULL, 0, 1);
+       if (ret) {
+               DPRINT(("on_each_cpu() failed: %d\n", ret));
+               goto cleanup_reserve;
+       }
+
+       /* officially change to the alternate interrupt handler */
+       pfm_alt_intr_handler = hdl;
+
+       spin_unlock(&pfm_alt_install_check);
+
+       return 0;
+
+cleanup_reserve:
+       for_each_online_cpu(i) {
+               /* don't unreserve more than we reserved */
+               if (i >= reserve_cpu) break;
+
+               pfm_unreserve_session(NULL, 1, i);
+       }
+
+       spin_unlock(&pfm_alt_install_check);
+
+       return ret;
+}
+EXPORT_SYMBOL_GPL(pfm_install_alt_pmu_interrupt);
+
+int
+pfm_remove_alt_pmu_interrupt(pfm_intr_handler_desc_t *hdl)
+{
+       int i;
+       int ret;
+
+       if (hdl == NULL) return -EINVAL;
+
+       /* cannot remove someone else's handler! */
+       if (pfm_alt_intr_handler != hdl) return -EINVAL;
+
+       /* one at a time in the install or remove, just fail the others */
+       if (!spin_trylock(&pfm_alt_install_check)) {
+               return -EBUSY;
+       }
+
+       pfm_alt_intr_handler = NULL;
+
+       ret = on_each_cpu(pfm_alt_restore_pmu_state, NULL, 0, 1);
+       if (ret) {
+               DPRINT(("on_each_cpu() failed: %d\n", ret));
+       }
+
+       for_each_online_cpu(i) {
+               pfm_unreserve_session(NULL, 1, i);
+       }
+
+       spin_unlock(&pfm_alt_install_check);
+
+       return 0;
+}
+EXPORT_SYMBOL_GPL(pfm_remove_alt_pmu_interrupt);
+
 /*
  * perfmon initialization routine, called from the initcall() table
  */
diff -urN linux/arch/ia64/kernel/ptrace.c linux/arch/ia64/kernel/ptrace.c
--- linux/arch/ia64/kernel/ptrace.c     2005/05/19 12:08:09     1.37
+++ linux/arch/ia64/kernel/ptrace.c     2005/06/07 13:45:26     1.38
@@ -692,16 +692,30 @@
                        unsigned long cfm)
 {
        struct unw_frame_info info, prev_info;
-       unsigned long ip, pr;
+       unsigned long ip, sp, pr;
 
        unw_init_from_blocked_task(&info, child);
        while (1) {
                prev_info = info;
                if (unw_unwind(&info) < 0)
                        return;
-               if (unw_get_rp(&info, &ip) < 0)
+
+               unw_get_sp(&info, &sp);
+               if ((long)((unsigned long)child + IA64_STK_OFFSET - sp)
+                   < IA64_PT_REGS_SIZE) {
+                       dprintk("ptrace.%s: ran off the top of the kernel "
+                               "stack\n", __FUNCTION__);
+                       return;
+               }
+               if (unw_get_pr (&prev_info, &pr) < 0) {
+                       unw_get_rp(&prev_info, &ip);
+                       dprintk("ptrace.%s: failed to read "
+                               "predicate register (ip=0x%lx)\n",
+                               __FUNCTION__, ip);
                        return;
-               if (ip < FIXADDR_USER_END)
+               }
+               if (unw_is_intr_frame(&info)
+                   && (pr & (1UL << PRED_USER_STACK)))
                        break;
        }
 
diff -urN linux/arch/ia64/kernel/smpboot.c linux/arch/ia64/kernel/smpboot.c
--- linux/arch/ia64/kernel/smpboot.c    2005/05/19 12:08:09     1.40
+++ linux/arch/ia64/kernel/smpboot.c    2005/06/07 13:45:27     1.41
@@ -624,7 +624,7 @@
        __u16   thread_id;
        __u16   proc_fixed_addr;
        __u8    valid;
-}mt_info[NR_CPUS] __devinit;
+} mt_info[NR_CPUS] __devinitdata;
 
 #ifdef CONFIG_HOTPLUG_CPU
 static inline void
diff -urN linux/arch/ia64/kernel/sys_ia64.c linux/arch/ia64/kernel/sys_ia64.c
--- linux/arch/ia64/kernel/sys_ia64.c   2005/05/19 12:08:09     1.32
+++ linux/arch/ia64/kernel/sys_ia64.c   2005/06/07 13:45:27     1.33
@@ -182,13 +182,6 @@
                }
        }
 
-       /*
-        * A zero mmap always succeeds in Linux, independent of whether or not 
the
-        * remaining arguments are valid.
-        */
-       if (len == 0)
-               goto out;
-
        /* Careful about overflows.. */
        len = PAGE_ALIGN(len);
        if (!len || len > TASK_SIZE) {
diff -urN linux/arch/ia64/sn/kernel/setup.c linux/arch/ia64/sn/kernel/setup.c
--- linux/arch/ia64/sn/kernel/setup.c   2005/05/19 12:08:10     1.32
+++ linux/arch/ia64/sn/kernel/setup.c   2005/06/07 13:45:27     1.33
@@ -271,6 +271,8 @@
        int major = sn_sal_rev_major(), minor = sn_sal_rev_minor();
        extern void sn_cpu_init(void);
 
+       ia64_sn_plat_set_error_handling_features();
+
        /*
         * If the generic code has enabled vga console support - lets
         * get rid of it again. This is a kludge for the fact that ACPI
diff -urN linux/arch/m68knommu/kernel/process.c 
linux/arch/m68knommu/kernel/process.c
--- linux/arch/m68knommu/kernel/process.c       2005/01/13 14:05:28     1.8
+++ linux/arch/m68knommu/kernel/process.c       2005/06/07 13:45:27     1.9
@@ -45,11 +45,13 @@
  */
 void default_idle(void)
 {
-       while(1) {
-               if (need_resched())
-                       __asm__("stop #0x2000" : : : "cc");
-               schedule();
+       local_irq_disable();
+       while (!need_resched()) {
+               /* This stop will re-enable interrupts */
+               __asm__("stop #0x2000" : : : "cc");
+               local_irq_disable();
        }
+       local_irq_enable();
 }
 
 void (*idle)(void) = default_idle;
@@ -63,7 +65,12 @@
 void cpu_idle(void)
 {
        /* endless idle loop with no priority at all */
-       idle();
+       while (1) {
+               idle();
+               preempt_enable_no_resched();
+               schedule();
+               preempt_disable();
+       }
 }
 
 void machine_restart(char * __unused)
diff -urN linux/arch/mips/defconfig linux/arch/mips/defconfig
--- linux/arch/mips/defconfig   2005/06/03 13:08:04     1.291
+++ linux/arch/mips/defconfig   2005/06/07 13:45:27     1.292
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:17 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:35:47 2005
 #
 CONFIG_MIPS=y
 
@@ -625,7 +625,6 @@
 CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/atlas_defconfig 
linux/arch/mips/configs/atlas_defconfig
--- linux/arch/mips/configs/atlas_defconfig     2005/06/03 13:08:04     1.55
+++ linux/arch/mips/configs/atlas_defconfig     2005/06/07 13:45:27     1.56
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:20 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:35:50 2005
 #
 CONFIG_MIPS=y
 
@@ -715,6 +715,7 @@
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -793,7 +794,6 @@
 CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIO_RAW=y
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/capcella_defconfig 
linux/arch/mips/configs/capcella_defconfig
--- linux/arch/mips/configs/capcella_defconfig  2005/06/03 13:08:04     1.55
+++ linux/arch/mips/configs/capcella_defconfig  2005/06/07 13:45:27     1.56
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:22 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:35:51 2005
 #
 CONFIG_MIPS=y
 
@@ -402,6 +402,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -476,7 +477,6 @@
 CONFIG_SERIO_LIBPS2=m
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/cobalt_defconfig 
linux/arch/mips/configs/cobalt_defconfig
--- linux/arch/mips/configs/cobalt_defconfig    2005/06/03 13:08:04     1.52
+++ linux/arch/mips/configs/cobalt_defconfig    2005/06/07 13:45:27     1.53
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:24 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:35:52 2005
 #
 CONFIG_MIPS=y
 
@@ -387,6 +387,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -461,7 +462,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=y
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/db1000_defconfig 
linux/arch/mips/configs/db1000_defconfig
--- linux/arch/mips/configs/db1000_defconfig    2005/06/03 13:08:04     1.58
+++ linux/arch/mips/configs/db1000_defconfig    2005/06/07 13:45:27     1.59
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:27 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:35:53 2005
 #
 CONFIG_MIPS=y
 
@@ -520,7 +520,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/db1100_defconfig 
linux/arch/mips/configs/db1100_defconfig
--- linux/arch/mips/configs/db1100_defconfig    2005/06/03 13:08:04     1.57
+++ linux/arch/mips/configs/db1100_defconfig    2005/06/07 13:45:27     1.58
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:29 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:35:54 2005
 #
 CONFIG_MIPS=y
 
@@ -497,7 +497,6 @@
 CONFIG_SERIO_LIBPS2=m
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/db1500_defconfig 
linux/arch/mips/configs/db1500_defconfig
--- linux/arch/mips/configs/db1500_defconfig    2005/06/03 13:08:04     1.60
+++ linux/arch/mips/configs/db1500_defconfig    2005/06/07 13:45:27     1.61
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:32 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:35:55 2005
 #
 CONFIG_MIPS=y
 
@@ -113,6 +113,7 @@
 CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
 CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
 CONFIG_SOC_AU1500=y
 CONFIG_SOC_AU1X00=y
@@ -497,6 +498,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -583,7 +585,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/db1550_defconfig 
linux/arch/mips/configs/db1550_defconfig
--- linux/arch/mips/configs/db1550_defconfig    2005/06/03 13:08:04     1.35
+++ linux/arch/mips/configs/db1550_defconfig    2005/06/07 13:45:27     1.36
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:34 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:35:57 2005
 #
 CONFIG_MIPS=y
 
@@ -528,6 +528,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -622,7 +623,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/ddb5476_defconfig 
linux/arch/mips/configs/ddb5476_defconfig
--- linux/arch/mips/configs/ddb5476_defconfig   2005/06/03 13:08:04     1.52
+++ linux/arch/mips/configs/ddb5476_defconfig   2005/06/07 13:45:27     1.53
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:37 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:35:58 2005
 #
 CONFIG_MIPS=y
 
@@ -404,6 +404,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -478,7 +479,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=y
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/ddb5477_defconfig 
linux/arch/mips/configs/ddb5477_defconfig
--- linux/arch/mips/configs/ddb5477_defconfig   2005/06/03 13:08:04     1.52
+++ linux/arch/mips/configs/ddb5477_defconfig   2005/06/07 13:45:27     1.53
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:39 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:00 2005
 #
 CONFIG_MIPS=y
 
@@ -388,6 +388,7 @@
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -462,7 +463,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=y
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/decstation_defconfig 
linux/arch/mips/configs/decstation_defconfig
--- linux/arch/mips/configs/decstation_defconfig        2005/06/03 13:08:04     
1.53
+++ linux/arch/mips/configs/decstation_defconfig        2005/06/07 13:45:27     
1.54
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:42 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:01 2005
 #
 CONFIG_MIPS=y
 
@@ -436,7 +436,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/e55_defconfig 
linux/arch/mips/configs/e55_defconfig
--- linux/arch/mips/configs/e55_defconfig       2005/06/03 13:08:04     1.54
+++ linux/arch/mips/configs/e55_defconfig       2005/06/07 13:45:27     1.55
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:44 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:01 2005
 #
 CONFIG_MIPS=y
 
@@ -452,7 +452,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/ev64120_defconfig 
linux/arch/mips/configs/ev64120_defconfig
--- linux/arch/mips/configs/ev64120_defconfig   2005/06/03 13:08:04     1.51
+++ linux/arch/mips/configs/ev64120_defconfig   2005/06/07 13:45:27     1.52
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:46 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:03 2005
 #
 CONFIG_MIPS=y
 
@@ -375,6 +375,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -456,7 +457,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/ev96100_defconfig 
linux/arch/mips/configs/ev96100_defconfig
--- linux/arch/mips/configs/ev96100_defconfig   2005/06/03 13:08:04     1.52
+++ linux/arch/mips/configs/ev96100_defconfig   2005/06/07 13:45:27     1.53
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:48 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:03 2005
 #
 CONFIG_MIPS=y
 
@@ -412,7 +412,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/ip22_defconfig 
linux/arch/mips/configs/ip22_defconfig
--- linux/arch/mips/configs/ip22_defconfig      2005/06/03 13:08:04     1.61
+++ linux/arch/mips/configs/ip22_defconfig      2005/06/07 13:45:27     1.62
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:50 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:04 2005
 #
 CONFIG_MIPS=y
 
@@ -625,7 +625,6 @@
 CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/ip27_defconfig 
linux/arch/mips/configs/ip27_defconfig
--- linux/arch/mips/configs/ip27_defconfig      2005/06/03 13:08:04     1.65
+++ linux/arch/mips/configs/ip27_defconfig      2005/06/07 13:45:27     1.66
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:53 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:06 2005
 #
 CONFIG_MIPS=y
 
@@ -499,6 +499,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -553,7 +554,6 @@
 CONFIG_SERIO_LIBPS2=m
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/ip32_defconfig 
linux/arch/mips/configs/ip32_defconfig
--- linux/arch/mips/configs/ip32_defconfig      2005/06/03 13:08:04     1.55
+++ linux/arch/mips/configs/ip32_defconfig      2005/06/07 13:45:27     1.56
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:55 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:07 2005
 #
 CONFIG_MIPS=y
 
@@ -443,6 +443,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -519,7 +520,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=y
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/it8172_defconfig 
linux/arch/mips/configs/it8172_defconfig
--- linux/arch/mips/configs/it8172_defconfig    2005/06/03 13:08:04     1.51
+++ linux/arch/mips/configs/it8172_defconfig    2005/06/07 13:45:27     1.52
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:57 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:08 2005
 #
 CONFIG_MIPS=y
 
@@ -500,7 +500,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/ivr_defconfig 
linux/arch/mips/configs/ivr_defconfig
--- linux/arch/mips/configs/ivr_defconfig       2005/06/03 13:08:04     1.51
+++ linux/arch/mips/configs/ivr_defconfig       2005/06/07 13:45:27     1.52
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:55:59 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:09 2005
 #
 CONFIG_MIPS=y
 
@@ -395,6 +395,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -469,7 +470,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/jaguar-atx_defconfig 
linux/arch/mips/configs/jaguar-atx_defconfig
--- linux/arch/mips/configs/jaguar-atx_defconfig        2005/06/03 13:08:04     
1.56
+++ linux/arch/mips/configs/jaguar-atx_defconfig        2005/06/07 13:45:27     
1.57
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:56:01 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:11 2005
 #
 CONFIG_MIPS=y
 
@@ -388,6 +388,7 @@
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 CONFIG_MV643XX_ETH=y
 CONFIG_MV643XX_ETH_0=y
 CONFIG_MV643XX_ETH_1=y
@@ -437,7 +438,6 @@
 #
 # CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/jmr3927_defconfig 
linux/arch/mips/configs/jmr3927_defconfig
--- linux/arch/mips/configs/jmr3927_defconfig   2005/06/03 13:08:04     1.52
+++ linux/arch/mips/configs/jmr3927_defconfig   2005/06/07 13:45:27     1.53
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:56:03 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:12 2005
 #
 CONFIG_MIPS=y
 
@@ -364,6 +364,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -438,7 +439,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=y
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/lasat200_defconfig 
linux/arch/mips/configs/lasat200_defconfig
--- linux/arch/mips/configs/lasat200_defconfig  2005/06/03 13:08:04     1.52
+++ linux/arch/mips/configs/lasat200_defconfig  2005/06/07 13:45:27     1.53
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:56:05 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:13 2005
 #
 CONFIG_MIPS=y
 
@@ -495,6 +495,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -569,7 +570,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/malta_defconfig 
linux/arch/mips/configs/malta_defconfig
--- linux/arch/mips/configs/malta_defconfig     2005/06/03 13:08:04     1.54
+++ linux/arch/mips/configs/malta_defconfig     2005/06/07 13:45:27     1.55
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:56:08 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:15 2005
 #
 CONFIG_MIPS=y
 
@@ -746,6 +746,7 @@
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -821,7 +822,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/mpc30x_defconfig 
linux/arch/mips/configs/mpc30x_defconfig
--- linux/arch/mips/configs/mpc30x_defconfig    2005/06/03 13:08:04     1.56
+++ linux/arch/mips/configs/mpc30x_defconfig    2005/06/07 13:45:27     1.57
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:56:10 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:16 2005
 #
 CONFIG_MIPS=y
 
@@ -380,6 +380,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -454,7 +455,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/ocelot_3_defconfig 
linux/arch/mips/configs/ocelot_3_defconfig
--- linux/arch/mips/configs/ocelot_3_defconfig  2005/06/03 13:08:04     1.24
+++ linux/arch/mips/configs/ocelot_3_defconfig  2005/06/07 13:45:27     1.25
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:56:13 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:18 2005
 #
 CONFIG_MIPS=y
 
@@ -489,6 +489,7 @@
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 CONFIG_MV643XX_ETH=y
 CONFIG_MV643XX_ETH_0=y
 CONFIG_MV643XX_ETH_1=y
@@ -572,7 +573,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/ocelot_c_defconfig 
linux/arch/mips/configs/ocelot_c_defconfig
--- linux/arch/mips/configs/ocelot_c_defconfig  2005/06/03 13:08:04     1.50
+++ linux/arch/mips/configs/ocelot_c_defconfig  2005/06/07 13:45:27     1.51
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:56:15 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:19 2005
 #
 CONFIG_MIPS=y
 
@@ -373,6 +373,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 # CONFIG_MV643XX_ETH is not set
 
 #
@@ -448,7 +449,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=y
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/ocelot_defconfig 
linux/arch/mips/configs/ocelot_defconfig
--- linux/arch/mips/configs/ocelot_defconfig    2005/06/03 13:08:04     1.52
+++ linux/arch/mips/configs/ocelot_defconfig    2005/06/07 13:45:27     1.53
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:56:16 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:20 2005
 #
 CONFIG_MIPS=y
 
@@ -408,7 +408,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=y
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/ocelot_g_defconfig 
linux/arch/mips/configs/ocelot_g_defconfig
--- linux/arch/mips/configs/ocelot_g_defconfig  2005/06/03 13:08:04     1.45
+++ linux/arch/mips/configs/ocelot_g_defconfig  2005/06/07 13:45:27     1.46
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 13:56:19 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:23 2005
 #
 CONFIG_MIPS=y
 
@@ -377,6 +377,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -451,7 +452,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=y
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/pb1100_defconfig 
linux/arch/mips/configs/pb1100_defconfig
--- linux/arch/mips/configs/pb1100_defconfig    2005/06/03 13:08:04     1.54
+++ linux/arch/mips/configs/pb1100_defconfig    2005/06/07 13:45:27     1.55
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 14:00:26 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:24 2005
 #
 CONFIG_MIPS=y
 
@@ -514,7 +514,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/pb1500_defconfig 
linux/arch/mips/configs/pb1500_defconfig
--- linux/arch/mips/configs/pb1500_defconfig    2005/06/03 13:08:05     1.60
+++ linux/arch/mips/configs/pb1500_defconfig    2005/06/07 13:45:27     1.61
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 14:00:28 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:27 2005
 #
 CONFIG_MIPS=y
 
@@ -524,6 +524,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -618,7 +619,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/pb1550_defconfig 
linux/arch/mips/configs/pb1550_defconfig
--- linux/arch/mips/configs/pb1550_defconfig    2005/06/03 13:08:05     1.50
+++ linux/arch/mips/configs/pb1550_defconfig    2005/06/07 13:45:27     1.51
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 14:00:31 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:32 2005
 #
 CONFIG_MIPS=y
 
@@ -524,6 +524,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -610,7 +611,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/rm200_defconfig 
linux/arch/mips/configs/rm200_defconfig
--- linux/arch/mips/configs/rm200_defconfig     2005/06/03 13:08:05     1.61
+++ linux/arch/mips/configs/rm200_defconfig     2005/06/07 13:45:27     1.62
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 14:00:34 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:39 2005
 #
 CONFIG_MIPS=y
 
@@ -757,6 +757,7 @@
 # CONFIG_SK98LIN is not set
 CONFIG_VIA_VELOCITY=m
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -845,7 +846,6 @@
 CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/sb1250-swarm_defconfig 
linux/arch/mips/configs/sb1250-swarm_defconfig
--- linux/arch/mips/configs/sb1250-swarm_defconfig      2005/06/03 13:08:05     
1.58
+++ linux/arch/mips/configs/sb1250-swarm_defconfig      2005/06/07 13:45:27     
1.59
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 14:00:36 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:40 2005
 #
 CONFIG_MIPS=y
 
@@ -424,6 +424,7 @@
 CONFIG_NET_SB1250_MAC=y
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -477,7 +478,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/sead_defconfig 
linux/arch/mips/configs/sead_defconfig
--- linux/arch/mips/configs/sead_defconfig      2005/06/03 13:08:05     1.50
+++ linux/arch/mips/configs/sead_defconfig      2005/06/07 13:45:27     1.51
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 14:00:38 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:41 2005
 #
 CONFIG_MIPS=y
 
@@ -273,7 +273,6 @@
 #
 # CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/tb0226_defconfig 
linux/arch/mips/configs/tb0226_defconfig
--- linux/arch/mips/configs/tb0226_defconfig    2005/06/03 13:08:05     1.54
+++ linux/arch/mips/configs/tb0226_defconfig    2005/06/07 13:45:27     1.55
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 14:00:40 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:42 2005
 #
 CONFIG_MIPS=y
 
@@ -478,7 +478,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/tb0229_defconfig 
linux/arch/mips/configs/tb0229_defconfig
--- linux/arch/mips/configs/tb0229_defconfig    2005/06/03 13:08:05     1.57
+++ linux/arch/mips/configs/tb0229_defconfig    2005/06/07 13:45:27     1.58
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 14:00:42 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:45 2005
 #
 CONFIG_MIPS=y
 
@@ -408,6 +408,7 @@
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -492,7 +493,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/workpad_defconfig 
linux/arch/mips/configs/workpad_defconfig
--- linux/arch/mips/configs/workpad_defconfig   2005/06/03 13:08:05     1.54
+++ linux/arch/mips/configs/workpad_defconfig   2005/06/07 13:45:27     1.55
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 14:00:44 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:45 2005
 #
 CONFIG_MIPS=y
 
@@ -452,7 +452,6 @@
 # CONFIG_SERIO_LIBPS2 is not set
 CONFIG_SERIO_RAW=m
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/mips/configs/yosemite_defconfig 
linux/arch/mips/configs/yosemite_defconfig
--- linux/arch/mips/configs/yosemite_defconfig  2005/06/03 13:08:05     1.56
+++ linux/arch/mips/configs/yosemite_defconfig  2005/06/07 13:45:27     1.57
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5
-# Fri Jun  3 14:00:46 2005
+# Linux kernel version: 2.6.12-rc6
+# Tue Jun  7 13:36:46 2005
 #
 CONFIG_MIPS=y
 
@@ -374,6 +374,7 @@
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
 CONFIG_TITAN_GE=y
 
 #
@@ -420,7 +421,6 @@
 #
 # CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
diff -urN linux/arch/ppc/Kconfig linux/arch/ppc/Kconfig
--- linux/arch/ppc/Kconfig      2005/05/19 12:08:12     1.48
+++ linux/arch/ppc/Kconfig      2005/06/07 13:45:28     1.49
@@ -1143,12 +1143,12 @@
 
 config PCI_8260
        bool
-       depends on PCI && 8260 && !8272
+       depends on PCI && 8260
        default y
 
 config 8260_PCI9
        bool "  Enable workaround for MPC826x erratum PCI 9"
-       depends on PCI_8260
+       depends on PCI_8260 && !ADS8272
        default y
 
 choice
diff -urN linux/arch/ppc/boot/images/Makefile 
linux/arch/ppc/boot/images/Makefile
--- linux/arch/ppc/boot/images/Makefile 2005/05/19 12:08:13     1.11
+++ linux/arch/ppc/boot/images/Makefile 2005/06/07 13:45:28     1.12
@@ -22,7 +22,8 @@
 $(obj)/uImage: $(obj)/vmlinux.gz
        $(Q)rm -f $@
        $(call if_changed,uimage)
-       @echo '  Image: $@' $(if $(wildcard $@),'is ready','not made')
+       @echo -n '  Image: $@ '
+       @if [ -f $@ ]; then echo 'is ready' ; else echo 'not made'; fi
 
 # Files generated that shall be removed upon make clean
 clean-files    := sImage vmapus vmlinux* miboot* zImage* uImage
diff -urN linux/arch/ppc/configs/mpc8555_cds_defconfig 
linux/arch/ppc/configs/mpc8555_cds_defconfig
--- linux/arch/ppc/configs/mpc8555_cds_defconfig        2005/02/07 02:54:35     
1.1
+++ linux/arch/ppc/configs/mpc8555_cds_defconfig        2005/06/07 13:45:28     
1.2
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11-rc1
-# Thu Jan 20 01:25:35 2005
+# Linux kernel version: 2.6.12-rc4
+# Tue May 17 11:56:01 2005
 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -11,6 +11,7 @@
 CONFIG_PPC=y
 CONFIG_PPC32=y
 CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
 
 #
 # Code maturity level options
@@ -18,6 +19,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
 
 #
 # General setup
@@ -29,12 +31,14 @@
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
 # CONFIG_AUDIT is not set
-CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_HOTPLUG is not set
 CONFIG_KOBJECT_UEVENT=y
 # CONFIG_IKCONFIG is not set
 CONFIG_EMBEDDED=y
 # CONFIG_KALLSYMS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 # CONFIG_EPOLL is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -44,6 +48,7 @@
 CONFIG_CC_ALIGN_LOOPS=0
 CONFIG_CC_ALIGN_JUMPS=0
 # CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
 
 #
 # Loadable module support
@@ -62,10 +67,12 @@
 CONFIG_E500=y
 CONFIG_BOOKE=y
 CONFIG_FSL_BOOKE=y
+# CONFIG_PHYS_64BIT is not set
 CONFIG_SPE=y
 CONFIG_MATH_EMULATION=y
 # CONFIG_CPU_FREQ is not set
 CONFIG_PPC_GEN550=y
+# CONFIG_PM is not set
 CONFIG_85xx=y
 CONFIG_PPC_INDIRECT_PCI_BE=y
 
@@ -76,6 +83,7 @@
 CONFIG_MPC8555_CDS=y
 # CONFIG_MPC8560_ADS is not set
 # CONFIG_SBC8560 is not set
+# CONFIG_STX_GP3 is not set
 CONFIG_MPC8555=y
 CONFIG_85xx_PCI2=y
 
@@ -90,6 +98,7 @@
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_CMDLINE_BOOL is not set
+CONFIG_ISA_DMA_API=y
 
 #
 # Bus options
@@ -105,10 +114,6 @@
 # CONFIG_PCCARD is not set
 
 #
-# PC-card bridges
-#
-
-#
 # Advanced setup
 #
 # CONFIG_ADVANCED_OPTIONS is not set
@@ -180,7 +185,59 @@
 #
 # ATA/ATAPI/MFM/RLL support
 #
-# CONFIG_IDE is not set
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+CONFIG_BLK_DEV_IDEPCI=y
+CONFIG_IDEPCI_SHARE_IRQ=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+CONFIG_IDEDMA_PCI_AUTO=y
+# CONFIG_IDEDMA_ONLYDISK is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+CONFIG_BLK_DEV_VIA82CXXX=y
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_IVB is not set
+CONFIG_IDEDMA_AUTO=y
+# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
@@ -220,7 +277,6 @@
 #
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
@@ -370,14 +426,6 @@
 # CONFIG_INPUT_EVBUG is not set
 
 #
-# Input I/O drivers
-#
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-# CONFIG_SERIO is not set
-# CONFIG_SERIO_I8042 is not set
-
-#
 # Input Device Drivers
 #
 # CONFIG_INPUT_KEYBOARD is not set
@@ -387,6 +435,13 @@
 # CONFIG_INPUT_MISC is not set
 
 #
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+
+#
 # Character devices
 #
 # CONFIG_VT is not set
@@ -406,6 +461,7 @@
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_CPM is not set
+# CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
@@ -434,6 +490,11 @@
 # CONFIG_RAW_DRIVER is not set
 
 #
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
 # I2C support
 #
 CONFIG_I2C=y
@@ -456,11 +517,11 @@
 # CONFIG_I2C_AMD8111 is not set
 # CONFIG_I2C_I801 is not set
 # CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
 # CONFIG_I2C_ISA is not set
 CONFIG_I2C_MPC=y
 # CONFIG_I2C_NFORCE2 is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_PIIX4 is not set
 # CONFIG_I2C_PROSAVAGE is not set
 # CONFIG_I2C_SAVAGE4 is not set
 # CONFIG_SCx200_ACB is not set
@@ -483,7 +544,9 @@
 # CONFIG_SENSORS_ASB100 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
 # CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
 # CONFIG_SENSORS_LM63 is not set
 # CONFIG_SENSORS_LM75 is not set
@@ -494,9 +557,11 @@
 # CONFIG_SENSORS_LM85 is not set
 # CONFIG_SENSORS_LM87 is not set
 # CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SIS5595 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_W83781D is not set
@@ -506,10 +571,12 @@
 #
 # Other I2C Chip support
 #
+# CONFIG_SENSORS_DS1337 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_M41T00 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -538,7 +605,6 @@
 # Graphics support
 #
 # CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
@@ -548,13 +614,9 @@
 #
 # USB support
 #
-# CONFIG_USB is not set
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; 
see USB_STORAGE Help for more information
-#
+# CONFIG_USB is not set
 
 #
 # USB Gadget Support
@@ -585,6 +647,10 @@
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -646,7 +712,6 @@
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
-# CONFIG_EXPORTFS is not set
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -698,7 +763,9 @@
 #
 # Kernel hacking
 #
+# CONFIG_PRINTK_TIME is not set
 # CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_KGDB_CONSOLE is not set
 # CONFIG_SERIAL_TEXT_DEBUG is not set
 
diff -urN linux/arch/ppc/kernel/head_fsl_booke.S 
linux/arch/ppc/kernel/head_fsl_booke.S
--- linux/arch/ppc/kernel/head_fsl_booke.S      2005/05/19 12:08:13     1.3
+++ linux/arch/ppc/kernel/head_fsl_booke.S      2005/06/07 13:45:28     1.4
@@ -232,7 +232,8 @@
        tlbwe
 
 /* 7. Jump to KERNELBASE mapping */
-       li      r7,0
+       lis     r7,MSR_KERNEL@h
+       ori     r7,r7,MSR_KERNEL@l
        bl      1f                      /* Find our address */
 1:     mflr    r9
        rlwimi  r6,r9,0,20,31
@@ -293,6 +294,18 @@
        mtspr   SPRN_HID0, r2
 #endif
 
+#if !defined(CONFIG_BDI_SWITCH)
+       /*
+        * The Abatron BDI JTAG debugger does not tolerate others
+        * mucking with the debug registers.
+        */
+       lis     r2,DBCR0_IDM@h
+       mtspr   SPRN_DBCR0,r2
+       /* clear any residual debug events */
+       li      r2,-1
+       mtspr   SPRN_DBSR,r2
+#endif
+
        /*
         * This is where the main kernel code starts.
         */
diff -urN linux/arch/ppc/kernel/traps.c linux/arch/ppc/kernel/traps.c
--- linux/arch/ppc/kernel/traps.c       2005/05/19 12:08:13     1.53
+++ linux/arch/ppc/kernel/traps.c       2005/06/07 13:45:28     1.54
@@ -408,12 +408,7 @@
 
        /* Early out if we are an invalid form of lswx */
        if ((instword & INST_STRING_MASK) == INST_LSWX)
-               if ((rA >= rT) || (NB_RB >= rT) || (rT == rA) || (rT == NB_RB))
-                       return -EINVAL;
-
-       /* Early out if we are an invalid form of lswi */
-       if ((instword & INST_STRING_MASK) == INST_LSWI)
-               if ((rA >= rT) || (rT == rA))
+               if ((rT == rA) || (rT == NB_RB))
                        return -EINVAL;
 
        EA = (rA == 0) ? 0 : regs->gpr[rA];
diff -urN linux/arch/ppc/platforms/pmac_cpufreq.c 
linux/arch/ppc/platforms/pmac_cpufreq.c
--- linux/arch/ppc/platforms/pmac_cpufreq.c     2005/04/29 11:15:03     1.18
+++ linux/arch/ppc/platforms/pmac_cpufreq.c     2005/06/07 13:45:28     1.19
@@ -85,14 +85,11 @@
 static int has_cpu_l2lve;
 
 
-#define PMAC_CPU_LOW_SPEED     1
-#define PMAC_CPU_HIGH_SPEED    0
-
 /* There are only two frequency states for each processor. Values
  * are in kHz for the time being.
  */
-#define CPUFREQ_HIGH                  PMAC_CPU_HIGH_SPEED
-#define CPUFREQ_LOW                   PMAC_CPU_LOW_SPEED
+#define CPUFREQ_HIGH                  0
+#define CPUFREQ_LOW                   1
 
 static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
        {CPUFREQ_HIGH,          0},
@@ -100,6 +97,11 @@
        {0,                     CPUFREQ_TABLE_END},
 };
 
+static struct freq_attr* pmac_cpu_freqs_attr[] = {
+       &cpufreq_freq_attr_scaling_available_freqs,
+       NULL,
+};
+
 static inline void local_delay(unsigned long ms)
 {
        if (no_schedule)
@@ -269,6 +271,8 @@
 #ifdef DEBUG_FREQ
        printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
 #endif
+       pmu_suspend();
+
        /* Disable all interrupt sources on openpic */
        pic_prio = openpic_get_priority();
        openpic_set_priority(0xf);
@@ -343,6 +347,8 @@
        debug_calc_bogomips();
 #endif
 
+       pmu_resume();
+
        preempt_enable();
 
        return 0;
@@ -355,7 +361,7 @@
        static unsigned long prev_l3cr;
 
        freqs.old = cur_freq;
-       freqs.new = (speed_mode == PMAC_CPU_HIGH_SPEED) ? hi_freq : low_freq;
+       freqs.new = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
        freqs.cpu = smp_processor_id();
 
        if (freqs.old == freqs.new)
@@ -363,7 +369,7 @@
 
        if (notify)
                cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-       if (speed_mode == PMAC_CPU_LOW_SPEED &&
+       if (speed_mode == CPUFREQ_LOW &&
            cpu_has_feature(CPU_FTR_L3CR)) {
                l3cr = _get_L3CR();
                if (l3cr & L3CR_L3E) {
@@ -371,8 +377,8 @@
                        _set_L3CR(0);
                }
        }
-       set_speed_proc(speed_mode == PMAC_CPU_LOW_SPEED);
-       if (speed_mode == PMAC_CPU_HIGH_SPEED &&
+       set_speed_proc(speed_mode == CPUFREQ_LOW);
+       if (speed_mode == CPUFREQ_HIGH &&
            cpu_has_feature(CPU_FTR_L3CR)) {
                l3cr = _get_L3CR();
                if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr)
@@ -380,7 +386,7 @@
        }
        if (notify)
                cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-       cur_freq = (speed_mode == PMAC_CPU_HIGH_SPEED) ? hi_freq : low_freq;
+       cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
 
        return 0;
 }
@@ -423,7 +429,8 @@
        policy->cpuinfo.transition_latency      = CPUFREQ_ETERNAL;
        policy->cur = cur_freq;
 
-       return cpufreq_frequency_table_cpuinfo(policy, &pmac_cpu_freqs[0]);
+       cpufreq_frequency_table_get_attr(pmac_cpu_freqs, policy->cpu);
+       return cpufreq_frequency_table_cpuinfo(policy, pmac_cpu_freqs);
 }
 
 static u32 __pmac read_gpio(struct device_node *np)
@@ -457,7 +464,7 @@
        no_schedule = 1;
        sleep_freq = cur_freq;
        if (cur_freq == low_freq)
-               do_set_cpu_speed(PMAC_CPU_HIGH_SPEED, 0);
+               do_set_cpu_speed(CPUFREQ_HIGH, 0);
        return 0;
 }
 
@@ -473,8 +480,8 @@
         * is that we force a switch to whatever it was, which is
         * probably high speed due to our suspend() routine
         */
-       do_set_cpu_speed(sleep_freq == low_freq ? PMAC_CPU_LOW_SPEED
-                        : PMAC_CPU_HIGH_SPEED, 0);
+       do_set_cpu_speed(sleep_freq == low_freq ?
+                        CPUFREQ_LOW : CPUFREQ_HIGH, 0);
 
        no_schedule = 0;
        return 0;
@@ -488,6 +495,7 @@
        .suspend        = pmac_cpufreq_suspend,
        .resume         = pmac_cpufreq_resume,
        .flags          = CPUFREQ_PM_NO_WARN,
+       .attr           = pmac_cpu_freqs_attr,
        .name           = "powermac",
        .owner          = THIS_MODULE,
 };
diff -urN linux/arch/ppc/platforms/pq2ads.h linux/arch/ppc/platforms/pq2ads.h
--- linux/arch/ppc/platforms/pq2ads.h   2005/01/25 04:28:02     1.4
+++ linux/arch/ppc/platforms/pq2ads.h   2005/06/07 13:45:28     1.5
@@ -49,10 +49,10 @@
 /* PCI interrupt controller */
 #define PCI_INT_STAT_REG       0xF8200000
 #define PCI_INT_MASK_REG       0xF8200004
-#define PIRQA                  (NR_SIU_INTS + 0)
-#define PIRQB                  (NR_SIU_INTS + 1)
-#define PIRQC                  (NR_SIU_INTS + 2)
-#define PIRQD                  (NR_SIU_INTS + 3)
+#define PIRQA                  (NR_CPM_INTS + 0)
+#define PIRQB                  (NR_CPM_INTS + 1)
+#define PIRQC                  (NR_CPM_INTS + 2)
+#define PIRQD                  (NR_CPM_INTS + 3)
 
 /*
  * PCI memory map definitions for MPC8266ADS-PCI.
@@ -68,28 +68,23 @@
  *     0x00000000-0x1FFFFFFF   0x00000000-0x1FFFFFFF   MPC8266 local memory
  */
 
-/* window for a PCI master to access MPC8266 memory */
-#define PCI_SLV_MEM_LOCAL      0x00000000      /* Local base */
-#define PCI_SLV_MEM_BUS                0x00000000      /* PCI base */
-
-/* window for the processor to access PCI memory with prefetching */
-#define PCI_MSTR_MEM_LOCAL     0x80000000      /* Local base */
-#define PCI_MSTR_MEM_BUS       0x80000000      /* PCI base   */
-#define PCI_MSTR_MEM_SIZE      0x20000000      /* 512MB */
-
-/* window for the processor to access PCI memory without prefetching */
-#define PCI_MSTR_MEMIO_LOCAL   0xA0000000      /* Local base */
-#define PCI_MSTR_MEMIO_BUS     0xA0000000      /* PCI base   */
-#define PCI_MSTR_MEMIO_SIZE    0x20000000      /* 512MB */
-
-/* window for the processor to access PCI I/O */
-#define PCI_MSTR_IO_LOCAL      0xF4000000      /* Local base */
-#define PCI_MSTR_IO_BUS         0x00000000     /* PCI base   */
-#define PCI_MSTR_IO_SIZE        0x04000000     /* 64MB */
-
-#define _IO_BASE               PCI_MSTR_IO_LOCAL
-#define _ISA_MEM_BASE          PCI_MSTR_MEMIO_LOCAL
-#define PCI_DRAM_OFFSET                PCI_SLV_MEM_BUS
+/* All the other PCI memory map definitions reside at syslib/m82xx_pci.h
+   Here we should redefine what is unique for this board */
+#define M82xx_PCI_SLAVE_MEM_LOCAL      0x00000000      /* Local base */
+#define M82xx_PCI_SLAVE_MEM_BUS                0x00000000      /* PCI base */
+#define M82xx_PCI_SLAVE_MEM_SIZE       0x10000000      /* 256 Mb */
+
+#define M82xx_PCI_SLAVE_SEC_WND_SIZE   ~(0x40000000 - 1U)      /* 2 x 512Mb  */
+#define M82xx_PCI_SLAVE_SEC_WND_BASE   0x80000000              /* PCI Memory 
base */
+
+#if defined(CONFIG_ADS8272)
+#define PCI_INT_TO_SIU         SIU_INT_IRQ2
+#elif defined(CONFIG_PQ2FADS)
+#define PCI_INT_TO_SIU         SIU_INT_IRQ6
+#else
+#warning PCI Bridge will be without interrupts support
+#endif
+
 #endif /* CONFIG_PCI */
 
 #endif /* __MACH_ADS8260_DEFS */
diff -urN linux/arch/ppc/platforms/83xx/mpc834x_sys.c 
linux/arch/ppc/platforms/83xx/mpc834x_sys.c
--- linux/arch/ppc/platforms/83xx/mpc834x_sys.c 2005/04/08 18:58:01     1.2
+++ linux/arch/ppc/platforms/83xx/mpc834x_sys.c 2005/06/07 13:45:29     1.3
@@ -127,7 +127,6 @@
 {
        /* we steal the lowest ioremap addr for virt space */
        io_block_mapping(VIRT_IMMRBAR, immrbar, 1024*1024, _PAGE_IO);
-       io_block_mapping(BCSR_VIRT_ADDR, BCSR_PHYS_ADDR, BCSR_SIZE, _PAGE_IO);
 }
 
 int
diff -urN linux/arch/ppc/platforms/83xx/mpc834x_sys.h 
linux/arch/ppc/platforms/83xx/mpc834x_sys.h
--- linux/arch/ppc/platforms/83xx/mpc834x_sys.h 2005/03/18 17:36:57     1.1
+++ linux/arch/ppc/platforms/83xx/mpc834x_sys.h 2005/06/07 13:45:29     1.2
@@ -26,9 +26,14 @@
 #define VIRT_IMMRBAR           ((uint)0xfe000000)
 
 #define BCSR_PHYS_ADDR         ((uint)0xf8000000)
-#define BCSR_VIRT_ADDR         ((uint)0xfe100000)
 #define BCSR_SIZE              ((uint)(32 * 1024))
 
+#define BCSR_MISC_REG2_OFF     0x07
+#define BCSR_MISC_REG2_PORESET 0x01
+
+#define BCSR_MISC_REG3_OFF     0x08
+#define BCSR_MISC_REG3_CNFLOCK 0x80
+
 #ifdef CONFIG_PCI
 /* PCI interrupt controller */
 #define PIRQA        MPC83xx_IRQ_IRQ4
diff -urN linux/arch/ppc/platforms/85xx/mpc8540_ads.c 
linux/arch/ppc/platforms/85xx/mpc8540_ads.c
--- linux/arch/ppc/platforms/85xx/mpc8540_ads.c 2005/04/08 18:58:01     1.7
+++ linux/arch/ppc/platforms/85xx/mpc8540_ads.c 2005/06/07 13:45:29     1.8
@@ -210,6 +210,9 @@
 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
        ppc_md.progress = gen550_progress;
 #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
+#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
+       ppc_md.early_serial_map = mpc85xx_early_serial_map;
+#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
 
        if (ppc_md.progress)
                ppc_md.progress("mpc8540ads_init(): exit", 0);
diff -urN linux/arch/ppc/platforms/85xx/mpc85xx_cds_common.c 
linux/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
--- linux/arch/ppc/platforms/85xx/mpc85xx_cds_common.c  2005/04/08 18:58:01     
1.9
+++ linux/arch/ppc/platforms/85xx/mpc85xx_cds_common.c  2005/06/07 13:45:29     
1.10
@@ -44,6 +44,7 @@
 #include <asm/machdep.h>
 #include <asm/prom.h>
 #include <asm/open_pic.h>
+#include <asm/i8259.h>
 #include <asm/bootinfo.h>
 #include <asm/pci-bridge.h>
 #include <asm/mpc85xx.h>
@@ -181,6 +182,7 @@
 mpc85xx_cds_init_IRQ(void)
 {
        bd_t *binfo = (bd_t *) __res;
+       int i;
 
        /* Determine the Physical Address of the OpenPIC regs */
        phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + 
MPC85xx_OPENPIC_OFFSET;
@@ -198,6 +200,15 @@
         */
        openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
 
+#ifdef CONFIG_PCI
+       openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);
+
+       for (i = 0; i < NUM_8259_INTERRUPTS; i++)
+               irq_desc[i].handler = &i8259_pic;
+
+       i8259_init(0);
+#endif
+
 #ifdef CONFIG_CPM2
        /* Setup CPM2 PIC */
         cpm2_init_IRQ();
@@ -231,7 +242,7 @@
                         * interrupt on slot */
                {
                        { 0, 1, 2, 3 }, /* 16 - PMC */
-                       { 3, 0, 0, 0 }, /* 17 P2P (Tsi320) */
+                       { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
                        { 0, 1, 2, 3 }, /* 18 - Slot 1 */
                        { 1, 2, 3, 0 }, /* 19 - Slot 2 */
                        { 2, 3, 0, 1 }, /* 20 - Slot 3 */
@@ -280,13 +291,135 @@
                        return PCIBIOS_DEVICE_NOT_FOUND;
 #endif
        /* We explicitly do not go past the Tundra 320 Bridge */
-       if (bus == 1)
+       if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
                return PCIBIOS_DEVICE_NOT_FOUND;
        if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
                return PCIBIOS_DEVICE_NOT_FOUND;
        else
                return PCIBIOS_SUCCESSFUL;
 }
+
+void __init
+mpc85xx_cds_enable_via(struct pci_controller *hose)
+{
+       u32 pci_class;
+       u16 vid, did;
+
+       early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
+       if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
+               return;
+
+       /* Configure P2P so that we can reach bus 1 */
+       early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
+       early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
+       early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);
+
+       early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
+       early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
+
+       if ((vid != PCI_VENDOR_ID_VIA) ||
+                       (did != PCI_DEVICE_ID_VIA_82C686))
+               return;
+
+       /* Enable USB and IDE functions */
+       early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
+}
+
+void __init
+mpc85xx_cds_fixup_via(struct pci_controller *hose)
+{
+       u32 pci_class;
+       u16 vid, did;
+
+       early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
+       if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
+               return;
+
+       /*
+        * Force the backplane P2P bridge to have a window
+        * open from 0x00000000-0x00001fff in PCI I/O space.
+        * This allows legacy I/O (i8259, etc) on the VIA
+        * southbridge to be accessed.
+        */
+       early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
+       early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
+       early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
+       early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);
+
+       early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
+       early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
+       if ((vid != PCI_VENDOR_ID_VIA) ||
+                       (did != PCI_DEVICE_ID_VIA_82C686))
+               return;
+
+       /*
+        * Since the P2P window was forced to cover the fixed
+        * legacy I/O addresses, it is necessary to manually
+        * place the base addresses for the IDE and USB functions
+        * within this window.
+        */
+       /* Function 1, IDE */
+       early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
+       early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
+       early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
+       early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
+       early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);
+
+       /* Function 2, USB ports 0-1 */
+       early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);
+
+       /* Function 3, USB ports 2-3 */
+       early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);
+
+       /* Function 5, Power Management */
+       early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
+       early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
+       early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);
+
+       /* Function 6, AC97 Interface */
+       early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
+}
+
+void __init
+mpc85xx_cds_pcibios_fixup(void)
+{
+        struct pci_dev *dev = NULL;
+       u_char          c;
+
+        if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+                                        PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
+                /*
+                 * U-Boot does not set the enable bits
+                 * for the IDE device. Force them on here.
+                 */
+                pci_read_config_byte(dev, 0x40, &c);
+                c |= 0x03; /* IDE: Chip Enable Bits */
+                pci_write_config_byte(dev, 0x40, c);
+
+               /*
+                * Since only primary interface works, force the
+                * IDE function to standard primary IDE interrupt
+                * w/ 8259 offset
+                */
+                dev->irq = 14;
+                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+        }
+
+       /*
+        * Force legacy USB interrupt routing
+        */
+        if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+                                        PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
+                dev->irq = 10;
+                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
+        }
+
+        if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+                                        PCI_DEVICE_ID_VIA_82C586_2, dev))) {
+                dev->irq = 11;
+                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
+        }
+}
 #endif /* CONFIG_PCI */
 
 TODC_ALLOC();
@@ -328,6 +461,9 @@
        loops_per_jiffy = freq / HZ;
 
 #ifdef CONFIG_PCI
+       /* VIA IDE configuration */
+        ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
+
        /* setup PCI host bridges */
        mpc85xx_setup_hose();
 #endif
@@ -459,6 +595,9 @@
 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
        ppc_md.progress = gen550_progress;
 #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
+#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
+       ppc_md.early_serial_map = mpc85xx_early_serial_map;
+#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
 
        if (ppc_md.progress)
                ppc_md.progress("mpc85xx_cds_init(): exit", 0);
diff -urN linux/arch/ppc/platforms/85xx/mpc85xx_cds_common.h 
linux/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
--- linux/arch/ppc/platforms/85xx/mpc85xx_cds_common.h  2005/03/18 17:36:57     
1.3
+++ linux/arch/ppc/platforms/85xx/mpc85xx_cds_common.h  2005/06/07 13:45:29     
1.4
@@ -77,4 +77,7 @@
 
 #define MPC85XX_PCI2_IO_SIZE         0x01000000
 
+#define NR_8259_INTS                16
+#define CPM_IRQ_OFFSET              NR_8259_INTS
+
 #endif /* __MACH_MPC85XX_CDS_H__ */
diff -urN linux/arch/ppc/platforms/85xx/sbc8560.c 
linux/arch/ppc/platforms/85xx/sbc8560.c
--- linux/arch/ppc/platforms/85xx/sbc8560.c     2005/03/18 17:36:57     1.6
+++ linux/arch/ppc/platforms/85xx/sbc8560.c     2005/06/07 13:45:29     1.7
@@ -221,6 +221,9 @@
 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
        ppc_md.progress = gen550_progress;
 #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
+#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
+       ppc_md.early_serial_map = sbc8560_early_serial_map;
+#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
 
        if (ppc_md.progress)
                ppc_md.progress("sbc8560_init(): exit", 0);
diff -urN linux/arch/ppc/syslib/m82xx_pci.c linux/arch/ppc/syslib/m82xx_pci.c
--- linux/arch/ppc/syslib/m82xx_pci.c   1970/01/01 00:00:00
+++ linux/arch/ppc/syslib/m82xx_pci.c   2005-06-07 14:45:29.342172000 +0100     
1.1
@@ -0,0 +1,383 @@
+/*
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004 Red Hat, Inc.
+ *
+ * 2005 (c) MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/immap_cpm2.h>
+#include <asm/mpc8260.h>
+#include <asm/cpm2.h>
+
+#include "m82xx_pci.h"
+
+/*
+ * Interrupt routing
+ */
+
+static inline int
+pq2pci_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+       static char pci_irq_table[][4] =
+       /*
+        *      PCI IDSEL/INTPIN->INTLINE
+        *        A      B      C      D
+        */
+       {
+               { PIRQA, PIRQB, PIRQC, PIRQD }, /* IDSEL 22 - PCI slot 0 */
+               { PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI slot 1 */
+               { PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI slot 2 */
+       };
+
+       const long min_idsel = 22, max_idsel = 24, irqs_per_slot = 4;
+       return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static void
+pq2pci_mask_irq(unsigned int irq)
+{
+       int bit = irq - NR_CPM_INTS;
+
+       *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+       return;
+}
+
+static void
+pq2pci_unmask_irq(unsigned int irq)
+{
+       int bit = irq - NR_CPM_INTS;
+
+       *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+       return;
+}
+
+static void
+pq2pci_mask_and_ack(unsigned int irq)
+{
+       int bit = irq - NR_CPM_INTS;
+
+       *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+       return;
+}
+
+static void
+pq2pci_end_irq(unsigned int irq)
+{
+       int bit = irq - NR_CPM_INTS;
+
+       *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+       return;
+}
+
+struct hw_interrupt_type pq2pci_ic = {
+       "PQ2 PCI",
+       NULL,
+       NULL,
+       pq2pci_unmask_irq,
+       pq2pci_mask_irq,
+       pq2pci_mask_and_ack,
+       pq2pci_end_irq,
+       0
+};
+
+static irqreturn_t
+pq2pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
+{
+       unsigned long stat, mask, pend;
+       int bit;
+
+       for(;;) {
+               stat = *(volatile unsigned long *) PCI_INT_STAT_REG;
+               mask = *(volatile unsigned long *) PCI_INT_MASK_REG;
+               pend = stat & ~mask & 0xf0000000;
+               if (!pend)
+                       break;
+               for (bit = 0; pend != 0; ++bit, pend <<= 1) {
+                       if (pend & 0x80000000)
+                               __do_IRQ(NR_CPM_INTS + bit, regs);
+               }
+       }
+
+       return IRQ_HANDLED;
+}
+
+static struct irqaction pq2pci_irqaction = {
+       .handler = pq2pci_irq_demux,
+       .flags   = SA_INTERRUPT,
+       .mask    = CPU_MASK_NONE,
+       .name    = "PQ2 PCI cascade",
+};
+
+
+void
+pq2pci_init_irq(void)
+{
+       int irq;
+       volatile cpm2_map_t *immap = cpm2_immr;
+#if defined CONFIG_ADS8272
+       /* configure chip select for PCI interrupt controller */
+       immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
+       immap->im_memctl.memc_or3 = 0xffff8010;
+#elif defined CONFIG_PQ2FADS
+       immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801;
+       immap->im_memctl.memc_or8 = 0xffff8010;
+#endif
+       for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
+               irq_desc[irq].handler = &pq2pci_ic;
+
+       /* make PCI IRQ level sensitive */
+       immap->im_intctl.ic_siexr &=
+               ~(1 << (14 - (PCI_INT_TO_SIU - SIU_INT_IRQ1)));
+
+       /* mask all PCI interrupts */
+       *(volatile unsigned long *) PCI_INT_MASK_REG |= 0xfff00000;
+
+       /* install the demultiplexer for the PCI cascade interrupt */
+       setup_irq(PCI_INT_TO_SIU, &pq2pci_irqaction);
+       return;
+}
+
+static int
+pq2pci_exclude_device(u_char bus, u_char devfn)
+{
+       return PCIBIOS_SUCCESSFUL;
+}
+
+/* PCI bus configuration registers.
+ */
+static void
+pq2ads_setup_pci(struct pci_controller *hose)
+{
+       __u32 val;
+       volatile cpm2_map_t *immap = cpm2_immr;
+       bd_t* binfo = (bd_t*) __res;
+       u32 sccr = immap->im_clkrst.car_sccr;
+       uint pci_div,freq,time;
+               /* PCI int lowest prio */
+       /* Each 4 bits is a device bus request  and the MS 4bits
+        is highest priority */
+       /* Bus                4bit value
+          ---                ----------
+          CPM high             0b0000
+          CPM middle           0b0001
+          CPM low              0b0010
+          PCI reguest          0b0011
+          Reserved             0b0100
+          Reserved             0b0101
+          Internal Core        0b0110
+          External Master 1    0b0111
+          External Master 2    0b1000
+          External Master 3    0b1001
+          The rest are reserved
+        */
+       immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
+       /* park bus on core */
+       immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE;
+       /*
+        * Set up master windows that allow the CPU to access PCI space. These
+        * windows are set up using the two SIU PCIBR registers.
+        */
+
+       immap->im_memctl.memc_pcimsk0 = M82xx_PCI_PRIM_WND_SIZE;
+       immap->im_memctl.memc_pcibr0  = M82xx_PCI_PRIM_WND_BASE | PCIBR_ENABLE;
+
+#ifdef M82xx_PCI_SEC_WND_SIZE
+       immap->im_memctl.memc_pcimsk1 = M82xx_PCI_SEC_WND_SIZE;
+       immap->im_memctl.memc_pcibr1  = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE;
+#endif
+
+#if defined CONFIG_ADS8272
+       immap->im_siu_conf.siu_82xx.sc_siumcr =
+               (immap->im_siu_conf.siu_82xx.sc_siumcr &
+               ~(SIUMCR_BBD | SIUMCR_ESE | SIUMCR_PBSE |
+               SIUMCR_CDIS | SIUMCR_DPPC11 | SIUMCR_L2CPC11 |
+               SIUMCR_LBPC11 | SIUMCR_APPC11 |
+               SIUMCR_CS10PC11 | SIUMCR_BCTLC11 | SIUMCR_MMR11)) |
+               SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 |
+               SIUMCR_APPC10 | SIUMCR_CS10PC00 |
+               SIUMCR_BCTLC00 | SIUMCR_MMR11 ;
+
+#elif defined CONFIG_PQ2FADS
+       /*
+        * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
+        * and local bus for PCI (SIUMCR [LBPC]).
+        */
+       immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+                               ~(SIUMCR_L2PC11 | SIUMCR_LBPC11 | 
SIUMCR_CS10PC11 | SIUMCR_APPC11) |
+                               SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | 
SIUMCR_APPC10;
+#endif
+       /* Enable PCI  */
+       immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
+
+       pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
+                       ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
+       freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div));
+       time = (int)666666/freq;
+       /* due to PCI Local Bus spec, some devices needs to wait such a long
+       time after RST  deassertion. More specifically, 0.508s for 66MHz & 
twice more for 33 */
+       printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting 
RST...\n",__FILE__,freq,
+       (time==1) ? "0.5 seconds":"1 second" );
+
+       {
+               int i;
+               for(i=0;i<(500*time);i++)
+                       udelay(1000);
+       }
+
+       /* setup ATU registers */
+       immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO |
+                               ((~(M82xx_PCI_IO_SIZE - 1U)) >> 
POTA_ADDR_SHIFT));
+       immap->im_pci.pci_potar0 = cpu_to_le32(M82xx_PCI_LOWER_IO >> 
POTA_ADDR_SHIFT);
+       immap->im_pci.pci_pobar0 = cpu_to_le32(M82xx_PCI_IO_BASE >> 
POTA_ADDR_SHIFT);
+
+       /* Set-up non-prefetchable window */
+       immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | 
((~(M82xx_PCI_MMIO_SIZE-1U)) >> POTA_ADDR_SHIFT));
+       immap->im_pci.pci_potar1 = cpu_to_le32(M82xx_PCI_LOWER_MMIO >> 
POTA_ADDR_SHIFT);
+       immap->im_pci.pci_pobar1 = cpu_to_le32((M82xx_PCI_LOWER_MMIO - 
M82xx_PCI_MMIO_OFFSET) >> POTA_ADDR_SHIFT);
+
+       /* Set-up prefetchable window */
+       immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN |
+               (~(M82xx_PCI_MEM_SIZE-1U) >> POTA_ADDR_SHIFT));
+       immap->im_pci.pci_potar2 = cpu_to_le32(M82xx_PCI_LOWER_MEM >> 
POTA_ADDR_SHIFT);
+       immap->im_pci.pci_pobar2 = cpu_to_le32((M82xx_PCI_LOWER_MEM - 
M82xx_PCI_MEM_OFFSET) >> POTA_ADDR_SHIFT);
+
+       /* Inbound transactions from PCI memory space */
+       immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN 
|
+                                       ((~(M82xx_PCI_SLAVE_MEM_SIZE-1U)) >> 
PITA_ADDR_SHIFT));
+       immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS  >> 
PITA_ADDR_SHIFT);
+       immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> 
PITA_ADDR_SHIFT);
+
+#if defined CONFIG_ADS8272
+       /* PCI int highest prio */
+       immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
+#elif defined CONFIG_PQ2FADS
+       immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
+#endif
+       /* park bus on PCI */
+       immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
+
+       /* Enable bus mastering and inbound memory transactions */
+       early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val);
+       val &= 0xffff0000;
+       val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
+       early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val);
+
+}
+
+void __init pq2_find_bridges(void)
+{
+       extern int pci_assign_all_busses;
+       struct pci_controller * hose;
+       int host_bridge;
+
+       pci_assign_all_busses = 1;
+
+       hose = pcibios_alloc_controller();
+
+       if (!hose)
+               return;
+
+       ppc_md.pci_swizzle = common_swizzle;
+
+       hose->first_busno = 0;
+       hose->bus_offset = 0;
+       hose->last_busno = 0xff;
+
+#ifdef CONFIG_ADS8272
+       hose->set_cfg_type = 1;
+#endif
+
+       setup_m8260_indirect_pci(hose,
+                                (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
+                                (unsigned 
long)&cpm2_immr->im_pci.pci_cfg_data);
+
+       /* Make sure it is a supported bridge */
+       early_read_config_dword(hose,
+                               0,
+                               PCI_DEVFN(0,0),
+                               PCI_VENDOR_ID,
+                               &host_bridge);
+       switch (host_bridge) {
+               case PCI_DEVICE_ID_MPC8265:
+                       break;
+               case PCI_DEVICE_ID_MPC8272:
+                       break;
+               default:
+                       printk("Attempting to use unrecognized host bridge ID"
+                               " 0x%08x.\n", host_bridge);
+                       break;
+       }
+
+       pq2ads_setup_pci(hose);
+
+       hose->io_space.start =  M82xx_PCI_LOWER_IO;
+       hose->io_space.end = M82xx_PCI_UPPER_IO;
+       hose->mem_space.start = M82xx_PCI_LOWER_MEM;
+       hose->mem_space.end = M82xx_PCI_UPPER_MMIO;
+       hose->pci_mem_offset = M82xx_PCI_MEM_OFFSET;
+
+       isa_io_base =
+       (unsigned long) ioremap(M82xx_PCI_IO_BASE,
+                                       M82xx_PCI_IO_SIZE);
+       hose->io_base_virt = (void *) isa_io_base;
+
+       /* setup resources */
+       pci_init_resource(&hose->mem_resources[0],
+                       M82xx_PCI_LOWER_MEM,
+                       M82xx_PCI_UPPER_MEM,
+                       IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable 
memory");
+
+       pci_init_resource(&hose->mem_resources[1],
+                       M82xx_PCI_LOWER_MMIO,
+                       M82xx_PCI_UPPER_MMIO,
+                       IORESOURCE_MEM, "PCI memory");
+
+       pci_init_resource(&hose->io_resource,
+                       M82xx_PCI_LOWER_IO,
+                       M82xx_PCI_UPPER_IO,
+                       IORESOURCE_IO | 1, "PCI I/O");
+
+       ppc_md.pci_exclude_device = pq2pci_exclude_device;
+       hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+       ppc_md.pci_map_irq = pq2pci_map_irq;
+       ppc_md.pcibios_fixup = NULL;
+       ppc_md.pcibios_fixup_bus = NULL;
+
+}
diff -urN linux/arch/ppc/syslib/m82xx_pci.h linux/arch/ppc/syslib/m82xx_pci.h
--- linux/arch/ppc/syslib/m82xx_pci.h   1970/01/01 00:00:00
+++ linux/arch/ppc/syslib/m82xx_pci.h   2005-06-07 14:45:29.359900000 +0100     
1.1
@@ -0,0 +1,92 @@
+
+#ifndef _PPC_KERNEL_M82XX_PCI_H
+#define _PPC_KERNEL_M82XX_PCI_H
+
+#include <asm/m8260_pci.h>
+/*
+ *   Local->PCI map (from CPU)                             controlled by
+ *   MPC826x master window
+ *
+ *   0xF6000000 - 0xF7FFFFFF    IO space
+ *   0x80000000 - 0xBFFFFFFF    CPU2PCI memory space       PCIBR0
+ *
+ *   0x80000000 - 0x9FFFFFFF    PCI Mem with prefetch      (Outbound ATU #1)
+ *   0xA0000000 - 0xBFFFFFFF    PCI Mem w/o  prefetch      (Outbound ATU #2)
+ *   0xF6000000 - 0xF7FFFFFF    32-bit PCI IO              (Outbound ATU #3)
+ *
+ *   PCI->Local map (from PCI)
+ *   MPC826x slave window                                  controlled by
+ *
+ *   0x00000000 - 0x07FFFFFF    MPC826x local memory       (Inbound ATU #1)
+ */
+
+/*
+ * Slave window that allows PCI masters to access MPC826x local memory.
+ * This window is set up using the first set of Inbound ATU registers
+ */
+
+#ifndef M82xx_PCI_SLAVE_MEM_LOCAL
+#define M82xx_PCI_SLAVE_MEM_LOCAL      (((struct bd_info *)__res)->bi_memstart)
+#define M82xx_PCI_SLAVE_MEM_BUS                (((struct bd_info 
*)__res)->bi_memstart)
+#define M82xx_PCI_SLAVE_MEM_SIZE       (((struct bd_info *)__res)->bi_memsize)
+#endif
+
+/*
+ * This is the window that allows the CPU to access PCI address space.
+ * It will be setup with the SIU PCIBR0 register. All three PCI master
+ * windows, which allow the CPU to access PCI prefetch, non prefetch,
+ * and IO space (see below), must all fit within this window.
+ */
+
+#ifndef M82xx_PCI_LOWER_MEM
+#define M82xx_PCI_LOWER_MEM            0x80000000
+#define M82xx_PCI_UPPER_MEM            0x9fffffff
+#define M82xx_PCI_MEM_OFFSET           0x00000000
+#define M82xx_PCI_MEM_SIZE             0x20000000
+#endif
+
+#ifndef M82xx_PCI_LOWER_MMIO
+#define M82xx_PCI_LOWER_MMIO           0xa0000000
+#define M82xx_PCI_UPPER_MMIO           0xafffffff
+#define M82xx_PCI_MMIO_OFFSET          0x00000000
+#define M82xx_PCI_MMIO_SIZE            0x20000000
+#endif
+
+#ifndef M82xx_PCI_LOWER_IO
+#define M82xx_PCI_LOWER_IO             0x00000000
+#define M82xx_PCI_UPPER_IO             0x01ffffff
+#define M82xx_PCI_IO_BASE              0xf6000000
+#define M82xx_PCI_IO_SIZE              0x02000000
+#endif
+
+#ifndef M82xx_PCI_PRIM_WND_SIZE
+#define M82xx_PCI_PRIM_WND_SIZE        ~(M82xx_PCI_IO_SIZE - 1U)
+#define M82xx_PCI_PRIM_WND_BASE                (M82xx_PCI_IO_BASE)
+#endif
+
+#ifndef M82xx_PCI_SEC_WND_SIZE
+#define M82xx_PCI_SEC_WND_SIZE                 ~(M82xx_PCI_MEM_SIZE + 
M82xx_PCI_MMIO_SIZE - 1U)
+#define M82xx_PCI_SEC_WND_BASE                 (M82xx_PCI_LOWER_MEM)
+#endif
+
+#ifndef POTA_ADDR_SHIFT
+#define POTA_ADDR_SHIFT                12
+#endif
+
+#ifndef PITA_ADDR_SHIFT
+#define PITA_ADDR_SHIFT                12
+#endif
+
+#ifndef _IO_BASE
+#define _IO_BASE isa_io_base
+#endif
+
+#ifdef CONFIG_8260_PCI9
+struct pci_controller;
+extern void setup_m8260_indirect_pci(struct pci_controller* hose,
+                                       u32 cfg_addr, u32 cfg_data);
+#else
+#define setup_m8260_indirect_pci setup_indirect_pci
+#endif
+
+#endif /* _PPC_KERNEL_M8260_PCI_H */
diff -urN linux/arch/ppc/syslib/Makefile linux/arch/ppc/syslib/Makefile
--- linux/arch/ppc/syslib/Makefile      2005/04/08 18:58:01     1.28
+++ linux/arch/ppc/syslib/Makefile      2005/06/07 13:45:29     1.29
@@ -81,7 +81,7 @@
 obj-$(CONFIG_SPRUCE)           += cpc700_pic.o indirect_pci.o pci_auto.o \
                                   todc_time.o
 obj-$(CONFIG_8260)             += m8260_setup.o
-obj-$(CONFIG_PCI_8260)         += m8260_pci.o indirect_pci.o
+obj-$(CONFIG_PCI_8260)         += m82xx_pci.o indirect_pci.o pci_auto.o
 obj-$(CONFIG_8260_PCI9)                += m8260_pci_erratum9.o
 obj-$(CONFIG_CPM2)             += cpm2_common.o cpm2_pic.o
 ifeq ($(CONFIG_PPC_GEN550),y)
@@ -97,7 +97,7 @@
 obj-$(CONFIG_40x)              += dcr.o
 obj-$(CONFIG_BOOKE)            += dcr.o
 obj-$(CONFIG_85xx)             += open_pic.o ppc85xx_common.o ppc85xx_setup.o \
-                                       ppc_sys.o mpc85xx_sys.o \
+                                       ppc_sys.o i8259.o mpc85xx_sys.o \
                                        mpc85xx_devices.o
 ifeq ($(CONFIG_85xx),y)
 obj-$(CONFIG_PCI)              += indirect_pci.o pci_auto.o
diff -urN linux/arch/ppc/syslib/m8260_pci_erratum9.c 
linux/arch/ppc/syslib/m8260_pci_erratum9.c
--- linux/arch/ppc/syslib/m8260_pci_erratum9.c  2004/08/06 00:33:23     1.2
+++ linux/arch/ppc/syslib/m8260_pci_erratum9.c  2005/06/07 13:45:29     1.3
@@ -31,7 +31,7 @@
 #include <asm/immap_cpm2.h>
 #include <asm/cpm2.h>
 
-#include "m8260_pci.h"
+#include "m82xx_pci.h"
 
 #ifdef CONFIG_8260_PCI9
 /*#include <asm/mpc8260_pci9.h>*/ /* included in asm/io.h */
@@ -248,11 +248,11 @@
 
 static inline int is_pci_mem(unsigned long addr)
 {
-       if (addr >= MPC826x_PCI_LOWER_MMIO &&
-           addr <= MPC826x_PCI_UPPER_MMIO)
+       if (addr >= M82xx_PCI_LOWER_MMIO &&
+               addr <= M82xx_PCI_UPPER_MMIO)
                return 1;
-       if (addr >= MPC826x_PCI_LOWER_MEM &&
-           addr <= MPC826x_PCI_UPPER_MEM)
+       if (addr >= M82xx_PCI_LOWER_MEM &&
+               addr <= M82xx_PCI_UPPER_MEM)
                return 1;
        return 0;
 }
diff -urN linux/arch/ppc/syslib/m8260_setup.c 
linux/arch/ppc/syslib/m8260_setup.c
--- linux/arch/ppc/syslib/m8260_setup.c 2005/04/08 18:58:01     1.9
+++ linux/arch/ppc/syslib/m8260_setup.c 2005/06/07 13:45:29     1.10
@@ -34,7 +34,8 @@
 unsigned char __res[sizeof(bd_t)];
 
 extern void cpm2_reset(void);
-extern void m8260_find_bridges(void);
+extern void pq2_find_bridges(void);
+extern void pq2pci_init_irq(void);
 extern void idma_pci9_init(void);
 
 /* Place-holder for board-specific init */
@@ -56,7 +57,7 @@
        idma_pci9_init();
 #endif
 #ifdef CONFIG_PCI_8260
-       m8260_find_bridges();
+       pq2_find_bridges();
 #endif
 #ifdef CONFIG_BLK_DEV_INITRD
        if (initrd_start)
@@ -173,6 +174,12 @@
         * in case the boot rom changed something on us.
         */
        cpm2_immr->im_intctl.ic_siprr = 0x05309770;
+
+#if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS))
+       /* Initialize stuff for the 82xx CPLD IC and install demux  */
+       pq2pci_init_irq();
+#endif
+
 }
 
 /*
diff -urN linux/arch/ppc/syslib/open_pic.c linux/arch/ppc/syslib/open_pic.c
--- linux/arch/ppc/syslib/open_pic.c    2005/05/26 09:12:38     1.23
+++ linux/arch/ppc/syslib/open_pic.c    2005/06/07 13:45:29     1.24
@@ -275,7 +275,7 @@
 }
 #endif
 
-#if defined(CONFIG_EPIC_SERIAL_MODE) || defined(CONFIG_PM)
+#if defined(CONFIG_EPIC_SERIAL_MODE)
 static void openpic_reset(void)
 {
        openpic_setfield(&OpenPIC->Global.Global_Configuration0,
@@ -993,8 +993,6 @@
                return 0;
        }
 
-       openpic_reset();
-
        /* OpenPIC sometimes seem to need some time to be fully back up... */
        do {
                openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
diff -urN linux/arch/ppc/syslib/ppc83xx_setup.c 
linux/arch/ppc/syslib/ppc83xx_setup.c
--- linux/arch/ppc/syslib/ppc83xx_setup.c       2005/03/18 17:36:58     1.1
+++ linux/arch/ppc/syslib/ppc83xx_setup.c       2005/06/07 13:45:29     1.2
@@ -29,6 +29,7 @@
 #include <asm/mmu.h>
 #include <asm/ppc_sys.h>
 #include <asm/kgdb.h>
+#include <asm/delay.h>
 
 #include <syslib/ppc83xx_setup.h>
 
@@ -117,7 +118,34 @@
 void
 mpc83xx_restart(char *cmd)
 {
+       volatile unsigned char __iomem *reg;
+       unsigned char tmp;
+
+       reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
+
        local_irq_disable();
+
+       /*
+        * Unlock the BCSR bits so a PRST will update the contents.
+        * Otherwise the reset asserts but doesn't clear.
+        */
+       tmp = in_8(reg + BCSR_MISC_REG3_OFF);
+       tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */
+       out_8(reg + BCSR_MISC_REG3_OFF, tmp);
+
+       /*
+        * Trigger a reset via a low->high transition of the
+        * PORESET bit.
+        */
+       tmp = in_8(reg + BCSR_MISC_REG2_OFF);
+       tmp &= ~BCSR_MISC_REG2_PORESET;
+       out_8(reg + BCSR_MISC_REG2_OFF, tmp);
+
+       udelay(1);
+
+       tmp |= BCSR_MISC_REG2_PORESET;
+       out_8(reg + BCSR_MISC_REG2_OFF, tmp);
+
        for(;;);
 }
 
diff -urN linux/arch/ppc/syslib/ppc85xx_setup.c 
linux/arch/ppc/syslib/ppc85xx_setup.c
--- linux/arch/ppc/syslib/ppc85xx_setup.c       2005/05/19 12:08:13     1.8
+++ linux/arch/ppc/syslib/ppc85xx_setup.c       2005/06/07 13:45:29     1.9
@@ -132,6 +132,12 @@
 }
 
 #ifdef CONFIG_PCI
+
+#if defined(CONFIG_MPC8555_CDS)
+extern void mpc85xx_cds_enable_via(struct pci_controller *hose);
+extern void mpc85xx_cds_fixup_via(struct pci_controller *hose);
+#endif
+
 static void __init
 mpc85xx_setup_pci1(struct pci_controller *hose)
 {
@@ -302,8 +308,18 @@
 
        ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 
+#if defined(CONFIG_MPC8555_CDS)
+       /* Pre pciauto_bus_scan VIA init */
+       mpc85xx_cds_enable_via(hose_a);
+#endif
+
        hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
 
+#if defined(CONFIG_MPC8555_CDS)
+       /* Post pciauto_bus_scan VIA fixup */
+       mpc85xx_cds_fixup_via(hose_a);
+#endif
+
 #ifdef CONFIG_85xx_PCI2
        hose_b = pcibios_alloc_controller();
 
diff -urN linux/arch/ppc/syslib/prom_init.c linux/arch/ppc/syslib/prom_init.c
--- linux/arch/ppc/syslib/prom_init.c   2005/04/08 18:58:01     1.14
+++ linux/arch/ppc/syslib/prom_init.c   2005/06/07 13:45:29     1.15
@@ -626,8 +626,18 @@
        l = call_prom("package-to-path", 3, 1, node,
                      mem_start, mem_end - mem_start);
        if (l >= 0) {
+               char *p, *ep;
+
                np->full_name = PTRUNRELOC((char *) mem_start);
                *(char *)(mem_start + l) = 0;
+               /* Fixup an Apple bug where they have bogus \0 chars in the
+                * middle of the path in some properties
+                */
+               for (p = (char *)mem_start, ep = p + l; p < ep; p++)
+                       if ((*p) == '\0') {
+                               memmove(p, p+1, ep - p);
+                               ep--;
+                       }
                mem_start = ALIGNUL(mem_start + l + 1);
        }
 
diff -urN linux/arch/ppc/syslib/m8260_pci.c linux/arch/ppc/syslib/m8260_pci.c
--- linux/arch/ppc/syslib/Attic/m8260_pci.c     2005-06-07 14:45:29.513885000 
+0100     1.2
+++ linux/arch/ppc/syslib/Attic/m8260_pci.c     1970/01/01 00:00:00+0100
@@ -1,193 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004 Red Hat, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <asm/immap_cpm2.h>
-#include <asm/mpc8260.h>
-
-#include "m8260_pci.h"
-
-
-/* PCI bus configuration registers.
- */
-
-static void __init m8260_setup_pci(struct pci_controller *hose)
-{
-       volatile cpm2_map_t *immap = cpm2_immr;
-       unsigned long pocmr;
-       u16 tempShort;
-
-#ifndef CONFIG_ATC     /* already done in U-Boot */
-       /* 
-        * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), 
-        * and local bus for PCI (SIUMCR [LBPC]).
-        */
-       immap->im_siu_conf.siu_82xx.sc_siumcr = 0x00640000;
-#endif
-
-       /* Make PCI lowest priority */
-       /* Each 4 bits is a device bus request  and the MS 4bits 
-          is highest priority */
-       /* Bus               4bit value 
-          ---               ----------
-          CPM high          0b0000
-          CPM middle        0b0001
-          CPM low           0b0010
-          PCI reguest       0b0011
-          Reserved          0b0100
-          Reserved          0b0101
-          Internal Core     0b0110
-          External Master 1 0b0111
-          External Master 2 0b1000
-          External Master 3 0b1001
-          The rest are reserved */
-       immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
-
-       /* Park bus on core while modifying PCI Bus accesses */
-       immap->im_siu_conf.siu_82xx.sc_ppc_acr = 0x6;
-
-       /* 
-        * Set up master window that allows the CPU to access PCI space. This 
-        * window is set up using the first SIU PCIBR registers.
-        */
-       immap->im_memctl.memc_pcimsk0 = MPC826x_PCI_MASK;
-       immap->im_memctl.memc_pcibr0 =  MPC826x_PCI_BASE | PCIBR_ENABLE;
-
-       /* Disable machine check on no response or target abort */
-       immap->im_pci.pci_emr = cpu_to_le32(0x1fe7);
-       /* Release PCI RST (by default the PCI RST signal is held low)  */
-       immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
-
-       /* give it some time */
-       mdelay(1);
-
-       /* 
-        * Set up master window that allows the CPU to access PCI Memory 
(prefetch) 
-        * space. This window is set up using the first set of Outbound ATU 
registers.
-        */
-       immap->im_pci.pci_potar0 = cpu_to_le32(MPC826x_PCI_LOWER_MEM >> 12);
-       immap->im_pci.pci_pobar0 = cpu_to_le32((MPC826x_PCI_LOWER_MEM - 
MPC826x_PCI_MEM_OFFSET) >> 12);
-       pocmr = ((MPC826x_PCI_UPPER_MEM - MPC826x_PCI_LOWER_MEM) >> 12) ^ 
0xfffff;
-       immap->im_pci.pci_pocmr0 = cpu_to_le32(pocmr | POCMR_ENABLE | 
POCMR_PREFETCH_EN);
-
-       /* 
-        * Set up master window that allows the CPU to access PCI Memory 
(non-prefetch) 
-        * space. This window is set up using the second set of Outbound ATU 
registers.
-        */
-       immap->im_pci.pci_potar1 = cpu_to_le32(MPC826x_PCI_LOWER_MMIO >> 12);
-       immap->im_pci.pci_pobar1 = cpu_to_le32((MPC826x_PCI_LOWER_MMIO - 
MPC826x_PCI_MMIO_OFFSET) >> 12);
-       pocmr = ((MPC826x_PCI_UPPER_MMIO - MPC826x_PCI_LOWER_MMIO) >> 12) ^ 
0xfffff;
-       immap->im_pci.pci_pocmr1 = cpu_to_le32(pocmr | POCMR_ENABLE);
-
-       /* 
-        * Set up master window that allows the CPU to access PCI IO space. 
This window
-        * is set up using the third set of Outbound ATU registers.
-        */
-       immap->im_pci.pci_potar2 = cpu_to_le32(MPC826x_PCI_IO_BASE >> 12);
-       immap->im_pci.pci_pobar2 = cpu_to_le32(MPC826x_PCI_LOWER_IO >> 12);
-       pocmr = ((MPC826x_PCI_UPPER_IO - MPC826x_PCI_LOWER_IO) >> 12) ^ 0xfffff;
-       immap->im_pci.pci_pocmr2 = cpu_to_le32(pocmr | POCMR_ENABLE | 
POCMR_PCI_IO);
-
-       /* 
-        * Set up slave window that allows PCI masters to access MPC826x local 
memory. 
-        * This window is set up using the first set of Inbound ATU registers
-        */
-
-       immap->im_pci.pci_pitar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_LOCAL >> 
12);
-       immap->im_pci.pci_pibar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_BUS >> 12);
-       pocmr = ((MPC826x_PCI_SLAVE_MEM_SIZE-1) >> 12) ^ 0xfffff;
-       immap->im_pci.pci_picmr0 = cpu_to_le32(pocmr | PICMR_ENABLE | 
PICMR_PREFETCH_EN);
-
-       /* See above for description - puts PCI request as highest priority */
-       immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
-
-       /* Park the bus on the PCI */
-       immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
-
-       /* Host mode - specify the bridge as a host-PCI bridge */
-       early_write_config_word(hose, 0, 0, PCI_CLASS_DEVICE, 
PCI_CLASS_BRIDGE_HOST);
-
-       /* Enable the host bridge to be a master on the PCI bus, and to act as 
a PCI memory target */
-       early_read_config_word(hose, 0, 0, PCI_COMMAND, &tempShort);
-       early_write_config_word(hose, 0, 0, PCI_COMMAND,
-                               tempShort | PCI_COMMAND_MASTER | 
PCI_COMMAND_MEMORY);
-}
-
-void __init m8260_find_bridges(void)
-{
-       extern int pci_assign_all_busses;
-       struct pci_controller * hose;
-
-       pci_assign_all_busses = 1;
-
-       hose = pcibios_alloc_controller();
-
-       if (!hose)
-               return;
-
-       ppc_md.pci_swizzle = common_swizzle;
-
-       hose->first_busno = 0;
-       hose->bus_offset = 0;
-       hose->last_busno = 0xff;
-
-       setup_m8260_indirect_pci(hose, 
-                                (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
-                                (unsigned 
long)&cpm2_immr->im_pci.pci_cfg_data);
-
-       m8260_setup_pci(hose);
-        hose->pci_mem_offset = MPC826x_PCI_MEM_OFFSET;
-
-        hose->io_base_virt = ioremap(MPC826x_PCI_IO_BASE,
-                                        MPC826x_PCI_IO_SIZE);
-        isa_io_base = (unsigned long) hose->io_base_virt;
- 
-        /* setup resources */
-        pci_init_resource(&hose->mem_resources[0],
-                         MPC826x_PCI_LOWER_MEM,
-                         MPC826x_PCI_UPPER_MEM,
-                         IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable 
memory");
-
-        pci_init_resource(&hose->mem_resources[1],
-                         MPC826x_PCI_LOWER_MMIO,
-                         MPC826x_PCI_UPPER_MMIO,
-                         IORESOURCE_MEM, "PCI memory");
-
-        pci_init_resource(&hose->io_resource,
-                         MPC826x_PCI_LOWER_IO,
-                         MPC826x_PCI_UPPER_IO,
-                         IORESOURCE_IO, "PCI I/O");
-}
diff -urN linux/arch/ppc/syslib/m8260_pci.h linux/arch/ppc/syslib/m8260_pci.h
--- linux/arch/ppc/syslib/Attic/m8260_pci.h     2005-06-07 14:45:29.529966000 
+0100     1.2
+++ linux/arch/ppc/syslib/Attic/m8260_pci.h     1970/01/01 00:00:00+0100
@@ -1,76 +0,0 @@
-
-#ifndef _PPC_KERNEL_M8260_PCI_H
-#define _PPC_KERNEL_M8260_PCI_H
-
-#include <asm/m8260_pci.h>
-
-/*
- *   Local->PCI map (from CPU)                             controlled by
- *   MPC826x master window
- *
- *   0x80000000 - 0xBFFFFFFF    Total CPU2PCI space        PCIBR0
- *                       
- *   0x80000000 - 0x9FFFFFFF    PCI Mem with prefetch      (Outbound ATU #1)
- *   0xA0000000 - 0xAFFFFFFF    PCI Mem w/o  prefetch      (Outbound ATU #2)
- *   0xB0000000 - 0xB0FFFFFF    32-bit PCI IO              (Outbound ATU #3)
- *                      
- *   PCI->Local map (from PCI)
- *   MPC826x slave window                                  controlled by
- *
- *   0x00000000 - 0x07FFFFFF    MPC826x local memory       (Inbound ATU #1)
- */
-
-/* 
- * Slave window that allows PCI masters to access MPC826x local memory. 
- * This window is set up using the first set of Inbound ATU registers
- */
-
-#ifndef MPC826x_PCI_SLAVE_MEM_LOCAL
-#define MPC826x_PCI_SLAVE_MEM_LOCAL    (((struct bd_info *)__res)->bi_memstart)
-#define MPC826x_PCI_SLAVE_MEM_BUS      (((struct bd_info *)__res)->bi_memstart)
-#define MPC826x_PCI_SLAVE_MEM_SIZE     (((struct bd_info *)__res)->bi_memsize)
-#endif
-
-/* 
- * This is the window that allows the CPU to access PCI address space.
- * It will be setup with the SIU PCIBR0 register. All three PCI master
- * windows, which allow the CPU to access PCI prefetch, non prefetch,
- * and IO space (see below), must all fit within this window. 
- */
-#ifndef MPC826x_PCI_BASE
-#define MPC826x_PCI_BASE       0x80000000
-#define MPC826x_PCI_MASK       0xc0000000
-#endif
-
-#ifndef MPC826x_PCI_LOWER_MEM
-#define MPC826x_PCI_LOWER_MEM  0x80000000
-#define MPC826x_PCI_UPPER_MEM  0x9fffffff
-#define MPC826x_PCI_MEM_OFFSET 0x00000000
-#endif
-
-#ifndef MPC826x_PCI_LOWER_MMIO
-#define MPC826x_PCI_LOWER_MMIO  0xa0000000
-#define MPC826x_PCI_UPPER_MMIO  0xafffffff
-#define MPC826x_PCI_MMIO_OFFSET 0x00000000
-#endif
-
-#ifndef MPC826x_PCI_LOWER_IO
-#define MPC826x_PCI_LOWER_IO   0x00000000
-#define MPC826x_PCI_UPPER_IO   0x00ffffff
-#define MPC826x_PCI_IO_BASE    0xb0000000
-#define MPC826x_PCI_IO_SIZE    0x01000000
-#endif
-
-#ifndef _IO_BASE
-#define _IO_BASE isa_io_base
-#endif
-
-#ifdef CONFIG_8260_PCI9
-struct pci_controller;
-extern void setup_m8260_indirect_pci(struct pci_controller* hose,
-                                    u32 cfg_addr, u32 cfg_data);
-#else
-#define setup_m8260_indirect_pci setup_indirect_pci
-#endif
-
-#endif /* _PPC_KERNEL_M8260_PCI_H */
diff -urN linux/arch/ppc64/kernel/entry.S linux/arch/ppc64/kernel/entry.S
--- linux/arch/ppc64/kernel/entry.S     2005/04/08 18:58:02     1.37
+++ linux/arch/ppc64/kernel/entry.S     2005/06/07 13:45:29     1.38
@@ -436,15 +436,6 @@
        REST_8GPRS(14, r1)
        REST_10GPRS(22, r1)
 
-#ifdef CONFIG_PPC_ISERIES
-       clrrdi  r7,r1,THREAD_SHIFT      /* get current_thread_info() */
-       ld      r7,TI_FLAGS(r7)         /* Get run light flag */
-       mfspr   r9,CTRLF
-       srdi    r7,r7,TIF_RUN_LIGHT
-       insrdi  r9,r7,1,63              /* Insert run light into CTRL */
-       mtspr   CTRLT,r9
-#endif
-
        /* convert old thread to its task_struct for return value */
        addi    r3,r3,-THREAD
        ld      r7,_NIP(r1)     /* Return to _switch caller in new task */
diff -urN linux/arch/ppc64/kernel/head.S linux/arch/ppc64/kernel/head.S
--- linux/arch/ppc64/kernel/head.S      2005/04/29 11:15:04     1.41
+++ linux/arch/ppc64/kernel/head.S      2005/06/07 13:45:29     1.42
@@ -626,10 +626,10 @@
        lhz     r24,PACAPACAINDEX(r13)  /* Get processor # */
        cmpwi   0,r24,0                 /* Are we processor 0? */
        beq     .__start_initialization_iSeries /* Start up the first processor 
*/
-       mfspr   r4,CTRLF
-       li      r5,RUNLATCH             /* Turn off the run light */
+       mfspr   r4,SPRN_CTRLF
+       li      r5,CTRL_RUNLATCH        /* Turn off the run light */
        andc    r4,r4,r5
-       mtspr   CTRLT,r4
+       mtspr   SPRN_CTRLT,r4
 
 1:
        HMT_LOW
@@ -2082,9 +2082,9 @@
        mfspr   r4, HID0
        ori     r4, r4, 0x1
        mtspr   HID0, r4
-       mfspr   r4, CTRLF
+       mfspr   r4, SPRN_CTRLF
        oris    r4, r4, 0x40
-       mtspr   CTRLT, r4
+       mtspr   SPRN_CTRLT, r4
        blr
 #endif
 
diff -urN linux/arch/ppc64/kernel/iSeries_setup.c 
linux/arch/ppc64/kernel/iSeries_setup.c
--- linux/arch/ppc64/kernel/iSeries_setup.c     2005/04/08 18:58:02     1.26
+++ linux/arch/ppc64/kernel/iSeries_setup.c     2005/06/07 13:45:29     1.27
@@ -852,6 +852,28 @@
 
 late_initcall(iSeries_src_init);
 
+static int set_spread_lpevents(char *str)
+{
+       unsigned long i;
+       unsigned long val = simple_strtoul(str, NULL, 0);
+
+       /*
+        * The parameter is the number of processors to share in processing
+        * lp events.
+        */
+       if (( val > 0) && (val <= NR_CPUS)) {
+               for (i = 1; i < val; ++i)
+                       paca[i].lpqueue_ptr = paca[0].lpqueue_ptr;
+
+               printk("lpevent processing spread over %ld processors\n", val);
+       } else {
+               printk("invalid spread_lpevents %ld\n", val);
+       }
+
+       return 1;
+}
+__setup("spread_lpevents=", set_spread_lpevents);
+
 void __init iSeries_early_setup(void)
 {
        iSeries_fixup_klimit();
diff -urN linux/arch/ppc64/kernel/idle.c linux/arch/ppc64/kernel/idle.c
--- linux/arch/ppc64/kernel/idle.c      2005/03/18 17:36:59     1.18
+++ linux/arch/ppc64/kernel/idle.c      2005/06/07 13:45:29     1.19
@@ -75,13 +75,9 @@
 {
        struct paca_struct *lpaca;
        long oldval;
-       unsigned long CTRL;
 
        /* ensure iSeries run light will be out when idle */
-       clear_thread_flag(TIF_RUN_LIGHT);
-       CTRL = mfspr(CTRLF);
-       CTRL &= ~RUNLATCH;
-       mtspr(CTRLT, CTRL);
+       ppc64_runlatch_off();
 
        lpaca = get_paca();
 
@@ -111,7 +107,9 @@
                        }
                }
 
+               ppc64_runlatch_on();
                schedule();
+               ppc64_runlatch_off();
        }
 
        return 0;
diff -urN linux/arch/ppc64/kernel/mf.c linux/arch/ppc64/kernel/mf.c
--- linux/arch/ppc64/kernel/mf.c        2004/11/15 11:49:20     1.10
+++ linux/arch/ppc64/kernel/mf.c        2005/06/07 13:45:29     1.11
@@ -1,7 +1,7 @@
 /*
   * mf.c
   * Copyright (C) 2001 Troy D. Armstrong  IBM Corporation
-  * Copyright (C) 2004 Stephen Rothwell  IBM Corporation
+  * Copyright (C) 2004-2005 Stephen Rothwell  IBM Corporation
   *
   * This modules exists as an interface between a Linux secondary partition
   * running on an iSeries and the primary partition's Virtual Service
@@ -36,10 +36,12 @@
 
 #include <asm/time.h>
 #include <asm/uaccess.h>
+#include <asm/paca.h>
 #include <asm/iSeries/vio.h>
 #include <asm/iSeries/mf.h>
 #include <asm/iSeries/HvLpConfig.h>
 #include <asm/iSeries/ItSpCommArea.h>
+#include <asm/iSeries/ItLpQueue.h>
 
 /*
  * This is the structure layout for the Machine Facilites LPAR event
@@ -696,36 +698,23 @@
        complete(&rtc->com);
 }
 
-int mf_get_rtc(struct rtc_time *tm)
+static int rtc_set_tm(int rc, u8 *ce_msg, struct rtc_time *tm)
 {
-       struct ce_msg_comp_data ce_complete;
-       struct rtc_time_data rtc_data;
-       int rc;
-
-       memset(&ce_complete, 0, sizeof(ce_complete));
-       memset(&rtc_data, 0, sizeof(rtc_data));
-       init_completion(&rtc_data.com);
-       ce_complete.handler = &get_rtc_time_complete;
-       ce_complete.token = &rtc_data;
-       rc = signal_ce_msg_simple(0x40, &ce_complete);
-       if (rc)
-               return rc;
-       wait_for_completion(&rtc_data.com);
        tm->tm_wday = 0;
        tm->tm_yday = 0;
        tm->tm_isdst = 0;
-       if (rtc_data.rc) {
+       if (rc) {
                tm->tm_sec = 0;
                tm->tm_min = 0;
                tm->tm_hour = 0;
                tm->tm_mday = 15;
                tm->tm_mon = 5;
                tm->tm_year = 52;
-               return rtc_data.rc;
+               return rc;
        }
 
-       if ((rtc_data.ce_msg.ce_msg[2] == 0xa9) ||
-           (rtc_data.ce_msg.ce_msg[2] == 0xaf)) {
+       if ((ce_msg[2] == 0xa9) ||
+           (ce_msg[2] == 0xaf)) {
                /* TOD clock is not set */
                tm->tm_sec = 1;
                tm->tm_min = 1;
@@ -736,7 +725,6 @@
                mf_set_rtc(tm);
        }
        {
-               u8 *ce_msg = rtc_data.ce_msg.ce_msg;
                u8 year = ce_msg[5];
                u8 sec = ce_msg[6];
                u8 min = ce_msg[7];
@@ -765,6 +753,63 @@
        return 0;
 }
 
+int mf_get_rtc(struct rtc_time *tm)
+{
+       struct ce_msg_comp_data ce_complete;
+       struct rtc_time_data rtc_data;
+       int rc;
+
+       memset(&ce_complete, 0, sizeof(ce_complete));
+       memset(&rtc_data, 0, sizeof(rtc_data));
+       init_completion(&rtc_data.com);
+       ce_complete.handler = &get_rtc_time_complete;
+       ce_complete.token = &rtc_data;
+       rc = signal_ce_msg_simple(0x40, &ce_complete);
+       if (rc)
+               return rc;
+       wait_for_completion(&rtc_data.com);
+       return rtc_set_tm(rtc_data.rc, rtc_data.ce_msg.ce_msg, tm);
+}
+
+struct boot_rtc_time_data {
+       int busy;
+       struct ce_msg_data ce_msg;
+       int rc;
+};
+
+static void get_boot_rtc_time_complete(void *token, struct ce_msg_data *ce_msg)
+{
+       struct boot_rtc_time_data *rtc = token;
+
+       memcpy(&rtc->ce_msg, ce_msg, sizeof(rtc->ce_msg));
+       rtc->rc = 0;
+       rtc->busy = 0;
+}
+
+int mf_get_boot_rtc(struct rtc_time *tm)
+{
+       struct ce_msg_comp_data ce_complete;
+       struct boot_rtc_time_data rtc_data;
+       int rc;
+
+       memset(&ce_complete, 0, sizeof(ce_complete));
+       memset(&rtc_data, 0, sizeof(rtc_data));
+       rtc_data.busy = 1;
+       ce_complete.handler = &get_boot_rtc_time_complete;
+       ce_complete.token = &rtc_data;
+       rc = signal_ce_msg_simple(0x40, &ce_complete);
+       if (rc)
+               return rc;
+       /* We need to poll here as we are not yet taking interrupts */
+       while (rtc_data.busy) {
+               extern unsigned long lpevent_count;
+               struct ItLpQueue *lpq = get_paca()->lpqueue_ptr;
+               if (lpq && ItLpQueue_isLpIntPending(lpq))
+                       lpevent_count += ItLpQueue_process(lpq, NULL);
+       }
+       return rtc_set_tm(rtc_data.rc, rtc_data.ce_msg.ce_msg, tm);
+}
+
 int mf_set_rtc(struct rtc_time *tm)
 {
        char ce_time[12];
diff -urN linux/arch/ppc64/kernel/pSeries_reconfig.c 
linux/arch/ppc64/kernel/pSeries_reconfig.c
--- linux/arch/ppc64/kernel/pSeries_reconfig.c  2005/04/08 18:58:02     1.1
+++ linux/arch/ppc64/kernel/pSeries_reconfig.c  2005/06/07 13:45:29     1.2
@@ -47,14 +47,6 @@
                remove_proc_entry(pp->name, np->pde);
                pp = pp->next;
        }
-
-       /* Assuming that symlinks have the same parent directory as
-        * np->pde.
-        */
-       if (np->name_link)
-               remove_proc_entry(np->name_link->name, parent->pde);
-       if (np->addr_link)
-               remove_proc_entry(np->addr_link->name, parent->pde);
        if (np->pde)
                remove_proc_entry(np->pde->name, parent->pde);
 }
diff -urN linux/arch/ppc64/kernel/process.c linux/arch/ppc64/kernel/process.c
--- linux/arch/ppc64/kernel/process.c   2005/03/18 17:36:59     1.39
+++ linux/arch/ppc64/kernel/process.c   2005/06/07 13:45:29     1.40
@@ -378,9 +378,6 @@
                childregs->gpr[1] = sp + sizeof(struct pt_regs);
                p->thread.regs = NULL;  /* no user register state */
                clear_ti_thread_flag(p->thread_info, TIF_32BIT);
-#ifdef CONFIG_PPC_ISERIES
-               set_ti_thread_flag(p->thread_info, TIF_RUN_LIGHT);
-#endif
        } else {
                childregs->gpr[1] = usp;
                p->thread.regs = childregs;
diff -urN linux/arch/ppc64/kernel/prom_init.c 
linux/arch/ppc64/kernel/prom_init.c
--- linux/arch/ppc64/kernel/prom_init.c 2005/05/26 09:12:38     1.12
+++ linux/arch/ppc64/kernel/prom_init.c 2005/06/07 13:45:29     1.13
@@ -211,13 +211,23 @@
  */
 #define ADDR(x)                (u32) ((unsigned long)(x) - offset)
 
+/*
+ * Error results ... some OF calls will return "-1" on error, some
+ * will return 0, some will return either. To simplify, here are
+ * macros to use with any ihandle or phandle return value to check if
+ * it is valid
+ */
+
+#define PROM_ERROR             (-1u)
+#define PHANDLE_VALID(p)       ((p) != 0 && (p) != PROM_ERROR)
+#define IHANDLE_VALID(i)       ((i) != 0 && (i) != PROM_ERROR)
+
+
 /* This is the one and *ONLY* place where we actually call open
  * firmware from, since we need to make sure we're running in 32b
  * mode when we do.  We switch back to 64b mode upon return.
  */
 
-#define PROM_ERROR     (-1)
-
 static int __init call_prom(const char *service, int nargs, int nret, ...)
 {
        int i;
@@ -587,14 +597,13 @@
 {
        unsigned long offset = reloc_offset();
        ihandle elfloader;
-       int ret;
 
        elfloader = call_prom("open", 1, 1, ADDR("/packages/elf-loader"));
        if (elfloader == 0) {
                prom_printf("couldn't open /packages/elf-loader\n");
                return;
        }
-       ret = call_prom("call-method", 3, 1, ADDR("process-elf-header"),
+       call_prom("call-method", 3, 1, ADDR("process-elf-header"),
                        elfloader, ADDR(&fake_elf));
        call_prom("close", 1, 0, elfloader);
 }
@@ -646,7 +655,7 @@
            base = _ALIGN_UP(base + 0x100000, align)) {
                prom_debug("    trying: 0x%x\n\r", base);
                addr = (unsigned long)prom_claim(base, size, 0);
-               if ((int)addr != PROM_ERROR)
+               if (addr != PROM_ERROR)
                        break;
                addr = 0;
                if (align == 0)
@@ -708,7 +717,7 @@
        for(; base > RELOC(alloc_bottom); base = _ALIGN_DOWN(base - 0x100000, 
align))  {
                prom_debug("    trying: 0x%x\n\r", base);
                addr = (unsigned long)prom_claim(base, size, 0);
-               if ((int)addr != PROM_ERROR)
+               if (addr != PROM_ERROR)
                        break;
                addr = 0;
        }
@@ -902,18 +911,19 @@
 {
        unsigned long offset = reloc_offset();
        struct prom_t *_prom = PTRRELOC(&prom);
-       phandle prom_rtas, rtas_node;
+       phandle rtas_node;
+       ihandle rtas_inst;
        u32 base, entry = 0;
        u32 size = 0;
 
        prom_debug("prom_instantiate_rtas: start...\n");
 
-       prom_rtas = call_prom("finddevice", 1, 1, ADDR("/rtas"));
-       prom_debug("prom_rtas: %x\n", prom_rtas);
-       if (prom_rtas == (phandle) -1)
+       rtas_node = call_prom("finddevice", 1, 1, ADDR("/rtas"));
+       prom_debug("rtas_node: %x\n", rtas_node);
+       if (!PHANDLE_VALID(rtas_node))
                return;
 
-       prom_getprop(prom_rtas, "rtas-size", &size, sizeof(size));
+       prom_getprop(rtas_node, "rtas-size", &size, sizeof(size));
        if (size == 0)
                return;
 
@@ -922,14 +932,18 @@
                prom_printf("RTAS allocation failed !\n");
                return;
        }
-       prom_printf("instantiating rtas at 0x%x", base);
 
-       rtas_node = call_prom("open", 1, 1, ADDR("/rtas"));
-       prom_printf("...");
+       rtas_inst = call_prom("open", 1, 1, ADDR("/rtas"));
+       if (!IHANDLE_VALID(rtas_inst)) {
+               prom_printf("opening rtas package failed");
+               return;
+       }
+
+       prom_printf("instantiating rtas at 0x%x ...", base);
 
        if (call_prom("call-method", 3, 2,
                      ADDR("instantiate-rtas"),
-                     rtas_node, base) != PROM_ERROR) {
+                     rtas_inst, base) != PROM_ERROR) {
                entry = (long)_prom->args.rets[1];
        }
        if (entry == 0) {
@@ -940,8 +954,8 @@
 
        reserve_mem(base, size);
 
-       prom_setprop(prom_rtas, "linux,rtas-base", &base, sizeof(base));
-       prom_setprop(prom_rtas, "linux,rtas-entry", &entry, sizeof(entry));
+       prom_setprop(rtas_node, "linux,rtas-base", &base, sizeof(base));
+       prom_setprop(rtas_node, "linux,rtas-entry", &entry, sizeof(entry));
 
        prom_debug("rtas base     = 0x%x\n", base);
        prom_debug("rtas entry    = 0x%x\n", entry);
@@ -1062,7 +1076,7 @@
 
                prom_printf("opening PHB %s", path);
                phb_node = call_prom("open", 1, 1, path);
-               if ( (long)phb_node <= 0)
+               if (phb_node == 0)
                        prom_printf("... failed\n");
                else
                        prom_printf("... done\n");
@@ -1279,12 +1293,12 @@
 
        /* get a handle for the stdout device */
        _prom->chosen = call_prom("finddevice", 1, 1, ADDR("/chosen"));
-       if ((long)_prom->chosen <= 0)
+       if (!PHANDLE_VALID(_prom->chosen))
                prom_panic("cannot find chosen"); /* msg won't be printed :( */
 
        /* get device tree root */
        _prom->root = call_prom("finddevice", 1, 1, ADDR("/"));
-       if ((long)_prom->root <= 0)
+       if (!PHANDLE_VALID(_prom->root))
                prom_panic("cannot find device tree root"); /* msg won't be 
printed :( */
 }
 
@@ -1356,9 +1370,8 @@
        }
        /* Default to pSeries. We need to know if we are running LPAR */
        rtas = call_prom("finddevice", 1, 1, ADDR("/rtas"));
-       if (rtas != (phandle) -1) {
-               unsigned long x;
-               x = prom_getproplen(rtas, "ibm,hypertas-functions");
+       if (PHANDLE_VALID(rtas)) {
+               int x = prom_getproplen(rtas, "ibm,hypertas-functions");
                if (x != PROM_ERROR) {
                        prom_printf("Hypertas detected, assuming LPAR !\n");
                        return PLATFORM_PSERIES_LPAR;
@@ -1426,12 +1439,13 @@
                 * leave some room at the end of the path for appending extra
                 * arguments
                 */
-               if (call_prom("package-to-path", 3, 1, node, path, 
PROM_SCRATCH_SIZE-10) < 0)
+               if (call_prom("package-to-path", 3, 1, node, path,
+                             PROM_SCRATCH_SIZE-10) == PROM_ERROR)
                        continue;
                prom_printf("found display   : %s, opening ... ", path);
                
                ih = call_prom("open", 1, 1, path);
-               if (ih == (ihandle)0 || ih == (ihandle)-1) {
+               if (ih == 0) {
                        prom_printf("failed\n");
                        continue;
                }
@@ -1514,6 +1528,12 @@
        return 0;
 }
 
+/*
+ * The Open Firmware 1275 specification states properties must be 31 bytes or
+ * less, however not all firmwares obey this. Make it 64 bytes to be safe.
+ */
+#define MAX_PROPERTY_NAME 64
+
 static void __init scan_dt_build_strings(phandle node, unsigned long 
*mem_start,
                                         unsigned long *mem_end)
 {
@@ -1527,10 +1547,12 @@
        /* get and store all property names */
        prev_name = RELOC("");
        for (;;) {
-               
-               /* 32 is max len of name including nul. */
-               namep = make_room(mem_start, mem_end, 32, 1);
-               if (call_prom("nextprop", 3, 1, node, prev_name, namep) <= 0) {
+               int rc;
+
+               /* 64 is max len of name including nul. */
+               namep = make_room(mem_start, mem_end, MAX_PROPERTY_NAME, 1);
+               rc = call_prom("nextprop", 3, 1, node, prev_name, namep);
+               if (rc != 1) {
                        /* No more nodes: unwind alloc */
                        *mem_start = (unsigned long)namep;
                        break;
@@ -1555,18 +1577,12 @@
        }
 }
 
-/*
- * The Open Firmware 1275 specification states properties must be 31 bytes or
- * less, however not all firmwares obey this. Make it 64 bytes to be safe.
- */
-#define MAX_PROPERTY_NAME 64
-
 static void __init scan_dt_build_struct(phandle node, unsigned long *mem_start,
                                        unsigned long *mem_end)
 {
        int l, align;
        phandle child;
-       char *namep, *prev_name, *sstart;
+       char *namep, *prev_name, *sstart, *p, *ep;
        unsigned long soff;
        unsigned char *valp;
        unsigned long offset = reloc_offset();
@@ -1588,6 +1604,14 @@
                        call_prom("package-to-path", 3, 1, node, namep, l);
                }
                namep[l] = '\0';
+               /* Fixup an Apple bug where they have bogus \0 chars in the
+                * middle of the path in some properties
+                */
+               for (p = namep, ep = namep + l; p < ep; p++)
+                       if (*p == '\0') {
+                               memmove(p, p+1, ep - p);
+                               ep--; l--;
+                       }
                *mem_start = _ALIGN(((unsigned long) namep) + strlen(namep) + 
1, 4);
        }
 
@@ -1599,7 +1623,10 @@
        prev_name = RELOC("");
        sstart = (char *)RELOC(dt_string_start);
        for (;;) {
-               if (call_prom("nextprop", 3, 1, node, prev_name, pname) <= 0)
+               int rc;
+
+               rc = call_prom("nextprop", 3, 1, node, prev_name, pname);
+               if (rc != 1)
                        break;
 
                /* find string offset */
@@ -1615,7 +1642,7 @@
                l = call_prom("getproplen", 2, 1, node, pname);
 
                /* sanity checks */
-               if (l < 0)
+               if (l == PROM_ERROR)
                        continue;
                if (l > MAX_PROPERTY_LENGTH) {
                        prom_printf("WARNING: ignoring large property ");
@@ -1763,17 +1790,18 @@
 
        /* Some G5s have a missing interrupt definition, fix it up here */
        u3 = call_prom("finddevice", 1, 1, ADDR("/u3@0,f8000000"));
-       if ((long)u3 <= 0)
+       if (!PHANDLE_VALID(u3))
                return;
        i2c = call_prom("finddevice", 1, 1, 
ADDR("/u3@0,f8000000/i2c@f8001000"));
-       if ((long)i2c <= 0)
+       if (!PHANDLE_VALID(i2c))
                return;
        mpic = call_prom("finddevice", 1, 1, 
ADDR("/u3@0,f8000000/mpic@f8040000"));
-       if ((long)mpic <= 0)
+       if (!PHANDLE_VALID(mpic))
                return;
 
        /* check if proper rev of u3 */
-       if (prom_getprop(u3, "device-rev", &u3_rev, sizeof(u3_rev)) <= 0)
+       if (prom_getprop(u3, "device-rev", &u3_rev, sizeof(u3_rev))
+           == PROM_ERROR)
                return;
        if (u3_rev != 0x35)
                return;
@@ -1881,6 +1909,12 @@
                     &getprop_rval, sizeof(getprop_rval));
 
        /*
+        * On pSeries, inform the firmware about our capabilities
+        */
+       if (RELOC(of_platform) & PLATFORM_PSERIES)
+               prom_send_capabilities();
+
+       /*
         * On pSeries, copy the CPU hold code
         */
                if (RELOC(of_platform) & PLATFORM_PSERIES)
diff -urN linux/arch/ppc64/kernel/rtc.c linux/arch/ppc64/kernel/rtc.c
--- linux/arch/ppc64/kernel/rtc.c       2005/04/08 18:58:02     1.17
+++ linux/arch/ppc64/kernel/rtc.c       2005/06/07 13:45:29     1.18
@@ -292,47 +292,10 @@
 
 void iSeries_get_boot_time(struct rtc_time *tm)
 {
-       unsigned long time;
-       static unsigned long lastsec = 1;
-
-       u32 dataWord1 = *((u32 *)(&xSpCommArea.xBcdTimeAtIplStart));
-       u32 dataWord2 = *(((u32 *)&(xSpCommArea.xBcdTimeAtIplStart)) + 1);
-       int year = 1970;
-       int year1 = ( dataWord1 >> 24 ) & 0x000000FF;
-       int year2 = ( dataWord1 >> 16 ) & 0x000000FF;
-       int sec = ( dataWord1 >> 8 ) & 0x000000FF;
-       int min = dataWord1 & 0x000000FF;
-       int hour = ( dataWord2 >> 24 ) & 0x000000FF;
-       int day = ( dataWord2 >> 8 ) & 0x000000FF;
-       int mon = dataWord2 & 0x000000FF;
-
        if ( piranha_simulator )
                return;
 
-       BCD_TO_BIN(sec);
-       BCD_TO_BIN(min);
-       BCD_TO_BIN(hour);
-       BCD_TO_BIN(day);
-       BCD_TO_BIN(mon);
-       BCD_TO_BIN(year1);
-       BCD_TO_BIN(year2);
-       year = year1 * 100 + year2;
-
-       time = mktime(year, mon, day, hour, min, sec);
-       time += ( jiffies / HZ );
-
-       /* Now THIS is a nasty hack!
-       * It ensures that the first two calls get different answers.  
-       * That way the loop in init_time (time.c) will not think
-       * the clock is stuck.
-       */
-       if ( lastsec ) {
-               time -= lastsec;
-               --lastsec;
-       }
-
-       to_tm(time, tm); 
-       tm->tm_year -= 1900;
+       mf_get_boot_rtc(tm);
        tm->tm_mon  -= 1;
 }
 #endif
diff -urN linux/arch/ppc64/kernel/setup.c linux/arch/ppc64/kernel/setup.c
--- linux/arch/ppc64/kernel/setup.c     2005/04/08 18:58:02     1.38
+++ linux/arch/ppc64/kernel/setup.c     2005/06/07 13:45:29     1.39
@@ -103,11 +103,6 @@
 
 extern void smp_release_cpus(void);
 
-unsigned long decr_overclock = 1;
-unsigned long decr_overclock_proc0 = 1;
-unsigned long decr_overclock_set = 0;
-unsigned long decr_overclock_proc0_set = 0;
-
 int have_of = 1;
 int boot_cpuid = 0;
 int boot_cpuid_phys = 0;
@@ -1120,64 +1115,15 @@
        printk("[dump]%04x %s\n", src, msg);
 }
 
-int set_spread_lpevents( char * str )
-{
-       /* The parameter is the number of processors to share in processing lp 
events */
-       unsigned long i;
-       unsigned long val = simple_strtoul( str, NULL, 0 );
-       if ( ( val > 0 ) && ( val <= NR_CPUS ) ) {
-               for ( i=1; i<val; ++i )
-                       paca[i].lpqueue_ptr = paca[0].lpqueue_ptr;
-               printk("lpevent processing spread over %ld processors\n", val);
-       }
-       else
-               printk("invalid spreaqd_lpevents %ld\n", val);
-       return 1;
-}      
-
 /* This should only be called on processor 0 during calibrate decr */
 void setup_default_decr(void)
 {
        struct paca_struct *lpaca = get_paca();
 
-       if ( decr_overclock_set && !decr_overclock_proc0_set )
-               decr_overclock_proc0 = decr_overclock;
-
-       lpaca->default_decr = tb_ticks_per_jiffy / decr_overclock_proc0;        
+       lpaca->default_decr = tb_ticks_per_jiffy;
        lpaca->next_jiffy_update_tb = get_tb() + tb_ticks_per_jiffy;
 }
 
-int set_decr_overclock_proc0( char * str )
-{
-       unsigned long val = simple_strtoul( str, NULL, 0 );
-       if ( ( val >= 1 ) && ( val <= 48 ) ) {
-               decr_overclock_proc0_set = 1;
-               decr_overclock_proc0 = val;
-               printk("proc 0 decrementer overclock factor of %ld\n", val);
-       }
-       else
-               printk("invalid proc 0 decrementer overclock factor of %ld\n", 
val);
-       return 1;
-}
-
-int set_decr_overclock( char * str )
-{
-       unsigned long val = simple_strtoul( str, NULL, 0 );
-       if ( ( val >= 1 ) && ( val <= 48 ) ) {
-               decr_overclock_set = 1;
-               decr_overclock = val;
-               printk("decrementer overclock factor of %ld\n", val);
-       }
-       else
-               printk("invalid decrementer overclock factor of %ld\n", val);
-       return 1;
-
-}
-
-__setup("spread_lpevents=", set_spread_lpevents );
-__setup("decr_overclock_proc0=", set_decr_overclock_proc0 );
-__setup("decr_overclock=", set_decr_overclock );
-
 #ifndef CONFIG_PPC_ISERIES
 /*
  * This function can be used by platforms to "find" legacy serial ports.
diff -urN linux/arch/ppc64/kernel/smp.c linux/arch/ppc64/kernel/smp.c
--- linux/arch/ppc64/kernel/smp.c       2005/05/19 12:08:14     1.49
+++ linux/arch/ppc64/kernel/smp.c       2005/06/07 13:45:29     1.50
@@ -334,7 +334,6 @@
        }
 }
 
-extern unsigned long decr_overclock;
 extern struct gettimeofday_struct do_gtod;
 
 struct thread_info *current_set[NR_CPUS];
@@ -491,7 +490,7 @@
        if (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))
                return -EINVAL;
 
-       paca[cpu].default_decr = tb_ticks_per_jiffy / decr_overclock;
+       paca[cpu].default_decr = tb_ticks_per_jiffy;
 
        if (!cpu_has_feature(CPU_FTR_SLB)) {
                void *tmp;
diff -urN linux/arch/ppc64/kernel/sysfs.c linux/arch/ppc64/kernel/sysfs.c
--- linux/arch/ppc64/kernel/sysfs.c     2005/03/18 17:36:59     1.12
+++ linux/arch/ppc64/kernel/sysfs.c     2005/06/07 13:45:29     1.13
@@ -113,7 +113,6 @@
 #ifdef CONFIG_PPC_PSERIES
        unsigned long set, reset;
        int ret;
-       unsigned int ctrl;
 #endif /* CONFIG_PPC_PSERIES */
 
        /* Only need to enable them once */
@@ -167,11 +166,8 @@
         * On SMT machines we have to set the run latch in the ctrl register
         * in order to make PMC6 spin.
         */
-       if (cpu_has_feature(CPU_FTR_SMT)) {
-               ctrl = mfspr(CTRLF);
-               ctrl |= RUNLATCH;
-               mtspr(CTRLT, ctrl);
-       }
+       if (cpu_has_feature(CPU_FTR_SMT))
+               ppc64_runlatch_on();
 #endif /* CONFIG_PPC_PSERIES */
 }
 
diff -urN linux/arch/ppc64/kernel/time.c linux/arch/ppc64/kernel/time.c
--- linux/arch/ppc64/kernel/time.c      2005/05/19 12:08:14     1.34
+++ linux/arch/ppc64/kernel/time.c      2005/06/07 13:45:29     1.35
@@ -325,9 +325,7 @@
 
        irq_enter();
 
-#ifndef CONFIG_PPC_ISERIES
        profile_tick(CPU_PROFILING, regs);
-#endif
 
        lpaca->lppaca.int_dword.fields.decr_int = 0;
 
@@ -515,6 +513,7 @@
        do_gtod.varp = &do_gtod.vars[0];
        do_gtod.var_idx = 0;
        do_gtod.varp->tb_orig_stamp = tb_last_stamp;
+       get_paca()->next_jiffy_update_tb = tb_last_stamp + tb_ticks_per_jiffy;
        do_gtod.varp->stamp_xsec = xtime.tv_sec * XSEC_PER_SEC;
        do_gtod.tb_ticks_per_sec = tb_ticks_per_sec;
        do_gtod.varp->tb_to_xs = tb_to_xs;
diff -urN linux/arch/s390/appldata/appldata_base.c 
linux/arch/s390/appldata/appldata_base.c
--- linux/arch/s390/appldata/appldata_base.c    2005/01/25 04:28:04     1.6
+++ linux/arch/s390/appldata/appldata_base.c    2005/06/07 13:45:29     1.7
@@ -28,6 +28,7 @@
 //#include <linux/kernel_stat.h>
 #include <linux/notifier.h>
 #include <linux/cpu.h>
+#include <linux/workqueue.h>
 
 #include "appldata.h"
 
@@ -133,9 +134,12 @@
 static int appldata_timer_active;
 
 /*
- * Tasklet
+ * Work queue
  */
-static struct tasklet_struct appldata_tasklet_struct;
+static struct workqueue_struct *appldata_wq;
+static void appldata_work_fn(void *data);
+static DECLARE_WORK(appldata_work, appldata_work_fn, NULL);
+
 
 /*
  * Ops list
@@ -144,11 +148,11 @@
 static LIST_HEAD(appldata_ops_list);
 
 
-/************************* timer, tasklet, DIAG ******************************/
+/*************************** timer, work, DIAG *******************************/
 /*
  * appldata_timer_function()
  *
- * schedule tasklet and reschedule timer
+ * schedule work and reschedule timer
  */
 static void appldata_timer_function(unsigned long data, struct pt_regs *regs)
 {
@@ -157,22 +161,22 @@
                atomic_read(&appldata_expire_count));
        if (atomic_dec_and_test(&appldata_expire_count)) {
                atomic_set(&appldata_expire_count, num_online_cpus());
-               tasklet_schedule((struct tasklet_struct *) data);
+               queue_work(appldata_wq, (struct work_struct *) data);
        }
 }
 
 /*
- * appldata_tasklet_function()
+ * appldata_work_fn()
  *
  * call data gathering function for each (active) module
  */
-static void appldata_tasklet_function(unsigned long data)
+static void appldata_work_fn(void *data)
 {
        struct list_head *lh;
        struct appldata_ops *ops;
        int i;
 
-       P_DEBUG("  -= Tasklet =-\n");
+       P_DEBUG("  -= Work Queue =-\n");
        i = 0;
        spin_lock(&appldata_ops_lock);
        list_for_each(lh, &appldata_ops_list) {
@@ -231,7 +235,7 @@
                        : "=d" (ry) : "d" (&(appldata_parameter_list)) : "cc");
        return (int) ry;
 }
-/********************** timer, tasklet, DIAG <END> ***************************/
+/************************ timer, work, DIAG <END> ****************************/
 
 
 /****************************** /proc stuff **********************************/
@@ -411,7 +415,7 @@
        struct list_head *lh;
 
        found = 0;
-       spin_lock_bh(&appldata_ops_lock);
+       spin_lock(&appldata_ops_lock);
        list_for_each(lh, &appldata_ops_list) {
                tmp_ops = list_entry(lh, struct appldata_ops, list);
                if (&tmp_ops->ctl_table[2] == ctl) {
@@ -419,15 +423,15 @@
                }
        }
        if (!found) {
-               spin_unlock_bh(&appldata_ops_lock);
+               spin_unlock(&appldata_ops_lock);
                return -ENODEV;
        }
        ops = ctl->data;
        if (!try_module_get(ops->owner)) {      // protect this function
-               spin_unlock_bh(&appldata_ops_lock);
+               spin_unlock(&appldata_ops_lock);
                return -ENODEV;
        }
-       spin_unlock_bh(&appldata_ops_lock);
+       spin_unlock(&appldata_ops_lock);
 
        if (!*lenp || *ppos) {
                *lenp = 0;
@@ -451,10 +455,11 @@
                return -EFAULT;
        }
 
-       spin_lock_bh(&appldata_ops_lock);
+       spin_lock(&appldata_ops_lock);
        if ((buf[0] == '1') && (ops->active == 0)) {
-               if (!try_module_get(ops->owner)) {      // protect tasklet
-                       spin_unlock_bh(&appldata_ops_lock);
+               // protect work queue callback
+               if (!try_module_get(ops->owner)) {
+                       spin_unlock(&appldata_ops_lock);
                        module_put(ops->owner);
                        return -ENODEV;
                }
@@ -485,7 +490,7 @@
                }
                module_put(ops->owner);
        }
-       spin_unlock_bh(&appldata_ops_lock);
+       spin_unlock(&appldata_ops_lock);
 out:
        *lenp = len;
        *ppos += len;
@@ -529,7 +534,7 @@
        }
        memset(ops->ctl_table, 0, 4*sizeof(struct ctl_table));
 
-       spin_lock_bh(&appldata_ops_lock);
+       spin_lock(&appldata_ops_lock);
        list_for_each(lh, &appldata_ops_list) {
                tmp_ops = list_entry(lh, struct appldata_ops, list);
                P_DEBUG("register_ops loop: %i) name = %s, ctl = %i\n",
@@ -541,18 +546,18 @@
                                APPLDATA_PROC_NAME_LENGTH) == 0) {
                        P_ERROR("Name \"%s\" already registered!\n", ops->name);
                        kfree(ops->ctl_table);
-                       spin_unlock_bh(&appldata_ops_lock);
+                       spin_unlock(&appldata_ops_lock);
                        return -EBUSY;
                }
                if (tmp_ops->ctl_nr == ops->ctl_nr) {
                        P_ERROR("ctl_nr %i already registered!\n", ops->ctl_nr);
                        kfree(ops->ctl_table);
-                       spin_unlock_bh(&appldata_ops_lock);
+                       spin_unlock(&appldata_ops_lock);
                        return -EBUSY;
                }
        }
        list_add(&ops->list, &appldata_ops_list);
-       spin_unlock_bh(&appldata_ops_lock);
+       spin_unlock(&appldata_ops_lock);
 
        ops->ctl_table[0].ctl_name = CTL_APPLDATA;
        ops->ctl_table[0].procname = appldata_proc_name;
@@ -583,12 +588,12 @@
  */
 void appldata_unregister_ops(struct appldata_ops *ops)
 {
-       spin_lock_bh(&appldata_ops_lock);
+       spin_lock(&appldata_ops_lock);
        unregister_sysctl_table(ops->sysctl_header);
        list_del(&ops->list);
        kfree(ops->ctl_table);
        ops->ctl_table = NULL;
-       spin_unlock_bh(&appldata_ops_lock);
+       spin_unlock(&appldata_ops_lock);
        P_INFO("%s-ops unregistered!\n", ops->name);
 }
 /********************** module-ops management <END> **************************/
@@ -602,7 +607,7 @@
        init_virt_timer(&per_cpu(appldata_timer, cpu));
        per_cpu(appldata_timer, cpu).function = appldata_timer_function;
        per_cpu(appldata_timer, cpu).data = (unsigned long)
-               &appldata_tasklet_struct;
+               &appldata_work;
        atomic_inc(&appldata_expire_count);
        spin_lock(&appldata_timer_lock);
        __appldata_vtimer_setup(APPLDATA_MOD_TIMER);
@@ -615,7 +620,7 @@
        del_virt_timer(&per_cpu(appldata_timer, cpu));
        if (atomic_dec_and_test(&appldata_expire_count)) {
                atomic_set(&appldata_expire_count, num_online_cpus());
-               tasklet_schedule(&appldata_tasklet_struct);
+               queue_work(appldata_wq, &appldata_work);
        }
        spin_lock(&appldata_timer_lock);
        __appldata_vtimer_setup(APPLDATA_MOD_TIMER);
@@ -648,7 +653,7 @@
 /*
  * appldata_init()
  *
- * init timer and tasklet, register /proc entries
+ * init timer, register /proc entries
  */
 static int __init appldata_init(void)
 {
@@ -657,6 +662,12 @@
        P_DEBUG("sizeof(parameter_list) = %lu\n",
                sizeof(struct appldata_parameter_list));
 
+       appldata_wq = create_singlethread_workqueue("appldata");
+       if (!appldata_wq) {
+               P_ERROR("Could not create work queue\n");
+               return -ENOMEM;
+       }
+
        for_each_online_cpu(i)
                appldata_online_cpu(i);
 
@@ -670,7 +681,6 @@
        appldata_table[1].de->owner = THIS_MODULE;
 #endif
 
-       tasklet_init(&appldata_tasklet_struct, appldata_tasklet_function, 0);
        P_DEBUG("Base interface initialized.\n");
        return 0;
 }
@@ -678,7 +688,7 @@
 /*
  * appldata_exit()
  *
- * stop timer and tasklet, unregister /proc entries
+ * stop timer, unregister /proc entries
  */
 static void __exit appldata_exit(void)
 {
@@ -690,7 +700,7 @@
        /*
         * ops list should be empty, but just in case something went wrong...
         */
-       spin_lock_bh(&appldata_ops_lock);
+       spin_lock(&appldata_ops_lock);
        list_for_each(lh, &appldata_ops_list) {
                ops = list_entry(lh, struct appldata_ops, list);
                rc = appldata_diag(ops->record_nr, APPLDATA_STOP_REC,
@@ -700,7 +710,7 @@
                                "return code: %d\n", ops->name, rc);
                }
        }
-       spin_unlock_bh(&appldata_ops_lock);
+       spin_unlock(&appldata_ops_lock);
 
        for_each_online_cpu(i)
                appldata_offline_cpu(i);
@@ -709,7 +719,7 @@
 
        unregister_sysctl_table(appldata_sysctl_header);
 
-       tasklet_kill(&appldata_tasklet_struct);
+       destroy_workqueue(appldata_wq);
        P_DEBUG("... module unloaded!\n");
 }
 /**************************** init / exit <END> ******************************/
diff -urN linux/arch/s390/appldata/appldata_mem.c 
linux/arch/s390/appldata/appldata_mem.c
--- linux/arch/s390/appldata/appldata_mem.c     2004/10/12 14:36:34     1.3
+++ linux/arch/s390/appldata/appldata_mem.c     2005/06/07 13:45:29     1.4
@@ -68,7 +68,7 @@
        u64 pgmajfault;         /* page faults (major only) */
 // <-- New in 2.6
 
-} appldata_mem_data;
+} __attribute__((packed)) appldata_mem_data;
 
 
 static inline void appldata_debug_print(struct appldata_mem_data *mem_data)
diff -urN linux/arch/s390/appldata/appldata_net_sum.c 
linux/arch/s390/appldata/appldata_net_sum.c
--- linux/arch/s390/appldata/appldata_net_sum.c 2004/04/12 20:23:26     1.2
+++ linux/arch/s390/appldata/appldata_net_sum.c 2005/06/07 13:45:29     1.3
@@ -57,7 +57,7 @@
        u64 rx_dropped;         /* no space in linux buffers     */
        u64 tx_dropped;         /* no space available in linux   */
        u64 collisions;         /* collisions while transmitting */
-} appldata_net_sum_data;
+} __attribute__((packed)) appldata_net_sum_data;
 
 
 static inline void appldata_print_debug(struct appldata_net_sum_data *net_data)
diff -urN linux/arch/s390/appldata/appldata_os.c 
linux/arch/s390/appldata/appldata_os.c
--- linux/arch/s390/appldata/appldata_os.c      2004/07/09 02:16:47     1.3
+++ linux/arch/s390/appldata/appldata_os.c      2005/06/07 13:45:29     1.4
@@ -49,7 +49,7 @@
        u32 per_cpu_softirq;    /* ... spent in softirqs            */
        u32 per_cpu_iowait;     /* ... spent while waiting for I/O  */
 // <-- New in 2.6
-};
+} __attribute__((packed));
 
 struct appldata_os_data {
        u64 timestamp;
@@ -75,7 +75,7 @@
 
        /* per cpu data */
        struct appldata_os_per_cpu os_cpu[0];
-};
+} __attribute__((packed));
 
 static struct appldata_os_data *appldata_os_data;
 
diff -urN linux/arch/s390/kernel/ptrace.c linux/arch/s390/kernel/ptrace.c
--- linux/arch/s390/kernel/ptrace.c     2005/05/19 12:08:15     1.25
+++ linux/arch/s390/kernel/ptrace.c     2005/06/07 13:45:30     1.26
@@ -40,6 +40,7 @@
 #include <asm/pgalloc.h>
 #include <asm/system.h>
 #include <asm/uaccess.h>
+#include <asm/unistd.h>
 
 #ifdef CONFIG_S390_SUPPORT
 #include "compat_ptrace.h"
@@ -130,13 +131,19 @@
 peek_user(struct task_struct *child, addr_t addr, addr_t data)
 {
        struct user *dummy = NULL;
-       addr_t offset, tmp;
+       addr_t offset, tmp, mask;
 
        /*
         * Stupid gdb peeks/pokes the access registers in 64 bit with
         * an alignment of 4. Programmers from hell...
         */
-       if ((addr & 3) || addr > sizeof(struct user) - __ADDR_MASK)
+       mask = __ADDR_MASK;
+#ifdef CONFIG_ARCH_S390X
+       if (addr >= (addr_t) &dummy->regs.acrs &&
+           addr < (addr_t) &dummy->regs.orig_gpr2)
+               mask = 3;
+#endif
+       if ((addr & mask) || addr > sizeof(struct user) - __ADDR_MASK)
                return -EIO;
 
        if (addr < (addr_t) &dummy->regs.acrs) {
@@ -153,6 +160,16 @@
                 * access registers are stored in the thread structure
                 */
                offset = addr - (addr_t) &dummy->regs.acrs;
+#ifdef CONFIG_ARCH_S390X
+               /*
+                * Very special case: old & broken 64 bit gdb reading
+                * from acrs[15]. Result is a 64 bit value. Read the
+                * 32 bit acrs[15] value and shift it by 32. Sick...
+                */
+               if (addr == (addr_t) &dummy->regs.acrs[15])
+                       tmp = ((unsigned long) child->thread.acrs[15]) << 32;
+               else
+#endif
                tmp = *(addr_t *)((addr_t) &child->thread.acrs + offset);
 
        } else if (addr == (addr_t) &dummy->regs.orig_gpr2) {
@@ -167,6 +184,9 @@
                 */
                offset = addr - (addr_t) &dummy->regs.fp_regs;
                tmp = *(addr_t *)((addr_t) &child->thread.fp_regs + offset);
+               if (addr == (addr_t) &dummy->regs.fp_regs.fpc)
+                       tmp &= (unsigned long) FPC_VALID_MASK
+                               << (BITS_PER_LONG - 32);
 
        } else if (addr < (addr_t) (&dummy->regs.per_info + 1)) {
                /*
@@ -191,13 +211,19 @@
 poke_user(struct task_struct *child, addr_t addr, addr_t data)
 {
        struct user *dummy = NULL;
-       addr_t offset;
+       addr_t offset, mask;
 
        /*
         * Stupid gdb peeks/pokes the access registers in 64 bit with
         * an alignment of 4. Programmers from hell indeed...
         */
-       if ((addr & 3) || addr > sizeof(struct user) - __ADDR_MASK)
+       mask = __ADDR_MASK;
+#ifdef CONFIG_ARCH_S390X
+       if (addr >= (addr_t) &dummy->regs.acrs &&
+           addr < (addr_t) &dummy->regs.orig_gpr2)
+               mask = 3;
+#endif
+       if ((addr & mask) || addr > sizeof(struct user) - __ADDR_MASK)
                return -EIO;
 
        if (addr < (addr_t) &dummy->regs.acrs) {
@@ -224,6 +250,17 @@
                 * access registers are stored in the thread structure
                 */
                offset = addr - (addr_t) &dummy->regs.acrs;
+#ifdef CONFIG_ARCH_S390X
+               /*
+                * Very special case: old & broken 64 bit gdb writing
+                * to acrs[15] with a 64 bit value. Ignore the lower
+                * half of the value and write the upper 32 bit to
+                * acrs[15]. Sick...
+                */
+               if (addr == (addr_t) &dummy->regs.acrs[15])
+                       child->thread.acrs[15] = (unsigned int) (data >> 32);
+               else
+#endif
                *(addr_t *)((addr_t) &child->thread.acrs + offset) = data;
 
        } else if (addr == (addr_t) &dummy->regs.orig_gpr2) {
@@ -237,7 +274,8 @@
                 * floating point regs. are stored in the thread structure
                 */
                if (addr == (addr_t) &dummy->regs.fp_regs.fpc &&
-                   (data & ~FPC_VALID_MASK) != 0)
+                   (data & ~((unsigned long) FPC_VALID_MASK
+                             << (BITS_PER_LONG - 32))) != 0)
                        return -EINVAL;
                offset = addr - (addr_t) &dummy->regs.fp_regs;
                *(addr_t *)((addr_t) &child->thread.fp_regs + offset) = data;
@@ -723,6 +761,13 @@
                                 ? 0x80 : 0));
 
        /*
+        * If the debuffer has set an invalid system call number,
+        * we prepare to skip the system call restart handling.
+        */
+       if (!entryexit && regs->gprs[2] >= NR_syscalls)
+               regs->trap = -1;
+
+       /*
         * this isn't the same as continuing with a signal, but it will do
         * for normal use.  strace only continues with a signal if the
         * stopping signal is not SIGTRAP.  -brl
diff -urN linux/arch/s390/mm/fault.c linux/arch/s390/mm/fault.c
--- linux/arch/s390/mm/fault.c  2005/04/08 18:58:03     1.20
+++ linux/arch/s390/mm/fault.c  2005/06/07 13:45:30     1.21
@@ -207,7 +207,7 @@
         * we are not in an interrupt and that there is a 
         * user context.
         */
-        if (user_address == 0 || in_interrupt() || !mm)
+        if (user_address == 0 || in_atomic() || !mm)
                 goto no_context;
 
        /*
diff -urN linux/arch/sparc64/kernel/pci_iommu.c 
linux/arch/sparc64/kernel/pci_iommu.c
--- linux/arch/sparc64/kernel/pci_iommu.c       2005/05/26 09:12:38     1.18
+++ linux/arch/sparc64/kernel/pci_iommu.c       2005/06/07 13:45:30     1.19
@@ -196,6 +196,34 @@
        return NULL;
 }
 
+static int iommu_alloc_ctx(struct pci_iommu *iommu)
+{
+       int lowest = iommu->ctx_lowest_free;
+       int sz = IOMMU_NUM_CTXS - lowest;
+       int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest);
+
+       if (unlikely(n == sz)) {
+               n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
+               if (unlikely(n == lowest)) {
+                       printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
+                       n = 0;
+               }
+       }
+       if (n)
+               __set_bit(n, iommu->ctx_bitmap);
+
+       return n;
+}
+
+static inline void iommu_free_ctx(struct pci_iommu *iommu, int ctx)
+{
+       if (likely(ctx)) {
+               __clear_bit(ctx, iommu->ctx_bitmap);
+               if (ctx < iommu->ctx_lowest_free)
+                       iommu->ctx_lowest_free = ctx;
+       }
+}
+
 /* Allocate and map kernel buffer of size SIZE using consistent mode
  * DMA for PCI device PDEV.  Return non-NULL cpu-side address if
  * successful and set *DMA_ADDRP to the PCI side dma address.
@@ -236,7 +264,7 @@
        npages = size >> IO_PAGE_SHIFT;
        ctx = 0;
        if (iommu->iommu_ctxflush)
-               ctx = iommu->iommu_cur_ctx++;
+               ctx = iommu_alloc_ctx(iommu);
        first_page = __pa(first_page);
        while (npages--) {
                iopte_val(*iopte) = (IOPTE_CONSISTENT(ctx) |
@@ -317,6 +345,8 @@
                }
        }
 
+       iommu_free_ctx(iommu, ctx);
+
        spin_unlock_irqrestore(&iommu->lock, flags);
 
        order = get_order(size);
@@ -360,7 +390,7 @@
        base_paddr = __pa(oaddr & IO_PAGE_MASK);
        ctx = 0;
        if (iommu->iommu_ctxflush)
-               ctx = iommu->iommu_cur_ctx++;
+               ctx = iommu_alloc_ctx(iommu);
        if (strbuf->strbuf_enabled)
                iopte_protection = IOPTE_STREAMING(ctx);
        else
@@ -380,39 +410,53 @@
        return PCI_DMA_ERROR_CODE;
 }
 
-static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu 
*iommu, u32 vaddr, unsigned long ctx, unsigned long npages)
+static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu 
*iommu, u32 vaddr, unsigned long ctx, unsigned long npages, int direction)
 {
        int limit;
 
-       PCI_STC_FLUSHFLAG_INIT(strbuf);
        if (strbuf->strbuf_ctxflush &&
            iommu->iommu_ctxflush) {
                unsigned long matchreg, flushreg;
+               u64 val;
 
                flushreg = strbuf->strbuf_ctxflush;
                matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
 
-               limit = 100000;
                pci_iommu_write(flushreg, ctx);
-               for(;;) {
-                       if (((long)pci_iommu_read(matchreg)) >= 0L)
-                               break;
-                       limit--;
-                       if (!limit)
-                               break;
-                       udelay(1);
+               val = pci_iommu_read(matchreg);
+               val &= 0xffff;
+               if (!val)
+                       goto do_flush_sync;
+
+               while (val) {
+                       if (val & 0x1)
+                               pci_iommu_write(flushreg, ctx);
+                       val >>= 1;
                }
-               if (!limit)
+               val = pci_iommu_read(matchreg);
+               if (unlikely(val)) {
                        printk(KERN_WARNING "pci_strbuf_flush: ctx flush "
-                              "timeout vaddr[%08x] ctx[%lx]\n",
-                              vaddr, ctx);
+                              "timeout matchreg[%lx] ctx[%lx]\n",
+                              val, ctx);
+                       goto do_page_flush;
+               }
        } else {
                unsigned long i;
 
+       do_page_flush:
                for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
                        pci_iommu_write(strbuf->strbuf_pflush, vaddr);
        }
 
+do_flush_sync:
+       /* If the device could not have possibly put dirty data into
+        * the streaming cache, no flush-flag synchronization needs
+        * to be performed.
+        */
+       if (direction == PCI_DMA_TODEVICE)
+               return;
+
+       PCI_STC_FLUSHFLAG_INIT(strbuf);
        pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
        (void) pci_iommu_read(iommu->write_complete_reg);
 
@@ -466,7 +510,7 @@
 
        /* Step 1: Kick data out of streaming buffers if necessary. */
        if (strbuf->strbuf_enabled)
-               pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages);
+               pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, 
direction);
 
        /* Step 2: Clear out first TSB entry. */
        iopte_make_dummy(iommu, base);
@@ -474,6 +518,8 @@
        free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
                               npages, ctx);
 
+       iommu_free_ctx(iommu, ctx);
+
        spin_unlock_irqrestore(&iommu->lock, flags);
 }
 
@@ -613,7 +659,7 @@
        /* Step 4: Choose a context if necessary. */
        ctx = 0;
        if (iommu->iommu_ctxflush)
-               ctx = iommu->iommu_cur_ctx++;
+               ctx = iommu_alloc_ctx(iommu);
 
        /* Step 5: Create the mappings. */
        if (strbuf->strbuf_enabled)
@@ -678,7 +724,7 @@
 
        /* Step 1: Kick data out of streaming buffers if necessary. */
        if (strbuf->strbuf_enabled)
-               pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages);
+               pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, 
direction);
 
        /* Step 2: Clear out first TSB entry. */
        iopte_make_dummy(iommu, base);
@@ -686,6 +732,8 @@
        free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
                               npages, ctx);
 
+       iommu_free_ctx(iommu, ctx);
+
        spin_unlock_irqrestore(&iommu->lock, flags);
 }
 
@@ -724,7 +772,7 @@
        }
 
        /* Step 2: Kick data out of streaming buffers. */
-       pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages);
+       pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 
        spin_unlock_irqrestore(&iommu->lock, flags);
 }
@@ -768,7 +816,7 @@
        i--;
        npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length)
                  - bus_addr) >> IO_PAGE_SHIFT;
-       pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages);
+       pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 
        spin_unlock_irqrestore(&iommu->lock, flags);
 }
diff -urN linux/arch/sparc64/kernel/pci_psycho.c 
linux/arch/sparc64/kernel/pci_psycho.c
--- linux/arch/sparc64/kernel/pci_psycho.c      2005/04/08 18:58:04     1.36
+++ linux/arch/sparc64/kernel/pci_psycho.c      2005/06/07 13:45:30     1.37
@@ -1212,7 +1212,7 @@
 
        /* Setup initial software IOMMU state. */
        spin_lock_init(&iommu->lock);
-       iommu->iommu_cur_ctx = 0;
+       iommu->ctx_lowest_free = 1;
 
        /* Register addresses. */
        iommu->iommu_control  = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
diff -urN linux/arch/sparc64/kernel/pci_sabre.c 
linux/arch/sparc64/kernel/pci_sabre.c
--- linux/arch/sparc64/kernel/pci_sabre.c       2005/04/08 18:58:04     1.34
+++ linux/arch/sparc64/kernel/pci_sabre.c       2005/06/07 13:45:30     1.35
@@ -1265,7 +1265,7 @@
 
        /* Setup initial software IOMMU state. */
        spin_lock_init(&iommu->lock);
-       iommu->iommu_cur_ctx = 0;
+       iommu->ctx_lowest_free = 1;
 
        /* Register addresses. */
        iommu->iommu_control  = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;
diff -urN linux/arch/sparc64/kernel/pci_schizo.c 
linux/arch/sparc64/kernel/pci_schizo.c
--- linux/arch/sparc64/kernel/pci_schizo.c      2005/04/08 18:58:04     1.27
+++ linux/arch/sparc64/kernel/pci_schizo.c      2005/06/07 13:45:30     1.28
@@ -1753,7 +1753,7 @@
 
        /* Setup initial software IOMMU state. */
        spin_lock_init(&iommu->lock);
-       iommu->iommu_cur_ctx = 0;
+       iommu->ctx_lowest_free = 1;
 
        /* Register addresses, SCHIZO has iommu ctx flushing. */
        iommu->iommu_control  = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
diff -urN linux/arch/sparc64/kernel/sbus.c linux/arch/sparc64/kernel/sbus.c
--- linux/arch/sparc64/kernel/sbus.c    2005/05/26 09:12:38     1.22
+++ linux/arch/sparc64/kernel/sbus.c    2005/06/07 13:45:30     1.23
@@ -117,17 +117,25 @@
 
 #define STRBUF_TAG_VALID       0x02UL
 
-static void sbus_strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned 
long npages)
+static void sbus_strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned 
long npages, int direction)
 {
        unsigned long n;
        int limit;
 
-       iommu->strbuf_flushflag = 0UL;
        n = npages;
        while (n--)
                upa_writeq(base + (n << IO_PAGE_SHIFT),
                           iommu->strbuf_regs + STRBUF_PFLUSH);
 
+       /* If the device could not have possibly put dirty data into
+        * the streaming cache, no flush-flag synchronization needs
+        * to be performed.
+        */
+       if (direction == SBUS_DMA_TODEVICE)
+               return;
+
+       iommu->strbuf_flushflag = 0UL;
+
        /* Whoopee cushion! */
        upa_writeq(__pa(&iommu->strbuf_flushflag),
                   iommu->strbuf_regs + STRBUF_FSYNC);
@@ -421,7 +429,7 @@
 
        spin_lock_irqsave(&iommu->lock, flags);
        free_streaming_cluster(iommu, dma_base, size >> IO_PAGE_SHIFT);
-       sbus_strbuf_flush(iommu, dma_base, size >> IO_PAGE_SHIFT);
+       sbus_strbuf_flush(iommu, dma_base, size >> IO_PAGE_SHIFT, direction);
        spin_unlock_irqrestore(&iommu->lock, flags);
 }
 
@@ -584,7 +592,7 @@
        iommu = sdev->bus->iommu;
        spin_lock_irqsave(&iommu->lock, flags);
        free_streaming_cluster(iommu, dvma_base, size >> IO_PAGE_SHIFT);
-       sbus_strbuf_flush(iommu, dvma_base, size >> IO_PAGE_SHIFT);
+       sbus_strbuf_flush(iommu, dvma_base, size >> IO_PAGE_SHIFT, direction);
        spin_unlock_irqrestore(&iommu->lock, flags);
 }
 
@@ -596,7 +604,7 @@
        size = (IO_PAGE_ALIGN(base + size) - (base & IO_PAGE_MASK));
 
        spin_lock_irqsave(&iommu->lock, flags);
-       sbus_strbuf_flush(iommu, base & IO_PAGE_MASK, size >> IO_PAGE_SHIFT);
+       sbus_strbuf_flush(iommu, base & IO_PAGE_MASK, size >> IO_PAGE_SHIFT, 
direction);
        spin_unlock_irqrestore(&iommu->lock, flags);
 }
 
@@ -620,7 +628,7 @@
        size = IO_PAGE_ALIGN(sg[i].dma_address + sg[i].dma_length) - base;
 
        spin_lock_irqsave(&iommu->lock, flags);
-       sbus_strbuf_flush(iommu, base, size >> IO_PAGE_SHIFT);
+       sbus_strbuf_flush(iommu, base, size >> IO_PAGE_SHIFT, direction);
        spin_unlock_irqrestore(&iommu->lock, flags);
 }
 
diff -urN linux/arch/sparc64/kernel/setup.c linux/arch/sparc64/kernel/setup.c
--- linux/arch/sparc64/kernel/setup.c   2005/04/08 18:58:04     1.60
+++ linux/arch/sparc64/kernel/setup.c   2005/06/07 13:45:30     1.61
@@ -383,6 +383,17 @@
                /* Use PROM debug console. */
                register_console(&prom_debug_console);
                break;
+       case 'P':
+               /* Force UltraSPARC-III P-Cache on. */
+               if (tlb_type != cheetah) {
+                       printk("BOOT: Ignoring P-Cache force option.\n");
+                       break;
+               }
+               cheetah_pcache_forced_on = 1;
+               add_taint(TAINT_MACHINE_CHECK);
+               cheetah_enable_pcache();
+               break;
+
        default:
                printk("Unknown boot switch (-%c)\n", c);
                break;
diff -urN linux/arch/sparc64/kernel/smp.c linux/arch/sparc64/kernel/smp.c
--- linux/arch/sparc64/kernel/smp.c     2005/04/08 18:58:04     1.77
+++ linux/arch/sparc64/kernel/smp.c     2005/06/07 13:45:30     1.78
@@ -123,6 +123,9 @@
 
        smp_setup_percpu_timer();
 
+       if (cheetah_pcache_forced_on)
+               cheetah_enable_pcache();
+
        local_irq_enable();
 
        calibrate_delay();
diff -urN linux/arch/sparc64/kernel/traps.c linux/arch/sparc64/kernel/traps.c
--- linux/arch/sparc64/kernel/traps.c   2005/04/08 18:58:04     1.54
+++ linux/arch/sparc64/kernel/traps.c   2005/06/07 13:45:30     1.55
@@ -421,6 +421,25 @@
        }
 }
 
+int cheetah_pcache_forced_on;
+
+void cheetah_enable_pcache(void)
+{
+       unsigned long dcr;
+
+       printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
+              smp_processor_id());
+
+       __asm__ __volatile__("ldxa [%%g0] %1, %0"
+                            : "=r" (dcr)
+                            : "i" (ASI_DCU_CONTROL_REG));
+       dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
+       __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
+                            "membar #Sync"
+                            : /* no outputs */
+                            : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
+}
+
 /* Cheetah error trap handling. */
 static unsigned long ecache_flush_physbase;
 static unsigned long ecache_flush_linesize;
diff -urN linux/arch/um/Kconfig.debug linux/arch/um/Kconfig.debug
--- linux/arch/um/Kconfig.debug 2005/04/08 18:58:06     1.4
+++ linux/arch/um/Kconfig.debug 2005/06/07 13:45:30     1.5
@@ -2,10 +2,6 @@
 
 source "lib/Kconfig.debug"
 
-config FRAME_POINTER
-       bool
-       default y if DEBUG_INFO
-
 config PT_PROXY
        bool "Enable ptrace proxy"
        depends on XTERM_CHAN && DEBUG_INFO && MODE_TT
diff -urN linux/arch/um/drivers/random.c linux/arch/um/drivers/random.c
--- linux/arch/um/drivers/random.c      2005/03/18 17:37:05     1.1
+++ linux/arch/um/drivers/random.c      2005/06/07 13:45:30     1.2
@@ -1,5 +1,10 @@
-/* Much of this ripped from hw_random.c */
-
+/* Copyright (C) 2005 Jeff Dike <jdike@addtoit.com> */
+/* Much of this ripped from drivers/char/hw_random.c, see there for other
+ * copyright.
+ *
+ * This software may be used and distributed according to the terms
+ * of the GNU General Public License, incorporated herein by reference.
+ */
 #include <linux/module.h>
 #include <linux/fs.h>
 #include <linux/miscdevice.h>
@@ -12,8 +17,6 @@
  */
 #define RNG_VERSION "1.0.0"
 #define RNG_MODULE_NAME "random"
-#define RNG_DRIVER_NAME   RNG_MODULE_NAME " virtual driver " RNG_VERSION
-#define PFX RNG_MODULE_NAME ": "
 
 #define RNG_MISCDEV_MINOR              183 /* official */
 
@@ -98,7 +101,7 @@
 
        err = misc_register (&rng_miscdev);
        if (err) {
-               printk (KERN_ERR PFX "misc device register failed\n");
+               printk (KERN_ERR RNG_MODULE_NAME ": misc device register 
failed\n");
                goto err_out_cleanup_hw;
        }
 
@@ -120,3 +123,6 @@
 
 module_init (rng_init);
 module_exit (rng_cleanup);
+
+MODULE_DESCRIPTION("UML Host Random Number Generator (RNG) driver");
+MODULE_LICENSE("GPL");
diff -urN linux/arch/um/drivers/ssl.c linux/arch/um/drivers/ssl.c
--- linux/arch/um/drivers/ssl.c 2005/05/19 12:08:16     1.11
+++ linux/arch/um/drivers/ssl.c 2005/06/07 13:45:30     1.12
@@ -22,7 +22,6 @@
 #include "init.h"
 #include "irq_user.h"
 #include "mconsole_kern.h"
-#include "2_5compat.h"
 
 static int ssl_version = 1;
 
diff -urN linux/arch/um/drivers/stdio_console.c 
linux/arch/um/drivers/stdio_console.c
--- linux/arch/um/drivers/stdio_console.c       2005/05/19 12:08:16     1.14
+++ linux/arch/um/drivers/stdio_console.c       2005/06/07 13:45:30     1.15
@@ -28,7 +28,6 @@
 #include "irq_user.h"
 #include "mconsole_kern.h"
 #include "init.h"
-#include "2_5compat.h"
 
 #define MAX_TTYS (16)
 
diff -urN linux/arch/um/drivers/ubd_kern.c linux/arch/um/drivers/ubd_kern.c
--- linux/arch/um/drivers/ubd_kern.c    2005/05/26 09:12:39     1.23
+++ linux/arch/um/drivers/ubd_kern.c    2005/06/07 13:45:30     1.24
@@ -49,7 +49,6 @@
 #include "irq_user.h"
 #include "irq_kern.h"
 #include "ubd_user.h"
-#include "2_5compat.h"
 #include "os.h"
 #include "mem.h"
 #include "mem_kern.h"
@@ -440,9 +439,9 @@
 __setup("udb", udb_setup);
 __uml_help(udb_setup,
 "udb\n"
-"    This option is here solely to catch ubd -> udb typos, which can be\n\n"
-"    to impossible to catch visually unless you specifically look for\n\n"
-"    them.  The only result of any option starting with 'udb' is an error\n\n"
+"    This option is here solely to catch ubd -> udb typos, which can be\n"
+"    to impossible to catch visually unless you specifically look for\n"
+"    them.  The only result of any option starting with 'udb' is an error\n"
 "    in the boot output.\n\n"
 );
 
diff -urN linux/arch/um/include/sysrq.h linux/arch/um/include/sysrq.h
--- linux/arch/um/include/sysrq.h       2002/10/31 20:59:34     1.1
+++ linux/arch/um/include/sysrq.h       2005/06/07 13:45:30     1.2
@@ -1,6 +1,7 @@
 #ifndef __UM_SYSRQ_H
 #define __UM_SYSRQ_H
 
-extern void show_trace(unsigned long *stack);
+struct task_struct;
+extern void show_trace(struct task_struct* task, unsigned long *stack);
 
 #endif
diff -urN linux/arch/um/include/2_5compat.h linux/arch/um/include/2_5compat.h
--- linux/arch/um/include/Attic/2_5compat.h     2005-06-07 14:45:30.858883000 
+0100     1.4
+++ linux/arch/um/include/Attic/2_5compat.h     1970/01/01 00:00:00+0100
@@ -1,24 +0,0 @@
-/* 
- * Copyright (C) 2001 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-
-#ifndef __2_5_COMPAT_H__
-#define __2_5_COMPAT_H__
-
-#define INIT_HARDSECT(arr, maj, sizes)
-
-#define SET_PRI(task) do ; while(0)
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff -urN linux/arch/um/kernel/exec_kern.c linux/arch/um/kernel/exec_kern.c
--- linux/arch/um/kernel/exec_kern.c    2005/01/13 14:05:40     1.8
+++ linux/arch/um/kernel/exec_kern.c    2005/06/07 13:45:30     1.9
@@ -16,7 +16,6 @@
 #include "kern.h"
 #include "irq_user.h"
 #include "tlb.h"
-#include "2_5compat.h"
 #include "os.h"
 #include "time_user.h"
 #include "choose-mode.h"
diff -urN linux/arch/um/kernel/main.c linux/arch/um/kernel/main.c
--- linux/arch/um/kernel/main.c 2005/01/25 04:28:07     1.5
+++ linux/arch/um/kernel/main.c 2005/06/07 13:45:30     1.6
@@ -71,7 +71,7 @@
 
 static void last_ditch_exit(int sig)
 {
-       CHOOSE_MODE(kmalloc_ok = 0, (void) 0);
+        kmalloc_ok = 0;
        signal(SIGINT, SIG_DFL);
        signal(SIGTERM, SIG_DFL);
        signal(SIGHUP, SIG_DFL);
@@ -87,7 +87,7 @@
 {
        char **new_argv;
        sigset_t mask;
-       int ret, i;
+       int ret, i, err;
 
        /* Enable all signals except SIGIO - in some environments, we can
         * enter with some signals blocked
@@ -160,27 +160,29 @@
         */
        change_sig(SIGPROF, 0);
 
+        /* This signal stuff used to be in the reboot case.  However,
+         * sometimes a SIGVTALRM can come in when we're halting (reproducably
+         * when writing out gcov information, presumably because that takes
+         * some time) and cause a segfault.
+         */
+
+        /* stop timers and set SIG*ALRM to be ignored */
+        disable_timer();
+
+        /* disable SIGIO for the fds and set SIGIO to be ignored */
+        err = deactivate_all_fds();
+        if(err)
+                printf("deactivate_all_fds failed, errno = %d\n", -err);
+
+        /* Let any pending signals fire now.  This ensures
+         * that they won't be delivered after the exec, when
+         * they are definitely not expected.
+         */
+        unblock_signals();
+
        /* Reboot */
        if(ret){
-               int err;
-
                printf("\n");
-
-               /* stop timers and set SIG*ALRM to be ignored */
-               disable_timer();
-
-               /* disable SIGIO for the fds and set SIGIO to be ignored */
-               err = deactivate_all_fds();
-               if(err)
-                       printf("deactivate_all_fds failed, errno = %d\n",
-                              -err);
-
-               /* Let any pending signals fire now.  This ensures
-                * that they won't be delivered after the exec, when
-                * they are definitely not expected.
-                */
-               unblock_signals();
-
                execvp(new_argv[0], new_argv);
                perror("Failed to exec kernel");
                ret = 1;
diff -urN linux/arch/um/kernel/process_kern.c 
linux/arch/um/kernel/process_kern.c
--- linux/arch/um/kernel/process_kern.c 2005/05/19 12:08:17     1.16
+++ linux/arch/um/kernel/process_kern.c 2005/06/07 13:45:30     1.17
@@ -43,7 +43,6 @@
 #include "tlb.h"
 #include "frame_kern.h"
 #include "sigcontext.h"
-#include "2_5compat.h"
 #include "os.h"
 #include "mode.h"
 #include "mode_kern.h"
@@ -55,18 +54,6 @@
  */
 struct cpu_task cpu_tasks[NR_CPUS] = { [0 ... NR_CPUS - 1] = { -1, NULL } };
 
-struct task_struct *get_task(int pid, int require)
-{
-        struct task_struct *ret;
-
-        read_lock(&tasklist_lock);
-       ret = find_task_by_pid(pid);
-        read_unlock(&tasklist_lock);
-
-        if(require && (ret == NULL)) panic("get_task couldn't find a task\n");
-        return(ret);
-}
-
 int external_pid(void *t)
 {
        struct task_struct *task = t ? t : current;
@@ -189,7 +176,6 @@
 
        while(1){
                /* endless idle loop with no priority at all */
-               SET_PRI(current);
 
                /*
                 * although we are an idle CPU, we do not want to
@@ -212,11 +198,6 @@
        return(PAGE_SIZE);
 }
 
-unsigned long page_mask(void)
-{
-       return(PAGE_MASK);
-}
-
 void *um_virt_to_phys(struct task_struct *task, unsigned long addr, 
                      pte_t *pte_out)
 {
@@ -349,11 +330,6 @@
        return(new);
 }
 
-void *get_init_task(void)
-{
-       return(&init_thread_union.thread_info.task);
-}
-
 int copy_to_user_proc(void __user *to, void *from, int size)
 {
        return(copy_to_user(to, from, size));
@@ -480,15 +456,3 @@
        return sp & ~0xf;
 }
 #endif
-
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff -urN linux/arch/um/kernel/ptrace.c linux/arch/um/kernel/ptrace.c
--- linux/arch/um/kernel/ptrace.c       2005/05/26 09:12:39     1.15
+++ linux/arch/um/kernel/ptrace.c       2005/06/07 13:45:30     1.16
@@ -322,11 +322,9 @@
                                            UPT_SYSCALL_ARG2(regs),
                                            UPT_SYSCALL_ARG3(regs),
                                            UPT_SYSCALL_ARG4(regs));
-               else {
-                        int res = UPT_SYSCALL_RET(regs);
-                       audit_syscall_exit(current, AUDITSC_RESULT(res),
-                                           res);
-                }
+               else audit_syscall_exit(current,
+                                        AUDITSC_RESULT(UPT_SYSCALL_RET(regs)),
+                                        UPT_SYSCALL_RET(regs));
        }
 
        /* Fake a debug trap */
@@ -356,14 +354,3 @@
                current->exit_code = 0;
        }
 }
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff -urN linux/arch/um/kernel/sysrq.c linux/arch/um/kernel/sysrq.c
--- linux/arch/um/kernel/sysrq.c        2005/01/25 04:28:07     1.10
+++ linux/arch/um/kernel/sysrq.c        2005/06/07 13:45:30     1.11
@@ -3,6 +3,7 @@
  * Licensed under the GPL
  */
 
+#include "linux/config.h"
 #include "linux/sched.h"
 #include "linux/kernel.h"
 #include "linux/module.h"
@@ -12,14 +13,14 @@
 #include "sysrq.h"
 #include "user_util.h"
 
-void show_trace(unsigned long * stack)
+/* Catch non-i386 SUBARCH's. */
+#if !defined(CONFIG_UML_X86) || defined(CONFIG_64BIT)
+void show_trace(struct task_struct *task, unsigned long * stack)
 {
-       /* XXX: Copy the CONFIG_FRAME_POINTER stack-walking backtrace from
-        * arch/i386/kernel/traps.c, and then move this to sys-i386/sysrq.c.*/
         unsigned long addr;
 
         if (!stack) {
-                stack = (unsigned long*) &stack;
+               stack = (unsigned long*) &stack;
                WARN_ON(1);
        }
 
@@ -35,6 +36,7 @@
         }
         printk("\n");
 }
+#endif
 
 /*
  * stack dumps generator - this is used by arch-independent code.
@@ -44,7 +46,7 @@
 {
        unsigned long stack;
 
-       show_trace(&stack);
+       show_trace(current, &stack);
 }
 EXPORT_SYMBOL(dump_stack);
 
@@ -59,7 +61,11 @@
        int i;
 
        if (esp == NULL) {
-               if (task != current) {
+               if (task != current && task != NULL) {
+                       /* XXX: Isn't this bogus? I.e. isn't this the
+                        * *userspace* stack of this task? If not so, use this
+                        * even when task == current (as in i386).
+                        */
                        esp = (unsigned long *) KSTK_ESP(task);
                        /* Which one? No actual difference - just coding 
style.*/
                        //esp = (unsigned long *) 
PT_REGS_IP(&task->thread.regs);
@@ -77,5 +83,6 @@
                printk("%08lx ", *stack++);
        }
 
-       show_trace(esp);
+       printk("Call Trace: \n");
+       show_trace(current, esp);
 }
diff -urN linux/arch/um/kernel/trap_kern.c linux/arch/um/kernel/trap_kern.c
--- linux/arch/um/kernel/trap_kern.c    2005/05/26 09:12:39     1.11
+++ linux/arch/um/kernel/trap_kern.c    2005/06/07 13:45:30     1.12
@@ -23,7 +23,6 @@
 #include "kern.h"
 #include "chan_kern.h"
 #include "mconsole_kern.h"
-#include "2_5compat.h"
 #include "mem.h"
 #include "mem_kern.h"
 
diff -urN linux/arch/um/kernel/um_arch.c linux/arch/um/kernel/um_arch.c
--- linux/arch/um/kernel/um_arch.c      2005/05/19 12:08:17     1.14
+++ linux/arch/um/kernel/um_arch.c      2005/06/07 13:45:30     1.15
@@ -111,12 +111,6 @@
        .show   = show_cpuinfo,
 };
 
-pte_t * __bad_pagetable(void)
-{
-       panic("Someone should implement __bad_pagetable");
-       return(NULL);
-}
-
 /* Set in linux_main */
 unsigned long host_task_size;
 unsigned long task_size;
diff -urN linux/arch/um/kernel/initrd_kern.c linux/arch/um/kernel/initrd_kern.c
--- linux/arch/um/kernel/Attic/initrd_kern.c    2005-06-07 14:45:31.088491000 
+0100     1.3
+++ linux/arch/um/kernel/Attic/initrd_kern.c    1970/01/01 00:00:00+0100
@@ -1,59 +0,0 @@
-/*
- * Copyright (C) 2000, 2001, 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-
-#include "linux/init.h"
-#include "linux/bootmem.h"
-#include "linux/initrd.h"
-#include "asm/types.h"
-#include "user_util.h"
-#include "kern_util.h"
-#include "initrd.h"
-#include "init.h"
-#include "os.h"
-
-/* Changed by uml_initrd_setup, which is a setup */
-static char *initrd __initdata = NULL;
-
-static int __init read_initrd(void)
-{
-       void *area;
-       long long size;
-       int err;
-
-       if(initrd == NULL) return 0;
-       err = os_file_size(initrd, &size);
-       if(err) return 0;
-       area = alloc_bootmem(size);
-       if(area == NULL) return 0;
-       if(load_initrd(initrd, area, size) == -1) return 0;
-       initrd_start = (unsigned long) area;
-       initrd_end = initrd_start + size;
-       return 0;
-}
-
-__uml_postsetup(read_initrd);
-
-static int __init uml_initrd_setup(char *line, int *add)
-{
-       initrd = line;
-       return 0;
-}
-
-__uml_setup("initrd=", uml_initrd_setup, 
-"initrd=<initrd image>\n"
-"    This is used to boot UML from an initrd image.  The argument is the\n"
-"    name of the file containing the image.\n\n"
-);
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff -urN linux/arch/um/kernel/initrd_user.c linux/arch/um/kernel/initrd_user.c
--- linux/arch/um/kernel/Attic/initrd_user.c    2005-06-07 14:45:31.102600000 
+0100     1.3
+++ linux/arch/um/kernel/Attic/initrd_user.c    1970/01/01 00:00:00+0100
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2000, 2001 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-
-#include <unistd.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <errno.h>
-
-#include "user_util.h"
-#include "kern_util.h"
-#include "user.h"
-#include "initrd.h"
-#include "os.h"
-
-int load_initrd(char *filename, void *buf, int size)
-{
-       int fd, n;
-
-       fd = os_open_file(filename, of_read(OPENFLAGS()), 0);
-       if(fd < 0){
-               printk("Opening '%s' failed - err = %d\n", filename, -fd);
-               return(-1);
-       }
-       n = os_read_file(fd, buf, size);
-       if(n != size){
-               printk("Read of %d bytes from '%s' failed, err = %d\n", size,
-                      filename, -n);
-               return(-1);
-       }
-
-       os_close_file(fd);
-       return(0);
-}
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff -urN linux/arch/um/kernel/tt/process_kern.c 
linux/arch/um/kernel/tt/process_kern.c
--- linux/arch/um/kernel/tt/process_kern.c      2005/05/19 12:08:18     1.11
+++ linux/arch/um/kernel/tt/process_kern.c      2005/06/07 13:45:31     1.12
@@ -32,10 +32,6 @@
        unsigned long flags;
        int err, vtalrm, alrm, prof, cpu;
        char c;
-       /* jailing and SMP are incompatible, so this doesn't need to be 
-        * made per-cpu 
-        */
-       static int reading;
 
        from = prev;
        to = next;
@@ -59,13 +55,11 @@
        c = 0;
        set_current(to);
 
-       reading = 0;
        err = os_write_file(to->thread.mode.tt.switch_pipe[1], &c, sizeof(c));
        if(err != sizeof(c))
                panic("write of switch_pipe failed, err = %d", -err);
 
-       reading = 1;
-        if(from->thread.mode.tt.switch_pipe[0] == -1)
+       if(from->thread.mode.tt.switch_pipe[0] == -1)
                os_kill_process(os_getpid(), 0);
 
        err = os_read_file(from->thread.mode.tt.switch_pipe[0], &c, sizeof(c));
diff -urN linux/arch/um/sys-i386/sysrq.c linux/arch/um/sys-i386/sysrq.c
--- linux/arch/um/sys-i386/sysrq.c      2004/12/04 18:16:01     1.2
+++ linux/arch/um/sys-i386/sysrq.c      2005/06/07 13:45:31     1.3
@@ -3,12 +3,15 @@
  * Licensed under the GPL
  */
 
+#include "linux/config.h"
 #include "linux/kernel.h"
 #include "linux/smp.h"
 #include "linux/sched.h"
+#include "linux/kallsyms.h"
 #include "asm/ptrace.h"
 #include "sysrq.h"
 
+/* This is declared by <linux/sched.h> */
 void show_regs(struct pt_regs *regs)
 {
         printk("\n");
@@ -31,5 +34,80 @@
               0xffff & PT_REGS_DS(regs), 
               0xffff & PT_REGS_ES(regs));
 
-        show_trace((unsigned long *) &regs);
+        show_trace(NULL, (unsigned long *) &regs);
 }
+
+/* Copied from i386. */
+static inline int valid_stack_ptr(struct thread_info *tinfo, void *p)
+{
+       return  p > (void *)tinfo &&
+               p < (void *)tinfo + THREAD_SIZE - 3;
+}
+
+/* Adapted from i386 (we also print the address we read from). */
+static inline unsigned long print_context_stack(struct thread_info *tinfo,
+                               unsigned long *stack, unsigned long ebp)
+{
+       unsigned long addr;
+
+#ifdef CONFIG_FRAME_POINTER
+       while (valid_stack_ptr(tinfo, (void *)ebp)) {
+               addr = *(unsigned long *)(ebp + 4);
+               printk("%08lx:  [<%08lx>]", ebp + 4, addr);
+               print_symbol(" %s", addr);
+               printk("\n");
+               ebp = *(unsigned long *)ebp;
+       }
+#else
+       while (valid_stack_ptr(tinfo, stack)) {
+               addr = *stack;
+               if (__kernel_text_address(addr)) {
+                       printk("%08lx:  [<%08lx>]", (unsigned long) stack, 
addr);
+                       print_symbol(" %s", addr);
+                       printk("\n");
+               }
+               stack++;
+       }
+#endif
+       return ebp;
+}
+
+void show_trace(struct task_struct* task, unsigned long * stack)
+{
+       unsigned long ebp;
+       struct thread_info *context;
+
+       /* Turn this into BUG_ON if possible. */
+       if (!stack) {
+               stack = (unsigned long*) &stack;
+               printk("show_trace: got NULL stack, implicit assumption task == 
current");
+               WARN_ON(1);
+       }
+
+       if (!task)
+               task = current;
+
+       if (task != current) {
+               //ebp = (unsigned long) KSTK_EBP(task);
+               /* Which one? No actual difference - just coding style.*/
+               ebp = (unsigned long) PT_REGS_EBP(&task->thread.regs);
+       } else {
+               asm ("movl %%ebp, %0" : "=r" (ebp) : );
+       }
+
+       context = (struct thread_info *)
+               ((unsigned long)stack & (~(THREAD_SIZE - 1)));
+       print_context_stack(context, stack, ebp);
+
+       /*while (((long) stack & (THREAD_SIZE-1)) != 0) {
+               addr = *stack;
+               if (__kernel_text_address(addr)) {
+                       printk("%08lx:  [<%08lx>]", (unsigned long) stack, 
addr);
+                       print_symbol(" %s", addr);
+                       printk("\n");
+               }
+               stack++;
+       }*/
+       printk("\n");
+}
+
diff -urN linux/arch/um/sys-ppc/sysrq.c linux/arch/um/sys-ppc/sysrq.c
--- linux/arch/um/sys-ppc/sysrq.c       2002/10/31 20:59:34     1.1
+++ linux/arch/um/sys-ppc/sysrq.c       2005/06/07 13:45:31     1.2
@@ -27,17 +27,5 @@
                 0xffff & regs->xds, 0xffff & regs->xes);
 #endif
 
-        show_trace(&regs->gpr[1]);
+        show_trace(current, &regs->gpr[1]);
 }
-
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff -urN linux/arch/um/sys-x86_64/syscalls.c 
linux/arch/um/sys-x86_64/syscalls.c
--- linux/arch/um/sys-x86_64/syscalls.c 2005/05/26 09:12:39     1.4
+++ linux/arch/um/sys-x86_64/syscalls.c 2005/06/07 13:45:31     1.5
@@ -133,23 +133,27 @@
 
 #ifdef CONFIG_MODE_SKAS
 
+/* XXX: Must also call arch_prctl in the host, beside saving the segment 
bases! */
 static long arch_prctl_skas(int code, unsigned long addr)
 {
        long ret = 0;
 
        switch(code){
-       case ARCH_SET_GS:
-               current->thread.regs.regs.skas.regs[GS_BASE / sizeof(unsigned 
long)] = addr;
-               break;
        case ARCH_SET_FS:
                current->thread.regs.regs.skas.regs[FS_BASE / sizeof(unsigned 
long)] = addr;
                break;
+       case ARCH_SET_GS:
+               current->thread.regs.regs.skas.regs[GS_BASE / sizeof(unsigned 
long)] = addr;
+               break;
        case ARCH_GET_FS:
-               ret = put_user(current->thread.regs.regs.skas.regs[GS / 
sizeof(unsigned long)], &addr);
+               ret = put_user(current->thread.regs.regs.skas.
+                               regs[FS_BASE / sizeof(unsigned long)],
+                               (unsigned long __user *)addr);
                break;
        case ARCH_GET_GS:
-               ret = put_user(current->thread.regs.regs.skas.regs[FS / 
sizeof(unsigned \
-long)], &addr);
+               ret = put_user(current->thread.regs.regs.skas.
+                               regs[GS_BASE / sizeof(unsigned long)],
+                               (unsigned long __user *)addr);
                break;
        default:
                ret = -EINVAL;
diff -urN linux/arch/um/sys-x86_64/sysrq.c linux/arch/um/sys-x86_64/sysrq.c
--- linux/arch/um/sys-x86_64/sysrq.c    2005/02/07 02:54:39     1.2
+++ linux/arch/um/sys-x86_64/sysrq.c    2005/06/07 13:45:31     1.3
@@ -36,14 +36,5 @@
 void show_regs(struct pt_regs *regs)
 {
        __show_regs(regs);
-       show_trace((unsigned long *) &regs);
+       show_trace(current, (unsigned long *) &regs);
 }
-
-/* Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff -urN linux/arch/x86_64/Kconfig linux/arch/x86_64/Kconfig
--- linux/arch/x86_64/Kconfig   2005/05/26 09:12:39     1.44
+++ linux/arch/x86_64/Kconfig   2005/06/07 13:45:31     1.45
@@ -305,6 +305,7 @@
 
 config X86_PM_TIMER
        bool "PM timer"
+       depends on ACPI
        default y
        help
          Support the ACPI PM timer for time keeping. This is slow,
@@ -421,7 +422,7 @@
 
 config PCI_MMCONFIG
        bool "Support mmconfig PCI config space access"
-       depends on PCI
+       depends on PCI && ACPI
        select ACPI_BOOT
 
 config UNORDERED_IO
diff -urN linux/arch/x86_64/kernel/io_apic.c linux/arch/x86_64/kernel/io_apic.c
--- linux/arch/x86_64/kernel/io_apic.c  2005/05/26 09:12:40     1.35
+++ linux/arch/x86_64/kernel/io_apic.c  2005/06/07 13:45:31     1.36
@@ -37,6 +37,7 @@
 #include <asm/desc.h>
 #include <asm/proto.h>
 #include <asm/mach_apic.h>
+#include <asm/acpi.h>
 
 #define __apicdebuginit  __init
 
diff -urN linux/arch/x86_64/kernel/mpparse.c linux/arch/x86_64/kernel/mpparse.c
--- linux/arch/x86_64/kernel/mpparse.c  2005/05/26 09:12:40     1.29
+++ linux/arch/x86_64/kernel/mpparse.c  2005/06/07 13:45:31     1.30
@@ -30,6 +30,7 @@
 #include <asm/pgalloc.h>
 #include <asm/io_apic.h>
 #include <asm/proto.h>
+#include <asm/acpi.h>
 
 /* Have we found an MP table */
 int smp_found_config;
diff -urN linux/arch/x86_64/kernel/signal.c linux/arch/x86_64/kernel/signal.c
--- linux/arch/x86_64/kernel/signal.c   2005/05/26 09:12:40     1.31
+++ linux/arch/x86_64/kernel/signal.c   2005/06/07 13:45:31     1.32
@@ -28,6 +28,7 @@
 #include <asm/uaccess.h>
 #include <asm/i387.h>
 #include <asm/proto.h>
+#include <asm/ia32_unistd.h>
 
 /* #define DEBUG_SIG 1 */
 
diff -urN linux/arch/x86_64/kernel/time.c linux/arch/x86_64/kernel/time.c
--- linux/arch/x86_64/kernel/time.c     2005/05/26 09:12:40     1.37
+++ linux/arch/x86_64/kernel/time.c     2005/06/07 13:45:31     1.38
@@ -27,7 +27,9 @@
 #include <linux/bcd.h>
 #include <linux/kallsyms.h>
 #include <linux/acpi.h>
+#ifdef CONFIG_ACPI
 #include <acpi/achware.h>      /* for PM timer frequency */
+#endif
 #include <asm/8253pit.h>
 #include <asm/pgtable.h>
 #include <asm/vsyscall.h>
diff -urN linux/arch/x86_64/kernel/traps.c linux/arch/x86_64/kernel/traps.c
--- linux/arch/x86_64/kernel/traps.c    2005/04/29 11:15:05     1.43
+++ linux/arch/x86_64/kernel/traps.c    2005/06/07 13:45:31     1.44
@@ -332,10 +332,12 @@
        printk(KERN_ALERT "Kernel BUG at %.50s:%d\n", f.filename, f.line);
 } 
 
+#ifdef CONFIG_BUG
 void out_of_line_bug(void)
 { 
        BUG(); 
 } 
+#endif
 
 static DEFINE_SPINLOCK(die_lock);
 static int die_owner = -1;
diff -urN linux/arch/x86_64/kernel/x8664_ksyms.c 
linux/arch/x86_64/kernel/x8664_ksyms.c
--- linux/arch/x86_64/kernel/x8664_ksyms.c      2005/05/19 12:08:19     1.30
+++ linux/arch/x86_64/kernel/x8664_ksyms.c      2005/06/07 13:45:31     1.31
@@ -193,8 +193,9 @@
 extern void do_softirq_thunk(void);
 EXPORT_SYMBOL(do_softirq_thunk);
 
-void out_of_line_bug(void);
+#ifdef CONFIG_BUG
 EXPORT_SYMBOL(out_of_line_bug);
+#endif
 
 EXPORT_SYMBOL(init_level4_pgt);
 
diff -urN linux/drivers/acpi/Kconfig linux/drivers/acpi/Kconfig
--- linux/drivers/acpi/Kconfig  2005/04/08 18:58:08     1.24
+++ linux/drivers/acpi/Kconfig  2005/06/07 13:45:31     1.25
@@ -40,13 +40,12 @@
          available at:
          <http://www.acpi.info>
 
+if ACPI
+
 config ACPI_BOOT
        bool
-       depends on ACPI || X86_HT
        default y
 
-if ACPI
-
 config ACPI_INTERPRETER
        bool
        depends on !IA64_SGI_SN
diff -urN linux/drivers/acpi/pci_irq.c linux/drivers/acpi/pci_irq.c
--- linux/drivers/acpi/pci_irq.c        2005/04/08 18:58:08     1.26
+++ linux/drivers/acpi/pci_irq.c        2005/06/07 13:45:31     1.27
@@ -391,7 +391,6 @@
        u8                      pin = 0;
        int                     edge_level = ACPI_LEVEL_SENSITIVE;
        int                     active_high_low = ACPI_ACTIVE_LOW;
-       extern int              via_interrupt_line_quirk;
        char                    *link = NULL;
 
        ACPI_FUNCTION_TRACE("acpi_pci_irq_enable");
@@ -444,9 +443,6 @@
                }
        }
 
-       if (via_interrupt_line_quirk)
-               pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq & 15);
-
        dev->irq = acpi_register_gsi(irq, edge_level, active_high_low);
 
        printk(KERN_INFO PREFIX "PCI Interrupt %s[%c] -> ",
diff -urN linux/drivers/atm/Makefile linux/drivers/atm/Makefile
--- linux/drivers/atm/Makefile  2004/12/04 18:16:02     1.28
+++ linux/drivers/atm/Makefile  2005/06/07 13:45:31     1.29
@@ -39,7 +39,8 @@
   fore_200e-objs               += fore200e_pca_fw.o
   # guess the target endianess to choose the right PCA-200E firmware image
   ifeq ($(CONFIG_ATM_FORE200E_PCA_DEFAULT_FW),y)
-    CONFIG_ATM_FORE200E_PCA_FW = $(shell if test -n "`$(CC) -E -dM 
$(src)/../../include/asm/byteorder.h | grep ' __LITTLE_ENDIAN '`"; then echo 
$(obj)/pca200e.bin; else echo $(obj)/pca200e_ecd.bin2; fi)
+    byteorder.h                        := include$(if $(patsubst 
$(srctree),,$(objtree)),2)/asm/byteorder.h
+    CONFIG_ATM_FORE200E_PCA_FW := $(obj)/pca200e$(if $(shell $(CC) -E -dM 
$(byteorder.h) | grep ' __LITTLE_ENDIAN '),.bin,_ecd.bin2)
   endif
 endif
 
diff -urN linux/drivers/atm/fore200e.c linux/drivers/atm/fore200e.c
--- linux/drivers/atm/fore200e.c        2005/05/19 12:08:20     1.36
+++ linux/drivers/atm/fore200e.c        2005/06/07 13:45:31     1.37
@@ -383,8 +383,7 @@
     switch(fore200e->state) {
 
     case FORE200E_STATE_COMPLETE:
-       if (fore200e->stats)
-           kfree(fore200e->stats);
+       kfree(fore200e->stats);
 
     case FORE200E_STATE_IRQ:
        free_irq(fore200e->irq, fore200e->atm_dev);
@@ -963,8 +962,7 @@
                entry, txq->tail, entry->vc_map, entry->skb);
 
        /* free copy of misaligned data */
-       if (entry->data)
-           kfree(entry->data);
+       kfree(entry->data);
        
        /* remove DMA mapping */
        fore200e->bus->dma_unmap(fore200e, entry->tpd->tsd[ 0 ].buffer, 
entry->tpd->tsd[ 0 ].length,
diff -urN linux/drivers/atm/he.c linux/drivers/atm/he.c
--- linux/drivers/atm/he.c      2005/05/19 12:08:20     1.21
+++ linux/drivers/atm/he.c      2005/06/07 13:45:31     1.22
@@ -412,8 +412,7 @@
 init_one_failure:
        if (atm_dev)
                atm_dev_deregister(atm_dev);
-       if (he_dev)
-               kfree(he_dev);
+       kfree(he_dev);
        pci_disable_device(pci_dev);
        return err;
 }
@@ -2534,8 +2533,7 @@
 open_failed:
 
        if (err) {
-               if (he_vcc)
-                       kfree(he_vcc);
+               kfree(he_vcc);
                clear_bit(ATM_VF_ADDR, &vcc->flags);
        }
        else
diff -urN linux/drivers/atm/nicstar.c linux/drivers/atm/nicstar.c
--- linux/drivers/atm/nicstar.c 2005/04/08 18:58:10     1.36
+++ linux/drivers/atm/nicstar.c 2005/06/07 13:45:31     1.37
@@ -676,10 +676,10 @@
    PRINTK("nicstar%d: RSQ base at 0x%x.\n", i, (u32) card->rsq.base);
       
    /* Initialize SCQ0, the only VBR SCQ used */
-   card->scq1 = (scq_info *) NULL;
-   card->scq2 = (scq_info *) NULL;
+   card->scq1 = NULL;
+   card->scq2 = NULL;
    card->scq0 = get_scq(VBR_SCQSIZE, NS_VRSCD0);
-   if (card->scq0 == (scq_info *) NULL)
+   if (card->scq0 == NULL)
    {
       printk("nicstar%d: can't get SCQ0.\n", i);
       error = 12;
@@ -993,24 +993,24 @@
    int i;
 
    if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
-      return (scq_info *) NULL;
+      return NULL;
 
    scq = (scq_info *) kmalloc(sizeof(scq_info), GFP_KERNEL);
-   if (scq == (scq_info *) NULL)
-      return (scq_info *) NULL;
+   if (scq == NULL)
+      return NULL;
    scq->org = kmalloc(2 * size, GFP_KERNEL);
    if (scq->org == NULL)
    {
       kfree(scq);
-      return (scq_info *) NULL;
+      return NULL;
    }
    scq->skb = (struct sk_buff **) kmalloc(sizeof(struct sk_buff *) *
                                           (size / NS_SCQE_SIZE), GFP_KERNEL);
-   if (scq->skb == (struct sk_buff **) NULL)
+   if (scq->skb == NULL)
    {
       kfree(scq->org);
       kfree(scq);
-      return (scq_info *) NULL;
+      return NULL;
    }
    scq->num_entries = size / NS_SCQE_SIZE;
    scq->base = (ns_scqe *) ALIGN_ADDRESS(scq->org, size);
@@ -1498,7 +1498,7 @@
          vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
 
          scq = get_scq(CBR_SCQSIZE, vc->cbr_scd);
-         if (scq == (scq_info *) NULL)
+         if (scq == NULL)
          {
             PRINTK("nicstar%d: can't get fixed rate SCQ.\n", card->index);
             card->scd2vc[frscdi] = NULL;
diff -urN linux/drivers/atm/zatm.c linux/drivers/atm/zatm.c
--- linux/drivers/atm/zatm.c    2005/04/08 18:58:10     1.29
+++ linux/drivers/atm/zatm.c    2005/06/07 13:45:31     1.30
@@ -902,7 +902,7 @@
                zatm_dev->tx_bw += vcc->qos.txtp.min_pcr;
                dealloc_shaper(vcc->dev,zatm_vcc->shaper);
        }
-       if (zatm_vcc->ring) kfree(zatm_vcc->ring);
+       kfree(zatm_vcc->ring);
 }
 
 
@@ -1339,12 +1339,9 @@
        return 0;
     out:
        for (i = 0; i < NR_MBX; i++)
-               if (zatm_dev->mbx_start[i] != 0)
-                       kfree((void *) zatm_dev->mbx_start[i]);
-       if (zatm_dev->rx_map != NULL)
-               kfree(zatm_dev->rx_map);
-       if (zatm_dev->tx_map != NULL)
-               kfree(zatm_dev->tx_map);
+               kfree(zatm_dev->mbx_start[i]);
+       kfree(zatm_dev->rx_map);
+       kfree(zatm_dev->tx_map);
        free_irq(zatm_dev->irq, dev);
        return error;
 }
diff -urN linux/drivers/block/ub.c linux/drivers/block/ub.c
--- linux/drivers/block/ub.c    2005/04/08 18:58:10     1.8
+++ linux/drivers/block/ub.c    2005/06/07 13:45:32     1.9
@@ -8,13 +8,12 @@
  * and is not licensed separately. See file COPYING for details.
  *
  * TODO (sorted by decreasing priority)
+ *  -- Kill first_open (Al Viro fixed the block layer now)
  *  -- Do resets with usb_device_reset (needs a thread context, use khubd)
  *  -- set readonly flag for CDs, set removable flag for CF readers
  *  -- do inquiry and verify we got a disk and not a tape (for LUN mismatch)
- *  -- support pphaneuf's SDDR-75 with two LUNs (also broken capacity...)
  *  -- special case some senses, e.g. 3a/0 -> no media present, reduce retries
  *  -- verify the 13 conditions and do bulk resets
- *  -- normal pool of commands instead of cmdv[]?
  *  -- kill last_pipe and simply do two-state clearing on both pipes
  *  -- verify protocol (bulk) from USB descriptors (maybe...)
  *  -- highmem and sg
@@ -49,7 +48,14 @@
 #define US_SC_SCSI     0x06            /* Transparent */
 
 /*
+ * This many LUNs per USB device.
+ * Every one of them takes a host, see UB_MAX_HOSTS.
  */
+#define UB_MAX_LUNS   4
+
+/*
+ */
+
 #define UB_MINORS_PER_MAJOR    8
 
 #define UB_MAX_CDB_SIZE      16                /* Corresponds to Bulk */
@@ -65,7 +71,7 @@
        u32     Tag;                    /* unique per command id */
        __le32  DataTransferLength;     /* size of data */
        u8      Flags;                  /* direction in bit 0 */
-       u8      Lun;                    /* LUN normally 0 */
+       u8      Lun;                    /* LUN */
        u8      Length;                 /* of of the CDB */
        u8      CDB[UB_MAX_CDB_SIZE];   /* max command */
 };
@@ -168,6 +174,7 @@
        unsigned int len;               /* Requested length */
        // struct scatterlist sgv[UB_MAX_REQ_SG];
 
+       struct ub_lun *lun;
        void (*done)(struct ub_dev *, struct ub_scsi_cmd *);
        void *back;
 };
@@ -252,25 +259,47 @@
 };
 
 /*
- * The UB device instance.
+ * The block device instance (one per LUN).
+ */
+struct ub_lun {
+       struct ub_dev *udev;
+       struct list_head link;
+       struct gendisk *disk;
+       int id;                         /* Host index */
+       int num;                        /* LUN number */
+       char name[16];
+
+       int changed;                    /* Media was changed */
+       int removable;
+       int readonly;
+       int first_open;                 /* Kludge. See ub_bd_open. */
+
+       /* Use Ingo's mempool if or when we have more than one command. */
+       /*
+        * Currently we never need more than one command for the whole device.
+        * However, giving every LUN a command is a cheap and automatic way
+        * to enforce fairness between them.
+        */
+       int cmda[1];
+       struct ub_scsi_cmd cmdv[1];
+
+       struct ub_capacity capacity; 
+};
+
+/*
+ * The USB device instance.
  */
 struct ub_dev {
        spinlock_t lock;
-       int id;                         /* Number among ub's */
        atomic_t poison;                /* The USB device is disconnected */
        int openc;                      /* protected by ub_lock! */
                                        /* kref is too implicit for our taste */
        unsigned int tagcnt;
-       int changed;                    /* Media was changed */
-       int removable;
-       int readonly;
-       int first_open;                 /* Kludge. See ub_bd_open. */
-       char name[8];
+       char name[12];
        struct usb_device *dev;
        struct usb_interface *intf;
 
-       struct ub_capacity capacity; 
-       struct gendisk *disk;
+       struct list_head luns;
 
        unsigned int send_bulk_pipe;    /* cached pipe values */
        unsigned int recv_bulk_pipe;
@@ -279,10 +308,6 @@
 
        struct tasklet_struct tasklet;
 
-       /* XXX Use Ingo's mempool (once we have more than one) */
-       int cmda[1];
-       struct ub_scsi_cmd cmdv[1];
-
        struct ub_scsi_cmd_queue cmd_queue;
        struct ub_scsi_cmd top_rqs_cmd; /* REQUEST SENSE */
        unsigned char top_sense[UB_SENSE_SIZE];
@@ -301,9 +326,9 @@
 /*
  */
 static void ub_cleanup(struct ub_dev *sc);
-static int ub_bd_rq_fn_1(struct ub_dev *sc, struct request *rq);
-static int ub_cmd_build_block(struct ub_dev *sc, struct ub_scsi_cmd *cmd,
-    struct request *rq);
+static int ub_bd_rq_fn_1(struct ub_lun *lun, struct request *rq);
+static int ub_cmd_build_block(struct ub_dev *sc, struct ub_lun *lun,
+    struct ub_scsi_cmd *cmd, struct request *rq);
 static int ub_cmd_build_packet(struct ub_dev *sc, struct ub_scsi_cmd *cmd,
     struct request *rq);
 static void ub_rw_cmd_done(struct ub_dev *sc, struct ub_scsi_cmd *cmd);
@@ -320,8 +345,10 @@
 static int ub_submit_clear_stall(struct ub_dev *sc, struct ub_scsi_cmd *cmd,
     int stalled_pipe);
 static void ub_top_sense_done(struct ub_dev *sc, struct ub_scsi_cmd *scmd);
-static int ub_sync_tur(struct ub_dev *sc);
-static int ub_sync_read_cap(struct ub_dev *sc, struct ub_capacity *ret);
+static int ub_sync_tur(struct ub_dev *sc, struct ub_lun *lun);
+static int ub_sync_read_cap(struct ub_dev *sc, struct ub_lun *lun,
+    struct ub_capacity *ret);
+static int ub_probe_lun(struct ub_dev *sc, int lnum);
 
 /*
  */
@@ -342,6 +369,7 @@
  */
 #define UB_MAX_HOSTS  26
 static char ub_hostv[UB_MAX_HOSTS];
+
 static DEFINE_SPINLOCK(ub_lock);       /* Locks globals and ->openc */
 
 /*
@@ -406,6 +434,8 @@
 {
        struct usb_interface *intf;
        struct ub_dev *sc;
+       struct list_head *p;
+       struct ub_lun *lun;
        int cnt;
        unsigned long flags;
        int nc, nh;
@@ -421,9 +451,15 @@
        spin_lock_irqsave(&sc->lock, flags);
 
        cnt += sprintf(page + cnt,
-           "qlen %d qmax %d changed %d removable %d readonly %d\n",
-           sc->cmd_queue.qlen, sc->cmd_queue.qmax,
-           sc->changed, sc->removable, sc->readonly);
+           "qlen %d qmax %d\n",
+           sc->cmd_queue.qlen, sc->cmd_queue.qmax);
+
+       list_for_each (p, &sc->luns) {
+               lun = list_entry(p, struct ub_lun, link);
+               cnt += sprintf(page + cnt,
+                   "lun %u changed %d removable %d readonly %d\n",
+                   lun->num, lun->changed, lun->removable, lun->readonly);
+       }
 
        if ((nc = sc->tr.cur + 1) == SCMD_TRACE_SZ) nc = 0;
        for (j = 0; j < SCMD_TRACE_SZ; j++) {
@@ -523,53 +559,63 @@
  */
 static void ub_cleanup(struct ub_dev *sc)
 {
+       struct list_head *p;
+       struct ub_lun *lun;
        request_queue_t *q;
 
-       /* I don't think queue can be NULL. But... Stolen from sx8.c */
-       if ((q = sc->disk->queue) != NULL)
-               blk_cleanup_queue(q);
-
-       /*
-        * If we zero disk->private_data BEFORE put_disk, we have to check
-        * for NULL all over the place in open, release, check_media and
-        * revalidate, because the block level semaphore is well inside the
-        * put_disk. But we cannot zero after the call, because *disk is gone.
-        * The sd.c is blatantly racy in this area.
-        */
-       /* disk->private_data = NULL; */
-       put_disk(sc->disk);
-       sc->disk = NULL;
+       while (!list_empty(&sc->luns)) {
+               p = sc->luns.next;
+               lun = list_entry(p, struct ub_lun, link);
+               list_del(p);
+
+               /* I don't think queue can be NULL. But... Stolen from sx8.c */
+               if ((q = lun->disk->queue) != NULL)
+                       blk_cleanup_queue(q);
+               /*
+                * If we zero disk->private_data BEFORE put_disk, we have
+                * to check for NULL all over the place in open, release,
+                * check_media and revalidate, because the block level
+                * semaphore is well inside the put_disk.
+                * But we cannot zero after the call, because *disk is gone.
+                * The sd.c is blatantly racy in this area.
+                */
+               /* disk->private_data = NULL; */
+               put_disk(lun->disk);
+               lun->disk = NULL;
+
+               ub_id_put(lun->id);
+               kfree(lun);
+       }
 
-       ub_id_put(sc->id);
        kfree(sc);
 }
 
 /*
  * The "command allocator".
  */
-static struct ub_scsi_cmd *ub_get_cmd(struct ub_dev *sc)
+static struct ub_scsi_cmd *ub_get_cmd(struct ub_lun *lun)
 {
        struct ub_scsi_cmd *ret;
 
-       if (sc->cmda[0])
+       if (lun->cmda[0])
                return NULL;
-       ret = &sc->cmdv[0];
-       sc->cmda[0] = 1;
+       ret = &lun->cmdv[0];
+       lun->cmda[0] = 1;
        return ret;
 }
 
-static void ub_put_cmd(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+static void ub_put_cmd(struct ub_lun *lun, struct ub_scsi_cmd *cmd)
 {
-       if (cmd != &sc->cmdv[0]) {
+       if (cmd != &lun->cmdv[0]) {
                printk(KERN_WARNING "%s: releasing a foreign cmd %p\n",
-                   sc->name, cmd);
+                   lun->name, cmd);
                return;
        }
-       if (!sc->cmda[0]) {
-               printk(KERN_WARNING "%s: releasing a free cmd\n", sc->name);
+       if (!lun->cmda[0]) {
+               printk(KERN_WARNING "%s: releasing a free cmd\n", lun->name);
                return;
        }
-       sc->cmda[0] = 0;
+       lun->cmda[0] = 0;
 }
 
 /*
@@ -630,29 +676,30 @@
 
 static void ub_bd_rq_fn(request_queue_t *q)
 {
-       struct ub_dev *sc = q->queuedata;
+       struct ub_lun *lun = q->queuedata;
        struct request *rq;
 
        while ((rq = elv_next_request(q)) != NULL) {
-               if (ub_bd_rq_fn_1(sc, rq) != 0) {
+               if (ub_bd_rq_fn_1(lun, rq) != 0) {
                        blk_stop_queue(q);
                        break;
                }
        }
 }
 
-static int ub_bd_rq_fn_1(struct ub_dev *sc, struct request *rq)
+static int ub_bd_rq_fn_1(struct ub_lun *lun, struct request *rq)
 {
+       struct ub_dev *sc = lun->udev;
        struct ub_scsi_cmd *cmd;
        int rc;
 
-       if (atomic_read(&sc->poison) || sc->changed) {
+       if (atomic_read(&sc->poison) || lun->changed) {
                blkdev_dequeue_request(rq);
                ub_end_rq(rq, 0);
                return 0;
        }
 
-       if ((cmd = ub_get_cmd(sc)) == NULL)
+       if ((cmd = ub_get_cmd(lun)) == NULL)
                return -1;
        memset(cmd, 0, sizeof(struct ub_scsi_cmd));
 
@@ -661,32 +708,30 @@
        if (blk_pc_request(rq)) {
                rc = ub_cmd_build_packet(sc, cmd, rq);
        } else {
-               rc = ub_cmd_build_block(sc, cmd, rq);
+               rc = ub_cmd_build_block(sc, lun, cmd, rq);
        }
        if (rc != 0) {
-               ub_put_cmd(sc, cmd);
+               ub_put_cmd(lun, cmd);
                ub_end_rq(rq, 0);
-               blk_start_queue(sc->disk->queue);
                return 0;
        }
-
        cmd->state = UB_CMDST_INIT;
+       cmd->lun = lun;
        cmd->done = ub_rw_cmd_done;
        cmd->back = rq;
 
        cmd->tag = sc->tagcnt++;
        if ((rc = ub_submit_scsi(sc, cmd)) != 0) {
-               ub_put_cmd(sc, cmd);
+               ub_put_cmd(lun, cmd);
                ub_end_rq(rq, 0);
-               blk_start_queue(sc->disk->queue);
                return 0;
        }
 
        return 0;
 }
 
-static int ub_cmd_build_block(struct ub_dev *sc, struct ub_scsi_cmd *cmd,
-    struct request *rq)
+static int ub_cmd_build_block(struct ub_dev *sc, struct ub_lun *lun,
+    struct ub_scsi_cmd *cmd, struct request *rq)
 {
        int ub_dir;
 #if 0 /* We use rq->buffer for now */
@@ -707,7 +752,7 @@
        sg = &cmd->sgv[0];
        n_elem = blk_rq_map_sg(q, rq, sg);
        if (n_elem <= 0) {
-               ub_put_cmd(sc, cmd);
+               ub_put_cmd(lun, cmd);
                ub_end_rq(rq, 0);
                blk_start_queue(q);
                return 0;               /* request with no s/g entries? */
@@ -716,7 +761,7 @@
        if (n_elem != 1) {              /* Paranoia */
                printk(KERN_WARNING "%s: request with %d segments\n",
                    sc->name, n_elem);
-               ub_put_cmd(sc, cmd);
+               ub_put_cmd(lun, cmd);
                ub_end_rq(rq, 0);
                blk_start_queue(q);
                return 0;
@@ -748,8 +793,8 @@
         * The call to blk_queue_hardsect_size() guarantees that request
         * is aligned, but it is given in terms of 512 byte units, always.
         */
-       block = rq->sector >> sc->capacity.bshift;
-       nblks = rq->nr_sectors >> sc->capacity.bshift;
+       block = rq->sector >> lun->capacity.bshift;
+       nblks = rq->nr_sectors >> lun->capacity.bshift;
 
        cmd->cdb[0] = (ub_dir == UB_DIR_READ)? READ_10: WRITE_10;
        /* 10-byte uses 4 bytes of LBA: 2147483648KB, 2097152MB, 2048GB */
@@ -803,7 +848,8 @@
 static void ub_rw_cmd_done(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
 {
        struct request *rq = cmd->back;
-       struct gendisk *disk = sc->disk;
+       struct ub_lun *lun = cmd->lun;
+       struct gendisk *disk = lun->disk;
        request_queue_t *q = disk->queue;
        int uptodate;
 
@@ -818,7 +864,7 @@
        else
                uptodate = 0;
 
-       ub_put_cmd(sc, cmd);
+       ub_put_cmd(lun, cmd);
        ub_end_rq(rq, uptodate);
        blk_start_queue(q);
 }
@@ -887,7 +933,7 @@
        bcb->Tag = cmd->tag;            /* Endianness is not important */
        bcb->DataTransferLength = cpu_to_le32(cmd->len);
        bcb->Flags = (cmd->dir == UB_DIR_READ) ? 0x80 : 0;
-       bcb->Lun = 0;                   /* No multi-LUN yet */
+       bcb->Lun = (cmd->lun != NULL) ? cmd->lun->num : 0;
        bcb->Length = cmd->cdb_len;
 
        /* copy the command payload */
@@ -1002,9 +1048,8 @@
                         * The control pipe clears itself - nothing to do.
                         * XXX Might try to reset the device here and retry.
                         */
-                       printk(KERN_NOTICE "%s: "
-                           "stall on control pipe for device %u\n",
-                           sc->name, sc->dev->devnum);
+                       printk(KERN_NOTICE "%s: stall on control pipe\n",
+                           sc->name);
                        goto Bad_End;
                }
 
@@ -1025,9 +1070,8 @@
                         * The control pipe clears itself - nothing to do.
                         * XXX Might try to reset the device here and retry.
                         */
-                       printk(KERN_NOTICE "%s: "
-                           "stall on control pipe for device %u\n",
-                           sc->name, sc->dev->devnum);
+                       printk(KERN_NOTICE "%s: stall on control pipe\n",
+                           sc->name);
                        goto Bad_End;
                }
 
@@ -1046,9 +1090,8 @@
                        rc = ub_submit_clear_stall(sc, cmd, sc->last_pipe);
                        if (rc != 0) {
                                printk(KERN_NOTICE "%s: "
-                                   "unable to submit clear for device %u"
-                                   " (code %d)\n",
-                                   sc->name, sc->dev->devnum, rc);
+                                   "unable to submit clear (%d)\n",
+                                   sc->name, rc);
                                /*
                                 * This is typically ENOMEM or some other such 
shit.
                                 * Retrying is pointless. Just do Bad End on 
it...
@@ -1107,9 +1150,8 @@
                        rc = ub_submit_clear_stall(sc, cmd, sc->last_pipe);
                        if (rc != 0) {
                                printk(KERN_NOTICE "%s: "
-                                   "unable to submit clear for device %u"
-                                   " (code %d)\n",
-                                   sc->name, sc->dev->devnum, rc);
+                                   "unable to submit clear (%d)\n",
+                                   sc->name, rc);
                                /*
                                 * This is typically ENOMEM or some other such 
shit.
                                 * Retrying is pointless. Just do Bad End on 
it...
@@ -1140,9 +1182,8 @@
                        rc = ub_submit_clear_stall(sc, cmd, sc->last_pipe);
                        if (rc != 0) {
                                printk(KERN_NOTICE "%s: "
-                                   "unable to submit clear for device %u"
-                                   " (code %d)\n",
-                                   sc->name, sc->dev->devnum, rc);
+                                   "unable to submit clear (%d)\n",
+                                   sc->name, rc);
                                /*
                                 * This is typically ENOMEM or some other such 
shit.
                                 * Retrying is pointless. Just do Bad End on 
it...
@@ -1164,9 +1205,8 @@
                         * encounter such a thing, try to read the CSW again.
                         */
                        if (++cmd->stat_count >= 4) {
-                               printk(KERN_NOTICE "%s: "
-                                   "unable to get CSW on device %u\n",
-                                   sc->name, sc->dev->devnum);
+                               printk(KERN_NOTICE "%s: unable to get CSW\n",
+                                   sc->name);
                                goto Bad_End;
                        }
                        __ub_state_stat(sc, cmd);
@@ -1207,10 +1247,8 @@
                         */
                        if (++cmd->stat_count >= 4) {
                                printk(KERN_NOTICE "%s: "
-                                   "tag mismatch orig 0x%x reply 0x%x "
-                                   "on device %u\n",
-                                   sc->name, cmd->tag, bcs->Tag,
-                                   sc->dev->devnum);
+                                   "tag mismatch orig 0x%x reply 0x%x\n",
+                                   sc->name, cmd->tag, bcs->Tag);
                                goto Bad_End;
                        }
                        __ub_state_stat(sc, cmd);
@@ -1244,8 +1282,8 @@
 
        } else {
                printk(KERN_WARNING "%s: "
-                   "wrong command state %d on device %u\n",
-                   sc->name, cmd->state, sc->dev->devnum);
+                   "wrong command state %d\n",
+                   sc->name, cmd->state);
                goto Bad_End;
        }
        return;
@@ -1288,7 +1326,6 @@
 
        if ((rc = usb_submit_urb(&sc->work_urb, GFP_ATOMIC)) != 0) {
                /* XXX Clear stalls */
-               printk("%s: CSW #%d submit failed (%d)\n", sc->name, cmd->tag, 
rc); /* P3 */
                ub_complete(&sc->work_done);
                ub_state_done(sc, cmd, rc);
                return;
@@ -1333,6 +1370,7 @@
        scmd->state = UB_CMDST_INIT;
        scmd->data = sc->top_sense;
        scmd->len = UB_SENSE_SIZE;
+       scmd->lun = cmd->lun;
        scmd->done = ub_top_sense_done;
        scmd->back = cmd;
 
@@ -1411,14 +1449,14 @@
        }
        if (cmd != scmd->back) {
                printk(KERN_WARNING "%s: "
-                   "sense done for wrong command 0x%x on device %u\n",
-                   sc->name, cmd->tag, sc->dev->devnum);
+                   "sense done for wrong command 0x%x\n",
+                   sc->name, cmd->tag);
                return;
        }
        if (cmd->state != UB_CMDST_SENSE) {
                printk(KERN_WARNING "%s: "
-                   "sense done with bad cmd state %d on device %u\n",
-                   sc->name, cmd->state, sc->dev->devnum);
+                   "sense done with bad cmd state %d\n",
+                   sc->name, cmd->state);
                return;
        }
 
@@ -1429,68 +1467,32 @@
        ub_scsi_urb_compl(sc, cmd);
 }
 
-#if 0
-/* Determine what the maximum LUN supported is */
-int usb_stor_Bulk_max_lun(struct us_data *us)
-{
-       int result;
-
-       /* issue the command */
-       result = usb_stor_control_msg(us, us->recv_ctrl_pipe,
-                                US_BULK_GET_MAX_LUN, 
-                                USB_DIR_IN | USB_TYPE_CLASS | 
-                                USB_RECIP_INTERFACE,
-                                0, us->ifnum, us->iobuf, 1, HZ);
-
-       /* 
-        * Some devices (i.e. Iomega Zip100) need this -- apparently
-        * the bulk pipes get STALLed when the GetMaxLUN request is
-        * processed.   This is, in theory, harmless to all other devices
-        * (regardless of if they stall or not).
-        */
-       if (result < 0) {
-               usb_stor_clear_halt(us, us->recv_bulk_pipe);
-               usb_stor_clear_halt(us, us->send_bulk_pipe);
-       }
-
-       US_DEBUGP("GetMaxLUN command result is %d, data is %d\n", 
-                 result, us->iobuf[0]);
-
-       /* if we have a successful request, return the result */
-       if (result == 1)
-               return us->iobuf[0];
-
-       /* return the default -- no LUNs */
-       return 0;
-}
-#endif
-
 /*
  * This is called from a process context.
  */
-static void ub_revalidate(struct ub_dev *sc)
+static void ub_revalidate(struct ub_dev *sc, struct ub_lun *lun)
 {
 
-       sc->readonly = 0;       /* XXX Query this from the device */
+       lun->readonly = 0;      /* XXX Query this from the device */
 
-       sc->capacity.nsec = 0;
-       sc->capacity.bsize = 512;
-       sc->capacity.bshift = 0;
+       lun->capacity.nsec = 0;
+       lun->capacity.bsize = 512;
+       lun->capacity.bshift = 0;
 
-       if (ub_sync_tur(sc) != 0)
+       if (ub_sync_tur(sc, lun) != 0)
                return;                 /* Not ready */
-       sc->changed = 0;
+       lun->changed = 0;
 
-       if (ub_sync_read_cap(sc, &sc->capacity) != 0) {
+       if (ub_sync_read_cap(sc, lun, &lun->capacity) != 0) {
                /*
                 * The retry here means something is wrong, either with the
                 * device, with the transport, or with our code.
                 * We keep this because sd.c has retries for capacity.
                 */
-               if (ub_sync_read_cap(sc, &sc->capacity) != 0) {
-                       sc->capacity.nsec = 0;
-                       sc->capacity.bsize = 512;
-                       sc->capacity.bshift = 0;
+               if (ub_sync_read_cap(sc, lun, &lun->capacity) != 0) {
+                       lun->capacity.nsec = 0;
+                       lun->capacity.bsize = 512;
+                       lun->capacity.bshift = 0;
                }
        }
 }
@@ -1503,12 +1505,15 @@
 static int ub_bd_open(struct inode *inode, struct file *filp)
 {
        struct gendisk *disk = inode->i_bdev->bd_disk;
+       struct ub_lun *lun;
        struct ub_dev *sc;
        unsigned long flags;
        int rc;
 
-       if ((sc = disk->private_data) == NULL)
+       if ((lun = disk->private_data) == NULL)
                return -ENXIO;
+       sc = lun->udev;
+
        spin_lock_irqsave(&ub_lock, flags);
        if (atomic_read(&sc->poison)) {
                spin_unlock_irqrestore(&ub_lock, flags);
@@ -1529,15 +1534,15 @@
         * The bottom line is, Al Viro says that we should not allow
         * bdev->bd_invalidated to be set when doing add_disk no matter what.
         */
-       if (sc->first_open) {
-               if (sc->changed) {
-                       sc->first_open = 0;
+       if (lun->first_open) {
+               lun->first_open = 0;
+               if (lun->changed) {
                        rc = -ENOMEDIUM;
                        goto err_open;
                }
        }
 
-       if (sc->removable || sc->readonly)
+       if (lun->removable || lun->readonly)
                check_disk_change(inode->i_bdev);
 
        /*
@@ -1545,12 +1550,12 @@
         * under some pretty murky conditions (a failure of READ CAPACITY).
         * We may need it one day.
         */
-       if (sc->removable && sc->changed && !(filp->f_flags & O_NDELAY)) {
+       if (lun->removable && lun->changed && !(filp->f_flags & O_NDELAY)) {
                rc = -ENOMEDIUM;
                goto err_open;
        }
 
-       if (sc->readonly && (filp->f_mode & FMODE_WRITE)) {
+       if (lun->readonly && (filp->f_mode & FMODE_WRITE)) {
                rc = -EROFS;
                goto err_open;
        }
@@ -1567,7 +1572,8 @@
 static int ub_bd_release(struct inode *inode, struct file *filp)
 {
        struct gendisk *disk = inode->i_bdev->bd_disk;
-       struct ub_dev *sc = disk->private_data;
+       struct ub_lun *lun = disk->private_data;
+       struct ub_dev *sc = lun->udev;
 
        ub_put(sc);
        return 0;
@@ -1597,20 +1603,14 @@
  */
 static int ub_bd_revalidate(struct gendisk *disk)
 {
-       struct ub_dev *sc = disk->private_data;
+       struct ub_lun *lun = disk->private_data;
 
-       ub_revalidate(sc);
-       /* This is pretty much a long term P3 */
-       if (!atomic_read(&sc->poison)) {                /* Cover sc->dev */
-               printk(KERN_INFO "%s: device %u capacity nsec %ld bsize %u\n",
-                   sc->name, sc->dev->devnum,
-                   sc->capacity.nsec, sc->capacity.bsize);
-       }
+       ub_revalidate(lun->udev, lun);
 
        /* XXX Support sector size switching like in sr.c */
-       blk_queue_hardsect_size(disk->queue, sc->capacity.bsize);
-       set_capacity(disk, sc->capacity.nsec);
-       // set_disk_ro(sdkp->disk, sc->readonly);
+       blk_queue_hardsect_size(disk->queue, lun->capacity.bsize);
+       set_capacity(disk, lun->capacity.nsec);
+       // set_disk_ro(sdkp->disk, lun->readonly);
 
        return 0;
 }
@@ -1626,9 +1626,9 @@
  */
 static int ub_bd_media_changed(struct gendisk *disk)
 {
-       struct ub_dev *sc = disk->private_data;
+       struct ub_lun *lun = disk->private_data;
 
-       if (!sc->removable)
+       if (!lun->removable)
                return 0;
 
        /*
@@ -1640,12 +1640,12 @@
         * will fail, then block layer discards the data. Since we never
         * spin drives up, such devices simply cannot be used with ub anyway.
         */
-       if (ub_sync_tur(sc) != 0) {
-               sc->changed = 1;
+       if (ub_sync_tur(lun->udev, lun) != 0) {
+               lun->changed = 1;
                return 1;
        }
 
-       return sc->changed;
+       return lun->changed;
 }
 
 static struct block_device_operations ub_bd_fops = {
@@ -1669,7 +1669,7 @@
 /*
  * Test if the device has a check condition on it, synchronously.
  */
-static int ub_sync_tur(struct ub_dev *sc)
+static int ub_sync_tur(struct ub_dev *sc, struct ub_lun *lun)
 {
        struct ub_scsi_cmd *cmd;
        enum { ALLOC_SIZE = sizeof(struct ub_scsi_cmd) };
@@ -1688,6 +1688,7 @@
        cmd->cdb_len = 6;
        cmd->dir = UB_DIR_NONE;
        cmd->state = UB_CMDST_INIT;
+       cmd->lun = lun;                 /* This may be NULL, but that's ok */
        cmd->done = ub_probe_done;
        cmd->back = &compl;
 
@@ -1718,7 +1719,8 @@
 /*
  * Read the SCSI capacity synchronously (for probing).
  */
-static int ub_sync_read_cap(struct ub_dev *sc, struct ub_capacity *ret)
+static int ub_sync_read_cap(struct ub_dev *sc, struct ub_lun *lun,
+    struct ub_capacity *ret)
 {
        struct ub_scsi_cmd *cmd;
        char *p;
@@ -1743,6 +1745,7 @@
        cmd->state = UB_CMDST_INIT;
        cmd->data = p;
        cmd->len = 8;
+       cmd->lun = lun;
        cmd->done = ub_probe_done;
        cmd->back = &compl;
 
@@ -1812,6 +1815,90 @@
 }
 
 /*
+ * Get number of LUNs by the way of Bulk GetMaxLUN command.
+ */
+static int ub_sync_getmaxlun(struct ub_dev *sc)
+{
+       int ifnum = sc->intf->cur_altsetting->desc.bInterfaceNumber;
+       unsigned char *p;
+       enum { ALLOC_SIZE = 1 };
+       struct usb_ctrlrequest *cr;
+       struct completion compl;
+       struct timer_list timer;
+       int nluns;
+       int rc;
+
+       init_completion(&compl);
+
+       rc = -ENOMEM;
+       if ((p = kmalloc(ALLOC_SIZE, GFP_KERNEL)) == NULL)
+               goto err_alloc;
+       *p = 55;
+
+       cr = &sc->work_cr;
+       cr->bRequestType = USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE;
+       cr->bRequest = US_BULK_GET_MAX_LUN;
+       cr->wValue = cpu_to_le16(0);
+       cr->wIndex = cpu_to_le16(ifnum);
+       cr->wLength = cpu_to_le16(1);
+
+       usb_fill_control_urb(&sc->work_urb, sc->dev, sc->recv_ctrl_pipe,
+           (unsigned char*) cr, p, 1, ub_probe_urb_complete, &compl);
+       sc->work_urb.transfer_flags = 0;
+       sc->work_urb.actual_length = 0;
+       sc->work_urb.error_count = 0;
+       sc->work_urb.status = 0;
+
+       if ((rc = usb_submit_urb(&sc->work_urb, GFP_KERNEL)) != 0) {
+               if (rc == -EPIPE) {
+                       printk("%s: Stall at GetMaxLUN, using 1 LUN\n",
+                            sc->name); /* P3 */
+               } else {
+                       printk(KERN_WARNING
+                            "%s: Unable to submit GetMaxLUN (%d)\n",
+                            sc->name, rc);
+               }
+               goto err_submit;
+       }
+
+       init_timer(&timer);
+       timer.function = ub_probe_timeout;
+       timer.data = (unsigned long) &compl;
+       timer.expires = jiffies + UB_CTRL_TIMEOUT;
+       add_timer(&timer);
+
+       wait_for_completion(&compl);
+
+       del_timer_sync(&timer);
+       usb_kill_urb(&sc->work_urb);
+
+       if (sc->work_urb.actual_length != 1) {
+               printk("%s: GetMaxLUN returned %d bytes\n", sc->name,
+                   sc->work_urb.actual_length); /* P3 */
+               nluns = 0;
+       } else {
+               if ((nluns = *p) == 55) {
+                       nluns = 0;
+               } else {
+                       /* GetMaxLUN returns the maximum LUN number */
+                       nluns += 1;
+                       if (nluns > UB_MAX_LUNS)
+                               nluns = UB_MAX_LUNS;
+               }
+               printk("%s: GetMaxLUN returned %d, using %d LUNs\n", sc->name,
+                   *p, nluns); /* P3 */
+       }
+
+       kfree(p);
+       return nluns;
+
+err_submit:
+       kfree(p);
+err_alloc:
+       return rc;
+}
+
+/*
  * Clear initial stalls.
  */
 static int ub_probe_clear_stall(struct ub_dev *sc, int stalled_pipe)
@@ -1897,8 +1984,8 @@
        }
 
        if (ep_in == NULL || ep_out == NULL) {
-               printk(KERN_NOTICE "%s: device %u failed endpoint check\n",
-                   sc->name, sc->dev->devnum);
+               printk(KERN_NOTICE "%s: failed endpoint check\n",
+                   sc->name);
                return -EIO;
        }
 
@@ -1921,8 +2008,7 @@
     const struct usb_device_id *dev_id)
 {
        struct ub_dev *sc;
-       request_queue_t *q;
-       struct gendisk *disk;
+       int nluns;
        int rc;
        int i;
 
@@ -1931,6 +2017,7 @@
                goto err_core;
        memset(sc, 0, sizeof(struct ub_dev));
        spin_lock_init(&sc->lock);
+       INIT_LIST_HEAD(&sc->luns);
        usb_init_urb(&sc->work_urb);
        tasklet_init(&sc->tasklet, ub_scsi_action, (unsigned long)sc);
        atomic_set(&sc->poison, 0);
@@ -1942,19 +2029,16 @@
        ub_init_completion(&sc->work_done);
        sc->work_done.done = 1;         /* A little yuk, but oh well... */
 
-       rc = -ENOSR;
-       if ((sc->id = ub_id_get()) == -1)
-               goto err_id;
-       snprintf(sc->name, 8, DRV_NAME "%c", sc->id + 'a');
-
        sc->dev = interface_to_usbdev(intf);
        sc->intf = intf;
        // sc->ifnum = intf->cur_altsetting->desc.bInterfaceNumber;
-
        usb_set_intfdata(intf, sc);
        usb_get_dev(sc->dev);
        // usb_get_intf(sc->intf);      /* Do we need this? */
 
+       snprintf(sc->name, 12, DRV_NAME "(%d.%d)",
+           sc->dev->bus->busnum, sc->dev->devnum);
+
        /* XXX Verify that we can handle the device (from descriptors) */
 
        ub_get_pipes(sc, sc->dev, intf);
@@ -1992,35 +2076,88 @@
         * In any case it's not our business how revaliadation is implemented.
         */
        for (i = 0; i < 3; i++) {       /* Retries for benh's key */
-               if ((rc = ub_sync_tur(sc)) <= 0) break;
+               if ((rc = ub_sync_tur(sc, NULL)) <= 0) break;
                if (rc != 0x6) break;
                msleep(10);
        }
 
-       sc->removable = 1;              /* XXX Query this from the device */
-       sc->changed = 1;                /* ub_revalidate clears only */
-       sc->first_open = 1;
+       nluns = 1;
+       for (i = 0; i < 3; i++) {
+               if ((rc = ub_sync_getmaxlun(sc)) < 0) {
+                       /* 
+                        * Some devices (i.e. Iomega Zip100) need this --
+                        * apparently the bulk pipes get STALLed when the
+                        * GetMaxLUN request is processed.
+                        * XXX I have a ZIP-100, verify it does this.
+                        */
+                       if (rc == -EPIPE) {
+                               ub_probe_clear_stall(sc, sc->recv_bulk_pipe);
+                               ub_probe_clear_stall(sc, sc->send_bulk_pipe);
+                       }
+                       break;
+               }
+               if (rc != 0) {
+                       nluns = rc;
+                       break;
+               }
+               mdelay(100);
+       }
 
-       ub_revalidate(sc);
-       /* This is pretty much a long term P3 */
-       printk(KERN_INFO "%s: device %u capacity nsec %ld bsize %u\n",
-           sc->name, sc->dev->devnum, sc->capacity.nsec, sc->capacity.bsize);
+       for (i = 0; i < nluns; i++) {
+               ub_probe_lun(sc, i);
+       }
+       return 0;
+
+       /* device_remove_file(&sc->intf->dev, &dev_attr_diag); */
+err_diag:
+       usb_set_intfdata(intf, NULL);
+       // usb_put_intf(sc->intf);
+       usb_put_dev(sc->dev);
+       kfree(sc);
+err_core:
+       return rc;
+}
+
+static int ub_probe_lun(struct ub_dev *sc, int lnum)
+{
+       struct ub_lun *lun;
+       request_queue_t *q;
+       struct gendisk *disk;
+       int rc;
+
+       rc = -ENOMEM;
+       if ((lun = kmalloc(sizeof(struct ub_lun), GFP_KERNEL)) == NULL)
+               goto err_alloc;
+       memset(lun, 0, sizeof(struct ub_lun));
+       lun->num = lnum;
+
+       rc = -ENOSR;
+       if ((lun->id = ub_id_get()) == -1)
+               goto err_id;
+
+       lun->udev = sc;
+       list_add(&lun->link, &sc->luns);
+
+       snprintf(lun->name, 16, DRV_NAME "%c(%d.%d.%d)",
+           lun->id + 'a', sc->dev->bus->busnum, sc->dev->devnum, lun->num);
+
+       lun->removable = 1;             /* XXX Query this from the device */
+       lun->changed = 1;               /* ub_revalidate clears only */
+       lun->first_open = 1;
+       ub_revalidate(sc, lun);
 
-       /*
-        * Just one disk per sc currently, but maybe more.
-        */
        rc = -ENOMEM;
        if ((disk = alloc_disk(UB_MINORS_PER_MAJOR)) == NULL)
                goto err_diskalloc;
 
-       sc->disk = disk;
-       sprintf(disk->disk_name, DRV_NAME "%c", sc->id + 'a');
-       sprintf(disk->devfs_name, DEVFS_NAME "/%c", sc->id + 'a');
+       lun->disk = disk;
+       sprintf(disk->disk_name, DRV_NAME "%c", lun->id + 'a');
+       sprintf(disk->devfs_name, DEVFS_NAME "/%c", lun->id + 'a');
        disk->major = UB_MAJOR;
-       disk->first_minor = sc->id * UB_MINORS_PER_MAJOR;
+       disk->first_minor = lun->id * UB_MINORS_PER_MAJOR;
        disk->fops = &ub_bd_fops;
-       disk->private_data = sc;
-       disk->driverfs_dev = &intf->dev;
+       disk->private_data = lun;
+       disk->driverfs_dev = &sc->intf->dev;    /* XXX Many to one ok? */
 
        rc = -ENOMEM;
        if ((q = blk_init_queue(ub_bd_rq_fn, &sc->lock)) == NULL)
@@ -2028,28 +2165,17 @@
 
        disk->queue = q;
 
-        // blk_queue_bounce_limit(q, hba[i]->pdev->dma_mask);
+       blk_queue_bounce_limit(q, BLK_BOUNCE_HIGH);
        blk_queue_max_hw_segments(q, UB_MAX_REQ_SG);
        blk_queue_max_phys_segments(q, UB_MAX_REQ_SG);
-       // blk_queue_segment_boundary(q, CARM_SG_BOUNDARY);
+       blk_queue_segment_boundary(q, 0xffffffff);      /* Dubious. */
        blk_queue_max_sectors(q, UB_MAX_SECTORS);
-       blk_queue_hardsect_size(q, sc->capacity.bsize);
-
-       /*
-        * This is a serious infraction, caused by a deficiency in the
-        * USB sg interface (usb_sg_wait()). We plan to remove this once
-        * we get mileage on the driver and can justify a change to USB API.
-        * See blk_queue_bounce_limit() to understand this part.
-        *
-        * XXX And I still need to be aware of the DMA mask in the HC.
-        */
-       q->bounce_pfn = blk_max_low_pfn;
-       q->bounce_gfp = GFP_NOIO;
+       blk_queue_hardsect_size(q, lun->capacity.bsize);
 
-       q->queuedata = sc;
+       q->queuedata = lun;
 
-       set_capacity(disk, sc->capacity.nsec);
-       if (sc->removable)
+       set_capacity(disk, lun->capacity.nsec);
+       if (lun->removable)
                disk->flags |= GENHD_FL_REMOVABLE;
 
        add_disk(disk);
@@ -2059,22 +2185,20 @@
 err_blkqinit:
        put_disk(disk);
 err_diskalloc:
-       device_remove_file(&sc->intf->dev, &dev_attr_diag);
-err_diag:
-       usb_set_intfdata(intf, NULL);
-       // usb_put_intf(sc->intf);
-       usb_put_dev(sc->dev);
-       ub_id_put(sc->id);
+       list_del(&lun->link);
+       ub_id_put(lun->id);
 err_id:
-       kfree(sc);
-err_core:
+       kfree(lun);
+err_alloc:
        return rc;
 }
 
 static void ub_disconnect(struct usb_interface *intf)
 {
        struct ub_dev *sc = usb_get_intfdata(intf);
-       struct gendisk *disk = sc->disk;
+       struct list_head *p;
+       struct ub_lun *lun;
+       struct gendisk *disk;
        unsigned long flags;
 
        /*
@@ -2124,14 +2248,18 @@
        /*
         * Unregister the upper layer.
         */
-       if (disk->flags & GENHD_FL_UP)
-               del_gendisk(disk);
-       /*
-        * I wish I could do:
-        *    set_bit(QUEUE_FLAG_DEAD, &q->queue_flags);
-        * As it is, we rely on our internal poisoning and let
-        * the upper levels to spin furiously failing all the I/O.
-        */
+       list_for_each (p, &sc->luns) {
+               lun = list_entry(p, struct ub_lun, link);
+               disk = lun->disk;
+               if (disk->flags & GENHD_FL_UP)
+                       del_gendisk(disk);
+               /*
+                * I wish I could do:
+                *    set_bit(QUEUE_FLAG_DEAD, &q->queue_flags);
+                * As it is, we rely on our internal poisoning and let
+                * the upper levels to spin furiously failing all the I/O.
+                */
+       }
 
        /*
         * Taking a lock on a structure which is about to be freed
@@ -2182,8 +2310,8 @@
 {
        int rc;
 
-       /* P3 */ printk("ub: sizeof ub_scsi_cmd %zu ub_dev %zu\n",
-                       sizeof(struct ub_scsi_cmd), sizeof(struct ub_dev));
+       /* P3 */ printk("ub: sizeof ub_scsi_cmd %zu ub_dev %zu ub_lun %zu\n",
+                       sizeof(struct ub_scsi_cmd), sizeof(struct ub_dev), 
sizeof(struct ub_lun));
 
        if ((rc = register_blkdev(UB_MAJOR, DRV_NAME)) != 0)
                goto err_regblkdev;
diff -urN linux/drivers/cdrom/viocd.c linux/drivers/cdrom/viocd.c
--- linux/drivers/cdrom/viocd.c 2005/02/07 02:54:43     1.8
+++ linux/drivers/cdrom/viocd.c 2005/06/07 13:45:32     1.9
@@ -488,6 +488,20 @@
                                         & (CDC_DVD_RAM | CDC_RAM)) != 0;
                }
                break;
+       case GPCMD_GET_CONFIGURATION:
+               if (cgc->cmd[3] == CDF_RWRT) {
+                       struct rwrt_feature_desc *rfd = (struct 
rwrt_feature_desc *)(cgc->buffer + sizeof(struct feature_header));
+
+                       if ((buflen >=
+                            (sizeof(struct feature_header) + sizeof(*rfd))) &&
+                           (cdi->ops->capability & ~cdi->mask
+                            & (CDC_DVD_RAM | CDC_RAM))) {
+                               rfd->feature_code = cpu_to_be16(CDF_RWRT);
+                               rfd->curr = 1;
+                               ret = 0;
+                       }
+               }
+               break;
        default:
                if (cgc->sense) {
                        /* indicate Unknown code */
diff -urN linux/drivers/char/ipmi/ipmi_devintf.c 
linux/drivers/char/ipmi/ipmi_devintf.c
--- linux/drivers/char/ipmi/ipmi_devintf.c      2005/05/26 09:12:40     1.13
+++ linux/drivers/char/ipmi/ipmi_devintf.c      2005/06/07 13:45:32     1.14
@@ -520,7 +520,7 @@
                 " interface.  Other values will set the major device number"
                 " to that value.");
 
-static struct class *ipmi_class;
+static struct class_simple *ipmi_class;
 
 static void ipmi_new_smi(int if_num)
 {
@@ -534,7 +534,7 @@
 
 static void ipmi_smi_gone(int if_num)
 {
-       class_simple_device_remove(ipmi_class, MKDEV(ipmi_major, if_num));
+       class_simple_device_remove(MKDEV(ipmi_major, if_num));
        devfs_remove("ipmidev/%d", if_num);
 }
 
diff -urN linux/drivers/cpufreq/cpufreq_conservative.c 
linux/drivers/cpufreq/cpufreq_conservative.c
--- linux/drivers/cpufreq/cpufreq_conservative.c        1970/01/01 00:00:00
+++ linux/drivers/cpufreq/cpufreq_conservative.c        2005-06-07 
14:45:32.380205000 +0100     1.1
@@ -0,0 +1,586 @@
+/*
+ *  drivers/cpufreq/cpufreq_conservative.c
+ *
+ *  Copyright (C)  2001 Russell King
+ *            (C)  2003 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>.
+ *                      Jun Nakajima <jun.nakajima@intel.com>
+ *            (C)  2004 Alexander Clouter <alex-kernel@digriz.org.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/smp.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/ctype.h>
+#include <linux/cpufreq.h>
+#include <linux/sysctl.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/sysfs.h>
+#include <linux/sched.h>
+#include <linux/kmod.h>
+#include <linux/workqueue.h>
+#include <linux/jiffies.h>
+#include <linux/kernel_stat.h>
+#include <linux/percpu.h>
+
+/*
+ * dbs is used in this file as a shortform for demandbased switching
+ * It helps to keep variable names smaller, simpler
+ */
+
+#define DEF_FREQUENCY_UP_THRESHOLD             (80)
+#define MIN_FREQUENCY_UP_THRESHOLD             (0)
+#define MAX_FREQUENCY_UP_THRESHOLD             (100)
+
+#define DEF_FREQUENCY_DOWN_THRESHOLD           (20)
+#define MIN_FREQUENCY_DOWN_THRESHOLD           (0)
+#define MAX_FREQUENCY_DOWN_THRESHOLD           (100)
+
+/* 
+ * The polling frequency of this governor depends on the capability of 
+ * the processor. Default polling frequency is 1000 times the transition
+ * latency of the processor. The governor will work on any processor with 
+ * transition latency <= 10mS, using appropriate sampling 
+ * rate.
+ * For CPUs with transition latency > 10mS (mostly drivers with 
CPUFREQ_ETERNAL)
+ * this governor will not work.
+ * All times here are in uS.
+ */
+static unsigned int                            def_sampling_rate;
+#define MIN_SAMPLING_RATE                      (def_sampling_rate / 2)
+#define MAX_SAMPLING_RATE                      (500 * def_sampling_rate)
+#define DEF_SAMPLING_RATE_LATENCY_MULTIPLIER   (100000)
+#define DEF_SAMPLING_DOWN_FACTOR               (5)
+#define TRANSITION_LATENCY_LIMIT               (10 * 1000)
+
+static void do_dbs_timer(void *data);
+
+struct cpu_dbs_info_s {
+       struct cpufreq_policy   *cur_policy;
+       unsigned int            prev_cpu_idle_up;
+       unsigned int            prev_cpu_idle_down;
+       unsigned int            enable;
+};
+static DEFINE_PER_CPU(struct cpu_dbs_info_s, cpu_dbs_info);
+
+static unsigned int dbs_enable;        /* number of CPUs using this policy */
+
+static DECLARE_MUTEX   (dbs_sem);
+static DECLARE_WORK    (dbs_work, do_dbs_timer, NULL);
+
+struct dbs_tuners {
+       unsigned int            sampling_rate;
+       unsigned int            sampling_down_factor;
+       unsigned int            up_threshold;
+       unsigned int            down_threshold;
+       unsigned int            ignore_nice;
+       unsigned int            freq_step;
+};
+
+static struct dbs_tuners dbs_tuners_ins = {
+       .up_threshold           = DEF_FREQUENCY_UP_THRESHOLD,
+       .down_threshold         = DEF_FREQUENCY_DOWN_THRESHOLD,
+       .sampling_down_factor   = DEF_SAMPLING_DOWN_FACTOR,
+};
+
+static inline unsigned int get_cpu_idle_time(unsigned int cpu)
+{
+       return  kstat_cpu(cpu).cpustat.idle +
+               kstat_cpu(cpu).cpustat.iowait +
+               ( !dbs_tuners_ins.ignore_nice ? 
+                 kstat_cpu(cpu).cpustat.nice :
+                 0);
+}
+
+/************************** sysfs interface ************************/
+static ssize_t show_sampling_rate_max(struct cpufreq_policy *policy, char *buf)
+{
+       return sprintf (buf, "%u\n", MAX_SAMPLING_RATE);
+}
+
+static ssize_t show_sampling_rate_min(struct cpufreq_policy *policy, char *buf)
+{
+       return sprintf (buf, "%u\n", MIN_SAMPLING_RATE);
+}
+
+#define define_one_ro(_name)                                   \
+static struct freq_attr _name =                                \
+__ATTR(_name, 0444, show_##_name, NULL)
+
+define_one_ro(sampling_rate_max);
+define_one_ro(sampling_rate_min);
+
+/* cpufreq_conservative Governor Tunables */
+#define show_one(file_name, object)                                    \
+static ssize_t show_##file_name                                                
\
+(struct cpufreq_policy *unused, char *buf)                             \
+{                                                                      \
+       return sprintf(buf, "%u\n", dbs_tuners_ins.object);             \
+}
+show_one(sampling_rate, sampling_rate);
+show_one(sampling_down_factor, sampling_down_factor);
+show_one(up_threshold, up_threshold);
+show_one(down_threshold, down_threshold);
+show_one(ignore_nice, ignore_nice);
+show_one(freq_step, freq_step);
+
+static ssize_t store_sampling_down_factor(struct cpufreq_policy *unused, 
+               const char *buf, size_t count)
+{
+       unsigned int input;
+       int ret;
+       ret = sscanf (buf, "%u", &input);
+       if (ret != 1 )
+               return -EINVAL;
+
+       down(&dbs_sem);
+       dbs_tuners_ins.sampling_down_factor = input;
+       up(&dbs_sem);
+
+       return count;
+}
+
+static ssize_t store_sampling_rate(struct cpufreq_policy *unused, 
+               const char *buf, size_t count)
+{
+       unsigned int input;
+       int ret;
+       ret = sscanf (buf, "%u", &input);
+
+       down(&dbs_sem);
+       if (ret != 1 || input > MAX_SAMPLING_RATE || input < MIN_SAMPLING_RATE) 
{
+               up(&dbs_sem);
+               return -EINVAL;
+       }
+
+       dbs_tuners_ins.sampling_rate = input;
+       up(&dbs_sem);
+
+       return count;
+}
+
+static ssize_t store_up_threshold(struct cpufreq_policy *unused, 
+               const char *buf, size_t count)
+{
+       unsigned int input;
+       int ret;
+       ret = sscanf (buf, "%u", &input);
+
+       down(&dbs_sem);
+       if (ret != 1 || input > MAX_FREQUENCY_UP_THRESHOLD || 
+                       input < MIN_FREQUENCY_UP_THRESHOLD ||
+                       input <= dbs_tuners_ins.down_threshold) {
+               up(&dbs_sem);
+               return -EINVAL;
+       }
+
+       dbs_tuners_ins.up_threshold = input;
+       up(&dbs_sem);
+
+       return count;
+}
+
+static ssize_t store_down_threshold(struct cpufreq_policy *unused, 
+               const char *buf, size_t count)
+{
+       unsigned int input;
+       int ret;
+       ret = sscanf (buf, "%u", &input);
+
+       down(&dbs_sem);
+       if (ret != 1 || input > MAX_FREQUENCY_DOWN_THRESHOLD || 
+                       input < MIN_FREQUENCY_DOWN_THRESHOLD ||
+                       input >= dbs_tuners_ins.up_threshold) {
+               up(&dbs_sem);
+               return -EINVAL;
+       }
+
+       dbs_tuners_ins.down_threshold = input;
+       up(&dbs_sem);
+
+       return count;
+}
+
+static ssize_t store_ignore_nice(struct cpufreq_policy *policy,
+               const char *buf, size_t count)
+{
+       unsigned int input;
+       int ret;
+
+       unsigned int j;
+       
+       ret = sscanf (buf, "%u", &input);
+       if ( ret != 1 )
+               return -EINVAL;
+
+       if ( input > 1 )
+               input = 1;
+       
+       down(&dbs_sem);
+       if ( input == dbs_tuners_ins.ignore_nice ) { /* nothing to do */
+               up(&dbs_sem);
+               return count;
+       }
+       dbs_tuners_ins.ignore_nice = input;
+
+       /* we need to re-evaluate prev_cpu_idle_up and prev_cpu_idle_down */
+       for_each_online_cpu(j) {
+               struct cpu_dbs_info_s *j_dbs_info;
+               j_dbs_info = &per_cpu(cpu_dbs_info, j);
+               j_dbs_info->prev_cpu_idle_up = get_cpu_idle_time(j);
+               j_dbs_info->prev_cpu_idle_down = j_dbs_info->prev_cpu_idle_up;
+       }
+       up(&dbs_sem);
+
+       return count;
+}
+
+static ssize_t store_freq_step(struct cpufreq_policy *policy,
+               const char *buf, size_t count)
+{
+       unsigned int input;
+       int ret;
+
+       ret = sscanf (buf, "%u", &input);
+
+       if ( ret != 1 )
+               return -EINVAL;
+
+       if ( input > 100 )
+               input = 100;
+       
+       /* no need to test here if freq_step is zero as the user might actually
+        * want this, they would be crazy though :) */
+       down(&dbs_sem);
+       dbs_tuners_ins.freq_step = input;
+       up(&dbs_sem);
+
+       return count;
+}
+
+#define define_one_rw(_name) \
+static struct freq_attr _name = \
+__ATTR(_name, 0644, show_##_name, store_##_name)
+
+define_one_rw(sampling_rate);
+define_one_rw(sampling_down_factor);
+define_one_rw(up_threshold);
+define_one_rw(down_threshold);
+define_one_rw(ignore_nice);
+define_one_rw(freq_step);
+
+static struct attribute * dbs_attributes[] = {
+       &sampling_rate_max.attr,
+       &sampling_rate_min.attr,
+       &sampling_rate.attr,
+       &sampling_down_factor.attr,
+       &up_threshold.attr,
+       &down_threshold.attr,
+       &ignore_nice.attr,
+       &freq_step.attr,
+       NULL
+};
+
+static struct attribute_group dbs_attr_group = {
+       .attrs = dbs_attributes,
+       .name = "conservative",
+};
+
+/************************** sysfs end ************************/
+
+static void dbs_check_cpu(int cpu)
+{
+       unsigned int idle_ticks, up_idle_ticks, down_idle_ticks;
+       unsigned int freq_step;
+       unsigned int freq_down_sampling_rate;
+       static int down_skip[NR_CPUS];
+       static int requested_freq[NR_CPUS];
+       static unsigned short init_flag = 0;
+       struct cpu_dbs_info_s *this_dbs_info;
+       struct cpu_dbs_info_s *dbs_info;
+
+       struct cpufreq_policy *policy;
+       unsigned int j;
+
+       this_dbs_info = &per_cpu(cpu_dbs_info, cpu);
+       if (!this_dbs_info->enable)
+               return;
+
+       policy = this_dbs_info->cur_policy;
+
+       if ( init_flag == 0 ) {
+               for ( /* NULL */; init_flag < NR_CPUS; init_flag++ ) {
+                       dbs_info = &per_cpu(cpu_dbs_info, init_flag);
+                       requested_freq[cpu] = dbs_info->cur_policy->cur;
+               }
+               init_flag = 1;
+       }
+       
+       /* 
+        * The default safe range is 20% to 80% 
+        * Every sampling_rate, we check
+        *      - If current idle time is less than 20%, then we try to 
+        *        increase frequency
+        * Every sampling_rate*sampling_down_factor, we check
+        *      - If current idle time is more than 80%, then we try to
+        *        decrease frequency
+        *
+        * Any frequency increase takes it to the maximum frequency. 
+        * Frequency reduction happens at minimum steps of 
+        * 5% (default) of max_frequency 
+        */
+
+       /* Check for frequency increase */
+
+       idle_ticks = UINT_MAX;
+       for_each_cpu_mask(j, policy->cpus) {
+               unsigned int tmp_idle_ticks, total_idle_ticks;
+               struct cpu_dbs_info_s *j_dbs_info;
+
+               j_dbs_info = &per_cpu(cpu_dbs_info, j);
+               /* Check for frequency increase */
+               total_idle_ticks = get_cpu_idle_time(j);
+               tmp_idle_ticks = total_idle_ticks -
+                       j_dbs_info->prev_cpu_idle_up;
+               j_dbs_info->prev_cpu_idle_up = total_idle_ticks;
+
+               if (tmp_idle_ticks < idle_ticks)
+                       idle_ticks = tmp_idle_ticks;
+       }
+
+       /* Scale idle ticks by 100 and compare with up and down ticks */
+       idle_ticks *= 100;
+       up_idle_ticks = (100 - dbs_tuners_ins.up_threshold) *
+               usecs_to_jiffies(dbs_tuners_ins.sampling_rate);
+
+       if (idle_ticks < up_idle_ticks) {
+               down_skip[cpu] = 0;
+               for_each_cpu_mask(j, policy->cpus) {
+                       struct cpu_dbs_info_s *j_dbs_info;
+
+                       j_dbs_info = &per_cpu(cpu_dbs_info, j);
+                       j_dbs_info->prev_cpu_idle_down = 
+                                       j_dbs_info->prev_cpu_idle_up;
+               }
+               /* if we are already at full speed then break out early */
+               if (requested_freq[cpu] == policy->max)
+                       return;
+               
+               freq_step = (dbs_tuners_ins.freq_step * policy->max) / 100;
+
+               /* max freq cannot be less than 100. But who knows.... */
+               if (unlikely(freq_step == 0))
+                       freq_step = 5;
+               
+               requested_freq[cpu] += freq_step;
+               if (requested_freq[cpu] > policy->max)
+                       requested_freq[cpu] = policy->max;
+
+               __cpufreq_driver_target(policy, requested_freq[cpu], 
+                       CPUFREQ_RELATION_H);
+               return;
+       }
+
+       /* Check for frequency decrease */
+       down_skip[cpu]++;
+       if (down_skip[cpu] < dbs_tuners_ins.sampling_down_factor)
+               return;
+
+       idle_ticks = UINT_MAX;
+       for_each_cpu_mask(j, policy->cpus) {
+               unsigned int tmp_idle_ticks, total_idle_ticks;
+               struct cpu_dbs_info_s *j_dbs_info;
+
+               j_dbs_info = &per_cpu(cpu_dbs_info, j);
+               total_idle_ticks = j_dbs_info->prev_cpu_idle_up;
+               tmp_idle_ticks = total_idle_ticks -
+                       j_dbs_info->prev_cpu_idle_down;
+               j_dbs_info->prev_cpu_idle_down = total_idle_ticks;
+
+               if (tmp_idle_ticks < idle_ticks)
+                       idle_ticks = tmp_idle_ticks;
+       }
+
+       /* Scale idle ticks by 100 and compare with up and down ticks */
+       idle_ticks *= 100;
+       down_skip[cpu] = 0;
+
+       freq_down_sampling_rate = dbs_tuners_ins.sampling_rate *
+               dbs_tuners_ins.sampling_down_factor;
+       down_idle_ticks = (100 - dbs_tuners_ins.down_threshold) *
+                       usecs_to_jiffies(freq_down_sampling_rate);
+
+       if (idle_ticks > down_idle_ticks) {
+               /* if we are already at the lowest speed then break out early
+                * or if we 'cannot' reduce the speed as the user might want
+                * freq_step to be zero */
+               if (requested_freq[cpu] == policy->min
+                               || dbs_tuners_ins.freq_step == 0)
+                       return;
+
+               freq_step = (dbs_tuners_ins.freq_step * policy->max) / 100;
+
+               /* max freq cannot be less than 100. But who knows.... */
+               if (unlikely(freq_step == 0))
+                       freq_step = 5;
+
+               requested_freq[cpu] -= freq_step;
+               if (requested_freq[cpu] < policy->min)
+                       requested_freq[cpu] = policy->min;
+
+               __cpufreq_driver_target(policy,
+                       requested_freq[cpu],
+                       CPUFREQ_RELATION_H);
+               return;
+       }
+}
+
+static void do_dbs_timer(void *data)
+{ 
+       int i;
+       down(&dbs_sem);
+       for_each_online_cpu(i)
+               dbs_check_cpu(i);
+       schedule_delayed_work(&dbs_work, 
+                       usecs_to_jiffies(dbs_tuners_ins.sampling_rate));
+       up(&dbs_sem);
+} 
+
+static inline void dbs_timer_init(void)
+{
+       INIT_WORK(&dbs_work, do_dbs_timer, NULL);
+       schedule_delayed_work(&dbs_work,
+                       usecs_to_jiffies(dbs_tuners_ins.sampling_rate));
+       return;
+}
+
+static inline void dbs_timer_exit(void)
+{
+       cancel_delayed_work(&dbs_work);
+       return;
+}
+
+static int cpufreq_governor_dbs(struct cpufreq_policy *policy,
+                                  unsigned int event)
+{
+       unsigned int cpu = policy->cpu;
+       struct cpu_dbs_info_s *this_dbs_info;
+       unsigned int j;
+
+       this_dbs_info = &per_cpu(cpu_dbs_info, cpu);
+
+       switch (event) {
+       case CPUFREQ_GOV_START:
+               if ((!cpu_online(cpu)) || 
+                   (!policy->cur))
+                       return -EINVAL;
+
+               if (policy->cpuinfo.transition_latency >
+                               (TRANSITION_LATENCY_LIMIT * 1000))
+                       return -EINVAL;
+               if (this_dbs_info->enable) /* Already enabled */
+                       break;
+                
+               down(&dbs_sem);
+               for_each_cpu_mask(j, policy->cpus) {
+                       struct cpu_dbs_info_s *j_dbs_info;
+                       j_dbs_info = &per_cpu(cpu_dbs_info, j);
+                       j_dbs_info->cur_policy = policy;
+               
+                       j_dbs_info->prev_cpu_idle_up = get_cpu_idle_time(j);
+                       j_dbs_info->prev_cpu_idle_down
+                               = j_dbs_info->prev_cpu_idle_up;
+               }
+               this_dbs_info->enable = 1;
+               sysfs_create_group(&policy->kobj, &dbs_attr_group);
+               dbs_enable++;
+               /*
+                * Start the timerschedule work, when this governor
+                * is used for first time
+                */
+               if (dbs_enable == 1) {
+                       unsigned int latency;
+                       /* policy latency is in nS. Convert it to uS first */
+
+                       latency = policy->cpuinfo.transition_latency;
+                       if (latency < 1000)
+                               latency = 1000;
+
+                       def_sampling_rate = (latency / 1000) *
+                                       DEF_SAMPLING_RATE_LATENCY_MULTIPLIER;
+                       dbs_tuners_ins.sampling_rate = def_sampling_rate;
+                       dbs_tuners_ins.ignore_nice = 0;
+                       dbs_tuners_ins.freq_step = 5;
+
+                       dbs_timer_init();
+               }
+               
+               up(&dbs_sem);
+               break;
+
+       case CPUFREQ_GOV_STOP:
+               down(&dbs_sem);
+               this_dbs_info->enable = 0;
+               sysfs_remove_group(&policy->kobj, &dbs_attr_group);
+               dbs_enable--;
+               /*
+                * Stop the timerschedule work, when this governor
+                * is used for first time
+                */
+               if (dbs_enable == 0) 
+                       dbs_timer_exit();
+               
+               up(&dbs_sem);
+
+               break;
+
+       case CPUFREQ_GOV_LIMITS:
+               down(&dbs_sem);
+               if (policy->max < this_dbs_info->cur_policy->cur)
+                       __cpufreq_driver_target(
+                                       this_dbs_info->cur_policy,
+                                       policy->max, CPUFREQ_RELATION_H);
+               else if (policy->min > this_dbs_info->cur_policy->cur)
+                       __cpufreq_driver_target(
+                                       this_dbs_info->cur_policy,
+                                       policy->min, CPUFREQ_RELATION_L);
+               up(&dbs_sem);
+               break;
+       }
+       return 0;
+}
+
+static struct cpufreq_governor cpufreq_gov_dbs = {
+       .name           = "conservative",
+       .governor       = cpufreq_governor_dbs,
+       .owner          = THIS_MODULE,
+};
+
+static int __init cpufreq_gov_dbs_init(void)
+{
+       return cpufreq_register_governor(&cpufreq_gov_dbs);
+}
+
+static void __exit cpufreq_gov_dbs_exit(void)
+{
+       /* Make sure that the scheduled work is indeed not running */
+       flush_scheduled_work();
+
+       cpufreq_unregister_governor(&cpufreq_gov_dbs);
+}
+
+
+MODULE_AUTHOR ("Alexander Clouter <alex-kernel@digriz.org.uk>");
+MODULE_DESCRIPTION ("'cpufreq_conservative' - A dynamic cpufreq governor for "
+               "Low Latency Frequency Transition capable processors "
+               "optimised for use in a battery environment");
+MODULE_LICENSE ("GPL");
+
+module_init(cpufreq_gov_dbs_init);
+module_exit(cpufreq_gov_dbs_exit);
diff -urN linux/drivers/cpufreq/Kconfig linux/drivers/cpufreq/Kconfig
--- linux/drivers/cpufreq/Kconfig       2005/03/18 17:37:16     1.12
+++ linux/drivers/cpufreq/Kconfig       2005/06/07 13:45:32     1.13
@@ -46,6 +46,10 @@
          This will show detail CPU frequency translation table in sysfs file
          system
 
+# Note that it is not currently possible to set the other governors (such as 
ondemand)
+# as the default, since if they fail to initialise, cpufreq will be
+# left in an undefined state.
+
 choice
        prompt "Default CPUFreq governor"
        default CPU_FREQ_DEFAULT_GOV_USERSPACE if CPU_FREQ_SA1100 || 
CPU_FREQ_SA1110
@@ -115,4 +119,24 @@
 
          If in doubt, say N.
 
+config CPU_FREQ_GOV_CONSERVATIVE
+       tristate "'conservative' cpufreq governor"
+       depends on CPU_FREQ
+       help
+         'conservative' - this driver is rather similar to the 'ondemand'
+         governor both in its source code and its purpose, the difference is
+         its optimisation for better suitability in a battery powered
+         environment.  The frequency is gracefully increased and decreased
+         rather than jumping to 100% when speed is required.
+
+         If you have a desktop machine then you should really be considering
+         the 'ondemand' governor instead, however if you are using a laptop,
+         PDA or even an AMD64 based computer (due to the unacceptable
+         step-by-step latency issues between the minimum and maximum frequency
+         transitions in the CPU) you will probably want to use this governor.
+
+         For details, take a look at linux/Documentation/cpu-freq.
+
+         If in doubt, say N.
+
 endif  # CPU_FREQ
diff -urN linux/drivers/cpufreq/Makefile linux/drivers/cpufreq/Makefile
--- linux/drivers/cpufreq/Makefile      2005/01/25 04:28:14     1.6
+++ linux/drivers/cpufreq/Makefile      2005/06/07 13:45:32     1.7
@@ -8,6 +8,7 @@
 obj-$(CONFIG_CPU_FREQ_GOV_POWERSAVE)   += cpufreq_powersave.o
 obj-$(CONFIG_CPU_FREQ_GOV_USERSPACE)   += cpufreq_userspace.o
 obj-$(CONFIG_CPU_FREQ_GOV_ONDEMAND)    += cpufreq_ondemand.o
+obj-$(CONFIG_CPU_FREQ_GOV_CONSERVATIVE)        += cpufreq_conservative.o
 
 # CPUfreq cross-arch helpers
 obj-$(CONFIG_CPU_FREQ_TABLE)           += freq_table.o
diff -urN linux/drivers/cpufreq/cpufreq.c linux/drivers/cpufreq/cpufreq.c
--- linux/drivers/cpufreq/cpufreq.c     2005/05/19 12:08:22     1.16
+++ linux/drivers/cpufreq/cpufreq.c     2005/06/07 13:45:32     1.17
@@ -258,7 +258,7 @@
                            (likely(cpufreq_cpu_data[freqs->cpu]->cur)) &&
                            (unlikely(freqs->old != 
cpufreq_cpu_data[freqs->cpu]->cur)))
                        {
-                               printk(KERN_WARNING "Warning: CPU frequency is 
%u, "
+                               dprintk(KERN_WARNING "Warning: CPU frequency is 
%u, "
                                       "cpufreq assumed %u kHz.\n", freqs->old, 
cpufreq_cpu_data[freqs->cpu]->cur);
                                freqs->old = cpufreq_cpu_data[freqs->cpu]->cur;
                        }
@@ -814,7 +814,7 @@
 {
        struct cpufreq_freqs freqs;
 
-       printk(KERN_WARNING "Warning: CPU frequency out of sync: cpufreq and 
timing "
+       dprintk(KERN_WARNING "Warning: CPU frequency out of sync: cpufreq and 
timing "
               "core thinks of %u, is %u kHz.\n", old_freq, new_freq);
 
        freqs.cpu = cpu;
@@ -923,7 +923,7 @@
                struct cpufreq_freqs freqs;
 
                if (!(cpufreq_driver->flags & CPUFREQ_PM_NO_WARN))
-                       printk(KERN_DEBUG "Warning: CPU frequency is %u, "
+                       dprintk(KERN_DEBUG "Warning: CPU frequency is %u, "
                               "cpufreq assumed %u kHz.\n",
                               cur_freq, cpu_policy->cur);
 
@@ -1004,7 +1004,7 @@
                        struct cpufreq_freqs freqs;
 
                        if (!(cpufreq_driver->flags & CPUFREQ_PM_NO_WARN))
-                               printk(KERN_WARNING "Warning: CPU frequency"
+                               dprintk(KERN_WARNING "Warning: CPU frequency"
                                       "is %u, cpufreq assumed %u kHz.\n",
                                       cur_freq, cpu_policy->cur);
 
diff -urN linux/drivers/cpufreq/cpufreq_ondemand.c 
linux/drivers/cpufreq/cpufreq_ondemand.c
--- linux/drivers/cpufreq/cpufreq_ondemand.c    2005/01/25 04:28:14     1.4
+++ linux/drivers/cpufreq/cpufreq_ondemand.c    2005/06/07 13:45:32     1.5
@@ -34,13 +34,9 @@
  */
 
 #define DEF_FREQUENCY_UP_THRESHOLD             (80)
-#define MIN_FREQUENCY_UP_THRESHOLD             (0)
+#define MIN_FREQUENCY_UP_THRESHOLD             (11)
 #define MAX_FREQUENCY_UP_THRESHOLD             (100)
 
-#define DEF_FREQUENCY_DOWN_THRESHOLD           (20)
-#define MIN_FREQUENCY_DOWN_THRESHOLD           (0)
-#define MAX_FREQUENCY_DOWN_THRESHOLD           (100)
-
 /* 
  * The polling frequency of this governor depends on the capability of 
  * the processor. Default polling frequency is 1000 times the transition
@@ -55,9 +51,9 @@
 #define MIN_SAMPLING_RATE                      (def_sampling_rate / 2)
 #define MAX_SAMPLING_RATE                      (500 * def_sampling_rate)
 #define DEF_SAMPLING_RATE_LATENCY_MULTIPLIER   (1000)
-#define DEF_SAMPLING_DOWN_FACTOR               (10)
+#define DEF_SAMPLING_DOWN_FACTOR               (1)
+#define MAX_SAMPLING_DOWN_FACTOR               (10)
 #define TRANSITION_LATENCY_LIMIT               (10 * 1000)
-#define sampling_rate_in_HZ(x)                 (((x * HZ) < (1000 * 
1000))?1:((x * HZ) / (1000 * 1000)))
 
 static void do_dbs_timer(void *data);
 
@@ -78,15 +74,23 @@
        unsigned int            sampling_rate;
        unsigned int            sampling_down_factor;
        unsigned int            up_threshold;
-       unsigned int            down_threshold;
+       unsigned int            ignore_nice;
 };
 
 static struct dbs_tuners dbs_tuners_ins = {
        .up_threshold           = DEF_FREQUENCY_UP_THRESHOLD,
-       .down_threshold         = DEF_FREQUENCY_DOWN_THRESHOLD,
        .sampling_down_factor   = DEF_SAMPLING_DOWN_FACTOR,
 };
 
+static inline unsigned int get_cpu_idle_time(unsigned int cpu)
+{
+       return  kstat_cpu(cpu).cpustat.idle +
+               kstat_cpu(cpu).cpustat.iowait +
+               ( !dbs_tuners_ins.ignore_nice ? 
+                 kstat_cpu(cpu).cpustat.nice :
+                 0);
+}
+
 /************************** sysfs interface ************************/
 static ssize_t show_sampling_rate_max(struct cpufreq_policy *policy, char *buf)
 {
@@ -115,7 +119,7 @@
 show_one(sampling_rate, sampling_rate);
 show_one(sampling_down_factor, sampling_down_factor);
 show_one(up_threshold, up_threshold);
-show_one(down_threshold, down_threshold);
+show_one(ignore_nice, ignore_nice);
 
 static ssize_t store_sampling_down_factor(struct cpufreq_policy *unused, 
                const char *buf, size_t count)
@@ -126,6 +130,9 @@
        if (ret != 1 )
                return -EINVAL;
 
+       if (input > MAX_SAMPLING_DOWN_FACTOR || input < 1)
+               return -EINVAL;
+
        down(&dbs_sem);
        dbs_tuners_ins.sampling_down_factor = input;
        up(&dbs_sem);
@@ -161,8 +168,7 @@
 
        down(&dbs_sem);
        if (ret != 1 || input > MAX_FREQUENCY_UP_THRESHOLD || 
-                       input < MIN_FREQUENCY_UP_THRESHOLD ||
-                       input <= dbs_tuners_ins.down_threshold) {
+                       input < MIN_FREQUENCY_UP_THRESHOLD) {
                up(&dbs_sem);
                return -EINVAL;
        }
@@ -173,22 +179,35 @@
        return count;
 }
 
-static ssize_t store_down_threshold(struct cpufreq_policy *unused, 
+static ssize_t store_ignore_nice(struct cpufreq_policy *policy,
                const char *buf, size_t count)
 {
        unsigned int input;
        int ret;
+
+       unsigned int j;
+       
        ret = sscanf (buf, "%u", &input);
+       if ( ret != 1 )
+               return -EINVAL;
 
+       if ( input > 1 )
+               input = 1;
+       
        down(&dbs_sem);
-       if (ret != 1 || input > MAX_FREQUENCY_DOWN_THRESHOLD || 
-                       input < MIN_FREQUENCY_DOWN_THRESHOLD ||
-                       input >= dbs_tuners_ins.up_threshold) {
+       if ( input == dbs_tuners_ins.ignore_nice ) { /* nothing to do */
                up(&dbs_sem);
-               return -EINVAL;
+               return count;
        }
+       dbs_tuners_ins.ignore_nice = input;
 
-       dbs_tuners_ins.down_threshold = input;
+       /* we need to re-evaluate prev_cpu_idle_up and prev_cpu_idle_down */
+       for_each_online_cpu(j) {
+               struct cpu_dbs_info_s *j_dbs_info;
+               j_dbs_info = &per_cpu(cpu_dbs_info, j);
+               j_dbs_info->prev_cpu_idle_up = get_cpu_idle_time(j);
+               j_dbs_info->prev_cpu_idle_down = j_dbs_info->prev_cpu_idle_up;
+       }
        up(&dbs_sem);
 
        return count;
@@ -201,7 +220,7 @@
 define_one_rw(sampling_rate);
 define_one_rw(sampling_down_factor);
 define_one_rw(up_threshold);
-define_one_rw(down_threshold);
+define_one_rw(ignore_nice);
 
 static struct attribute * dbs_attributes[] = {
        &sampling_rate_max.attr,
@@ -209,7 +228,7 @@
        &sampling_rate.attr,
        &sampling_down_factor.attr,
        &up_threshold.attr,
-       &down_threshold.attr,
+       &ignore_nice.attr,
        NULL
 };
 
@@ -222,9 +241,8 @@
 
 static void dbs_check_cpu(int cpu)
 {
-       unsigned int idle_ticks, up_idle_ticks, down_idle_ticks;
-       unsigned int total_idle_ticks;
-       unsigned int freq_down_step;
+       unsigned int idle_ticks, up_idle_ticks, total_ticks;
+       unsigned int freq_next;
        unsigned int freq_down_sampling_rate;
        static int down_skip[NR_CPUS];
        struct cpu_dbs_info_s *this_dbs_info;
@@ -238,38 +256,25 @@
 
        policy = this_dbs_info->cur_policy;
        /* 
-        * The default safe range is 20% to 80% 
-        * Every sampling_rate, we check
-        *      - If current idle time is less than 20%, then we try to 
-        *        increase frequency
-        * Every sampling_rate*sampling_down_factor, we check
-        *      - If current idle time is more than 80%, then we try to
-        *        decrease frequency
+        * Every sampling_rate, we check, if current idle time is less
+        * than 20% (default), then we try to increase frequency
+        * Every sampling_rate*sampling_down_factor, we look for a the lowest
+        * frequency which can sustain the load while keeping idle time over
+        * 30%. If such a frequency exist, we try to decrease to this frequency.
         *
         * Any frequency increase takes it to the maximum frequency. 
         * Frequency reduction happens at minimum steps of 
-        * 5% of max_frequency 
+        * 5% (default) of current frequency 
         */
 
        /* Check for frequency increase */
-       total_idle_ticks = kstat_cpu(cpu).cpustat.idle +
-               kstat_cpu(cpu).cpustat.iowait;
-       idle_ticks = total_idle_ticks -
-               this_dbs_info->prev_cpu_idle_up;
-       this_dbs_info->prev_cpu_idle_up = total_idle_ticks;
-       
-
+       idle_ticks = UINT_MAX;
        for_each_cpu_mask(j, policy->cpus) {
-               unsigned int tmp_idle_ticks;
+               unsigned int tmp_idle_ticks, total_idle_ticks;
                struct cpu_dbs_info_s *j_dbs_info;
 
-               if (j == cpu)
-                       continue;
-
                j_dbs_info = &per_cpu(cpu_dbs_info, j);
-               /* Check for frequency increase */
-               total_idle_ticks = kstat_cpu(j).cpustat.idle +
-                       kstat_cpu(j).cpustat.iowait;
+               total_idle_ticks = get_cpu_idle_time(j);
                tmp_idle_ticks = total_idle_ticks -
                        j_dbs_info->prev_cpu_idle_up;
                j_dbs_info->prev_cpu_idle_up = total_idle_ticks;
@@ -281,13 +286,23 @@
        /* Scale idle ticks by 100 and compare with up and down ticks */
        idle_ticks *= 100;
        up_idle_ticks = (100 - dbs_tuners_ins.up_threshold) *
-                       sampling_rate_in_HZ(dbs_tuners_ins.sampling_rate);
+                       usecs_to_jiffies(dbs_tuners_ins.sampling_rate);
 
        if (idle_ticks < up_idle_ticks) {
+               down_skip[cpu] = 0;
+               for_each_cpu_mask(j, policy->cpus) {
+                       struct cpu_dbs_info_s *j_dbs_info;
+
+                       j_dbs_info = &per_cpu(cpu_dbs_info, j);
+                       j_dbs_info->prev_cpu_idle_down = 
+                                       j_dbs_info->prev_cpu_idle_up;
+               }
+               /* if we are already at full speed then break out early */
+               if (policy->cur == policy->max)
+                       return;
+               
                __cpufreq_driver_target(policy, policy->max, 
                        CPUFREQ_RELATION_H);
-               down_skip[cpu] = 0;
-               this_dbs_info->prev_cpu_idle_down = total_idle_ticks;
                return;
        }
 
@@ -296,23 +311,14 @@
        if (down_skip[cpu] < dbs_tuners_ins.sampling_down_factor)
                return;
 
-       total_idle_ticks = kstat_cpu(cpu).cpustat.idle +
-               kstat_cpu(cpu).cpustat.iowait;
-       idle_ticks = total_idle_ticks -
-               this_dbs_info->prev_cpu_idle_down;
-       this_dbs_info->prev_cpu_idle_down = total_idle_ticks;
-
+       idle_ticks = UINT_MAX;
        for_each_cpu_mask(j, policy->cpus) {
-               unsigned int tmp_idle_ticks;
+               unsigned int tmp_idle_ticks, total_idle_ticks;
                struct cpu_dbs_info_s *j_dbs_info;
 
-               if (j == cpu)
-                       continue;
-
                j_dbs_info = &per_cpu(cpu_dbs_info, j);
-               /* Check for frequency increase */
-               total_idle_ticks = kstat_cpu(j).cpustat.idle +
-                       kstat_cpu(j).cpustat.iowait;
+               /* Check for frequency decrease */
+               total_idle_ticks = j_dbs_info->prev_cpu_idle_up;
                tmp_idle_ticks = total_idle_ticks -
                        j_dbs_info->prev_cpu_idle_down;
                j_dbs_info->prev_cpu_idle_down = total_idle_ticks;
@@ -321,38 +327,37 @@
                        idle_ticks = tmp_idle_ticks;
        }
 
-       /* Scale idle ticks by 100 and compare with up and down ticks */
-       idle_ticks *= 100;
        down_skip[cpu] = 0;
+       /* if we cannot reduce the frequency anymore, break out early */
+       if (policy->cur == policy->min)
+               return;
 
+       /* Compute how many ticks there are between two measurements */
        freq_down_sampling_rate = dbs_tuners_ins.sampling_rate *
                dbs_tuners_ins.sampling_down_factor;
-       down_idle_ticks = (100 - dbs_tuners_ins.down_threshold) *
-                       sampling_rate_in_HZ(freq_down_sampling_rate);
+       total_ticks = usecs_to_jiffies(freq_down_sampling_rate);
 
-       if (idle_ticks > down_idle_ticks ) {
-               freq_down_step = (5 * policy->max) / 100;
-
-               /* max freq cannot be less than 100. But who knows.... */
-               if (unlikely(freq_down_step == 0))
-                       freq_down_step = 5;
+       /*
+        * The optimal frequency is the frequency that is the lowest that
+        * can support the current CPU usage without triggering the up
+        * policy. To be safe, we focus 10 points under the threshold.
+        */
+       freq_next = ((total_ticks - idle_ticks) * 100) / total_ticks;
+       freq_next = (freq_next * policy->cur) / 
+                       (dbs_tuners_ins.up_threshold - 10);
 
-               __cpufreq_driver_target(policy,
-                       policy->cur - freq_down_step, 
-                       CPUFREQ_RELATION_H);
-               return;
-       }
+       if (freq_next <= ((policy->cur * 95) / 100))
+               __cpufreq_driver_target(policy, freq_next, CPUFREQ_RELATION_L);
 }
 
 static void do_dbs_timer(void *data)
 { 
        int i;
        down(&dbs_sem);
-       for (i = 0; i < NR_CPUS; i++)
-               if (cpu_online(i))
-                       dbs_check_cpu(i);
+       for_each_online_cpu(i)
+               dbs_check_cpu(i);
        schedule_delayed_work(&dbs_work, 
-                       sampling_rate_in_HZ(dbs_tuners_ins.sampling_rate));
+                       usecs_to_jiffies(dbs_tuners_ins.sampling_rate));
        up(&dbs_sem);
 } 
 
@@ -360,7 +365,7 @@
 {
        INIT_WORK(&dbs_work, do_dbs_timer, NULL);
        schedule_delayed_work(&dbs_work,
-                       sampling_rate_in_HZ(dbs_tuners_ins.sampling_rate));
+                       usecs_to_jiffies(dbs_tuners_ins.sampling_rate));
        return;
 }
 
@@ -397,12 +402,9 @@
                        j_dbs_info = &per_cpu(cpu_dbs_info, j);
                        j_dbs_info->cur_policy = policy;
                
-                       j_dbs_info->prev_cpu_idle_up = 
-                               kstat_cpu(j).cpustat.idle +
-                               kstat_cpu(j).cpustat.iowait;
-                       j_dbs_info->prev_cpu_idle_down = 
-                               kstat_cpu(j).cpustat.idle +
-                               kstat_cpu(j).cpustat.iowait;
+                       j_dbs_info->prev_cpu_idle_up = get_cpu_idle_time(j);
+                       j_dbs_info->prev_cpu_idle_down
+                               = j_dbs_info->prev_cpu_idle_up;
                }
                this_dbs_info->enable = 1;
                sysfs_create_group(&policy->kobj, &dbs_attr_group);
@@ -422,6 +424,7 @@
                        def_sampling_rate = (latency / 1000) *
                                        DEF_SAMPLING_RATE_LATENCY_MULTIPLIER;
                        dbs_tuners_ins.sampling_rate = def_sampling_rate;
+                       dbs_tuners_ins.ignore_nice = 0;
 
                        dbs_timer_init();
                }
@@ -461,12 +464,11 @@
        return 0;
 }
 
-struct cpufreq_governor cpufreq_gov_dbs = {
+static struct cpufreq_governor cpufreq_gov_dbs = {
        .name           = "ondemand",
        .governor       = cpufreq_governor_dbs,
        .owner          = THIS_MODULE,
 };
-EXPORT_SYMBOL(cpufreq_gov_dbs);
 
 static int __init cpufreq_gov_dbs_init(void)
 {
diff -urN linux/drivers/cpufreq/cpufreq_stats.c 
linux/drivers/cpufreq/cpufreq_stats.c
--- linux/drivers/cpufreq/cpufreq_stats.c       2005/01/25 04:28:14     1.1
+++ linux/drivers/cpufreq/cpufreq_stats.c       2005/06/07 13:45:32     1.2
@@ -19,6 +19,7 @@
 #include <linux/percpu.h>
 #include <linux/kobject.h>
 #include <linux/spinlock.h>
+#include <asm/cputime.h>
 
 static spinlock_t cpufreq_stats_lock;
 
@@ -29,20 +30,14 @@
        .show = _show,\
 };
 
-static unsigned long
-delta_time(unsigned long old, unsigned long new)
-{
-       return (old > new) ? (old - new): (new + ~old + 1);
-}
-
 struct cpufreq_stats {
        unsigned int cpu;
        unsigned int total_trans;
-       unsigned long long last_time;
+       unsigned long long  last_time;
        unsigned int max_state;
        unsigned int state_num;
        unsigned int last_index;
-       unsigned long long *time_in_state;
+       cputime64_t *time_in_state;
        unsigned int *freq_table;
 #ifdef CONFIG_CPU_FREQ_STAT_DETAILS
        unsigned int *trans_table;
@@ -60,12 +55,16 @@
 cpufreq_stats_update (unsigned int cpu)
 {
        struct cpufreq_stats *stat;
+       unsigned long long cur_time;
+
+       cur_time = get_jiffies_64();
        spin_lock(&cpufreq_stats_lock);
        stat = cpufreq_stats_table[cpu];
        if (stat->time_in_state)
-               stat->time_in_state[stat->last_index] +=
-                       delta_time(stat->last_time, jiffies);
-       stat->last_time = jiffies;
+               stat->time_in_state[stat->last_index] =
+                       cputime64_add(stat->time_in_state[stat->last_index],
+                                     cputime_sub(cur_time, stat->last_time));
+       stat->last_time = cur_time;
        spin_unlock(&cpufreq_stats_lock);
        return 0;
 }
@@ -90,8 +89,8 @@
                return 0;
        cpufreq_stats_update(stat->cpu);
        for (i = 0; i < stat->state_num; i++) {
-               len += sprintf(buf + len, "%u %llu\n",
-                       stat->freq_table[i], stat->time_in_state[i]);
+               len += sprintf(buf + len, "%u %llu\n", stat->freq_table[i], 
+                       (unsigned long 
long)cputime64_to_clock_t(stat->time_in_state[i]));
        }
        return len;
 }
@@ -107,16 +106,30 @@
        if(!stat)
                return 0;
        cpufreq_stats_update(stat->cpu);
+       len += snprintf(buf + len, PAGE_SIZE - len, "   From  :    To\n");
+       len += snprintf(buf + len, PAGE_SIZE - len, "         : ");
+       for (i = 0; i < stat->state_num; i++) {
+               if (len >= PAGE_SIZE)
+                       break;
+               len += snprintf(buf + len, PAGE_SIZE - len, "%9u ",
+                               stat->freq_table[i]);
+       }
+       if (len >= PAGE_SIZE)
+               return len;
+
+       len += snprintf(buf + len, PAGE_SIZE - len, "\n");
+
        for (i = 0; i < stat->state_num; i++) {
                if (len >= PAGE_SIZE)
                        break;
-               len += snprintf(buf + len, PAGE_SIZE - len, "%9u:\t",
+
+               len += snprintf(buf + len, PAGE_SIZE - len, "%9u: ",
                                stat->freq_table[i]);
 
                for (j = 0; j < stat->state_num; j++)   {
                        if (len >= PAGE_SIZE)
                                break;
-                       len += snprintf(buf + len, PAGE_SIZE - len, "%u\t",
+                       len += snprintf(buf + len, PAGE_SIZE - len, "%9u ",
                                        stat->trans_table[i*stat->max_state+j]);
                }
                len += snprintf(buf + len, PAGE_SIZE - len, "\n");
@@ -197,7 +210,7 @@
                count++;
        }
 
-       alloc_size = count * sizeof(int) + count * sizeof(long long);
+       alloc_size = count * sizeof(int) + count * sizeof(cputime64_t);
 
 #ifdef CONFIG_CPU_FREQ_STAT_DETAILS
        alloc_size += count * count * sizeof(int);
@@ -224,7 +237,7 @@
        }
        stat->state_num = j;
        spin_lock(&cpufreq_stats_lock);
-       stat->last_time = jiffies;
+       stat->last_time = get_jiffies_64();
        stat->last_index = freq_table_get_index(stat, policy->cur);
        spin_unlock(&cpufreq_stats_lock);
        cpufreq_cpu_put(data);
diff -urN linux/drivers/firmware/pcdp.c linux/drivers/firmware/pcdp.c
--- linux/drivers/firmware/pcdp.c       2005/01/13 14:05:58     1.8
+++ linux/drivers/firmware/pcdp.c       2005/06/07 13:45:32     1.9
@@ -11,6 +11,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/config.h>
 #include <linux/acpi.h>
 #include <linux/console.h>
 #include <linux/efi.h>
diff -urN linux/drivers/i2c/busses/i2c-ali1563.c 
linux/drivers/i2c/busses/i2c-ali1563.c
--- linux/drivers/i2c/busses/i2c-ali1563.c      2005/01/13 14:05:58     1.5
+++ linux/drivers/i2c/busses/i2c-ali1563.c      2005/06/07 13:45:32     1.6
@@ -2,6 +2,7 @@
  *     i2c-ali1563.c - i2c driver for the ALi 1563 Southbridge
  *
  *     Copyright (C) 2004 Patrick Mochel
+ *                   2005 Rudolf Marek <r.marek@sh.cvut.cz>
  *
  *     The 1563 southbridge is deceptively similar to the 1533, with a
  *     few notable exceptions. One of those happens to be the fact they
@@ -57,10 +58,11 @@
 #define HST_CNTL2_BLOCK                0x05
 
 
+#define HST_CNTL2_SIZEMASK     0x38
 
 static unsigned short ali1563_smba;
 
-static int ali1563_transaction(struct i2c_adapter * a)
+static int ali1563_transaction(struct i2c_adapter * a, int size)
 {
        u32 data;
        int timeout;
@@ -73,7 +75,7 @@
 
        data = inb_p(SMB_HST_STS);
        if (data & HST_STS_BAD) {
-               dev_warn(&a->dev,"ali1563: Trying to reset busy device\n");
+               dev_err(&a->dev, "ali1563: Trying to reset busy device\n");
                outb_p(data | HST_STS_BAD,SMB_HST_STS);
                data = inb_p(SMB_HST_STS);
                if (data & HST_STS_BAD)
@@ -94,19 +96,31 @@
 
        if (timeout && !(data & HST_STS_BAD))
                return 0;
-       dev_warn(&a->dev, "SMBus Error: %s%s%s%s%s\n",
-               timeout ? "Timeout " : "",
-               data & HST_STS_FAIL ? "Transaction Failed " : "",
-               data & HST_STS_BUSERR ? "No response or Bus Collision " : "",
-               data & HST_STS_DEVERR ? "Device Error " : "",
-               !(data & HST_STS_DONE) ? "Transaction Never Finished " : "");
 
-       if (!(data & HST_STS_DONE))
+       if (!timeout) {
+               dev_err(&a->dev, "Timeout - Trying to KILL transaction!\n");
                /* Issue 'kill' to host controller */
                outb_p(HST_CNTL2_KILL,SMB_HST_CNTL2);
-       else
-               /* Issue timeout to reset all devices on bus */
+               data = inb_p(SMB_HST_STS);
+       }
+
+       /* device error - no response, ignore the autodetection case */
+       if ((data & HST_STS_DEVERR) && (size != HST_CNTL2_QUICK)) {
+               dev_err(&a->dev, "Device error!\n");
+       }
+
+       /* bus collision */
+       if (data & HST_STS_BUSERR) {
+               dev_err(&a->dev, "Bus collision!\n");
+               /* Issue timeout, hoping it helps */
                outb_p(HST_CNTL1_TIMEOUT,SMB_HST_CNTL1);
+       }
+
+       if (data & HST_STS_FAIL) {
+               dev_err(&a->dev, "Cleaning fail after KILL!\n");
+               outb_p(0x0,SMB_HST_CNTL2);
+       }
+
        return -1;
 }
 
@@ -149,7 +163,7 @@
 
        if (timeout && !(data & HST_STS_BAD))
                return 0;
-       dev_warn(&a->dev, "SMBus Error: %s%s%s%s%s\n",
+       dev_err(&a->dev, "SMBus Error: %s%s%s%s%s\n",
                timeout ? "Timeout " : "",
                data & HST_STS_FAIL ? "Transaction Failed " : "",
                data & HST_STS_BUSERR ? "No response or Bus Collision " : "",
@@ -242,13 +256,15 @@
        }
 
        outb_p(((addr & 0x7f) << 1) | (rw & 0x01), SMB_HST_ADD);
-       outb_p(inb_p(SMB_HST_CNTL2) | (size << 3), SMB_HST_CNTL2);
+       outb_p((inb_p(SMB_HST_CNTL2) & ~HST_CNTL2_SIZEMASK) | (size << 3), 
SMB_HST_CNTL2);
 
        /* Write the command register */
+
        switch(size) {
        case HST_CNTL2_BYTE:
                if (rw== I2C_SMBUS_WRITE)
-                       outb_p(cmd, SMB_HST_CMD);
+                       /* Beware it uses DAT0 register and not CMD! */
+                       outb_p(cmd, SMB_HST_DAT0);
                break;
        case HST_CNTL2_BYTE_DATA:
                outb_p(cmd, SMB_HST_CMD);
@@ -268,7 +284,7 @@
                goto Done;
        }
 
-       if ((error = ali1563_transaction(a)))
+       if ((error = ali1563_transaction(a, size)))
                goto Done;
 
        if ((rw == I2C_SMBUS_WRITE) || (size == HST_CNTL2_QUICK))
diff -urN linux/drivers/ide/ide-cd.c linux/drivers/ide/ide-cd.c
--- linux/drivers/ide/ide-cd.c  2005/04/08 18:58:14     1.96
+++ linux/drivers/ide/ide-cd.c  2005/06/07 13:45:32     1.97
@@ -1932,8 +1932,11 @@
 
                /*
                 * check if dma is safe
+                *
+                * NOTE! The "len" and "addr" checks should possibly have
+                * separate masks.
                 */
-               if ((rq->data_len & mask) || (addr & mask))
+               if ((rq->data_len & 15) || (addr & mask))
                        info->dma = 0;
        }
 
@@ -3255,16 +3258,12 @@
        return capacity * sectors_per_frame;
 }
 
-static
-int ide_cdrom_cleanup(ide_drive_t *drive)
+static int ide_cd_remove(struct device *dev)
 {
+       ide_drive_t *drive = to_ide_device(dev);
        struct cdrom_info *info = drive->driver_data;
 
-       if (ide_unregister_subdriver(drive)) {
-               printk(KERN_ERR "%s: %s: failed to ide_unregister_subdriver\n",
-                       __FUNCTION__, drive->name);
-               return 1;
-       }
+       ide_unregister_subdriver(drive, info->driver);
 
        del_gendisk(info->disk);
 
@@ -3297,7 +3296,7 @@
        kfree(info);
 }
 
-static int ide_cdrom_attach (ide_drive_t *drive);
+static int ide_cd_probe(struct device *);
 
 #ifdef CONFIG_PROC_FS
 static int proc_idecd_read_capacity
@@ -3320,19 +3319,20 @@
 
 static ide_driver_t ide_cdrom_driver = {
        .owner                  = THIS_MODULE,
-       .name                   = "ide-cdrom",
+       .gen_driver = {
+               .name           = "ide-cdrom",
+               .bus            = &ide_bus_type,
+               .probe          = ide_cd_probe,
+               .remove         = ide_cd_remove,
+       },
        .version                = IDECD_VERSION,
        .media                  = ide_cdrom,
-       .busy                   = 0,
        .supports_dsc_overlap   = 1,
-       .cleanup                = ide_cdrom_cleanup,
        .do_request             = ide_do_rw_cdrom,
        .end_request            = ide_end_request,
        .error                  = __ide_error,
        .abort                  = __ide_abort,
        .proc                   = idecd_proc,
-       .attach                 = ide_cdrom_attach,
-       .drives                 = LIST_HEAD_INIT(ide_cdrom_driver.drives),
 };
 
 static int idecd_open(struct inode * inode, struct file * file)
@@ -3418,8 +3418,9 @@
 module_param(ignore, charp, 0400);
 MODULE_DESCRIPTION("ATAPI CD-ROM Driver");
 
-static int ide_cdrom_attach (ide_drive_t *drive)
+static int ide_cd_probe(struct device *dev)
 {
+       ide_drive_t *drive = to_ide_device(dev);
        struct cdrom_info *info;
        struct gendisk *g;
        struct request_sense sense;
@@ -3453,11 +3454,8 @@
 
        ide_init_disk(g, drive);
 
-       if (ide_register_subdriver(drive, &ide_cdrom_driver)) {
-               printk(KERN_ERR "%s: Failed to register the driver with 
ide.c\n",
-                       drive->name);
-               goto out_put_disk;
-       }
+       ide_register_subdriver(drive, &ide_cdrom_driver);
+
        memset(info, 0, sizeof (struct cdrom_info));
 
        kref_init(&info->kref);
@@ -3470,7 +3468,6 @@
 
        drive->driver_data = info;
 
-       DRIVER(drive)->busy++;
        g->minors = 1;
        snprintf(g->devfs_name, sizeof(g->devfs_name),
                        "%s/cd", drive->devfs_name);
@@ -3478,8 +3475,7 @@
        g->flags = GENHD_FL_CD | GENHD_FL_REMOVABLE;
        if (ide_cdrom_setup(drive)) {
                struct cdrom_device_info *devinfo = &info->devinfo;
-               DRIVER(drive)->busy--;
-               ide_unregister_subdriver(drive);
+               ide_unregister_subdriver(drive, &ide_cdrom_driver);
                if (info->buffer != NULL)
                        kfree(info->buffer);
                if (info->toc != NULL)
@@ -3492,7 +3488,6 @@
                drive->driver_data = NULL;
                goto failed;
        }
-       DRIVER(drive)->busy--;
 
        cdrom_read_toc(drive, &sense);
        g->fops = &idecd_ops;
@@ -3500,23 +3495,20 @@
        add_disk(g);
        return 0;
 
-out_put_disk:
-       put_disk(g);
 out_free_cd:
        kfree(info);
 failed:
-       return 1;
+       return -ENODEV;
 }
 
 static void __exit ide_cdrom_exit(void)
 {
-       ide_unregister_driver(&ide_cdrom_driver);
+       driver_unregister(&ide_cdrom_driver.gen_driver);
 }
  
 static int ide_cdrom_init(void)
 {
-       ide_register_driver(&ide_cdrom_driver);
-       return 0;
+       return driver_register(&ide_cdrom_driver.gen_driver);
 }
 
 module_init(ide_cdrom_init);
diff -urN linux/drivers/ide/ide-disk.c linux/drivers/ide/ide-disk.c
--- linux/drivers/ide/ide-disk.c        2005/04/08 18:58:14     1.81
+++ linux/drivers/ide/ide-disk.c        2005/06/07 13:45:32     1.82
@@ -1024,14 +1024,16 @@
                printk(KERN_INFO "%s: wcache flush failed!\n", drive->name);
 }
 
-static int idedisk_cleanup (ide_drive_t *drive)
+static int ide_disk_remove(struct device *dev)
 {
+       ide_drive_t *drive = to_ide_device(dev);
        struct ide_disk_obj *idkp = drive->driver_data;
        struct gendisk *g = idkp->disk;
 
        ide_cacheflush_p(drive);
-       if (ide_unregister_subdriver(drive))
-               return 1;
+
+       ide_unregister_subdriver(drive, idkp->driver);
+
        del_gendisk(g);
 
        ide_disk_put(idkp);
@@ -1052,7 +1054,7 @@
        kfree(idkp);
 }
 
-static int idedisk_attach(ide_drive_t *drive);
+static int ide_disk_probe(struct device *dev);
 
 static void ide_device_shutdown(struct device *dev)
 {
@@ -1082,27 +1084,23 @@
        dev->bus->suspend(dev, PMSG_SUSPEND);
 }
 
-/*
- *      IDE subdriver functions, registered with ide.c
- */
 static ide_driver_t idedisk_driver = {
        .owner                  = THIS_MODULE,
        .gen_driver = {
+               .name           = "ide-disk",
+               .bus            = &ide_bus_type,
+               .probe          = ide_disk_probe,
+               .remove         = ide_disk_remove,
                .shutdown       = ide_device_shutdown,
        },
-       .name                   = "ide-disk",
        .version                = IDEDISK_VERSION,
        .media                  = ide_disk,
-       .busy                   = 0,
        .supports_dsc_overlap   = 0,
-       .cleanup                = idedisk_cleanup,
        .do_request             = ide_do_rw_disk,
        .end_request            = ide_end_request,
        .error                  = __ide_error,
        .abort                  = __ide_abort,
        .proc                   = idedisk_proc,
-       .attach                 = idedisk_attach,
-       .drives                 = LIST_HEAD_INIT(idedisk_driver.drives),
 };
 
 static int idedisk_open(struct inode *inode, struct file *filp)
@@ -1199,8 +1197,9 @@
 
 MODULE_DESCRIPTION("ATA DISK Driver");
 
-static int idedisk_attach(ide_drive_t *drive)
+static int ide_disk_probe(struct device *dev)
 {
+       ide_drive_t *drive = to_ide_device(dev);
        struct ide_disk_obj *idkp;
        struct gendisk *g;
 
@@ -1222,10 +1221,7 @@
 
        ide_init_disk(g, drive);
 
-       if (ide_register_subdriver(drive, &idedisk_driver)) {
-               printk (KERN_ERR "ide-disk: %s: Failed to register the driver 
with ide.c\n", drive->name);
-               goto out_put_disk;
-       }
+       ide_register_subdriver(drive, &idedisk_driver);
 
        memset(idkp, 0, sizeof(*idkp));
 
@@ -1239,7 +1235,6 @@
 
        drive->driver_data = idkp;
 
-       DRIVER(drive)->busy++;
        idedisk_setup(drive);
        if ((!drive->head || drive->head > 16) && !drive->select.b.lba) {
                printk(KERN_ERR "%s: INVALID GEOMETRY: %d PHYSICAL HEADS?\n",
@@ -1247,7 +1242,7 @@
                drive->attach = 0;
        } else
                drive->attach = 1;
-       DRIVER(drive)->busy--;
+
        g->minors = 1 << PARTN_BITS;
        strcpy(g->devfs_name, drive->devfs_name);
        g->driverfs_dev = &drive->gendev;
@@ -1257,22 +1252,20 @@
        add_disk(g);
        return 0;
 
-out_put_disk:
-       put_disk(g);
 out_free_idkp:
        kfree(idkp);
 failed:
-       return 1;
+       return -ENODEV;
 }
 
 static void __exit idedisk_exit (void)
 {
-       ide_unregister_driver(&idedisk_driver);
+       driver_unregister(&idedisk_driver.gen_driver);
 }
 
 static int idedisk_init (void)
 {
-       return ide_register_driver(&idedisk_driver);
+       return driver_register(&idedisk_driver.gen_driver);
 }
 
 module_init(idedisk_init);
diff -urN linux/drivers/ide/ide-floppy.c linux/drivers/ide/ide-floppy.c
--- linux/drivers/ide/ide-floppy.c      2005/04/08 18:58:14     1.61
+++ linux/drivers/ide/ide-floppy.c      2005/06/07 13:45:32     1.62
@@ -1865,13 +1865,13 @@
        idefloppy_add_settings(drive);
 }
 
-static int idefloppy_cleanup (ide_drive_t *drive)
+static int ide_floppy_remove(struct device *dev)
 {
+       ide_drive_t *drive = to_ide_device(dev);
        idefloppy_floppy_t *floppy = drive->driver_data;
        struct gendisk *g = floppy->disk;
 
-       if (ide_unregister_subdriver(drive))
-               return 1;
+       ide_unregister_subdriver(drive, floppy->driver);
 
        del_gendisk(g);
 
@@ -1916,26 +1916,24 @@
 
 #endif /* CONFIG_PROC_FS */
 
-static int idefloppy_attach(ide_drive_t *drive);
+static int ide_floppy_probe(struct device *);
 
-/*
- *     IDE subdriver functions, registered with ide.c
- */
 static ide_driver_t idefloppy_driver = {
        .owner                  = THIS_MODULE,
-       .name                   = "ide-floppy",
+       .gen_driver = {
+               .name           = "ide-floppy",
+               .bus            = &ide_bus_type,
+               .probe          = ide_floppy_probe,
+               .remove         = ide_floppy_remove,
+       },
        .version                = IDEFLOPPY_VERSION,
        .media                  = ide_floppy,
-       .busy                   = 0,
        .supports_dsc_overlap   = 0,
-       .cleanup                = idefloppy_cleanup,
        .do_request             = idefloppy_do_request,
        .end_request            = idefloppy_do_end_request,
        .error                  = __ide_error,
        .abort                  = __ide_abort,
        .proc                   = idefloppy_proc,
-       .attach                 = idefloppy_attach,
-       .drives                 = LIST_HEAD_INIT(idefloppy_driver.drives),
 };
 
 static int idefloppy_open(struct inode *inode, struct file *filp)
@@ -2122,8 +2120,9 @@
        .revalidate_disk= idefloppy_revalidate_disk
 };
 
-static int idefloppy_attach (ide_drive_t *drive)
+static int ide_floppy_probe(struct device *dev)
 {
+       ide_drive_t *drive = to_ide_device(dev);
        idefloppy_floppy_t *floppy;
        struct gendisk *g;
 
@@ -2152,10 +2151,7 @@
 
        ide_init_disk(g, drive);
 
-       if (ide_register_subdriver(drive, &idefloppy_driver)) {
-               printk (KERN_ERR "ide-floppy: %s: Failed to register the driver 
with ide.c\n", drive->name);
-               goto out_put_disk;
-       }
+       ide_register_subdriver(drive, &idefloppy_driver);
 
        memset(floppy, 0, sizeof(*floppy));
 
@@ -2169,9 +2165,8 @@
 
        drive->driver_data = floppy;
 
-       DRIVER(drive)->busy++;
        idefloppy_setup (drive, floppy);
-       DRIVER(drive)->busy--;
+
        g->minors = 1 << PARTN_BITS;
        g->driverfs_dev = &drive->gendev;
        strcpy(g->devfs_name, drive->devfs_name);
@@ -2181,19 +2176,17 @@
        add_disk(g);
        return 0;
 
-out_put_disk:
-       put_disk(g);
 out_free_floppy:
        kfree(floppy);
 failed:
-       return 1;
+       return -ENODEV;
 }
 
 MODULE_DESCRIPTION("ATAPI FLOPPY Driver");
 
 static void __exit idefloppy_exit (void)
 {
-       ide_unregister_driver(&idefloppy_driver);
+       driver_unregister(&idefloppy_driver.gen_driver);
 }
 
 /*
@@ -2202,8 +2195,7 @@
 static int idefloppy_init (void)
 {
        printk("ide-floppy driver " IDEFLOPPY_VERSION "\n");
-       ide_register_driver(&idefloppy_driver);
-       return 0;
+       return driver_register(&idefloppy_driver.gen_driver);
 }
 
 module_init(idefloppy_init);
diff -urN linux/drivers/ide/ide-probe.c linux/drivers/ide/ide-probe.c
--- linux/drivers/ide/ide-probe.c       2005/04/08 18:58:14     1.78
+++ linux/drivers/ide/ide-probe.c       2005/06/07 13:45:32     1.79
@@ -47,6 +47,7 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/ide.h>
+#include <linux/devfs_fs_kernel.h>
 #include <linux/spinlock.h>
 #include <linux/kmod.h>
 #include <linux/pci.h>
@@ -696,13 +697,13 @@
        SELECT_DRIVE(&hwif->drives[0]);
        hwif->OUTB(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
        mdelay(2);
-       rc = ide_wait_not_busy(hwif, 10000);
+       rc = ide_wait_not_busy(hwif, 35000);
        if (rc)
                return rc;
        SELECT_DRIVE(&hwif->drives[1]);
        hwif->OUTB(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
        mdelay(2);
-       rc = ide_wait_not_busy(hwif, 10000);
+       rc = ide_wait_not_busy(hwif, 35000);
 
        /* Exit function with master reselected (let's be sane) */
        SELECT_DRIVE(&hwif->drives[0]);
@@ -918,7 +919,7 @@
                           want them on default or a new "empty" class
                           for hotplug reprobing ? */
                        if (drive->present) {
-                               ata_attach(drive);
+                               device_register(&drive->gendev);
                        }
                }
        }
@@ -1279,10 +1280,51 @@
 
 EXPORT_SYMBOL_GPL(ide_init_disk);
 
+static void ide_remove_drive_from_hwgroup(ide_drive_t *drive)
+{
+       ide_hwgroup_t *hwgroup = drive->hwif->hwgroup;
+
+       if (drive == drive->next) {
+               /* special case: last drive from hwgroup. */
+               BUG_ON(hwgroup->drive != drive);
+               hwgroup->drive = NULL;
+       } else {
+               ide_drive_t *walk;
+
+               walk = hwgroup->drive;
+               while (walk->next != drive)
+                       walk = walk->next;
+               walk->next = drive->next;
+               if (hwgroup->drive == drive) {
+                       hwgroup->drive = drive->next;
+                       hwgroup->hwif = hwgroup->drive->hwif;
+               }
+       }
+       BUG_ON(hwgroup->drive == drive);
+}
+
 static void drive_release_dev (struct device *dev)
 {
        ide_drive_t *drive = container_of(dev, ide_drive_t, gendev);
 
+       spin_lock_irq(&ide_lock);
+       if (drive->devfs_name[0] != '\0') {
+               devfs_remove(drive->devfs_name);
+               drive->devfs_name[0] = '\0';
+       }
+       ide_remove_drive_from_hwgroup(drive);
+       if (drive->id != NULL) {
+               kfree(drive->id);
+               drive->id = NULL;
+       }
+       drive->present = 0;
+       /* Messed up locking ... */
+       spin_unlock_irq(&ide_lock);
+       blk_cleanup_queue(drive->queue);
+       spin_lock_irq(&ide_lock);
+       drive->queue = NULL;
+       spin_unlock_irq(&ide_lock);
+
        up(&drive->gendev_rel_sem);
 }
 
@@ -1306,7 +1348,6 @@
                drive->gendev.driver_data = drive;
                drive->gendev.release = drive_release_dev;
                if (drive->present) {
-                       device_register(&drive->gendev);
                        sprintf(drive->devfs_name, 
"ide/host%d/bus%d/target%d/lun%d",
                                (hwif->channel && hwif->mate) ?
                                hwif->mate->index : hwif->index,
@@ -1412,7 +1453,7 @@
                                hwif->chipset = ide_generic;
                        for (unit = 0; unit < MAX_DRIVES; ++unit)
                                if (hwif->drives[unit].present)
-                                       ata_attach(&hwif->drives[unit]);
+                                       
device_register(&hwif->drives[unit].gendev);
                }
        }
        return 0;
diff -urN linux/drivers/ide/ide-proc.c linux/drivers/ide/ide-proc.c
--- linux/drivers/ide/ide-proc.c        2005/05/26 09:12:41     1.43
+++ linux/drivers/ide/ide-proc.c        2005/06/07 13:45:32     1.44
@@ -307,17 +307,41 @@
        (char *page, char **start, off_t off, int count, int *eof, void *data)
 {
        ide_drive_t     *drive = (ide_drive_t *) data;
-       ide_driver_t    *driver = drive->driver;
+       struct device   *dev = &drive->gendev;
+       ide_driver_t    *ide_drv;
        int             len;
 
-       if (driver) {
+       down_read(&dev->bus->subsys.rwsem);
+       if (dev->driver) {
+               ide_drv = container_of(dev->driver, ide_driver_t, gen_driver);
                len = sprintf(page, "%s version %s\n",
-                               driver->name, driver->version);
+                               dev->driver->name, ide_drv->version);
        } else
                len = sprintf(page, "ide-default version 0.9.newide\n");
+       up_read(&dev->bus->subsys.rwsem);
        PROC_IDE_READ_RETURN(page,start,off,count,eof,len);
 }
 
+static int ide_replace_subdriver(ide_drive_t *drive, const char *driver)
+{
+       struct device *dev = &drive->gendev;
+       int ret = 1;
+
+       down_write(&dev->bus->subsys.rwsem);
+       device_release_driver(dev);
+       /* FIXME: device can still be in use by previous driver */
+       strlcpy(drive->driver_req, driver, sizeof(drive->driver_req));
+       device_attach(dev);
+       drive->driver_req[0] = 0;
+       if (dev->driver == NULL)
+               device_attach(dev);
+       if (dev->driver && !strcmp(dev->driver->name, driver))
+               ret = 0;
+       up_write(&dev->bus->subsys.rwsem);
+
+       return ret;
+}
+
 static int proc_ide_write_driver
        (struct file *file, const char __user *buffer, unsigned long count, 
void *data)
 {
@@ -488,16 +512,32 @@
        }
 }
 
-extern struct seq_operations ide_drivers_op;
+static int proc_print_driver(struct device_driver *drv, void *data)
+{
+       ide_driver_t *ide_drv = container_of(drv, ide_driver_t, gen_driver);
+       struct seq_file *s = data;
+
+       seq_printf(s, "%s version %s\n", drv->name, ide_drv->version);
+
+       return 0;
+}
+
+static int ide_drivers_show(struct seq_file *s, void *p)
+{
+       bus_for_each_drv(&ide_bus_type, NULL, s, proc_print_driver);
+       return 0;
+}
+
 static int ide_drivers_open(struct inode *inode, struct file *file)
 {
-       return seq_open(file, &ide_drivers_op);
+       return single_open(file, &ide_drivers_show, NULL);
 }
+
 static struct file_operations ide_drivers_operations = {
        .open           = ide_drivers_open,
        .read           = seq_read,
        .llseek         = seq_lseek,
-       .release        = seq_release,
+       .release        = single_release,
 };
 
 void proc_ide_create(void)
diff -urN linux/drivers/ide/ide-tape.c linux/drivers/ide/ide-tape.c
--- linux/drivers/ide/ide-tape.c        2005/04/08 18:58:14     1.65
+++ linux/drivers/ide/ide-tape.c        2005/06/07 13:45:32     1.66
@@ -4681,21 +4681,12 @@
        idetape_add_settings(drive);
 }
 
-static int idetape_cleanup (ide_drive_t *drive)
+static int ide_tape_remove(struct device *dev)
 {
+       ide_drive_t *drive = to_ide_device(dev);
        idetape_tape_t *tape = drive->driver_data;
-       unsigned long flags;
 
-       spin_lock_irqsave(&ide_lock, flags);
-       if (test_bit(IDETAPE_BUSY, &tape->flags) || drive->usage ||
-           tape->first_stage != NULL || tape->merge_stage_size) {
-               spin_unlock_irqrestore(&ide_lock, flags);
-               return 1;
-       }
-
-       spin_unlock_irqrestore(&ide_lock, flags);
-       DRIVER(drive)->busy = 0;
-       (void) ide_unregister_subdriver(drive);
+       ide_unregister_subdriver(drive, tape->driver);
 
        ide_unregister_region(tape->disk);
 
@@ -4710,6 +4701,8 @@
        ide_drive_t *drive = tape->drive;
        struct gendisk *g = tape->disk;
 
+       BUG_ON(tape->first_stage != NULL || tape->merge_stage_size);
+
        drive->dsc_overlap = 0;
        drive->driver_data = NULL;
        devfs_remove("%s/mt", drive->devfs_name);
@@ -4747,26 +4740,24 @@
 
 #endif
 
-static int idetape_attach(ide_drive_t *drive);
+static int ide_tape_probe(struct device *);
 
-/*
- *     IDE subdriver functions, registered with ide.c
- */
 static ide_driver_t idetape_driver = {
        .owner                  = THIS_MODULE,
-       .name                   = "ide-tape",
+       .gen_driver = {
+               .name           = "ide-tape",
+               .bus            = &ide_bus_type,
+               .probe          = ide_tape_probe,
+               .remove         = ide_tape_remove,
+       },
        .version                = IDETAPE_VERSION,
        .media                  = ide_tape,
-       .busy                   = 1,
        .supports_dsc_overlap   = 1,
-       .cleanup                = idetape_cleanup,
        .do_request             = idetape_do_request,
        .end_request            = idetape_end_request,
        .error                  = __ide_error,
        .abort                  = __ide_abort,
        .proc                   = idetape_proc,
-       .attach                 = idetape_attach,
-       .drives                 = LIST_HEAD_INIT(idetape_driver.drives),
 };
 
 /*
@@ -4829,8 +4820,9 @@
        .ioctl          = idetape_ioctl,
 };
 
-static int idetape_attach (ide_drive_t *drive)
+static int ide_tape_probe(struct device *dev)
 {
+       ide_drive_t *drive = to_ide_device(dev);
        idetape_tape_t *tape;
        struct gendisk *g;
        int minor;
@@ -4865,10 +4857,7 @@
 
        ide_init_disk(g, drive);
 
-       if (ide_register_subdriver(drive, &idetape_driver)) {
-               printk(KERN_ERR "ide-tape: %s: Failed to register the driver 
with ide.c\n", drive->name);
-               goto out_put_disk;
-       }
+       ide_register_subdriver(drive, &idetape_driver);
 
        memset(tape, 0, sizeof(*tape));
 
@@ -4902,12 +4891,11 @@
        ide_register_region(g);
 
        return 0;
-out_put_disk:
-       put_disk(g);
+
 out_free_tape:
        kfree(tape);
 failed:
-       return 1;
+       return -ENODEV;
 }
 
 MODULE_DESCRIPTION("ATAPI Streaming TAPE Driver");
@@ -4915,7 +4903,7 @@
 
 static void __exit idetape_exit (void)
 {
-       ide_unregister_driver(&idetape_driver);
+       driver_unregister(&idetape_driver.gen_driver);
        unregister_chrdev(IDETAPE_MAJOR, "ht");
 }
 
@@ -4928,8 +4916,7 @@
                printk(KERN_ERR "ide-tape: Failed to register character device 
interface\n");
                return -EBUSY;
        }
-       ide_register_driver(&idetape_driver);
-       return 0;
+       return driver_register(&idetape_driver.gen_driver);
 }
 
 module_init(idetape_init);
diff -urN linux/drivers/ide/ide.c linux/drivers/ide/ide.c
--- linux/drivers/ide/ide.c     2005/04/08 18:58:14     1.115
+++ linux/drivers/ide/ide.c     2005/06/07 13:45:32     1.116
@@ -196,8 +196,6 @@
 
 EXPORT_SYMBOL(ide_hwifs);
 
-static struct list_head ide_drives = LIST_HEAD_INIT(ide_drives);
-
 /*
  * Do not even *think* about calling this!
  */
@@ -358,54 +356,6 @@
        return system_bus_speed;
 }
 
-/*
- *     drives_lock protects the list of drives, drivers_lock the
- *     list of drivers.  Currently nobody takes both at once.
- */
-
-static DEFINE_SPINLOCK(drives_lock);
-static DEFINE_SPINLOCK(drivers_lock);
-static LIST_HEAD(drivers);
-
-/* Iterator for the driver list. */
-
-static void *m_start(struct seq_file *m, loff_t *pos)
-{
-       struct list_head *p;
-       loff_t l = *pos;
-       spin_lock(&drivers_lock);
-       list_for_each(p, &drivers)
-               if (!l--)
-                       return list_entry(p, ide_driver_t, drivers);
-       return NULL;
-}
-
-static void *m_next(struct seq_file *m, void *v, loff_t *pos)
-{
-       struct list_head *p = ((ide_driver_t *)v)->drivers.next;
-       (*pos)++;
-       return p==&drivers ? NULL : list_entry(p, ide_driver_t, drivers);
-}
-
-static void m_stop(struct seq_file *m, void *v)
-{
-       spin_unlock(&drivers_lock);
-}
-
-static int show_driver(struct seq_file *m, void *v)
-{
-       ide_driver_t *driver = v;
-       seq_printf(m, "%s version %s\n", driver->name, driver->version);
-       return 0;
-}
-
-struct seq_operations ide_drivers_op = {
-       .start  = m_start,
-       .next   = m_next,
-       .stop   = m_stop,
-       .show   = show_driver
-};
-
 #ifdef CONFIG_PROC_FS
 struct proc_dir_entry *proc_ide_root;
 #endif
@@ -630,7 +580,7 @@
        ide_hwif_t *hwif, *g;
        static ide_hwif_t tmp_hwif; /* protected by ide_cfg_sem */
        ide_hwgroup_t *hwgroup;
-       int irq_count = 0, unit, i;
+       int irq_count = 0, unit;
 
        BUG_ON(index >= MAX_HWIFS);
 
@@ -643,23 +593,22 @@
                goto abort;
        for (unit = 0; unit < MAX_DRIVES; ++unit) {
                drive = &hwif->drives[unit];
-               if (!drive->present)
+               if (!drive->present) {
+                       if (drive->devfs_name[0] != '\0') {
+                               devfs_remove(drive->devfs_name);
+                               drive->devfs_name[0] = '\0';
+                       }
                        continue;
-               if (drive->usage || DRIVER(drive)->busy)
-                       goto abort;
-               drive->dead = 1;
+               }
+               spin_unlock_irq(&ide_lock);
+               device_unregister(&drive->gendev);
+               down(&drive->gendev_rel_sem);
+               spin_lock_irq(&ide_lock);
        }
        hwif->present = 0;
 
        spin_unlock_irq(&ide_lock);
 
-       for (unit = 0; unit < MAX_DRIVES; ++unit) {
-               drive = &hwif->drives[unit];
-               if (!drive->present)
-                       continue;
-               DRIVER(drive)->cleanup(drive);
-       }
-
        destroy_proc_ide_interface(hwif);
 
        hwgroup = hwif->hwgroup;
@@ -687,44 +636,6 @@
         * Remove us from the hwgroup, and free
         * the hwgroup if we were the only member
         */
-       for (i = 0; i < MAX_DRIVES; ++i) {
-               drive = &hwif->drives[i];
-               if (drive->devfs_name[0] != '\0') {
-                       devfs_remove(drive->devfs_name);
-                       drive->devfs_name[0] = '\0';
-               }
-               if (!drive->present)
-                       continue;
-               if (drive == drive->next) {
-                       /* special case: last drive from hwgroup. */
-                       BUG_ON(hwgroup->drive != drive);
-                       hwgroup->drive = NULL;
-               } else {
-                       ide_drive_t *walk;
-
-                       walk = hwgroup->drive;
-                       while (walk->next != drive)
-                               walk = walk->next;
-                       walk->next = drive->next;
-                       if (hwgroup->drive == drive) {
-                               hwgroup->drive = drive->next;
-                               hwgroup->hwif = HWIF(hwgroup->drive);
-                       }
-               }
-               BUG_ON(hwgroup->drive == drive);
-               if (drive->id != NULL) {
-                       kfree(drive->id);
-                       drive->id = NULL;
-               }
-               drive->present = 0;
-               /* Messed up locking ... */
-               spin_unlock_irq(&ide_lock);
-               blk_cleanup_queue(drive->queue);
-               device_unregister(&drive->gendev);
-               down(&drive->gendev_rel_sem);
-               spin_lock_irq(&ide_lock);
-               drive->queue = NULL;
-       }
        if (hwif->next == hwif) {
                BUG_ON(hwgroup->hwif != hwif);
                kfree(hwgroup);
@@ -1304,73 +1215,6 @@
 
 EXPORT_SYMBOL(system_bus_clock);
 
-/*
- *     Locking is badly broken here - since way back.  That sucker is
- * root-only, but that's not an excuse...  The real question is what
- * exclusion rules do we want here.
- */
-int ide_replace_subdriver (ide_drive_t *drive, const char *driver)
-{
-       if (!drive->present || drive->usage || drive->dead)
-               goto abort;
-       if (DRIVER(drive)->cleanup(drive))
-               goto abort;
-       strlcpy(drive->driver_req, driver, sizeof(drive->driver_req));
-       if (ata_attach(drive)) {
-               spin_lock(&drives_lock);
-               list_del_init(&drive->list);
-               spin_unlock(&drives_lock);
-               drive->driver_req[0] = 0;
-               ata_attach(drive);
-       } else {
-               drive->driver_req[0] = 0;
-       }
-       if (drive->driver && !strcmp(drive->driver->name, driver))
-               return 0;
-abort:
-       return 1;
-}
-
-/**
- *     ata_attach              -       attach an ATA/ATAPI device
- *     @drive: drive to attach
- *
- *     Takes a drive that is as yet not assigned to any midlayer IDE
- *     driver (or is assigned to the default driver) and figures out
- *     which driver would like to own it. If nobody claims the drive
- *     then it is automatically attached to the default driver used for
- *     unclaimed objects.
- *
- *     A return of zero indicates attachment to a driver, of one
- *     attachment to the default driver.
- *
- *     Takes drivers_lock.
- */
-
-int ata_attach(ide_drive_t *drive)
-{
-       struct list_head *p;
-       spin_lock(&drivers_lock);
-       list_for_each(p, &drivers) {
-               ide_driver_t *driver = list_entry(p, ide_driver_t, drivers);
-               if (!try_module_get(driver->owner))
-                       continue;
-               spin_unlock(&drivers_lock);
-               if (driver->attach(drive) == 0) {
-                       module_put(driver->owner);
-                       drive->gendev.driver = &driver->gen_driver;
-                       return 0;
-               }
-               spin_lock(&drivers_lock);
-               module_put(driver->owner);
-       }
-       drive->gendev.driver = NULL;
-       spin_unlock(&drivers_lock);
-       if (ide_register_subdriver(drive, NULL))
-               panic("ide: default attach failed");
-       return 1;
-}
-
 static int generic_ide_suspend(struct device *dev, pm_message_t state)
 {
        ide_drive_t *drive = dev->driver_data;
@@ -2019,27 +1863,11 @@
 #endif
 }
 
-int ide_register_subdriver(ide_drive_t *drive, ide_driver_t *driver)
+void ide_register_subdriver(ide_drive_t *drive, ide_driver_t *driver)
 {
-       unsigned long flags;
-
-       spin_lock_irqsave(&ide_lock, flags);
-       if (!drive->present || drive->driver != NULL ||
-           drive->usage || drive->dead) {
-               spin_unlock_irqrestore(&ide_lock, flags);
-               return 1;
-       }
-       drive->driver = driver;
-       spin_unlock_irqrestore(&ide_lock, flags);
-       spin_lock(&drives_lock);
-       list_add_tail(&drive->list, driver ? &driver->drives : &ide_drives);
-       spin_unlock(&drives_lock);
-//     printk(KERN_INFO "%s: attached %s driver.\n", drive->name, 
driver->name);
 #ifdef CONFIG_PROC_FS
-       if (driver)
-               ide_add_proc_entries(drive->proc, driver->proc, drive);
+       ide_add_proc_entries(drive->proc, driver->proc, drive);
 #endif
-       return 0;
 }
 
 EXPORT_SYMBOL(ide_register_subdriver);
@@ -2047,136 +1875,51 @@
 /**
  *     ide_unregister_subdriver        -       disconnect drive from driver
  *     @drive: drive to unplug
+ *     @driver: driver
  *
  *     Disconnect a drive from the driver it was attached to and then
  *     clean up the various proc files and other objects attached to it.
  *
- *     Takes ide_setting_sem, ide_lock and drives_lock.
+ *     Takes ide_setting_sem and ide_lock.
  *     Caller must hold none of the locks.
- *
- *     No locking versus subdriver unload because we are moving to the
- *     default driver anyway. Wants double checking.
  */
 
-int ide_unregister_subdriver (ide_drive_t *drive)
+void ide_unregister_subdriver(ide_drive_t *drive, ide_driver_t *driver)
 {
        unsigned long flags;
        
        down(&ide_setting_sem);
        spin_lock_irqsave(&ide_lock, flags);
-       if (drive->usage || drive->driver == NULL || DRIVER(drive)->busy) {
-               spin_unlock_irqrestore(&ide_lock, flags);
-               up(&ide_setting_sem);
-               return 1;
-       }
 #ifdef CONFIG_PROC_FS
-       ide_remove_proc_entries(drive->proc, DRIVER(drive)->proc);
+       ide_remove_proc_entries(drive->proc, driver->proc);
 #endif
        auto_remove_settings(drive);
-       drive->driver = NULL;
        spin_unlock_irqrestore(&ide_lock, flags);
        up(&ide_setting_sem);
-       spin_lock(&drives_lock);
-       list_del_init(&drive->list);
-       spin_unlock(&drives_lock);
-       /* drive will be added to &ide_drives in ata_attach() */
-       return 0;
 }
 
 EXPORT_SYMBOL(ide_unregister_subdriver);
 
-static int ide_drive_remove(struct device * dev)
-{
-       ide_drive_t * drive = container_of(dev,ide_drive_t,gendev);
-       DRIVER(drive)->cleanup(drive);
-       return 0;
-}
-
-/**
- *     ide_register_driver     -       register IDE device driver
- *     @driver: the IDE device driver
- *
- *     Register a new device driver and then scan the devices
- *     on the IDE bus in case any should be attached to the
- *     driver we have just registered.  If so attach them.
- *
- *     Takes drivers_lock and drives_lock.
- */
-
-int ide_register_driver(ide_driver_t *driver)
-{
-       struct list_head list;
-       struct list_head *list_loop;
-       struct list_head *tmp_storage;
-
-       spin_lock(&drivers_lock);
-       list_add(&driver->drivers, &drivers);
-       spin_unlock(&drivers_lock);
-
-       INIT_LIST_HEAD(&list);
-       spin_lock(&drives_lock);
-       list_splice_init(&ide_drives, &list);
-       spin_unlock(&drives_lock);
-
-       list_for_each_safe(list_loop, tmp_storage, &list) {
-               ide_drive_t *drive = container_of(list_loop, ide_drive_t, list);
-               list_del_init(&drive->list);
-               if (drive->present)
-                       ata_attach(drive);
-       }
-       driver->gen_driver.name = (char *) driver->name;
-       driver->gen_driver.bus = &ide_bus_type;
-       driver->gen_driver.remove = ide_drive_remove;
-       return driver_register(&driver->gen_driver);
-}
-
-EXPORT_SYMBOL(ide_register_driver);
-
-/**
- *     ide_unregister_driver   -       unregister IDE device driver
- *     @driver: the IDE device driver
- *
- *     Called when a driver module is being unloaded. We reattach any
- *     devices to whatever driver claims them next (typically the default
- *     driver).
- *
- *     Takes drivers_lock and called functions will take ide_setting_sem.
- */
-
-void ide_unregister_driver(ide_driver_t *driver)
-{
-       ide_drive_t *drive;
-
-       spin_lock(&drivers_lock);
-       list_del(&driver->drivers);
-       spin_unlock(&drivers_lock);
-
-       driver_unregister(&driver->gen_driver);
-
-       while(!list_empty(&driver->drives)) {
-               drive = list_entry(driver->drives.next, ide_drive_t, list);
-               if (driver->cleanup(drive)) {
-                       printk(KERN_ERR "%s: cleanup_module() called while 
still busy\n", drive->name);
-                       BUG();
-               }
-               ata_attach(drive);
-       }
-}
-
-EXPORT_SYMBOL(ide_unregister_driver);
-
 /*
  * Probe module
  */
 
 EXPORT_SYMBOL(ide_lock);
 
+static int ide_bus_match(struct device *dev, struct device_driver *drv)
+{
+       return 1;
+}
+
 struct bus_type ide_bus_type = {
        .name           = "ide",
+       .match          = ide_bus_match,
        .suspend        = generic_ide_suspend,
        .resume         = generic_ide_resume,
 };
 
+EXPORT_SYMBOL_GPL(ide_bus_type);
+
 /*
  * This is gets invoked once during initialization, to set *everything* up
  */
diff -urN linux/drivers/ide/pci/amd74xx.c linux/drivers/ide/pci/amd74xx.c
--- linux/drivers/ide/pci/amd74xx.c     2005/01/13 14:06:00     1.28
+++ linux/drivers/ide/pci/amd74xx.c     2005/06/07 13:45:32     1.29
@@ -72,6 +72,7 @@
        { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,  0x50, AMD_UDMA_133 },
        { PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE,        0x50, AMD_UDMA_133 },
        { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE,        0x50, AMD_UDMA_133 },
+       { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE,        0x50, AMD_UDMA_133 },
        { 0 }
 };
 
@@ -487,6 +488,7 @@
        /* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2"),
        /* 13 */ DECLARE_NV_DEV("NFORCE-CK804"),
        /* 14 */ DECLARE_NV_DEV("NFORCE-MCP04"),
+       /* 15 */ DECLARE_NV_DEV("NFORCE-MCP51"),
 };
 
 static int __devinit amd74xx_probe(struct pci_dev *dev, const struct 
pci_device_id *id)
@@ -521,6 +523,7 @@
 #endif
        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE,  
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13 },
        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE,  
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14 },
+       { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE,  
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15 },
        { 0, },
 };
 MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
diff -urN linux/drivers/infiniband/core/sa_query.c 
linux/drivers/infiniband/core/sa_query.c
--- linux/drivers/infiniband/core/sa_query.c    2005/01/13 14:06:01     1.1
+++ linux/drivers/infiniband/core/sa_query.c    2005/06/07 13:45:33     1.2
@@ -587,7 +587,7 @@
 
        init_mad(query->sa_query.mad, agent);
 
-       query->sa_query.callback              = ib_sa_path_rec_callback;
+       query->sa_query.callback              = callback ? 
ib_sa_path_rec_callback : NULL;
        query->sa_query.release               = ib_sa_path_rec_release;
        query->sa_query.port                  = port;
        query->sa_query.mad->mad_hdr.method   = IB_MGMT_METHOD_GET;
@@ -663,7 +663,7 @@
 
        init_mad(query->sa_query.mad, agent);
 
-       query->sa_query.callback              = ib_sa_mcmember_rec_callback;
+       query->sa_query.callback              = callback ? 
ib_sa_mcmember_rec_callback : NULL;
        query->sa_query.release               = ib_sa_mcmember_rec_release;
        query->sa_query.port                  = port;
        query->sa_query.mad->mad_hdr.method   = method;
@@ -698,20 +698,21 @@
        if (!query)
                return;
 
-       switch (mad_send_wc->status) {
-       case IB_WC_SUCCESS:
-               /* No callback -- already got recv */
-               break;
-       case IB_WC_RESP_TIMEOUT_ERR:
-               query->callback(query, -ETIMEDOUT, NULL);
-               break;
-       case IB_WC_WR_FLUSH_ERR:
-               query->callback(query, -EINTR, NULL);
-               break;
-       default:
-               query->callback(query, -EIO, NULL);
-               break;
-       }
+       if (query->callback)
+               switch (mad_send_wc->status) {
+               case IB_WC_SUCCESS:
+                       /* No callback -- already got recv */
+                       break;
+               case IB_WC_RESP_TIMEOUT_ERR:
+                       query->callback(query, -ETIMEDOUT, NULL);
+                       break;
+               case IB_WC_WR_FLUSH_ERR:
+                       query->callback(query, -EINTR, NULL);
+                       break;
+               default:
+                       query->callback(query, -EIO, NULL);
+                       break;
+               }
 
        dma_unmap_single(agent->device->dma_device,
                         pci_unmap_addr(query, mapping),
@@ -736,7 +737,7 @@
        query = idr_find(&query_idr, mad_recv_wc->wc->wr_id);
        spin_unlock_irqrestore(&idr_lock, flags);
 
-       if (query) {
+       if (query && query->callback) {
                if (mad_recv_wc->wc->status == IB_WC_SUCCESS)
                        query->callback(query,
                                        
mad_recv_wc->recv_buf.mad->mad_hdr.status ?
diff -urN linux/drivers/infiniband/core/user_mad.c 
linux/drivers/infiniband/core/user_mad.c
--- linux/drivers/infiniband/core/user_mad.c    2005/04/29 11:15:06     1.4
+++ linux/drivers/infiniband/core/user_mad.c    2005/06/07 13:45:33     1.5
@@ -499,6 +499,7 @@
 static int ib_umad_close(struct inode *inode, struct file *filp)
 {
        struct ib_umad_file *file = filp->private_data;
+       struct ib_umad_packet *packet, *tmp;
        int i;
 
        for (i = 0; i < IB_UMAD_MAX_AGENTS; ++i)
@@ -507,6 +508,9 @@
                        ib_unregister_mad_agent(file->agent[i]);
                }
 
+       list_for_each_entry_safe(packet, tmp, &file->recv_list, list)
+               kfree(packet);
+
        kfree(file);
 
        return 0;
diff -urN linux/drivers/infiniband/include/ib_sa.h 
linux/drivers/infiniband/include/ib_sa.h
--- linux/drivers/infiniband/include/ib_sa.h    2005/01/25 04:28:16     1.2
+++ linux/drivers/infiniband/include/ib_sa.h    2005/06/07 13:45:33     1.3
@@ -147,7 +147,7 @@
        /* reserved */
        u8           sl;
        u8           mtu_selector;
-       enum ib_mtu  mtu;
+       u8           mtu;
        u8           rate_selector;
        u8           rate;
        u8           packet_life_time_selector;
@@ -180,7 +180,7 @@
        u32          qkey;
        u16          mlid;
        u8           mtu_selector;
-       enum         ib_mtu mtu;
+       u8           mtu;
        u8           traffic_class;
        u16          pkey;
        u8           rate_selector;
diff -urN linux/drivers/input/joydev.c linux/drivers/input/joydev.c
--- linux/drivers/input/joydev.c        2005/03/18 17:37:20     1.24
+++ linux/drivers/input/joydev.c        2005/06/07 13:45:33     1.25
@@ -422,7 +422,7 @@
                        joydev->nkey++;
                }
 
-       for (i = 0; i < BTN_JOYSTICK - BTN_MISC + 1; i++)
+       for (i = 0; i < BTN_JOYSTICK - BTN_MISC; i++)
                if (test_bit(i + BTN_MISC, dev->keybit)) {
                        joydev->keymap[i] = joydev->nkey;
                        joydev->keypam[joydev->nkey] = i + BTN_MISC;
diff -urN linux/drivers/input/mousedev.c linux/drivers/input/mousedev.c
--- linux/drivers/input/mousedev.c      2005/03/18 17:37:20     1.30
+++ linux/drivers/input/mousedev.c      2005/06/07 13:45:33     1.31
@@ -101,6 +101,7 @@
        unsigned char ready, buffer, bufsiz;
        unsigned char imexseq, impsseq;
        enum mousedev_emul mode;
+       unsigned long last_buttons;
 };
 
 #define MOUSEDEV_SEQ_LEN       6
@@ -224,7 +225,7 @@
                spin_lock_irqsave(&list->packet_lock, flags);
 
                p = &list->packets[list->head];
-               if (list->ready && p->buttons != packet->buttons) {
+               if (list->ready && p->buttons != mousedev->packet.buttons) {
                        unsigned int new_head = (list->head + 1) % 
PACKET_QUEUE_LEN;
                        if (new_head != list->tail) {
                                p = &list->packets[list->head = new_head];
@@ -249,10 +250,13 @@
                p->dz += packet->dz;
                p->buttons = mousedev->packet.buttons;
 
-               list->ready = 1;
+               if (p->dx || p->dy || p->dz || p->buttons != list->last_buttons)
+                       list->ready = 1;
 
                spin_unlock_irqrestore(&list->packet_lock, flags);
-               kill_fasync(&list->fasync, SIGIO, POLL_IN);
+
+               if (list->ready)
+                       kill_fasync(&list->fasync, SIGIO, POLL_IN);
        }
 
        wake_up_interruptible(&mousedev->wait);
@@ -477,9 +481,10 @@
        }
 
        if (!p->dx && !p->dy && !p->dz) {
-               if (list->tail == list->head)
+               if (list->tail == list->head) {
                        list->ready = 0;
-               else
+                       list->last_buttons = p->buttons;
+               } else
                        list->tail = (list->tail + 1) % PACKET_QUEUE_LEN;
        }
 
diff -urN linux/drivers/input/gameport/Kconfig 
linux/drivers/input/gameport/Kconfig
--- linux/drivers/input/gameport/Kconfig        2005/04/08 18:58:15     1.7
+++ linux/drivers/input/gameport/Kconfig        2005/06/07 13:45:33     1.8
@@ -68,23 +68,3 @@
        depends on PCI
 
 endif
-
-# Yes, SOUND_GAMEPORT looks a bit odd. Yes, it ends up being turned on
-# in every .config. Please don't touch it. It is here to handle an
-# unusual dependency between GAMEPORT and sound drivers.
-#
-# Some sound drivers call gameport functions. If GAMEPORT is
-# not selected, empty stubs are provided for the functions and all is
-# well.
-# If GAMEPORT is built in, everything is fine.
-# If GAMEPORT is a module, however, it would need to be loaded for the
-# sound driver to be able to link properly. Therefore, the sound
-# driver must be a module as well in that case. Since there's no way
-# to express that directly in Kconfig, we use SOUND_GAMEPORT to
-# express it. SOUND_GAMEPORT boils down to "if GAMEPORT is 'm',
-# anything that depends on SOUND_GAMEPORT must be 'm' as well. if
-# GAMEPORT is 'y' or 'n', it can be anything".
-config SOUND_GAMEPORT
-       tristate
-       default m if GAMEPORT=m
-       default y
diff -urN linux/drivers/input/keyboard/atkbd.c 
linux/drivers/input/keyboard/atkbd.c
--- linux/drivers/input/keyboard/atkbd.c        2005/05/26 09:12:41     1.27
+++ linux/drivers/input/keyboard/atkbd.c        2005/06/07 13:45:33     1.28
@@ -171,9 +171,9 @@
        unsigned char set2;
 } atkbd_scroll_keys[] = {
        { ATKBD_SCR_1,     0xc5 },
-       { ATKBD_SCR_2,     0xa9 },
-       { ATKBD_SCR_4,     0xb6 },
-       { ATKBD_SCR_8,     0xa7 },
+       { ATKBD_SCR_2,     0x9d },
+       { ATKBD_SCR_4,     0xa4 },
+       { ATKBD_SCR_8,     0x9b },
        { ATKBD_SCR_CLICK, 0xe0 },
        { ATKBD_SCR_LEFT,  0xcb },
        { ATKBD_SCR_RIGHT, 0xd2 },
diff -urN linux/drivers/input/mouse/psmouse-base.c 
linux/drivers/input/mouse/psmouse-base.c
--- linux/drivers/input/mouse/psmouse-base.c    2005/03/18 17:37:22     1.12
+++ linux/drivers/input/mouse/psmouse-base.c    2005/06/07 13:45:33     1.13
@@ -518,13 +518,16 @@
 /*
  * First, we check if it's a mouse. It should send 0x00 or 0x03
  * in case of an IntelliMouse in 4-byte mode or 0x04 for IM Explorer.
+ * Sunrex K8561 IR Keyboard/Mouse reports 0xff on second and subsequent
+ * ID queries, probably due to a firmware bug.
  */
 
        param[0] = 0xa5;
        if (ps2_command(ps2dev, param, PSMOUSE_CMD_GETID))
                return -1;
 
-       if (param[0] != 0x00 && param[0] != 0x03 && param[0] != 0x04)
+       if (param[0] != 0x00 && param[0] != 0x03 &&
+           param[0] != 0x04 && param[0] != 0xff)
                return -1;
 
 /*
@@ -972,7 +975,7 @@
                return -EINVAL;
 
        if (!strncmp(val, "any", 3)) {
-               *((unsigned int *)kp->arg) = -1UL;
+               *((unsigned int *)kp->arg) = -1U;
                return 0;
        }
 
diff -urN linux/drivers/input/mouse/synaptics.c 
linux/drivers/input/mouse/synaptics.c
--- linux/drivers/input/mouse/synaptics.c       2005/03/18 17:37:22     1.10
+++ linux/drivers/input/mouse/synaptics.c       2005/06/07 13:45:33     1.11
@@ -143,39 +143,6 @@
        return -1;
 }
 
-static void print_ident(struct synaptics_data *priv)
-{
-       printk(KERN_INFO "Synaptics Touchpad, model: %ld\n", 
SYN_ID_MODEL(priv->identity));
-       printk(KERN_INFO " Firmware: %ld.%ld\n", SYN_ID_MAJOR(priv->identity),
-              SYN_ID_MINOR(priv->identity));
-       if (SYN_MODEL_ROT180(priv->model_id))
-               printk(KERN_INFO " 180 degree mounted touchpad\n");
-       if (SYN_MODEL_PORTRAIT(priv->model_id))
-               printk(KERN_INFO " portrait touchpad\n");
-       printk(KERN_INFO " Sensor: %ld\n", SYN_MODEL_SENSOR(priv->model_id));
-       if (SYN_MODEL_NEWABS(priv->model_id))
-               printk(KERN_INFO " new absolute packet format\n");
-       if (SYN_MODEL_PEN(priv->model_id))
-               printk(KERN_INFO " pen detection\n");
-
-       if (SYN_CAP_EXTENDED(priv->capabilities)) {
-               printk(KERN_INFO " Touchpad has extended capability bits\n");
-               if (SYN_CAP_MULTI_BUTTON_NO(priv->ext_cap))
-                       printk(KERN_INFO " -> %d multi-buttons, i.e. besides 
standard buttons\n",
-                              (int)(SYN_CAP_MULTI_BUTTON_NO(priv->ext_cap)));
-               if (SYN_CAP_MIDDLE_BUTTON(priv->capabilities))
-                       printk(KERN_INFO " -> middle button\n");
-               if (SYN_CAP_FOUR_BUTTON(priv->capabilities))
-                       printk(KERN_INFO " -> four buttons\n");
-               if (SYN_CAP_MULTIFINGER(priv->capabilities))
-                       printk(KERN_INFO " -> multifinger detection\n");
-               if (SYN_CAP_PALMDETECT(priv->capabilities))
-                       printk(KERN_INFO " -> palm detection\n");
-               if (SYN_CAP_PASS_THROUGH(priv->capabilities))
-                       printk(KERN_INFO " -> pass-through port\n");
-       }
-}
-
 static int synaptics_query_hardware(struct psmouse *psmouse)
 {
        int retries = 0;
@@ -666,7 +633,11 @@
 
        priv->pkt_type = SYN_MODEL_NEWABS(priv->model_id) ? SYN_NEWABS : 
SYN_OLDABS;
 
-       print_ident(priv);
+       printk(KERN_INFO "Synaptics Touchpad, model: %ld, fw: %ld.%ld, id: 
%#lx, caps: %#lx/%#lx\n",
+               SYN_ID_MODEL(priv->identity),
+               SYN_ID_MAJOR(priv->identity), SYN_ID_MINOR(priv->identity),
+               priv->model_id, priv->capabilities, priv->ext_cap);
+
        set_input_params(&psmouse->dev, priv);
 
        psmouse->protocol_handler = synaptics_process_byte;
diff -urN linux/drivers/input/serio/i8042-x86ia64io.h 
linux/drivers/input/serio/i8042-x86ia64io.h
--- linux/drivers/input/serio/i8042-x86ia64io.h 2005/03/18 17:37:23     1.3
+++ linux/drivers/input/serio/i8042-x86ia64io.h 2005/06/07 13:45:33     1.4
@@ -88,9 +88,11 @@
 };
 
 /*
- * Some Fujitsu notebooks are ahving trouble with touhcpads if
+ * Some Fujitsu notebooks are having trouble with touchpads if
  * active multiplexing mode is activated. Luckily they don't have
  * external PS/2 ports so we can safely disable it.
+ * ... apparently some Toshibas don't like MUX mode either and
+ * die horrible death on reboot.
  */
 static struct dmi_system_id __initdata i8042_dmi_nomux_table[] = {
        {
@@ -115,12 +117,26 @@
                },
        },
        {
+               .ident = "Fujitsu Lifebook S6230",
+               .matches = {
+                       DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
+                       DMI_MATCH(DMI_PRODUCT_NAME, "LifeBook S6230"),
+               },
+       },
+       {
                .ident = "Fujitsu T70H",
                .matches = {
                        DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
                        DMI_MATCH(DMI_PRODUCT_NAME, "FMVLT70H"),
                },
        },
+       {
+               .ident = "Toshiba P10",
+               .matches = {
+                       DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+                       DMI_MATCH(DMI_PRODUCT_NAME, "Satellite P10"),
+               },
+       },
        { }
 };
 
@@ -215,11 +231,15 @@
 
 static void i8042_pnp_exit(void)
 {
-       if (i8042_pnp_kbd_registered)
+       if (i8042_pnp_kbd_registered) {
+               i8042_pnp_kbd_registered = 0;
                pnp_unregister_driver(&i8042_pnp_kbd_driver);
+       }
 
-       if (i8042_pnp_aux_registered)
+       if (i8042_pnp_aux_registered) {
+               i8042_pnp_aux_registered = 0;
                pnp_unregister_driver(&i8042_pnp_aux_driver);
+       }
 }
 
 static int i8042_pnp_init(void)
@@ -227,7 +247,7 @@
        int result_kbd, result_aux;
 
        if (i8042_nopnp) {
-               printk("i8042: PNP detection disabled\n");
+               printk(KERN_INFO "i8042: PNP detection disabled\n");
                return 0;
        }
 
@@ -241,7 +261,7 @@
 #if defined(__ia64__)
                return -ENODEV;
 #else
-               printk(KERN_WARNING "PNP: No PS/2 controller found. Probing 
ports directly.\n");
+               printk(KERN_INFO "PNP: No PS/2 controller found. Probing ports 
directly.\n");
                return 0;
 #endif
        }
@@ -265,7 +285,7 @@
                i8042_pnp_kbd_irq = i8042_kbd_irq;
        }
 
-       if (result_aux > 0 && !i8042_pnp_aux_irq) {
+       if (!i8042_pnp_aux_irq) {
                printk(KERN_WARNING "PNP: PS/2 controller doesn't have AUX irq; 
using default %#x\n", i8042_aux_irq);
                i8042_pnp_aux_irq = i8042_aux_irq;
        }
diff -urN linux/drivers/input/serio/i8042.c linux/drivers/input/serio/i8042.c
--- linux/drivers/input/serio/i8042.c   2005/03/18 17:37:23     1.28
+++ linux/drivers/input/serio/i8042.c   2005/06/07 13:45:33     1.29
@@ -698,6 +698,26 @@
        i8042_interrupt(0, NULL, NULL);
 }
 
+static int i8042_ctl_test(void)
+{
+       unsigned char param;
+
+       if (!i8042_reset)
+               return 0;
+
+       if (i8042_command(&param, I8042_CMD_CTL_TEST)) {
+               printk(KERN_ERR "i8042.c: i8042 controller self test 
timeout.\n");
+               return -1;
+       }
+
+       if (param != I8042_RET_CTL_TEST) {
+               printk(KERN_ERR "i8042.c: i8042 controller selftest failed. 
(%#x != %#x)\n",
+                        param, I8042_RET_CTL_TEST);
+               return -1;
+       }
+
+       return 0;
+}
 
 /*
  * i8042_controller init initializes the i8042 controller, and,
@@ -719,21 +739,8 @@
                return -1;
        }
 
-       if (i8042_reset) {
-
-               unsigned char param;
-
-               if (i8042_command(&param, I8042_CMD_CTL_TEST)) {
-                       printk(KERN_ERR "i8042.c: i8042 controller self test 
timeout.\n");
-                       return -1;
-               }
-
-               if (param != I8042_RET_CTL_TEST) {
-                       printk(KERN_ERR "i8042.c: i8042 controller selftest 
failed. (%#x != %#x)\n",
-                                param, I8042_RET_CTL_TEST);
-                       return -1;
-               }
-       }
+       if (i8042_ctl_test())
+               return -1;
 
 /*
  * Save the CTR for restoral on unload / reboot.
@@ -802,15 +809,11 @@
  */
 static void i8042_controller_reset(void)
 {
-       unsigned char param;
-
 /*
  * Reset the controller if requested.
  */
 
-       if (i8042_reset)
-               if (i8042_command(&param, I8042_CMD_CTL_TEST))
-                       printk(KERN_ERR "i8042.c: i8042 controller reset 
timeout.\n");
+       i8042_ctl_test();
 
 /*
  * Disable MUX mode if present.
@@ -922,8 +925,11 @@
        if (level != RESUME_ENABLE)
                return 0;
 
-       if (i8042_controller_init()) {
-               printk(KERN_ERR "i8042: resume failed\n");
+       if (i8042_ctl_test())
+               return -1;
+
+       if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
+               printk(KERN_ERR "i8042: Can't write CTR\n");
                return -1;
        }
 
diff -urN linux/drivers/input/touchscreen/gunze.c 
linux/drivers/input/touchscreen/gunze.c
--- linux/drivers/input/touchscreen/gunze.c     2005/03/18 17:37:23     1.8
+++ linux/drivers/input/touchscreen/gunze.c     2005/06/07 13:45:33     1.9
@@ -68,8 +68,7 @@
 
        if (gunze->idx != GUNZE_MAX_LENGTH || gunze->data[5] != ',' ||
                (gunze->data[0] != 'T' && gunze->data[0] != 'R')) {
-               gunze->data[10] = 0;
-               printk(KERN_WARNING "gunze.c: bad packet: >%s<\n", gunze->data);
+               printk(KERN_WARNING "gunze.c: bad packet: >%.*s<\n", 
GUNZE_MAX_LENGTH, gunze->data);
                return;
        }
 
diff -urN linux/drivers/macintosh/therm_adt746x.c 
linux/drivers/macintosh/therm_adt746x.c
--- linux/drivers/macintosh/therm_adt746x.c     2005/03/18 17:37:24     1.8
+++ linux/drivers/macintosh/therm_adt746x.c     2005/06/07 13:45:33     1.9
@@ -39,15 +39,16 @@
 #define MANUAL_MASK  0xe0
 #define AUTO_MASK    0x20
 
-static u8 TEMP_REG[3]    = {0x26, 0x25, 0x27}; /* local, cpu, gpu */
-static u8 LIMIT_REG[3]   = {0x6b, 0x6a, 0x6c}; /* local, cpu, gpu */
+static u8 TEMP_REG[3]    = {0x26, 0x25, 0x27}; /* local, sensor1, sensor2 */
+static u8 LIMIT_REG[3]   = {0x6b, 0x6a, 0x6c}; /* local, sensor1, sensor2 */
 static u8 MANUAL_MODE[2] = {0x5c, 0x5d};       
 static u8 REM_CONTROL[2] = {0x00, 0x40};
 static u8 FAN_SPEED[2]   = {0x28, 0x2a};
 static u8 FAN_SPD_SET[2] = {0x30, 0x31};
 
-static u8 default_limits_local[3] = {70, 50, 70};    /* local, cpu, gpu */
-static u8 default_limits_chip[3] = {80, 65, 80};    /* local, cpu, gpu */
+static u8 default_limits_local[3] = {70, 50, 70};    /* local, sensor1, 
sensor2 */
+static u8 default_limits_chip[3] = {80, 65, 80};    /* local, sensor1, sensor2 
*/
+static char *sensor_location[3] = {NULL, NULL, NULL};
 
 static int limit_adjust = 0;
 static int fan_speed = -1;
@@ -58,7 +59,7 @@
 MODULE_LICENSE("GPL");
 
 module_param(limit_adjust, int, 0644);
-MODULE_PARM_DESC(limit_adjust,"Adjust maximum temperatures (50 cpu, 70 gpu) "
+MODULE_PARM_DESC(limit_adjust,"Adjust maximum temperatures (50 sensor1, 70 
sensor2) "
                 "by N degrees.");
 
 module_param(fan_speed, int, 0644);
@@ -213,10 +214,10 @@
        if (th->last_speed[fan] != speed) {
                if (speed == -1)
                        printk(KERN_DEBUG "adt746x: Setting speed to automatic "
-                               "for %s fan.\n", fan?"GPU":"CPU");
+                               "for %s fan.\n", sensor_location[fan+1]);
                else
                        printk(KERN_DEBUG "adt746x: Setting speed to %d "
-                               "for %s fan.\n", speed, fan?"GPU":"CPU");
+                               "for %s fan.\n", speed, sensor_location[fan+1]);
        } else
                return;
        
@@ -300,11 +301,11 @@
                        printk(KERN_DEBUG "adt746x: setting fans speed to %d "
                                         "(limit exceeded by %d on %s) \n",
                                        new_speed, var,
-                                       fan_number?"GPU/pwr":"CPU");
+                                       sensor_location[fan_number+1]);
                        write_both_fan_speed(th, new_speed);
                        th->last_var[fan_number] = var;
                } else if (var < -2) {
-                       /* don't stop fan if GPU/power is cold and CPU is not
+                       /* don't stop fan if sensor2 is cold and sensor1 is not
                         * so cold (lastvar >= -1) */
                        if (i == 2 && lastvar < -1) {
                                if (th->last_speed[fan_number] != 0)
@@ -318,7 +319,7 @@
 
                if (started)
                        return; /* we don't want to re-stop the fan
-                               * if CPU is heating and GPU/power is not */
+                               * if sensor1 is heating and sensor2 is not */
        }
 }
 
@@ -353,7 +354,7 @@
 
 static void set_limit(struct thermostat *th, int i)
 {
-               /* Set CPU limit higher to avoid powerdowns */ 
+               /* Set sensor1 limit higher to avoid powerdowns */
                th->limits[i] = default_limits_chip[i] + limit_adjust;
                write_reg(th, LIMIT_REG[i], th->limits[i]);
                
@@ -461,6 +462,12 @@
        return sprintf(buf, "%d\n", data);                      \
 }
 
+#define BUILD_SHOW_FUNC_STR(name, data)                                \
+static ssize_t show_##name(struct device *dev, char *buf)      \
+{                                                              \
+       return sprintf(buf, "%s\n", data);                      \
+}
+
 #define BUILD_SHOW_FUNC_FAN(name, data)                                \
 static ssize_t show_##name(struct device *dev, char *buf)       \
 {                                                              \
@@ -476,7 +483,7 @@
        int val;                                                \
        int i;                                                  \
        val = simple_strtol(buf, NULL, 10);                     \
-       printk(KERN_INFO "Adjusting limits by %d°C\n", val);    \
+       printk(KERN_INFO "Adjusting limits by %d degrees\n", val);      \
        limit_adjust = val;                                     \
        for (i=0; i < 3; i++)                                   \
                set_limit(thermostat, i);                       \
@@ -495,35 +502,41 @@
        return n;                                               \
 }
 
-BUILD_SHOW_FUNC_INT(cpu_temperature,    (read_reg(thermostat, TEMP_REG[1])))
-BUILD_SHOW_FUNC_INT(gpu_temperature,    (read_reg(thermostat, TEMP_REG[2])))
-BUILD_SHOW_FUNC_INT(cpu_limit,          thermostat->limits[1])
-BUILD_SHOW_FUNC_INT(gpu_limit,          thermostat->limits[2])
+BUILD_SHOW_FUNC_INT(sensor1_temperature,        (read_reg(thermostat, 
TEMP_REG[1])))
+BUILD_SHOW_FUNC_INT(sensor2_temperature,        (read_reg(thermostat, 
TEMP_REG[2])))
+BUILD_SHOW_FUNC_INT(sensor1_limit,              thermostat->limits[1])
+BUILD_SHOW_FUNC_INT(sensor2_limit,              thermostat->limits[2])
+BUILD_SHOW_FUNC_STR(sensor1_location,           sensor_location[1])
+BUILD_SHOW_FUNC_STR(sensor2_location,           sensor_location[2])
 
 BUILD_SHOW_FUNC_INT(specified_fan_speed, fan_speed)
-BUILD_SHOW_FUNC_FAN(cpu_fan_speed,      0)
-BUILD_SHOW_FUNC_FAN(gpu_fan_speed,      1)
+BUILD_SHOW_FUNC_FAN(sensor1_fan_speed,  0)
+BUILD_SHOW_FUNC_FAN(sensor2_fan_speed,  1)
 
 BUILD_STORE_FUNC_INT(specified_fan_speed,fan_speed)
 BUILD_SHOW_FUNC_INT(limit_adjust,       limit_adjust)
 BUILD_STORE_FUNC_DEG(limit_adjust,      thermostat)
                
-static DEVICE_ATTR(cpu_temperature,    S_IRUGO,
-                  show_cpu_temperature,NULL);
-static DEVICE_ATTR(gpu_temperature,    S_IRUGO,
-                  show_gpu_temperature,NULL);
-static DEVICE_ATTR(cpu_limit,          S_IRUGO,
-                  show_cpu_limit,      NULL);
-static DEVICE_ATTR(gpu_limit,          S_IRUGO,
-                  show_gpu_limit,      NULL);
+static DEVICE_ATTR(sensor1_temperature,        S_IRUGO,
+                  show_sensor1_temperature,NULL);
+static DEVICE_ATTR(sensor2_temperature,        S_IRUGO,
+                  show_sensor2_temperature,NULL);
+static DEVICE_ATTR(sensor1_limit, S_IRUGO,
+                  show_sensor1_limit,  NULL);
+static DEVICE_ATTR(sensor2_limit, S_IRUGO,
+                  show_sensor2_limit,  NULL);
+static DEVICE_ATTR(sensor1_location, S_IRUGO,
+                  show_sensor1_location, NULL);
+static DEVICE_ATTR(sensor2_location, S_IRUGO,
+                  show_sensor2_location, NULL);
 
 static DEVICE_ATTR(specified_fan_speed,        S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH,
                   show_specified_fan_speed,store_specified_fan_speed);
 
-static DEVICE_ATTR(cpu_fan_speed,      S_IRUGO,
-                  show_cpu_fan_speed,  NULL);
-static DEVICE_ATTR(gpu_fan_speed,      S_IRUGO,
-                  show_gpu_fan_speed,  NULL);
+static DEVICE_ATTR(sensor1_fan_speed,  S_IRUGO,
+                  show_sensor1_fan_speed,      NULL);
+static DEVICE_ATTR(sensor2_fan_speed,  S_IRUGO,
+                  show_sensor2_fan_speed,      NULL);
 
 static DEVICE_ATTR(limit_adjust,       S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH,
                   show_limit_adjust,   store_limit_adjust);
@@ -534,6 +547,7 @@
 {
        struct device_node* np;
        u32 *prop;
+       int i = 0, offset = 0;
        
        np = of_find_node_by_name(NULL, "fan");
        if (!np)
@@ -545,6 +559,12 @@
        else
                return -ENODEV;
 
+       prop = (u32 *)get_property(np, "hwsensor-params-version", NULL);
+       printk(KERN_INFO "adt746x: version %d (%ssupported)\n", *prop,
+                        (*prop == 1)?"":"un");
+       if (*prop != 1)
+               return -ENODEV;
+
        prop = (u32 *)get_property(np, "reg", NULL);
        if (!prop)
                return -ENODEV;
@@ -563,6 +583,23 @@
                         "limit_adjust: %d, fan_speed: %d\n",
                         therm_bus, therm_address, limit_adjust, fan_speed);
 
+       if (get_property(np, "hwsensor-location", NULL)) {
+               for (i = 0; i < 3; i++) {
+                       sensor_location[i] = get_property(np,
+                                       "hwsensor-location", NULL) + offset;
+
+                       if (sensor_location[i] == NULL)
+                               sensor_location[i] = "";
+
+                       printk(KERN_INFO "sensor %d: %s\n", i, 
sensor_location[i]);
+                       offset += strlen(sensor_location[i]) + 1;
+               }
+       } else {
+               sensor_location[0] = "?";
+               sensor_location[1] = "?";
+               sensor_location[2] = "?";
+       }
+
        of_dev = of_platform_device_create(np, "temperatures");
        
        if (of_dev == NULL) {
@@ -570,15 +607,17 @@
                return -ENODEV;
        }
        
-       device_create_file(&of_dev->dev, &dev_attr_cpu_temperature);
-       device_create_file(&of_dev->dev, &dev_attr_gpu_temperature);
-       device_create_file(&of_dev->dev, &dev_attr_cpu_limit);
-       device_create_file(&of_dev->dev, &dev_attr_gpu_limit);
+       device_create_file(&of_dev->dev, &dev_attr_sensor1_temperature);
+       device_create_file(&of_dev->dev, &dev_attr_sensor2_temperature);
+       device_create_file(&of_dev->dev, &dev_attr_sensor1_limit);
+       device_create_file(&of_dev->dev, &dev_attr_sensor2_limit);
+       device_create_file(&of_dev->dev, &dev_attr_sensor1_location);
+       device_create_file(&of_dev->dev, &dev_attr_sensor2_location);
        device_create_file(&of_dev->dev, &dev_attr_limit_adjust);
        device_create_file(&of_dev->dev, &dev_attr_specified_fan_speed);
-       device_create_file(&of_dev->dev, &dev_attr_cpu_fan_speed);
+       device_create_file(&of_dev->dev, &dev_attr_sensor1_fan_speed);
        if(therm_type == ADT7460)
-               device_create_file(&of_dev->dev, &dev_attr_gpu_fan_speed);
+               device_create_file(&of_dev->dev, &dev_attr_sensor2_fan_speed);
 
 #ifndef CONFIG_I2C_KEYWEST
        request_module("i2c-keywest");
@@ -591,17 +630,19 @@
 thermostat_exit(void)
 {
        if (of_dev) {
-               device_remove_file(&of_dev->dev, &dev_attr_cpu_temperature);
-               device_remove_file(&of_dev->dev, &dev_attr_gpu_temperature);
-               device_remove_file(&of_dev->dev, &dev_attr_cpu_limit);
-               device_remove_file(&of_dev->dev, &dev_attr_gpu_limit);
+               device_remove_file(&of_dev->dev, &dev_attr_sensor1_temperature);
+               device_remove_file(&of_dev->dev, &dev_attr_sensor2_temperature);
+               device_remove_file(&of_dev->dev, &dev_attr_sensor1_limit);
+               device_remove_file(&of_dev->dev, &dev_attr_sensor2_limit);
+               device_remove_file(&of_dev->dev, &dev_attr_sensor1_location);
+               device_remove_file(&of_dev->dev, &dev_attr_sensor2_location);
                device_remove_file(&of_dev->dev, &dev_attr_limit_adjust);
                device_remove_file(&of_dev->dev, &dev_attr_specified_fan_speed);
-               device_remove_file(&of_dev->dev, &dev_attr_cpu_fan_speed);
+               device_remove_file(&of_dev->dev, &dev_attr_sensor1_fan_speed);
 
                if(therm_type == ADT7460)
                        device_remove_file(&of_dev->dev,
-                                          &dev_attr_gpu_fan_speed);
+                                          &dev_attr_sensor2_fan_speed);
 
                of_device_unregister(of_dev);
        }
diff -urN linux/drivers/macintosh/via-pmu.c linux/drivers/macintosh/via-pmu.c
--- linux/drivers/macintosh/via-pmu.c   2005/05/19 12:08:23     1.48
+++ linux/drivers/macintosh/via-pmu.c   2005/06/07 13:45:33     1.49
@@ -2421,7 +2421,7 @@
 
        /* Re-enable local CPU interrupts */
        local_irq_enable();
-       mdelay(100);
+       mdelay(10);
        preempt_enable();
 
        /* Re-enable clock spreading on some machines */
@@ -2549,7 +2549,9 @@
                return ret;
        }
 
-       printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
+       /* Stop environment and ADB interrupts */
+       pmu_request(&req, NULL, 2, PMU_SET_INTR_MASK, 0);
+       pmu_wait_complete(&req);
 
        /* Tell PMU what events will wake us up */
        pmu_request(&req, NULL, 4, PMU_POWER_EVENTS, PMU_PWR_CLR_WAKEUP_EVENTS,
@@ -2611,8 +2613,6 @@
        pmu_request(&req, NULL, 2, PMU_SET_INTR_MASK, pmu_intr_mask);
        pmu_wait_complete(&req);
 
-       printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
-
        pmac_wakeup_devices();
 
        return 0;
diff -urN linux/drivers/media/dvb/bt8xx/dst.c 
linux/drivers/media/dvb/bt8xx/dst.c
--- linux/drivers/media/dvb/bt8xx/dst.c 2005/05/26 09:12:42     1.4
+++ linux/drivers/media/dvb/bt8xx/dst.c 2005/06/07 13:45:33     1.5
@@ -906,22 +906,12 @@
        if (state->dst_type == DST_TYPE_IS_TERR)
                return 0;
 
-       if (state->voltage == SEC_VOLTAGE_OFF)
-               paket[4] = 0;
-       else
-               paket[4] = 1;
-
-       if (state->tone == SEC_TONE_ON)
-               paket[2] = 0x02;
-       else
-               paket[2] = 0;
-       if (state->minicmd == SEC_MINI_A)
-               paket[3] = 0x02;
-       else
-               paket[3] = 0;
-
+       paket[4] = state->tx_tuna[4];
+       paket[2] = state->tx_tuna[2];
+       paket[3] = state->tx_tuna[3];
        paket[7] = dst_check_sum (paket, 7);
        dst_command(state, paket, 8);
+
        return 0;
 }
 
@@ -980,7 +970,7 @@
 
 static int dst_write_tuna(struct dvb_frontend* fe)
 {
-       struct dst_state* state = (struct dst_state*) fe->demodulator_priv;
+       struct dst_state* state = fe->demodulator_priv;
        int retval;
        u8 reply;
 
@@ -1048,10 +1038,10 @@
 
 static int dst_set_diseqc(struct dvb_frontend* fe, struct 
dvb_diseqc_master_cmd* cmd)
 {
-       struct dst_state* state = (struct dst_state*) fe->demodulator_priv;
+       struct dst_state* state = fe->demodulator_priv;
        u8 paket[8] = { 0x00, 0x08, 0x04, 0xe0, 0x10, 0x38, 0xf0, 0xec };
 
-       if (state->dst_type == DST_TYPE_IS_TERR)
+       if (state->dst_type != DST_TYPE_IS_SAT)
                return 0;
 
        if (cmd->msg_len == 0 || cmd->msg_len > 4)
@@ -1064,39 +1054,32 @@
 
 static int dst_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage)
 {
-       u8 *val;
        int need_cmd;
-       struct dst_state* state = (struct dst_state*) fe->demodulator_priv;
+       struct dst_state* state = fe->demodulator_priv;
 
        state->voltage = voltage;
 
-       if (state->dst_type == DST_TYPE_IS_TERR)
+       if (state->dst_type != DST_TYPE_IS_SAT)
                return 0;
 
        need_cmd = 0;
-       val = &state->tx_tuna[0];
-       val[8] &= ~0x40;
        switch (voltage) {
-       case SEC_VOLTAGE_13:
-               if ((state->diseq_flags & HAS_POWER) == 0)
-                       need_cmd = 1;
-               state->diseq_flags |= HAS_POWER;
-               break;
+               case SEC_VOLTAGE_13:
+               case SEC_VOLTAGE_18:
+                       if ((state->diseq_flags & HAS_POWER) == 0)
+                               need_cmd = 1;
+                       state->diseq_flags |= HAS_POWER;
+                       state->tx_tuna[4] = 0x01;
+                       break;
 
-       case SEC_VOLTAGE_18:
-               if ((state->diseq_flags & HAS_POWER) == 0)
+               case SEC_VOLTAGE_OFF:
                        need_cmd = 1;
-               state->diseq_flags |= HAS_POWER;
-               val[8] |= 0x40;
-               break;
+                       state->diseq_flags &= ~(HAS_POWER | HAS_LOCK | 
ATTEMPT_TUNE);
+                       state->tx_tuna[4] = 0x00;
+                       break;
 
-       case SEC_VOLTAGE_OFF:
-               need_cmd = 1;
-               state->diseq_flags &= ~(HAS_POWER | HAS_LOCK | ATTEMPT_TUNE);
-               break;
-
-       default:
-               return -EINVAL;
+               default:
+                       return -EINVAL;
        }
        if (need_cmd)
                dst_tone_power_cmd(state);
@@ -1106,37 +1089,56 @@
 
 static int dst_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
 {
-       u8 *val;
-       struct dst_state* state = (struct dst_state*) fe->demodulator_priv;
+       struct dst_state* state = fe->demodulator_priv;
 
        state->tone = tone;
 
-       if (state->dst_type == DST_TYPE_IS_TERR)
+       if (state->dst_type != DST_TYPE_IS_SAT)
                return 0;
 
-       val = &state->tx_tuna[0];
+       switch (tone) {
+               case SEC_TONE_OFF:
+                       state->tx_tuna[2] = 0xff;
+                       break;
+
+               case SEC_TONE_ON:
+                       state->tx_tuna[2] = 0x02;
+                       break;
 
-       val[8] &= ~0x1;
+               default:
+                       return -EINVAL;
+       }
+       dst_tone_power_cmd(state);
 
-       switch (tone) {
-       case SEC_TONE_OFF:
-               break;
+       return 0;
+}
 
-       case SEC_TONE_ON:
-               val[8] |= 1;
-               break;
+static int dst_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t minicmd)
+{
+       struct dst_state *state = fe->demodulator_priv;
 
-       default:
-               return -EINVAL;
+       if (state->dst_type != DST_TYPE_IS_SAT)
+               return 0;
+
+       state->minicmd = minicmd;
+
+       switch (minicmd) {
+               case SEC_MINI_A:
+                       state->tx_tuna[3] = 0x02;
+                       break;
+               case SEC_MINI_B:
+                       state->tx_tuna[3] = 0xff;
+                       break;
        }
        dst_tone_power_cmd(state);
 
        return 0;
 }
 
+
 static int dst_init(struct dvb_frontend* fe)
 {
-       struct dst_state* state = (struct dst_state*) fe->demodulator_priv;
+       struct dst_state* state = fe->demodulator_priv;
        static u8 ini_satci_tuna[] = { 9, 0, 3, 0xb6, 1, 0, 0x73, 0x21, 0, 0 };
        static u8 ini_satfta_tuna[] = { 0, 0, 3, 0xb6, 1, 0x55, 0xbd, 0x50, 0, 
0 };
        static u8 ini_tvfta_tuna[] = { 0, 0, 3, 0xb6, 1, 7, 0x0, 0x0, 0, 0 };
@@ -1168,7 +1170,7 @@
 
 static int dst_read_status(struct dvb_frontend* fe, fe_status_t* status)
 {
-       struct dst_state* state = (struct dst_state*) fe->demodulator_priv;
+       struct dst_state* state = fe->demodulator_priv;
 
        *status = 0;
        if (state->diseq_flags & HAS_LOCK) {
@@ -1182,7 +1184,7 @@
 
 static int dst_read_signal_strength(struct dvb_frontend* fe, u16* strength)
 {
-       struct dst_state* state = (struct dst_state*) fe->demodulator_priv;
+       struct dst_state* state = fe->demodulator_priv;
 
        dst_get_signal(state);
        *strength = state->decode_strength;
@@ -1192,7 +1194,7 @@
 
 static int dst_read_snr(struct dvb_frontend* fe, u16* snr)
 {
-       struct dst_state* state = (struct dst_state*) fe->demodulator_priv;
+       struct dst_state* state = fe->demodulator_priv;
 
        dst_get_signal(state);
        *snr = state->decode_snr;
@@ -1202,7 +1204,7 @@
 
 static int dst_set_frontend(struct dvb_frontend* fe, struct 
dvb_frontend_parameters *p)
 {
-       struct dst_state* state = (struct dst_state*) fe->demodulator_priv;
+       struct dst_state* state = fe->demodulator_priv;
 
        dst_set_freq(state, p->frequency);
        if (verbose > 4)
@@ -1228,7 +1230,7 @@
 
 static int dst_get_frontend(struct dvb_frontend* fe, struct 
dvb_frontend_parameters *p)
 {
-       struct dst_state* state = (struct dst_state*) fe->demodulator_priv;
+       struct dst_state* state = fe->demodulator_priv;
 
        p->frequency = state->decode_freq;
        p->inversion = state->inversion;
@@ -1248,7 +1250,7 @@
 
 static void dst_release(struct dvb_frontend* fe)
 {
-       struct dst_state* state = (struct dst_state*) fe->demodulator_priv;
+       struct dst_state* state = fe->demodulator_priv;
        kfree(state);
 }
 
@@ -1346,7 +1348,7 @@
        .read_signal_strength = dst_read_signal_strength,
        .read_snr = dst_read_snr,
 
-       .diseqc_send_burst = dst_set_tone,
+       .diseqc_send_burst = dst_send_burst,
        .diseqc_send_master_cmd = dst_set_diseqc,
        .set_voltage = dst_set_voltage,
        .set_tone = dst_set_tone,
diff -urN linux/drivers/media/video/bttv-i2c.c 
linux/drivers/media/video/bttv-i2c.c
--- linux/drivers/media/video/bttv-i2c.c        2005/05/19 12:08:24     1.10
+++ linux/drivers/media/video/bttv-i2c.c        2005/06/07 13:45:33     1.11
@@ -363,6 +363,9 @@
 /* read EEPROM content */
 void __devinit bttv_readee(struct bttv *btv, unsigned char *eedata, int addr)
 {
+       memset(eedata, 0, 256);
+       if (0 != btv->i2c_rc)
+               return;
        btv->i2c_client.addr = addr >> 1;
        tveeprom_read(&btv->i2c_client, eedata, 256);
 }
diff -urN linux/drivers/net/bnx2.c linux/drivers/net/bnx2.c
--- linux/drivers/net/bnx2.c    1970/01/01 00:00:00
+++ linux/drivers/net/bnx2.c    2005-06-07 14:45:34.257012000 +0100     1.1
@@ -0,0 +1,5530 @@
+/* bnx2.c: Broadcom NX2 network driver.
+ *
+ * Copyright (c) 2004, 2005 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Written by: Michael Chan  (mchan@broadcom.com)
+ */
+
+#include "bnx2.h"
+#include "bnx2_fw.h"
+
+#define DRV_MODULE_NAME                "bnx2"
+#define PFX DRV_MODULE_NAME    ": "
+#define DRV_MODULE_VERSION     "1.2.19"
+#define DRV_MODULE_RELDATE     "May 23, 2005"
+
+#define RUN_AT(x) (jiffies + (x))
+
+/* Time in jiffies before concluding the transmitter is hung. */
+#define TX_TIMEOUT  (5*HZ)
+
+static char version[] __devinitdata =
+       "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" 
DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
+
+MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
+MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_MODULE_VERSION);
+
+static int disable_msi = 0;
+
+module_param(disable_msi, int, 0);
+MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
+
+typedef enum {
+       BCM5706 = 0,
+       NC370T,
+       NC370I,
+       BCM5706S,
+       NC370F,
+} board_t;
+
+/* indexed by board_t, above */
+static struct {
+       char *name;
+} board_info[] __devinitdata = {
+       { "Broadcom NetXtreme II BCM5706 1000Base-T" },
+       { "HP NC370T Multifunction Gigabit Server Adapter" },
+       { "HP NC370i Multifunction Gigabit Server Adapter" },
+       { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
+       { "HP NC370F Multifunction Gigabit Server Adapter" },
+       { 0 },
+       };
+
+static struct pci_device_id bnx2_pci_tbl[] = {
+       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
+         PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
+       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
+         PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
+       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
+         PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
+       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
+         PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
+       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
+         PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
+       { 0, }
+};
+
+static struct flash_spec flash_table[] =
+{
+       /* Slow EEPROM */
+       {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
+        1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
+        SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
+        "EEPROM - slow"},
+       /* Fast EEPROM */
+       {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
+        1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
+        SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
+        "EEPROM - fast"},
+       /* ATMEL AT45DB011B (buffered flash) */
+       {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
+        1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
+        BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
+        "Buffered flash"},
+       /* Saifun SA25F005 (non-buffered flash) */
+               /* strap, cfg1, & write1 need updates */
+       {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
+        0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
+        SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
+        "Non-buffered flash (64kB)"},
+       /* Saifun SA25F010 (non-buffered flash) */
+       /* strap, cfg1, & write1 need updates */
+       {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
+        0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
+        SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
+        "Non-buffered flash (128kB)"},
+       /* Saifun SA25F020 (non-buffered flash) */
+       /* strap, cfg1, & write1 need updates */
+       {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
+        0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
+        SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
+        "Non-buffered flash (256kB)"},
+};
+
+MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
+
+static u32
+bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
+{
+       REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
+       return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
+}
+
+static void
+bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
+{
+       REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
+       REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
+}
+
+static void
+bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
+{
+       offset += cid_addr;
+       REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
+       REG_WR(bp, BNX2_CTX_DATA, val);
+}
+
+static int
+bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
+{
+       u32 val1;
+       int i, ret;
+
+       if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+               val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
+               val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
+
+               REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
+               REG_RD(bp, BNX2_EMAC_MDIO_MODE);
+
+               udelay(40);
+       }
+
+       val1 = (bp->phy_addr << 21) | (reg << 16) |
+               BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
+               BNX2_EMAC_MDIO_COMM_START_BUSY;
+       REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
+
+       for (i = 0; i < 50; i++) {
+               udelay(10);
+
+               val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
+               if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
+                       udelay(5);
+
+                       val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
+                       val1 &= BNX2_EMAC_MDIO_COMM_DATA;
+
+                       break;
+               }
+       }
+
+       if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
+               *val = 0x0;
+               ret = -EBUSY;
+       }
+       else {
+               *val = val1;
+               ret = 0;
+       }
+
+       if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+               val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
+               val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
+
+               REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
+               REG_RD(bp, BNX2_EMAC_MDIO_MODE);
+
+               udelay(40);
+       }
+
+       return ret;
+}
+
+static int
+bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
+{
+       u32 val1;
+       int i, ret;
+
+       if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+               val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
+               val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
+
+               REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
+               REG_RD(bp, BNX2_EMAC_MDIO_MODE);
+
+               udelay(40);
+       }
+
+       val1 = (bp->phy_addr << 21) | (reg << 16) | val |
+               BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
+               BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
+       REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
+    
+       for (i = 0; i < 50; i++) {
+               udelay(10);
+
+               val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
+               if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
+                       udelay(5);
+                       break;
+               }
+       }
+
+       if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
+               ret = -EBUSY;
+       else
+               ret = 0;
+
+       if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+               val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
+               val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
+
+               REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
+               REG_RD(bp, BNX2_EMAC_MDIO_MODE);
+
+               udelay(40);
+       }
+
+       return ret;
+}
+
+static void
+bnx2_disable_int(struct bnx2 *bp)
+{
+       REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
+              BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
+       REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
+}
+
+static void
+bnx2_enable_int(struct bnx2 *bp)
+{
+       u32 val;
+
+       REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
+              BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
+
+       val = REG_RD(bp, BNX2_HC_COMMAND);
+       REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
+}
+
+static void
+bnx2_disable_int_sync(struct bnx2 *bp)
+{
+       atomic_inc(&bp->intr_sem);
+       bnx2_disable_int(bp);
+       synchronize_irq(bp->pdev->irq);
+}
+
+static void
+bnx2_netif_stop(struct bnx2 *bp)
+{
+       bnx2_disable_int_sync(bp);
+       if (netif_running(bp->dev)) {
+               netif_poll_disable(bp->dev);
+               netif_tx_disable(bp->dev);
+               bp->dev->trans_start = jiffies; /* prevent tx timeout */
+       }
+}
+
+static void
+bnx2_netif_start(struct bnx2 *bp)
+{
+       if (atomic_dec_and_test(&bp->intr_sem)) {
+               if (netif_running(bp->dev)) {
+                       netif_wake_queue(bp->dev);
+                       netif_poll_enable(bp->dev);
+                       bnx2_enable_int(bp);
+               }
+       }
+}
+
+static void
+bnx2_free_mem(struct bnx2 *bp)
+{
+       if (bp->stats_blk) {
+               pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
+                                   bp->stats_blk, bp->stats_blk_mapping);
+               bp->stats_blk = NULL;
+       }
+       if (bp->status_blk) {
+               pci_free_consistent(bp->pdev, sizeof(struct status_block),
+                                   bp->status_blk, bp->status_blk_mapping);
+               bp->status_blk = NULL;
+       }
+       if (bp->tx_desc_ring) {
+               pci_free_consistent(bp->pdev,
+                                   sizeof(struct tx_bd) * TX_DESC_CNT,
+                                   bp->tx_desc_ring, bp->tx_desc_mapping);
+               bp->tx_desc_ring = NULL;
+       }
+       if (bp->tx_buf_ring) {
+               kfree(bp->tx_buf_ring);
+               bp->tx_buf_ring = NULL;
+       }
+       if (bp->rx_desc_ring) {
+               pci_free_consistent(bp->pdev,
+                                   sizeof(struct rx_bd) * RX_DESC_CNT,
+                                   bp->rx_desc_ring, bp->rx_desc_mapping);
+               bp->rx_desc_ring = NULL;
+       }
+       if (bp->rx_buf_ring) {
+               kfree(bp->rx_buf_ring);
+               bp->rx_buf_ring = NULL;
+       }
+}
+
+static int
+bnx2_alloc_mem(struct bnx2 *bp)
+{
+       bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
+                                    GFP_KERNEL);
+       if (bp->tx_buf_ring == NULL)
+               return -ENOMEM;
+
+       memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
+       bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
+                                               sizeof(struct tx_bd) *
+                                               TX_DESC_CNT,
+                                               &bp->tx_desc_mapping);
+       if (bp->tx_desc_ring == NULL)
+               goto alloc_mem_err;
+
+       bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
+                                    GFP_KERNEL);
+       if (bp->rx_buf_ring == NULL)
+               goto alloc_mem_err;
+
+       memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
+       bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
+                                               sizeof(struct rx_bd) *
+                                               RX_DESC_CNT,
+                                               &bp->rx_desc_mapping);
+       if (bp->rx_desc_ring == NULL)
+               goto alloc_mem_err;
+
+       bp->status_blk = pci_alloc_consistent(bp->pdev,
+                                             sizeof(struct status_block),
+                                             &bp->status_blk_mapping);
+       if (bp->status_blk == NULL)
+               goto alloc_mem_err;
+
+       memset(bp->status_blk, 0, sizeof(struct status_block));
+
+       bp->stats_blk = pci_alloc_consistent(bp->pdev,
+                                            sizeof(struct statistics_block),
+                                            &bp->stats_blk_mapping);
+       if (bp->stats_blk == NULL)
+               goto alloc_mem_err;
+
+       memset(bp->stats_blk, 0, sizeof(struct statistics_block));
+
+       return 0;
+
+alloc_mem_err:
+       bnx2_free_mem(bp);
+       return -ENOMEM;
+}
+
+static void
+bnx2_report_link(struct bnx2 *bp)
+{
+       if (bp->link_up) {
+               netif_carrier_on(bp->dev);
+               printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
+
+               printk("%d Mbps ", bp->line_speed);
+
+               if (bp->duplex == DUPLEX_FULL)
+                       printk("full duplex");
+               else
+                       printk("half duplex");
+
+               if (bp->flow_ctrl) {
+                       if (bp->flow_ctrl & FLOW_CTRL_RX) {
+                               printk(", receive ");
+                               if (bp->flow_ctrl & FLOW_CTRL_TX)
+                                       printk("& transmit ");
+                       }
+                       else {
+                               printk(", transmit ");
+                       }
+                       printk("flow control ON");
+               }
+               printk("\n");
+       }
+       else {
+               netif_carrier_off(bp->dev);
+               printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
+       }
+}
+
+static void
+bnx2_resolve_flow_ctrl(struct bnx2 *bp)
+{
+       u32 local_adv, remote_adv;
+
+       bp->flow_ctrl = 0;
+       if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != 
+               (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
+
+               if (bp->duplex == DUPLEX_FULL) {
+                       bp->flow_ctrl = bp->req_flow_ctrl;
+               }
+               return;
+       }
+
+       if (bp->duplex != DUPLEX_FULL) {
+               return;
+       }
+
+       bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
+       bnx2_read_phy(bp, MII_LPA, &remote_adv);
+
+       if (bp->phy_flags & PHY_SERDES_FLAG) {
+               u32 new_local_adv = 0;
+               u32 new_remote_adv = 0;
+
+               if (local_adv & ADVERTISE_1000XPAUSE)
+                       new_local_adv |= ADVERTISE_PAUSE_CAP;
+               if (local_adv & ADVERTISE_1000XPSE_ASYM)
+                       new_local_adv |= ADVERTISE_PAUSE_ASYM;
+               if (remote_adv & ADVERTISE_1000XPAUSE)
+                       new_remote_adv |= ADVERTISE_PAUSE_CAP;
+               if (remote_adv & ADVERTISE_1000XPSE_ASYM)
+                       new_remote_adv |= ADVERTISE_PAUSE_ASYM;
+
+               local_adv = new_local_adv;
+               remote_adv = new_remote_adv;
+       }
+
+       /* See Table 28B-3 of 802.3ab-1999 spec. */
+       if (local_adv & ADVERTISE_PAUSE_CAP) {
+               if(local_adv & ADVERTISE_PAUSE_ASYM) {
+                       if (remote_adv & ADVERTISE_PAUSE_CAP) {
+                               bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
+                       }
+                       else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
+                               bp->flow_ctrl = FLOW_CTRL_RX;
+                       }
+               }
+               else {
+                       if (remote_adv & ADVERTISE_PAUSE_CAP) {
+                               bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
+                       }
+               }
+       }
+       else if (local_adv & ADVERTISE_PAUSE_ASYM) {
+               if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
+                       (remote_adv & ADVERTISE_PAUSE_ASYM)) {
+
+                       bp->flow_ctrl = FLOW_CTRL_TX;
+               }
+       }
+}
+
+static int
+bnx2_serdes_linkup(struct bnx2 *bp)
+{
+       u32 bmcr, local_adv, remote_adv, common;
+
+       bp->link_up = 1;
+       bp->line_speed = SPEED_1000;
+
+       bnx2_read_phy(bp, MII_BMCR, &bmcr);
+       if (bmcr & BMCR_FULLDPLX) {
+               bp->duplex = DUPLEX_FULL;
+       }
+       else {
+               bp->duplex = DUPLEX_HALF;
+       }
+
+       if (!(bmcr & BMCR_ANENABLE)) {
+               return 0;
+       }
+
+       bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
+       bnx2_read_phy(bp, MII_LPA, &remote_adv);
+
+       common = local_adv & remote_adv;
+       if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
+
+               if (common & ADVERTISE_1000XFULL) {
+                       bp->duplex = DUPLEX_FULL;
+               }
+               else {
+                       bp->duplex = DUPLEX_HALF;
+               }
+       }
+
+       return 0;
+}
+
+static int
+bnx2_copper_linkup(struct bnx2 *bp)
+{
+       u32 bmcr;
+
+       bnx2_read_phy(bp, MII_BMCR, &bmcr);
+       if (bmcr & BMCR_ANENABLE) {
+               u32 local_adv, remote_adv, common;
+
+               bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
+               bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
+
+               common = local_adv & (remote_adv >> 2);
+               if (common & ADVERTISE_1000FULL) {
+                       bp->line_speed = SPEED_1000;
+                       bp->duplex = DUPLEX_FULL;
+               }
+               else if (common & ADVERTISE_1000HALF) {
+                       bp->line_speed = SPEED_1000;
+                       bp->duplex = DUPLEX_HALF;
+               }
+               else {
+                       bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
+                       bnx2_read_phy(bp, MII_LPA, &remote_adv);
+
+                       common = local_adv & remote_adv;
+                       if (common & ADVERTISE_100FULL) {
+                               bp->line_speed = SPEED_100;
+                               bp->duplex = DUPLEX_FULL;
+                       }
+                       else if (common & ADVERTISE_100HALF) {
+                               bp->line_speed = SPEED_100;
+                               bp->duplex = DUPLEX_HALF;
+                       }
+                       else if (common & ADVERTISE_10FULL) {
+                               bp->line_speed = SPEED_10;
+                               bp->duplex = DUPLEX_FULL;
+                       }
+                       else if (common & ADVERTISE_10HALF) {
+                               bp->line_speed = SPEED_10;
+                               bp->duplex = DUPLEX_HALF;
+                       }
+                       else {
+                               bp->line_speed = 0;
+                               bp->link_up = 0;
+                       }
+               }
+       }
+       else {
+               if (bmcr & BMCR_SPEED100) {
+                       bp->line_speed = SPEED_100;
+               }
+               else {
+                       bp->line_speed = SPEED_10;
+               }
+               if (bmcr & BMCR_FULLDPLX) {
+                       bp->duplex = DUPLEX_FULL;
+               }
+               else {
+                       bp->duplex = DUPLEX_HALF;
+               }
+       }
+
+       return 0;
+}
+
+static int
+bnx2_set_mac_link(struct bnx2 *bp)
+{
+       u32 val;
+
+       REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
+       if (bp->link_up && (bp->line_speed == SPEED_1000) &&
+               (bp->duplex == DUPLEX_HALF)) {
+               REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
+       }
+
+       /* Configure the EMAC mode register. */
+       val = REG_RD(bp, BNX2_EMAC_MODE);
+
+       val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
+               BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK);
+
+       if (bp->link_up) {
+               if (bp->line_speed != SPEED_1000)
+                       val |= BNX2_EMAC_MODE_PORT_MII;
+               else
+                       val |= BNX2_EMAC_MODE_PORT_GMII;
+       }
+       else {
+               val |= BNX2_EMAC_MODE_PORT_GMII;
+       }
+
+       /* Set the MAC to operate in the appropriate duplex mode. */
+       if (bp->duplex == DUPLEX_HALF)
+               val |= BNX2_EMAC_MODE_HALF_DUPLEX;
+       REG_WR(bp, BNX2_EMAC_MODE, val);
+
+       /* Enable/disable rx PAUSE. */
+       bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
+
+       if (bp->flow_ctrl & FLOW_CTRL_RX)
+               bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
+       REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
+
+       /* Enable/disable tx PAUSE. */
+       val = REG_RD(bp, BNX2_EMAC_TX_MODE);
+       val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
+
+       if (bp->flow_ctrl & FLOW_CTRL_TX)
+               val |= BNX2_EMAC_TX_MODE_FLOW_EN;
+       REG_WR(bp, BNX2_EMAC_TX_MODE, val);
+
+       /* Acknowledge the interrupt. */
+       REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
+
+       return 0;
+}
+
+static int
+bnx2_set_link(struct bnx2 *bp)
+{
+       u32 bmsr;
+       u8 link_up;
+
+       if (bp->loopback == MAC_LOOPBACK) {
+               bp->link_up = 1;
+               return 0;
+       }
+
+       link_up = bp->link_up;
+
+       bnx2_read_phy(bp, MII_BMSR, &bmsr);
+       bnx2_read_phy(bp, MII_BMSR, &bmsr);
+
+       if ((bp->phy_flags & PHY_SERDES_FLAG) &&
+           (CHIP_NUM(bp) == CHIP_NUM_5706)) {
+               u32 val;
+
+               val = REG_RD(bp, BNX2_EMAC_STATUS);
+               if (val & BNX2_EMAC_STATUS_LINK)
+                       bmsr |= BMSR_LSTATUS;
+               else
+                       bmsr &= ~BMSR_LSTATUS;
+       }
+
+       if (bmsr & BMSR_LSTATUS) {
+               bp->link_up = 1;
+
+               if (bp->phy_flags & PHY_SERDES_FLAG) {
+                       bnx2_serdes_linkup(bp);
+               }
+               else {
+                       bnx2_copper_linkup(bp);
+               }
+               bnx2_resolve_flow_ctrl(bp);
+       }
+       else {
+               if ((bp->phy_flags & PHY_SERDES_FLAG) &&
+                       (bp->autoneg & AUTONEG_SPEED)) {
+
+                       u32 bmcr;
+
+                       bnx2_read_phy(bp, MII_BMCR, &bmcr);
+                       if (!(bmcr & BMCR_ANENABLE)) {
+                               bnx2_write_phy(bp, MII_BMCR, bmcr |
+                                       BMCR_ANENABLE);
+                       }
+               }
+               bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
+               bp->link_up = 0;
+       }
+
+       if (bp->link_up != link_up) {
+               bnx2_report_link(bp);
+       }
+
+       bnx2_set_mac_link(bp);
+
+       return 0;
+}
+
+static int
+bnx2_reset_phy(struct bnx2 *bp)
+{
+       int i;
+       u32 reg;
+
+        bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
+
+#define PHY_RESET_MAX_WAIT 100
+       for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
+               udelay(10);
+
+               bnx2_read_phy(bp, MII_BMCR, &reg);
+               if (!(reg & BMCR_RESET)) {
+                       udelay(20);
+                       break;
+               }
+       }
+       if (i == PHY_RESET_MAX_WAIT) {
+               return -EBUSY;
+       }
+       return 0;
+}
+
+static u32
+bnx2_phy_get_pause_adv(struct bnx2 *bp)
+{
+       u32 adv = 0;
+
+       if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
+               (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
+
+               if (bp->phy_flags & PHY_SERDES_FLAG) {
+                       adv = ADVERTISE_1000XPAUSE;
+               }
+               else {
+                       adv = ADVERTISE_PAUSE_CAP;
+               }
+       }
+       else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
+               if (bp->phy_flags & PHY_SERDES_FLAG) {
+                       adv = ADVERTISE_1000XPSE_ASYM;
+               }
+               else {
+                       adv = ADVERTISE_PAUSE_ASYM;
+               }
+       }
+       else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
+               if (bp->phy_flags & PHY_SERDES_FLAG) {
+                       adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
+               }
+               else {
+                       adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
+               }
+       }
+       return adv;
+}
+
+static int
+bnx2_setup_serdes_phy(struct bnx2 *bp)
+{
+       u32 adv, bmcr;
+       u32 new_adv = 0;
+
+       if (!(bp->autoneg & AUTONEG_SPEED)) {
+               u32 new_bmcr;
+
+               bnx2_read_phy(bp, MII_BMCR, &bmcr);
+               new_bmcr = bmcr & ~BMCR_ANENABLE;
+               new_bmcr |= BMCR_SPEED1000;
+               if (bp->req_duplex == DUPLEX_FULL) {
+                       new_bmcr |= BMCR_FULLDPLX;
+               }
+               else {
+                       new_bmcr &= ~BMCR_FULLDPLX;
+               }
+               if (new_bmcr != bmcr) {
+                       /* Force a link down visible on the other side */
+                       if (bp->link_up) {
+                               bnx2_read_phy(bp, MII_ADVERTISE, &adv);
+                               adv &= ~(ADVERTISE_1000XFULL |
+                                       ADVERTISE_1000XHALF);
+                               bnx2_write_phy(bp, MII_ADVERTISE, adv);
+                               bnx2_write_phy(bp, MII_BMCR, bmcr |
+                                       BMCR_ANRESTART | BMCR_ANENABLE);
+
+                               bp->link_up = 0;
+                               netif_carrier_off(bp->dev);
+                       }
+                       bnx2_write_phy(bp, MII_BMCR, new_bmcr);
+               }
+               return 0;
+       }
+
+       if (bp->advertising & ADVERTISED_1000baseT_Full)
+               new_adv |= ADVERTISE_1000XFULL;
+
+       new_adv |= bnx2_phy_get_pause_adv(bp);
+
+       bnx2_read_phy(bp, MII_ADVERTISE, &adv);
+       bnx2_read_phy(bp, MII_BMCR, &bmcr);
+
+       bp->serdes_an_pending = 0;
+       if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
+               /* Force a link down visible on the other side */
+               if (bp->link_up) {
+                       int i;
+
+                       bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
+                       for (i = 0; i < 110; i++) {
+                               udelay(100);
+                       }
+               }
+
+               bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
+               bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
+                       BMCR_ANENABLE);
+               bp->serdes_an_pending = SERDES_AN_TIMEOUT / bp->timer_interval;
+       }
+
+       return 0;
+}
+
+#define ETHTOOL_ALL_FIBRE_SPEED                                                
\
+       (ADVERTISED_1000baseT_Full)
+
+#define ETHTOOL_ALL_COPPER_SPEED                                       \
+       (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
+       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
+       ADVERTISED_1000baseT_Full)
+
+#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+       ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
+       
+#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
+
+static int
+bnx2_setup_copper_phy(struct bnx2 *bp)
+{
+       u32 bmcr;
+       u32 new_bmcr;
+
+       bnx2_read_phy(bp, MII_BMCR, &bmcr);
+
+       if (bp->autoneg & AUTONEG_SPEED) {
+               u32 adv_reg, adv1000_reg;
+               u32 new_adv_reg = 0;
+               u32 new_adv1000_reg = 0;
+
+               bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
+               adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
+                       ADVERTISE_PAUSE_ASYM);
+
+               bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
+               adv1000_reg &= PHY_ALL_1000_SPEED;
+
+               if (bp->advertising & ADVERTISED_10baseT_Half)
+                       new_adv_reg |= ADVERTISE_10HALF;
+               if (bp->advertising & ADVERTISED_10baseT_Full)
+                       new_adv_reg |= ADVERTISE_10FULL;
+               if (bp->advertising & ADVERTISED_100baseT_Half)
+                       new_adv_reg |= ADVERTISE_100HALF;
+               if (bp->advertising & ADVERTISED_100baseT_Full)
+                       new_adv_reg |= ADVERTISE_100FULL;
+               if (bp->advertising & ADVERTISED_1000baseT_Full)
+                       new_adv1000_reg |= ADVERTISE_1000FULL;
+               
+               new_adv_reg |= ADVERTISE_CSMA;
+
+               new_adv_reg |= bnx2_phy_get_pause_adv(bp);
+
+               if ((adv1000_reg != new_adv1000_reg) ||
+                       (adv_reg != new_adv_reg) ||
+                       ((bmcr & BMCR_ANENABLE) == 0)) {
+
+                       bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
+                       bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
+                       bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
+                               BMCR_ANENABLE);
+               }
+               else if (bp->link_up) {
+                       /* Flow ctrl may have changed from auto to forced */
+                       /* or vice-versa. */
+
+                       bnx2_resolve_flow_ctrl(bp);
+                       bnx2_set_mac_link(bp);
+               }
+               return 0;
+       }
+
+       new_bmcr = 0;
+       if (bp->req_line_speed == SPEED_100) {
+               new_bmcr |= BMCR_SPEED100;
+       }
+       if (bp->req_duplex == DUPLEX_FULL) {
+               new_bmcr |= BMCR_FULLDPLX;
+       }
+       if (new_bmcr != bmcr) {
+               u32 bmsr;
+               int i = 0;
+
+               bnx2_read_phy(bp, MII_BMSR, &bmsr);
+               bnx2_read_phy(bp, MII_BMSR, &bmsr);
+               
+               if (bmsr & BMSR_LSTATUS) {
+                       /* Force link down */
+                       bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
+                       do {
+                               udelay(100);
+                               bnx2_read_phy(bp, MII_BMSR, &bmsr);
+                               bnx2_read_phy(bp, MII_BMSR, &bmsr);
+                               i++;
+                       } while ((bmsr & BMSR_LSTATUS) && (i < 620));
+               }
+
+               bnx2_write_phy(bp, MII_BMCR, new_bmcr);
+
+               /* Normally, the new speed is setup after the link has
+                * gone down and up again. In some cases, link will not go
+                * down so we need to set up the new speed here.
+                */
+               if (bmsr & BMSR_LSTATUS) {
+                       bp->line_speed = bp->req_line_speed;
+                       bp->duplex = bp->req_duplex;
+                       bnx2_resolve_flow_ctrl(bp);
+                       bnx2_set_mac_link(bp);
+               }
+       }
+       return 0;
+}
+
+static int
+bnx2_setup_phy(struct bnx2 *bp)
+{
+       if (bp->loopback == MAC_LOOPBACK)
+               return 0;
+
+       if (bp->phy_flags & PHY_SERDES_FLAG) {
+               return (bnx2_setup_serdes_phy(bp));
+       }
+       else {
+               return (bnx2_setup_copper_phy(bp));
+       }
+}
+
+static int
+bnx2_init_serdes_phy(struct bnx2 *bp)
+{
+       bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
+
+       if (CHIP_NUM(bp) == CHIP_NUM_5706) {
+               REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
+       }
+
+       if (bp->dev->mtu > 1500) {
+               u32 val;
+
+               /* Set extended packet length bit */
+               bnx2_write_phy(bp, 0x18, 0x7);
+               bnx2_read_phy(bp, 0x18, &val);
+               bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
+
+               bnx2_write_phy(bp, 0x1c, 0x6c00);
+               bnx2_read_phy(bp, 0x1c, &val);
+               bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
+       }
+       else {
+               u32 val;
+
+               bnx2_write_phy(bp, 0x18, 0x7);
+               bnx2_read_phy(bp, 0x18, &val);
+               bnx2_write_phy(bp, 0x18, val & ~0x4007);
+
+               bnx2_write_phy(bp, 0x1c, 0x6c00);
+               bnx2_read_phy(bp, 0x1c, &val);
+               bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
+       }
+
+       return 0;
+}
+
+static int
+bnx2_init_copper_phy(struct bnx2 *bp)
+{
+       bp->phy_flags |= PHY_CRC_FIX_FLAG;
+
+       if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
+               bnx2_write_phy(bp, 0x18, 0x0c00);
+               bnx2_write_phy(bp, 0x17, 0x000a);
+               bnx2_write_phy(bp, 0x15, 0x310b);
+               bnx2_write_phy(bp, 0x17, 0x201f);
+               bnx2_write_phy(bp, 0x15, 0x9506);
+               bnx2_write_phy(bp, 0x17, 0x401f);
+               bnx2_write_phy(bp, 0x15, 0x14e2);
+               bnx2_write_phy(bp, 0x18, 0x0400);
+       }
+
+       if (bp->dev->mtu > 1500) {
+               u32 val;
+
+               /* Set extended packet length bit */
+               bnx2_write_phy(bp, 0x18, 0x7);
+               bnx2_read_phy(bp, 0x18, &val);
+               bnx2_write_phy(bp, 0x18, val | 0x4000);
+
+               bnx2_read_phy(bp, 0x10, &val);
+               bnx2_write_phy(bp, 0x10, val | 0x1);
+       }
+       else {
+               u32 val;
+
+               bnx2_write_phy(bp, 0x18, 0x7);
+               bnx2_read_phy(bp, 0x18, &val);
+               bnx2_write_phy(bp, 0x18, val & ~0x4007);
+
+               bnx2_read_phy(bp, 0x10, &val);
+               bnx2_write_phy(bp, 0x10, val & ~0x1);
+       }
+
+       return 0;
+}
+
+
+static int
+bnx2_init_phy(struct bnx2 *bp)
+{
+       u32 val;
+       int rc = 0;
+
+       bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
+       bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
+
+        REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
+
+       bnx2_reset_phy(bp);
+
+       bnx2_read_phy(bp, MII_PHYSID1, &val);
+       bp->phy_id = val << 16;
+       bnx2_read_phy(bp, MII_PHYSID2, &val);
+       bp->phy_id |= val & 0xffff;
+
+       if (bp->phy_flags & PHY_SERDES_FLAG) {
+               rc = bnx2_init_serdes_phy(bp);
+       }
+       else {
+               rc = bnx2_init_copper_phy(bp);
+       }
+
+       bnx2_setup_phy(bp);
+
+       return rc;
+}
+
+static int
+bnx2_set_mac_loopback(struct bnx2 *bp)
+{
+       u32 mac_mode;
+
+       mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
+       mac_mode &= ~BNX2_EMAC_MODE_PORT;
+       mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
+       REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
+       bp->link_up = 1;
+       return 0;
+}
+
+static int
+bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
+{
+       int i;
+       u32 val;
+
+       if (bp->fw_timed_out)
+               return -EBUSY;
+
+       bp->fw_wr_seq++;
+       msg_data |= bp->fw_wr_seq;
+
+       REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
+
+       /* wait for an acknowledgement. */
+       for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
+               udelay(5);
+
+               val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
+
+               if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
+                       break;
+       }
+
+       /* If we timed out, inform the firmware that this is the case. */
+       if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
+               ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
+
+               msg_data &= ~BNX2_DRV_MSG_CODE;
+               msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
+
+               REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
+
+               bp->fw_timed_out = 1;
+
+               return -EBUSY;
+       }
+
+       return 0;
+}
+
+static void
+bnx2_init_context(struct bnx2 *bp)
+{
+       u32 vcid;
+
+       vcid = 96;
+       while (vcid) {
+               u32 vcid_addr, pcid_addr, offset;
+
+               vcid--;
+
+               if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
+                       u32 new_vcid;
+
+                       vcid_addr = GET_PCID_ADDR(vcid);
+                       if (vcid & 0x8) {
+                               new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
+                       }
+                       else {
+                               new_vcid = vcid;
+                       }
+                       pcid_addr = GET_PCID_ADDR(new_vcid);
+               }
+               else {
+                       vcid_addr = GET_CID_ADDR(vcid);
+                       pcid_addr = vcid_addr;
+               }
+
+               REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
+               REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
+
+               /* Zero out the context. */
+               for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
+                       CTX_WR(bp, 0x00, offset, 0);
+               }
+
+               REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
+               REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
+       }
+}
+
+static int
+bnx2_alloc_bad_rbuf(struct bnx2 *bp)
+{
+       u16 *good_mbuf;
+       u32 good_mbuf_cnt;
+       u32 val;
+
+       good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
+       if (good_mbuf == NULL) {
+               printk(KERN_ERR PFX "Failed to allocate memory in "
+                                   "bnx2_alloc_bad_rbuf\n");
+               return -ENOMEM;
+       }
+
+       REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
+               BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
+
+       good_mbuf_cnt = 0;
+
+       /* Allocate a bunch of mbufs and save the good ones in an array. */
+       val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
+       while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
+               REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
+
+               val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
+
+               val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
+
+               /* The addresses with Bit 9 set are bad memory blocks. */
+               if (!(val & (1 << 9))) {
+                       good_mbuf[good_mbuf_cnt] = (u16) val;
+                       good_mbuf_cnt++;
+               }
+
+               val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
+       }
+
+       /* Free the good ones back to the mbuf pool thus discarding
+        * all the bad ones. */
+       while (good_mbuf_cnt) {
+               good_mbuf_cnt--;
+
+               val = good_mbuf[good_mbuf_cnt];
+               val = (val << 9) | val | 1;
+
+               REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
+       }
+       kfree(good_mbuf);
+       return 0;
+}
+
+static void
+bnx2_set_mac_addr(struct bnx2 *bp) 
+{
+       u32 val;
+       u8 *mac_addr = bp->dev->dev_addr;
+
+       val = (mac_addr[0] << 8) | mac_addr[1];
+
+       REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
+
+       val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 
+               (mac_addr[4] << 8) | mac_addr[5];
+
+       REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
+}
+
+static inline int
+bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
+{
+       struct sk_buff *skb;
+       struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
+       dma_addr_t mapping;
+       struct rx_bd *rxbd = &bp->rx_desc_ring[index];
+       unsigned long align;
+
+       skb = dev_alloc_skb(bp->rx_buf_size);
+       if (skb == NULL) {
+               return -ENOMEM;
+       }
+
+       if (unlikely((align = (unsigned long) skb->data & 0x7))) {
+               skb_reserve(skb, 8 - align);
+       }
+
+       skb->dev = bp->dev;
+       mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
+               PCI_DMA_FROMDEVICE);
+
+       rx_buf->skb = skb;
+       pci_unmap_addr_set(rx_buf, mapping, mapping);
+
+       rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
+       rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
+
+       bp->rx_prod_bseq += bp->rx_buf_use_size;
+
+       return 0;
+}
+
+static void
+bnx2_phy_int(struct bnx2 *bp)
+{
+       u32 new_link_state, old_link_state;
+
+       new_link_state = bp->status_blk->status_attn_bits &
+               STATUS_ATTN_BITS_LINK_STATE;
+       old_link_state = bp->status_blk->status_attn_bits_ack &
+               STATUS_ATTN_BITS_LINK_STATE;
+       if (new_link_state != old_link_state) {
+               if (new_link_state) {
+                       REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
+                               STATUS_ATTN_BITS_LINK_STATE);
+               }
+               else {
+                       REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
+                               STATUS_ATTN_BITS_LINK_STATE);
+               }
+               bnx2_set_link(bp);
+       }
+}
+
+static void
+bnx2_tx_int(struct bnx2 *bp)
+{
+       u16 hw_cons, sw_cons, sw_ring_cons;
+       int tx_free_bd = 0;
+
+       hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
+       if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
+               hw_cons++;
+       }
+       sw_cons = bp->tx_cons;
+
+       while (sw_cons != hw_cons) {
+               struct sw_bd *tx_buf;
+               struct sk_buff *skb;
+               int i, last;
+
+               sw_ring_cons = TX_RING_IDX(sw_cons);
+
+               tx_buf = &bp->tx_buf_ring[sw_ring_cons];
+               skb = tx_buf->skb;
+#ifdef BCM_TSO 
+               /* partial BD completions possible with TSO packets */
+               if (skb_shinfo(skb)->tso_size) {
+                       u16 last_idx, last_ring_idx;
+
+                       last_idx = sw_cons +
+                               skb_shinfo(skb)->nr_frags + 1;
+                       last_ring_idx = sw_ring_cons +
+                               skb_shinfo(skb)->nr_frags + 1;
+                       if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
+                               last_idx++;
+                       }
+                       if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
+                               break;
+                       }
+               }
+#endif
+               pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
+                       skb_headlen(skb), PCI_DMA_TODEVICE);
+
+               tx_buf->skb = NULL;
+               last = skb_shinfo(skb)->nr_frags;
+
+               for (i = 0; i < last; i++) {
+                       sw_cons = NEXT_TX_BD(sw_cons);
+
+                       pci_unmap_page(bp->pdev,
+                               pci_unmap_addr(
+                                       &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
+                                       mapping),
+                               skb_shinfo(skb)->frags[i].size,
+                               PCI_DMA_TODEVICE);
+               }
+
+               sw_cons = NEXT_TX_BD(sw_cons);
+
+               tx_free_bd += last + 1;
+
+               dev_kfree_skb_irq(skb);
+
+               hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
+               if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
+                       hw_cons++;
+               }
+       }
+
+       atomic_add(tx_free_bd, &bp->tx_avail_bd);
+
+       if (unlikely(netif_queue_stopped(bp->dev))) {
+               unsigned long flags;
+
+               spin_lock_irqsave(&bp->tx_lock, flags);
+               if ((netif_queue_stopped(bp->dev)) &&
+                       (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS)) {
+
+                       netif_wake_queue(bp->dev);
+               }
+               spin_unlock_irqrestore(&bp->tx_lock, flags);
+       }
+
+       bp->tx_cons = sw_cons;
+
+}
+
+static inline void
+bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
+       u16 cons, u16 prod)
+{
+       struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
+       struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
+       struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
+       struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
+
+       pci_dma_sync_single_for_device(bp->pdev,
+               pci_unmap_addr(cons_rx_buf, mapping),
+               bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
+
+       prod_rx_buf->skb = cons_rx_buf->skb;
+       pci_unmap_addr_set(prod_rx_buf, mapping,
+                       pci_unmap_addr(cons_rx_buf, mapping));
+
+       memcpy(prod_bd, cons_bd, 8);
+
+       bp->rx_prod_bseq += bp->rx_buf_use_size;
+
+}
+
+static int
+bnx2_rx_int(struct bnx2 *bp, int budget)
+{
+       u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
+       struct l2_fhdr *rx_hdr;
+       int rx_pkt = 0;
+
+       hw_cons = bp->status_blk->status_rx_quick_consumer_index0;
+       if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
+               hw_cons++;
+       }
+       sw_cons = bp->rx_cons;
+       sw_prod = bp->rx_prod;
+
+       /* Memory barrier necessary as speculative reads of the rx
+        * buffer can be ahead of the index in the status block
+        */
+       rmb();
+       while (sw_cons != hw_cons) {
+               unsigned int len;
+               u16 status;
+               struct sw_bd *rx_buf;
+               struct sk_buff *skb;
+
+               sw_ring_cons = RX_RING_IDX(sw_cons);
+               sw_ring_prod = RX_RING_IDX(sw_prod);
+
+               rx_buf = &bp->rx_buf_ring[sw_ring_cons];
+               skb = rx_buf->skb;
+               pci_dma_sync_single_for_cpu(bp->pdev,
+                       pci_unmap_addr(rx_buf, mapping),
+                       bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
+
+               rx_hdr = (struct l2_fhdr *) skb->data;
+               len = rx_hdr->l2_fhdr_pkt_len - 4;
+
+               if (rx_hdr->l2_fhdr_errors &
+                       (L2_FHDR_ERRORS_BAD_CRC |
+                       L2_FHDR_ERRORS_PHY_DECODE |
+                       L2_FHDR_ERRORS_ALIGNMENT |
+                       L2_FHDR_ERRORS_TOO_SHORT |
+                       L2_FHDR_ERRORS_GIANT_FRAME)) {
+
+                       goto reuse_rx;
+               }
+
+               /* Since we don't have a jumbo ring, copy small packets
+                * if mtu > 1500
+                */
+               if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
+                       struct sk_buff *new_skb;
+
+                       new_skb = dev_alloc_skb(len + 2);
+                       if (new_skb == NULL)
+                               goto reuse_rx;
+
+                       /* aligned copy */
+                       memcpy(new_skb->data,
+                               skb->data + bp->rx_offset - 2,
+                               len + 2);
+
+                       skb_reserve(new_skb, 2);
+                       skb_put(new_skb, len);
+                       new_skb->dev = bp->dev;
+
+                       bnx2_reuse_rx_skb(bp, skb,
+                               sw_ring_cons, sw_ring_prod);
+
+                       skb = new_skb;
+               }
+               else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
+                       pci_unmap_single(bp->pdev,
+                               pci_unmap_addr(rx_buf, mapping),
+                               bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
+
+                       skb_reserve(skb, bp->rx_offset);
+                       skb_put(skb, len);
+               }
+               else {
+reuse_rx:
+                       bnx2_reuse_rx_skb(bp, skb,
+                               sw_ring_cons, sw_ring_prod);
+                       goto next_rx;
+               }
+
+               skb->protocol = eth_type_trans(skb, bp->dev);
+
+               if ((len > (bp->dev->mtu + ETH_HLEN)) &&
+                       (htons(skb->protocol) != 0x8100)) {
+
+                       dev_kfree_skb_irq(skb);
+                       goto next_rx;
+
+               }
+
+               status = rx_hdr->l2_fhdr_status;
+               skb->ip_summed = CHECKSUM_NONE;
+               if (bp->rx_csum &&
+                       (status & (L2_FHDR_STATUS_TCP_SEGMENT |
+                       L2_FHDR_STATUS_UDP_DATAGRAM))) {
+
+                       u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
+
+                       if (cksum == 0xffff)
+                               skb->ip_summed = CHECKSUM_UNNECESSARY;
+               }
+
+#ifdef BCM_VLAN
+               if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
+                       vlan_hwaccel_receive_skb(skb, bp->vlgrp,
+                               rx_hdr->l2_fhdr_vlan_tag);
+               }
+               else
+#endif
+                       netif_receive_skb(skb);
+
+               bp->dev->last_rx = jiffies;
+               rx_pkt++;
+
+next_rx:
+               rx_buf->skb = NULL;
+
+               sw_cons = NEXT_RX_BD(sw_cons);
+               sw_prod = NEXT_RX_BD(sw_prod);
+
+               if ((rx_pkt == budget))
+                       break;
+       }
+       bp->rx_cons = sw_cons;
+       bp->rx_prod = sw_prod;
+
+       REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
+
+       REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
+
+       mmiowb();
+
+       return rx_pkt;
+
+}
+
+/* MSI ISR - The only difference between this and the INTx ISR
+ * is that the MSI interrupt is always serviced.
+ */
+static irqreturn_t
+bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
+{
+       struct net_device *dev = dev_instance;
+       struct bnx2 *bp = dev->priv;
+
+       REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
+               BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
+               BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
+
+       /* Return here if interrupt is disabled. */
+       if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
+               return IRQ_RETVAL(1);
+       }
+
+       if (netif_rx_schedule_prep(dev)) {
+               __netif_rx_schedule(dev);
+       }
+
+       return IRQ_RETVAL(1);
+}
+
+static irqreturn_t
+bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
+{
+       struct net_device *dev = dev_instance;
+       struct bnx2 *bp = dev->priv;
+
+       /* When using INTx, it is possible for the interrupt to arrive
+        * at the CPU before the status block posted prior to the
+        * interrupt. Reading a register will flush the status block.
+        * When using MSI, the MSI message will always complete after
+        * the status block write.
+        */
+       if ((bp->status_blk->status_idx == bp->last_status_idx) ||
+           (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
+            BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
+               return IRQ_RETVAL(0);
+
+       REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
+               BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
+               BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
+
+       /* Return here if interrupt is shared and is disabled. */
+       if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
+               return IRQ_RETVAL(1);
+       }
+
+       if (netif_rx_schedule_prep(dev)) {
+               __netif_rx_schedule(dev);
+       }
+
+       return IRQ_RETVAL(1);
+}
+
+static int
+bnx2_poll(struct net_device *dev, int *budget)
+{
+       struct bnx2 *bp = dev->priv;
+       int rx_done = 1;
+
+       bp->last_status_idx = bp->status_blk->status_idx;
+
+       rmb();
+       if ((bp->status_blk->status_attn_bits &
+               STATUS_ATTN_BITS_LINK_STATE) !=
+               (bp->status_blk->status_attn_bits_ack &
+               STATUS_ATTN_BITS_LINK_STATE)) {
+
+               unsigned long flags;
+
+               spin_lock_irqsave(&bp->phy_lock, flags);
+               bnx2_phy_int(bp);
+               spin_unlock_irqrestore(&bp->phy_lock, flags);
+       }
+
+       if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) {
+               bnx2_tx_int(bp);
+       }
+
+       if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
+               int orig_budget = *budget;
+               int work_done;
+
+               if (orig_budget > dev->quota)
+                       orig_budget = dev->quota;
+               
+               work_done = bnx2_rx_int(bp, orig_budget);
+               *budget -= work_done;
+               dev->quota -= work_done;
+               
+               if (work_done >= orig_budget) {
+                       rx_done = 0;
+               }
+       }
+       
+       if (rx_done) {
+               netif_rx_complete(dev);
+               REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
+                       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
+                       bp->last_status_idx);
+               return 0;
+       }
+
+       return 1;
+}
+
+/* Called with rtnl_lock from vlan functions and also dev->xmit_lock
+ * from set_multicast.
+ */
+static void
+bnx2_set_rx_mode(struct net_device *dev)
+{
+       struct bnx2 *bp = dev->priv;
+       u32 rx_mode, sort_mode;
+       int i;
+       unsigned long flags;
+
+       spin_lock_irqsave(&bp->phy_lock, flags);
+
+       rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
+                                 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
+       sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
+#ifdef BCM_VLAN
+       if (!bp->vlgrp) {
+               rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
+       }
+#else
+       rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
+#endif
+       if (dev->flags & IFF_PROMISC) {
+               /* Promiscuous mode. */
+               rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
+               sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
+       }
+       else if (dev->flags & IFF_ALLMULTI) {
+               for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
+                       REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
+                              0xffffffff);
+               }
+               sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
+       }
+       else {
+               /* Accept one or more multicast(s). */
+               struct dev_mc_list *mclist;
+               u32 mc_filter[NUM_MC_HASH_REGISTERS];
+               u32 regidx;
+               u32 bit;
+               u32 crc;
+
+               memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
+
+               for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
+                    i++, mclist = mclist->next) {
+
+                       crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
+                       bit = crc & 0xff;
+                       regidx = (bit & 0xe0) >> 5;
+                       bit &= 0x1f;
+                       mc_filter[regidx] |= (1 << bit);
+               }
+
+               for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
+                       REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
+                              mc_filter[i]);
+               }
+
+               sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
+       }
+
+       if (rx_mode != bp->rx_mode) {
+               bp->rx_mode = rx_mode;
+               REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
+       }
+
+       REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
+       REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
+       REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
+
+       spin_unlock_irqrestore(&bp->phy_lock, flags);
+}
+
+static void
+load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
+       u32 rv2p_proc)
+{
+       int i;
+       u32 val;
+
+
+       for (i = 0; i < rv2p_code_len; i += 8) {
+               REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
+               rv2p_code++;
+               REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
+               rv2p_code++;
+
+               if (rv2p_proc == RV2P_PROC1) {
+                       val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
+                       REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
+               }
+               else {
+                       val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
+                       REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
+               }
+       }
+
+       /* Reset the processor, un-stall is done later. */
+       if (rv2p_proc == RV2P_PROC1) {
+               REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
+       }
+       else {
+               REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
+       }
+}
+
+static void
+load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
+{
+       u32 offset;
+       u32 val;
+
+       /* Halt the CPU. */
+       val = REG_RD_IND(bp, cpu_reg->mode);
+       val |= cpu_reg->mode_value_halt;
+       REG_WR_IND(bp, cpu_reg->mode, val);
+       REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
+
+       /* Load the Text area. */
+       offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
+       if (fw->text) {
+               int j;
+
+               for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
+                       REG_WR_IND(bp, offset, fw->text[j]);
+               }
+       }
+
+       /* Load the Data area. */
+       offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
+       if (fw->data) {
+               int j;
+
+               for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
+                       REG_WR_IND(bp, offset, fw->data[j]);
+               }
+       }
+
+       /* Load the SBSS area. */
+       offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
+       if (fw->sbss) {
+               int j;
+
+               for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
+                       REG_WR_IND(bp, offset, fw->sbss[j]);
+               }
+       }
+
+       /* Load the BSS area. */
+       offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
+       if (fw->bss) {
+               int j;
+
+               for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
+                       REG_WR_IND(bp, offset, fw->bss[j]);
+               }
+       }
+
+       /* Load the Read-Only area. */
+       offset = cpu_reg->spad_base +
+               (fw->rodata_addr - cpu_reg->mips_view_base);
+       if (fw->rodata) {
+               int j;
+
+               for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
+                       REG_WR_IND(bp, offset, fw->rodata[j]);
+               }
+       }
+
+       /* Clear the pre-fetch instruction. */
+       REG_WR_IND(bp, cpu_reg->inst, 0);
+       REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
+
+       /* Start the CPU. */
+       val = REG_RD_IND(bp, cpu_reg->mode);
+       val &= ~cpu_reg->mode_value_halt;
+       REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
+       REG_WR_IND(bp, cpu_reg->mode, val);
+}
+
+static void
+bnx2_init_cpus(struct bnx2 *bp)
+{
+       struct cpu_reg cpu_reg;
+       struct fw_info fw;
+
+       /* Initialize the RV2P processor. */
+       load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
+       load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
+
+       /* Initialize the RX Processor. */
+       cpu_reg.mode = BNX2_RXP_CPU_MODE;
+       cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
+       cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
+       cpu_reg.state = BNX2_RXP_CPU_STATE;
+       cpu_reg.state_value_clear = 0xffffff;
+       cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
+       cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
+       cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
+       cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
+       cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
+       cpu_reg.spad_base = BNX2_RXP_SCRATCH;
+       cpu_reg.mips_view_base = 0x8000000;
+    
+       fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
+       fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
+       fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
+       fw.start_addr = bnx2_RXP_b06FwStartAddr;
+
+       fw.text_addr = bnx2_RXP_b06FwTextAddr;
+       fw.text_len = bnx2_RXP_b06FwTextLen;
+       fw.text_index = 0;
+       fw.text = bnx2_RXP_b06FwText;
+
+       fw.data_addr = bnx2_RXP_b06FwDataAddr;
+       fw.data_len = bnx2_RXP_b06FwDataLen;
+       fw.data_index = 0;
+       fw.data = bnx2_RXP_b06FwData;
+
+       fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
+       fw.sbss_len = bnx2_RXP_b06FwSbssLen;
+       fw.sbss_index = 0;
+       fw.sbss = bnx2_RXP_b06FwSbss;
+
+       fw.bss_addr = bnx2_RXP_b06FwBssAddr;
+       fw.bss_len = bnx2_RXP_b06FwBssLen;
+       fw.bss_index = 0;
+       fw.bss = bnx2_RXP_b06FwBss;
+
+       fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
+       fw.rodata_len = bnx2_RXP_b06FwRodataLen;
+       fw.rodata_index = 0;
+       fw.rodata = bnx2_RXP_b06FwRodata;
+
+       load_cpu_fw(bp, &cpu_reg, &fw);
+
+       /* Initialize the TX Processor. */
+       cpu_reg.mode = BNX2_TXP_CPU_MODE;
+       cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
+       cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
+       cpu_reg.state = BNX2_TXP_CPU_STATE;
+       cpu_reg.state_value_clear = 0xffffff;
+       cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
+       cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
+       cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
+       cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
+       cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
+       cpu_reg.spad_base = BNX2_TXP_SCRATCH;
+       cpu_reg.mips_view_base = 0x8000000;
+    
+       fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
+       fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
+       fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
+       fw.start_addr = bnx2_TXP_b06FwStartAddr;
+
+       fw.text_addr = bnx2_TXP_b06FwTextAddr;
+       fw.text_len = bnx2_TXP_b06FwTextLen;
+       fw.text_index = 0;
+       fw.text = bnx2_TXP_b06FwText;
+
+       fw.data_addr = bnx2_TXP_b06FwDataAddr;
+       fw.data_len = bnx2_TXP_b06FwDataLen;
+       fw.data_index = 0;
+       fw.data = bnx2_TXP_b06FwData;
+
+       fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
+       fw.sbss_len = bnx2_TXP_b06FwSbssLen;
+       fw.sbss_index = 0;
+       fw.sbss = bnx2_TXP_b06FwSbss;
+
+       fw.bss_addr = bnx2_TXP_b06FwBssAddr;
+       fw.bss_len = bnx2_TXP_b06FwBssLen;
+       fw.bss_index = 0;
+       fw.bss = bnx2_TXP_b06FwBss;
+
+       fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
+       fw.rodata_len = bnx2_TXP_b06FwRodataLen;
+       fw.rodata_index = 0;
+       fw.rodata = bnx2_TXP_b06FwRodata;
+
+       load_cpu_fw(bp, &cpu_reg, &fw);
+
+       /* Initialize the TX Patch-up Processor. */
+       cpu_reg.mode = BNX2_TPAT_CPU_MODE;
+       cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
+       cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
+       cpu_reg.state = BNX2_TPAT_CPU_STATE;
+       cpu_reg.state_value_clear = 0xffffff;
+       cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
+       cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
+       cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
+       cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
+       cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
+       cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
+       cpu_reg.mips_view_base = 0x8000000;
+    
+       fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
+       fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
+       fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
+       fw.start_addr = bnx2_TPAT_b06FwStartAddr;
+
+       fw.text_addr = bnx2_TPAT_b06FwTextAddr;
+       fw.text_len = bnx2_TPAT_b06FwTextLen;
+       fw.text_index = 0;
+       fw.text = bnx2_TPAT_b06FwText;
+
+       fw.data_addr = bnx2_TPAT_b06FwDataAddr;
+       fw.data_len = bnx2_TPAT_b06FwDataLen;
+       fw.data_index = 0;
+       fw.data = bnx2_TPAT_b06FwData;
+
+       fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
+       fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
+       fw.sbss_index = 0;
+       fw.sbss = bnx2_TPAT_b06FwSbss;
+
+       fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
+       fw.bss_len = bnx2_TPAT_b06FwBssLen;
+       fw.bss_index = 0;
+       fw.bss = bnx2_TPAT_b06FwBss;
+
+       fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
+       fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
+       fw.rodata_index = 0;
+       fw.rodata = bnx2_TPAT_b06FwRodata;
+
+       load_cpu_fw(bp, &cpu_reg, &fw);
+
+       /* Initialize the Completion Processor. */
+       cpu_reg.mode = BNX2_COM_CPU_MODE;
+       cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
+       cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
+       cpu_reg.state = BNX2_COM_CPU_STATE;
+       cpu_reg.state_value_clear = 0xffffff;
+       cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
+       cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
+       cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
+       cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
+       cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
+       cpu_reg.spad_base = BNX2_COM_SCRATCH;
+       cpu_reg.mips_view_base = 0x8000000;
+    
+       fw.ver_major = bnx2_COM_b06FwReleaseMajor;
+       fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
+       fw.ver_fix = bnx2_COM_b06FwReleaseFix;
+       fw.start_addr = bnx2_COM_b06FwStartAddr;
+
+       fw.text_addr = bnx2_COM_b06FwTextAddr;
+       fw.text_len = bnx2_COM_b06FwTextLen;
+       fw.text_index = 0;
+       fw.text = bnx2_COM_b06FwText;
+
+       fw.data_addr = bnx2_COM_b06FwDataAddr;
+       fw.data_len = bnx2_COM_b06FwDataLen;
+       fw.data_index = 0;
+       fw.data = bnx2_COM_b06FwData;
+
+       fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
+       fw.sbss_len = bnx2_COM_b06FwSbssLen;
+       fw.sbss_index = 0;
+       fw.sbss = bnx2_COM_b06FwSbss;
+
+       fw.bss_addr = bnx2_COM_b06FwBssAddr;
+       fw.bss_len = bnx2_COM_b06FwBssLen;
+       fw.bss_index = 0;
+       fw.bss = bnx2_COM_b06FwBss;
+
+       fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
+       fw.rodata_len = bnx2_COM_b06FwRodataLen;
+       fw.rodata_index = 0;
+       fw.rodata = bnx2_COM_b06FwRodata;
+
+       load_cpu_fw(bp, &cpu_reg, &fw);
+
+}
+
+static int
+bnx2_set_power_state(struct bnx2 *bp, int state)
+{
+       u16 pmcsr;
+
+       pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
+
+       switch (state) {
+       case 0: {
+               u32 val;
+
+               pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
+                       (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
+                       PCI_PM_CTRL_PME_STATUS);
+
+               if (pmcsr & PCI_PM_CTRL_STATE_MASK)
+                       /* delay required during transition out of D3hot */
+                       msleep(20);
+
+               val = REG_RD(bp, BNX2_EMAC_MODE);
+               val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
+               val &= ~BNX2_EMAC_MODE_MPKT;
+               REG_WR(bp, BNX2_EMAC_MODE, val);
+
+               val = REG_RD(bp, BNX2_RPM_CONFIG);
+               val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
+               REG_WR(bp, BNX2_RPM_CONFIG, val);
+               break;
+       }
+       case 3: {
+               int i;
+               u32 val, wol_msg;
+
+               if (bp->wol) {
+                       u32 advertising;
+                       u8 autoneg;
+
+                       autoneg = bp->autoneg;
+                       advertising = bp->advertising;
+
+                       bp->autoneg = AUTONEG_SPEED;
+                       bp->advertising = ADVERTISED_10baseT_Half |
+                               ADVERTISED_10baseT_Full |
+                               ADVERTISED_100baseT_Half |
+                               ADVERTISED_100baseT_Full |
+                               ADVERTISED_Autoneg;
+
+                       bnx2_setup_copper_phy(bp);
+
+                       bp->autoneg = autoneg;
+                       bp->advertising = advertising;
+
+                       bnx2_set_mac_addr(bp);
+
+                       val = REG_RD(bp, BNX2_EMAC_MODE);
+
+                       /* Enable port mode. */
+                       val &= ~BNX2_EMAC_MODE_PORT;
+                       val |= BNX2_EMAC_MODE_PORT_MII |
+                              BNX2_EMAC_MODE_MPKT_RCVD |
+                              BNX2_EMAC_MODE_ACPI_RCVD |
+                              BNX2_EMAC_MODE_FORCE_LINK |
+                              BNX2_EMAC_MODE_MPKT;
+
+                       REG_WR(bp, BNX2_EMAC_MODE, val);
+
+                       /* receive all multicast */
+                       for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
+                               REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
+                                      0xffffffff);
+                       }
+                       REG_WR(bp, BNX2_EMAC_RX_MODE,
+                              BNX2_EMAC_RX_MODE_SORT_MODE);
+
+                       val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
+                             BNX2_RPM_SORT_USER0_MC_EN;
+                       REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
+                       REG_WR(bp, BNX2_RPM_SORT_USER0, val);
+                       REG_WR(bp, BNX2_RPM_SORT_USER0, val |
+                              BNX2_RPM_SORT_USER0_ENA);
+
+                       /* Need to enable EMAC and RPM for WOL. */
+                       REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
+                              BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
+                              BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
+                              BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
+
+                       val = REG_RD(bp, BNX2_RPM_CONFIG);
+                       val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
+                       REG_WR(bp, BNX2_RPM_CONFIG, val);
+
+                       wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
+               }
+               else {
+                       wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
+               }
+
+               bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
+
+               pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
+               if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
+                   (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
+
+                       if (bp->wol)
+                               pmcsr |= 3;
+               }
+               else {
+                       pmcsr |= 3;
+               }
+               if (bp->wol) {
+                       pmcsr |= PCI_PM_CTRL_PME_ENABLE;
+               }
+               pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
+                                     pmcsr);
+
+               /* No more memory access after this point until
+                * device is brought back to D0.
+                */
+               udelay(50);
+               break;
+       }
+       default:
+               return -EINVAL;
+       }
+       return 0;
+}
+
+static int
+bnx2_acquire_nvram_lock(struct bnx2 *bp)
+{
+       u32 val;
+       int j;
+
+       /* Request access to the flash interface. */
+       REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
+       for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
+               val = REG_RD(bp, BNX2_NVM_SW_ARB);
+               if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
+                       break;
+
+               udelay(5);
+       }
+
+       if (j >= NVRAM_TIMEOUT_COUNT)
+               return -EBUSY;
+
+       return 0;
+}
+
+static int
+bnx2_release_nvram_lock(struct bnx2 *bp)
+{
+       int j;
+       u32 val;
+
+       /* Relinquish nvram interface. */
+       REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
+
+       for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
+               val = REG_RD(bp, BNX2_NVM_SW_ARB);
+               if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
+                       break;
+
+               udelay(5);
+       }
+
+       if (j >= NVRAM_TIMEOUT_COUNT)
+               return -EBUSY;
+
+       return 0;
+}
+
+
+static int
+bnx2_enable_nvram_write(struct bnx2 *bp)
+{
+       u32 val;
+
+       val = REG_RD(bp, BNX2_MISC_CFG);
+       REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
+
+       if (!bp->flash_info->buffered) {
+               int j;
+
+               REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
+               REG_WR(bp, BNX2_NVM_COMMAND,
+                      BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
+
+               for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
+                       udelay(5);
+
+                       val = REG_RD(bp, BNX2_NVM_COMMAND);
+                       if (val & BNX2_NVM_COMMAND_DONE)
+                               break;
+               }
+
+               if (j >= NVRAM_TIMEOUT_COUNT)
+                       return -EBUSY;
+       }
+       return 0;
+}
+
+static void
+bnx2_disable_nvram_write(struct bnx2 *bp)
+{
+       u32 val;
+
+       val = REG_RD(bp, BNX2_MISC_CFG);
+       REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
+}
+
+
+static void
+bnx2_enable_nvram_access(struct bnx2 *bp)
+{
+       u32 val;
+
+       val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
+       /* Enable both bits, even on read. */
+       REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, 
+              val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
+}
+
+static void
+bnx2_disable_nvram_access(struct bnx2 *bp)
+{
+       u32 val;
+
+       val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
+       /* Disable both bits, even after read. */
+       REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, 
+               val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
+                       BNX2_NVM_ACCESS_ENABLE_WR_EN));
+}
+
+static int
+bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
+{
+       u32 cmd;
+       int j;
+
+       if (bp->flash_info->buffered)
+               /* Buffered flash, no erase needed */
+               return 0;
+
+       /* Build an erase command */
+       cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
+             BNX2_NVM_COMMAND_DOIT;
+
+       /* Need to clear DONE bit separately. */
+       REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
+
+       /* Address of the NVRAM to read from. */
+       REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
+
+       /* Issue an erase command. */
+       REG_WR(bp, BNX2_NVM_COMMAND, cmd);
+
+       /* Wait for completion. */
+       for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
+               u32 val;
+
+               udelay(5);
+
+               val = REG_RD(bp, BNX2_NVM_COMMAND);
+               if (val & BNX2_NVM_COMMAND_DONE)
+                       break;
+       }
+
+       if (j >= NVRAM_TIMEOUT_COUNT)
+               return -EBUSY;
+
+       return 0;
+}
+
+static int
+bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
+{
+       u32 cmd;
+       int j;
+
+       /* Build the command word. */
+       cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
+
+       /* Calculate an offset of a buffered flash. */
+       if (bp->flash_info->buffered) {
+               offset = ((offset / bp->flash_info->page_size) <<
+                          bp->flash_info->page_bits) +
+                         (offset % bp->flash_info->page_size);
+       }
+
+       /* Need to clear DONE bit separately. */
+       REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
+
+       /* Address of the NVRAM to read from. */
+       REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
+
+       /* Issue a read command. */
+       REG_WR(bp, BNX2_NVM_COMMAND, cmd);
+
+       /* Wait for completion. */
+       for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
+               u32 val;
+
+               udelay(5);
+
+               val = REG_RD(bp, BNX2_NVM_COMMAND);
+               if (val & BNX2_NVM_COMMAND_DONE) {
+                       val = REG_RD(bp, BNX2_NVM_READ);
+
+                       val = be32_to_cpu(val);
+                       memcpy(ret_val, &val, 4);
+                       break;
+               }
+       }
+       if (j >= NVRAM_TIMEOUT_COUNT)
+               return -EBUSY;
+
+       return 0;
+}
+
+
+static int
+bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
+{
+       u32 cmd, val32;
+       int j;
+
+       /* Build the command word. */
+       cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
+
+       /* Calculate an offset of a buffered flash. */
+       if (bp->flash_info->buffered) {
+               offset = ((offset / bp->flash_info->page_size) <<
+                         bp->flash_info->page_bits) +
+                        (offset % bp->flash_info->page_size);
+       }
+
+       /* Need to clear DONE bit separately. */
+       REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
+
+       memcpy(&val32, val, 4);
+       val32 = cpu_to_be32(val32);
+
+       /* Write the data. */
+       REG_WR(bp, BNX2_NVM_WRITE, val32);
+
+       /* Address of the NVRAM to write to. */
+       REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
+
+       /* Issue the write command. */
+       REG_WR(bp, BNX2_NVM_COMMAND, cmd);
+
+       /* Wait for completion. */
+       for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
+               udelay(5);
+
+               if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
+                       break;
+       }
+       if (j >= NVRAM_TIMEOUT_COUNT)
+               return -EBUSY;
+
+       return 0;
+}
+
+static int
+bnx2_init_nvram(struct bnx2 *bp)
+{
+       u32 val;
+       int j, entry_count, rc;
+       struct flash_spec *flash;
+
+       /* Determine the selected interface. */
+       val = REG_RD(bp, BNX2_NVM_CFG1);
+
+       entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
+
+       rc = 0;
+       if (val & 0x40000000) {
+
+               /* Flash interface has been reconfigured */
+               for (j = 0, flash = &flash_table[0]; j < entry_count;
+                       j++, flash++) {
+
+                       if (val == flash->config1) {
+                               bp->flash_info = flash;
+                               break;
+                       }
+               }
+       }
+       else {
+               /* Not yet been reconfigured */
+
+               for (j = 0, flash = &flash_table[0]; j < entry_count;
+                       j++, flash++) {
+
+                       if ((val & FLASH_STRAP_MASK) == flash->strapping) {
+                               bp->flash_info = flash;
+
+                               /* Request access to the flash interface. */
+                               if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
+                                       return rc;
+
+                               /* Enable access to flash interface */
+                               bnx2_enable_nvram_access(bp);
+
+                               /* Reconfigure the flash interface */
+                               REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
+                               REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
+                               REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
+                               REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
+
+                               /* Disable access to flash interface */
+                               bnx2_disable_nvram_access(bp);
+                               bnx2_release_nvram_lock(bp);
+
+                               break;
+                       }
+               }
+       } /* if (val & 0x40000000) */
+
+       if (j == entry_count) {
+               bp->flash_info = NULL;
+               printk(KERN_ALERT "Unknown flash/EEPROM type.\n");
+               rc = -ENODEV;
+       }
+
+       return rc;
+}
+
+static int
+bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
+               int buf_size)
+{
+       int rc = 0;
+       u32 cmd_flags, offset32, len32, extra;
+
+       if (buf_size == 0)
+               return 0;
+
+       /* Request access to the flash interface. */
+       if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
+               return rc;
+
+       /* Enable access to flash interface */
+       bnx2_enable_nvram_access(bp);
+
+       len32 = buf_size;
+       offset32 = offset;
+       extra = 0;
+
+       cmd_flags = 0;
+
+       if (offset32 & 3) {
+               u8 buf[4];
+               u32 pre_len;
+
+               offset32 &= ~3;
+               pre_len = 4 - (offset & 3);
+
+               if (pre_len >= len32) {
+                       pre_len = len32;
+                       cmd_flags = BNX2_NVM_COMMAND_FIRST |
+                                   BNX2_NVM_COMMAND_LAST;
+               }
+               else {
+                       cmd_flags = BNX2_NVM_COMMAND_FIRST;
+               }
+
+               rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
+
+               if (rc)
+                       return rc;
+
+               memcpy(ret_buf, buf + (offset & 3), pre_len);
+
+               offset32 += 4;
+               ret_buf += pre_len;
+               len32 -= pre_len;
+       }
+       if (len32 & 3) {
+               extra = 4 - (len32 & 3);
+               len32 = (len32 + 4) & ~3;
+       }
+
+       if (len32 == 4) {
+               u8 buf[4];
+
+               if (cmd_flags)
+                       cmd_flags = BNX2_NVM_COMMAND_LAST;
+               else
+                       cmd_flags = BNX2_NVM_COMMAND_FIRST |
+                                   BNX2_NVM_COMMAND_LAST;
+
+               rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
+
+               memcpy(ret_buf, buf, 4 - extra);
+       }
+       else if (len32 > 0) {
+               u8 buf[4];
+
+               /* Read the first word. */
+               if (cmd_flags)
+                       cmd_flags = 0;
+               else
+                       cmd_flags = BNX2_NVM_COMMAND_FIRST;
+
+               rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
+
+               /* Advance to the next dword. */
+               offset32 += 4;
+               ret_buf += 4;
+               len32 -= 4;
+
+               while (len32 > 4 && rc == 0) {
+                       rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
+
+                       /* Advance to the next dword. */
+                       offset32 += 4;
+                       ret_buf += 4;
+                       len32 -= 4;
+               }
+
+               if (rc)
+                       return rc;
+
+               cmd_flags = BNX2_NVM_COMMAND_LAST;
+               rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
+
+               memcpy(ret_buf, buf, 4 - extra);
+       }
+
+       /* Disable access to flash interface */
+       bnx2_disable_nvram_access(bp);
+
+       bnx2_release_nvram_lock(bp);
+
+       return rc;
+}
+
+static int
+bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
+               int buf_size)
+{
+       u32 written, offset32, len32;
+       u8 *buf, start[4], end[4];
+       int rc = 0;
+       int align_start, align_end;
+
+       buf = data_buf;
+       offset32 = offset;
+       len32 = buf_size;
+       align_start = align_end = 0;
+
+       if ((align_start = (offset32 & 3))) {
+               offset32 &= ~3;
+               len32 += align_start;
+               if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
+                       return rc;
+       }
+
+       if (len32 & 3) {
+               if ((len32 > 4) || !align_start) {
+                       align_end = 4 - (len32 & 3);
+                       len32 += align_end;
+                       if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
+                               end, 4))) {
+                               return rc;
+                       }
+               }
+       }
+
+       if (align_start || align_end) {
+               buf = kmalloc(len32, GFP_KERNEL);
+               if (buf == 0)
+                       return -ENOMEM;
+               if (align_start) {
+                       memcpy(buf, start, 4);
+               }
+               if (align_end) {
+                       memcpy(buf + len32 - 4, end, 4);
+               }
+               memcpy(buf + align_start, data_buf, buf_size);
+       }
+
+       written = 0;
+       while ((written < len32) && (rc == 0)) {
+               u32 page_start, page_end, data_start, data_end;
+               u32 addr, cmd_flags;
+               int i;
+               u8 flash_buffer[264];
+
+               /* Find the page_start addr */
+               page_start = offset32 + written;
+               page_start -= (page_start % bp->flash_info->page_size);
+               /* Find the page_end addr */
+               page_end = page_start + bp->flash_info->page_size;
+               /* Find the data_start addr */
+               data_start = (written == 0) ? offset32 : page_start;
+               /* Find the data_end addr */
+               data_end = (page_end > offset32 + len32) ? 
+                       (offset32 + len32) : page_end;
+
+               /* Request access to the flash interface. */
+               if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
+                       goto nvram_write_end;
+
+               /* Enable access to flash interface */
+               bnx2_enable_nvram_access(bp);
+
+               cmd_flags = BNX2_NVM_COMMAND_FIRST;
+               if (bp->flash_info->buffered == 0) {
+                       int j;
+
+                       /* Read the whole page into the buffer
+                        * (non-buffer flash only) */
+                       for (j = 0; j < bp->flash_info->page_size; j += 4) {
+                               if (j == (bp->flash_info->page_size - 4)) {
+                                       cmd_flags |= BNX2_NVM_COMMAND_LAST;
+                               }
+                               rc = bnx2_nvram_read_dword(bp,
+                                       page_start + j, 
+                                       &flash_buffer[j], 
+                                       cmd_flags);
+
+                               if (rc)
+                                       goto nvram_write_end;
+
+                               cmd_flags = 0;
+                       }
+               }
+
+               /* Enable writes to flash interface (unlock write-protect) */
+               if ((rc = bnx2_enable_nvram_write(bp)) != 0)
+                       goto nvram_write_end;
+
+               /* Erase the page */
+               if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
+                       goto nvram_write_end;
+
+               /* Re-enable the write again for the actual write */
+               bnx2_enable_nvram_write(bp);
+
+               /* Loop to write back the buffer data from page_start to
+                * data_start */
+               i = 0;
+               if (bp->flash_info->buffered == 0) {
+                       for (addr = page_start; addr < data_start;
+                               addr += 4, i += 4) {
+                               
+                               rc = bnx2_nvram_write_dword(bp, addr,
+                                       &flash_buffer[i], cmd_flags);
+
+                               if (rc != 0)
+                                       goto nvram_write_end;
+
+                               cmd_flags = 0;
+                       }
+               }
+
+               /* Loop to write the new data from data_start to data_end */
+               for (addr = data_start; addr < data_end; addr += 4, i++) {
+                       if ((addr == page_end - 4) ||
+                               ((bp->flash_info->buffered) &&
+                                (addr == data_end - 4))) {
+
+                               cmd_flags |= BNX2_NVM_COMMAND_LAST;
+                       }
+                       rc = bnx2_nvram_write_dword(bp, addr, buf,
+                               cmd_flags);
+
+                       if (rc != 0)
+                               goto nvram_write_end;
+
+                       cmd_flags = 0;
+                       buf += 4;
+               }
+
+               /* Loop to write back the buffer data from data_end
+                * to page_end */
+               if (bp->flash_info->buffered == 0) {
+                       for (addr = data_end; addr < page_end;
+                               addr += 4, i += 4) {
+                       
+                               if (addr == page_end-4) {
+                                       cmd_flags = BNX2_NVM_COMMAND_LAST;
+                               }
+                               rc = bnx2_nvram_write_dword(bp, addr,
+                                       &flash_buffer[i], cmd_flags);
+
+                               if (rc != 0)
+                                       goto nvram_write_end;
+
+                               cmd_flags = 0;
+                       }
+               }
+
+               /* Disable writes to flash interface (lock write-protect) */
+               bnx2_disable_nvram_write(bp);
+
+               /* Disable access to flash interface */
+               bnx2_disable_nvram_access(bp);
+               bnx2_release_nvram_lock(bp);
+
+               /* Increment written */
+               written += data_end - data_start;
+       }
+
+nvram_write_end:
+       if (align_start || align_end)
+               kfree(buf);
+       return rc;
+}
+
+static int
+bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
+{
+       u32 val;
+       int i, rc = 0;
+
+       /* Wait for the current PCI transaction to complete before
+        * issuing a reset. */
+       REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
+              BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
+              BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
+              BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
+              BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
+       val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
+       udelay(5);
+
+       /* Deposit a driver reset signature so the firmware knows that
+        * this is a soft reset. */
+       REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
+                  BNX2_DRV_RESET_SIGNATURE_MAGIC);
+
+       bp->fw_timed_out = 0;
+
+       /* Wait for the firmware to tell us it is ok to issue a reset. */
+       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
+
+       /* Do a dummy read to force the chip to complete all current transaction
+        * before we issue a reset. */
+       val = REG_RD(bp, BNX2_MISC_ID);
+
+       val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
+             BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
+             BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
+
+       /* Chip reset. */
+       REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
+
+       if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
+           (CHIP_ID(bp) == CHIP_ID_5706_A1))
+               msleep(15);
+
+       /* Reset takes approximate 30 usec */
+       for (i = 0; i < 10; i++) {
+               val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
+               if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
+                           BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
+                       break;
+               }
+               udelay(10);
+       }
+
+       if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
+                  BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
+               printk(KERN_ERR PFX "Chip reset did not complete\n");
+               return -EBUSY;
+       }
+
+       /* Make sure byte swapping is properly configured. */
+       val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
+       if (val != 0x01020304) {
+               printk(KERN_ERR PFX "Chip not in correct endian mode\n");
+               return -ENODEV;
+       }
+
+       bp->fw_timed_out = 0;
+
+       /* Wait for the firmware to finish its initialization. */
+       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
+
+       if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
+               /* Adjust the voltage regular to two steps lower.  The default
+                * of this register is 0x0000000e. */
+               REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
+
+               /* Remove bad rbuf memory from the free pool. */
+               rc = bnx2_alloc_bad_rbuf(bp);
+       }
+
+       return rc;
+}
+
+static int
+bnx2_init_chip(struct bnx2 *bp)
+{
+       u32 val;
+
+       /* Make sure the interrupt is not active. */
+       REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
+
+       val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
+             BNX2_DMA_CONFIG_DATA_WORD_SWAP |
+#ifdef __BIG_ENDIAN
+             BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | 
+#endif
+             BNX2_DMA_CONFIG_CNTL_WORD_SWAP | 
+             DMA_READ_CHANS << 12 |
+             DMA_WRITE_CHANS << 16;
+
+       val |= (0x2 << 20) | (1 << 11);
+
+       if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
+               val |= (1 << 23);
+
+       if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
+           (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
+               val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
+
+       REG_WR(bp, BNX2_DMA_CONFIG, val);
+
+       if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
+               val = REG_RD(bp, BNX2_TDMA_CONFIG);
+               val |= BNX2_TDMA_CONFIG_ONE_DMA;
+               REG_WR(bp, BNX2_TDMA_CONFIG, val);
+       }
+
+       if (bp->flags & PCIX_FLAG) {
+               u16 val16;
+
+               pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
+                                    &val16);
+               pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
+                                     val16 & ~PCI_X_CMD_ERO);
+       }
+
+       REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
+              BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
+              BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
+              BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
+
+       /* Initialize context mapping and zero out the quick contexts.  The
+        * context block must have already been enabled. */
+       bnx2_init_context(bp);
+
+       bnx2_init_cpus(bp);
+       bnx2_init_nvram(bp);
+
+       bnx2_set_mac_addr(bp);
+
+       val = REG_RD(bp, BNX2_MQ_CONFIG);
+       val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
+       val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
+       REG_WR(bp, BNX2_MQ_CONFIG, val);
+
+       val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
+       REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
+       REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
+
+       val = (BCM_PAGE_BITS - 8) << 24;
+       REG_WR(bp, BNX2_RV2P_CONFIG, val);
+
+       /* Configure page size. */
+       val = REG_RD(bp, BNX2_TBDR_CONFIG);
+       val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
+       val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
+       REG_WR(bp, BNX2_TBDR_CONFIG, val);
+
+       val = bp->mac_addr[0] +
+             (bp->mac_addr[1] << 8) +
+             (bp->mac_addr[2] << 16) +
+             bp->mac_addr[3] +
+             (bp->mac_addr[4] << 8) +
+             (bp->mac_addr[5] << 16);
+       REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
+
+       /* Program the MTU.  Also include 4 bytes for CRC32. */
+       val = bp->dev->mtu + ETH_HLEN + 4;
+       if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
+               val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
+       REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
+
+       bp->last_status_idx = 0;
+       bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
+
+       /* Set up how to generate a link change interrupt. */
+       REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
+
+       REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
+              (u64) bp->status_blk_mapping & 0xffffffff);
+       REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
+
+       REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
+              (u64) bp->stats_blk_mapping & 0xffffffff);
+       REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
+              (u64) bp->stats_blk_mapping >> 32);
+
+       REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, 
+              (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
+
+       REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
+              (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
+
+       REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
+              (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
+
+       REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
+
+       REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
+
+       REG_WR(bp, BNX2_HC_COM_TICKS,
+              (bp->com_ticks_int << 16) | bp->com_ticks);
+
+       REG_WR(bp, BNX2_HC_CMD_TICKS,
+              (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
+
+       REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
+       REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
+
+       if (CHIP_ID(bp) == CHIP_ID_5706_A1)
+               REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
+       else {
+               REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
+                      BNX2_HC_CONFIG_TX_TMR_MODE |
+                      BNX2_HC_CONFIG_COLLECT_STATS);
+       }
+
+       /* Clear internal stats counters. */
+       REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
+
+       REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
+
+       /* Initialize the receive filter. */
+       bnx2_set_rx_mode(bp->dev);
+
+       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
+
+       REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
+       REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
+
+       udelay(20);
+
+       return 0;
+}
+
+
+static void
+bnx2_init_tx_ring(struct bnx2 *bp)
+{
+       struct tx_bd *txbd;
+       u32 val;
+
+       txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
+               
+       txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
+       txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
+
+       bp->tx_prod = 0;
+       bp->tx_cons = 0;
+       bp->tx_prod_bseq = 0;
+       atomic_set(&bp->tx_avail_bd, bp->tx_ring_size);
+       
+       val = BNX2_L2CTX_TYPE_TYPE_L2;
+       val |= BNX2_L2CTX_TYPE_SIZE_L2;
+       CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
+
+       val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
+       val |= 8 << 16;
+       CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
+
+       val = (u64) bp->tx_desc_mapping >> 32;
+       CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
+
+       val = (u64) bp->tx_desc_mapping & 0xffffffff;
+       CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
+}
+
+static void
+bnx2_init_rx_ring(struct bnx2 *bp)
+{
+       struct rx_bd *rxbd;
+       int i;
+       u16 prod, ring_prod; 
+       u32 val;
+
+       /* 8 for CRC and VLAN */
+       bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
+       /* 8 for alignment */
+       bp->rx_buf_size = bp->rx_buf_use_size + 8;
+
+       ring_prod = prod = bp->rx_prod = 0;
+       bp->rx_cons = 0;
+       bp->rx_prod_bseq = 0;
+               
+       rxbd = &bp->rx_desc_ring[0];
+       for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
+               rxbd->rx_bd_len = bp->rx_buf_use_size;
+               rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
+       }
+
+       rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
+       rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
+
+       val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
+       val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
+       val |= 0x02 << 8;
+       CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
+
+       val = (u64) bp->rx_desc_mapping >> 32;
+       CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
+
+       val = (u64) bp->rx_desc_mapping & 0xffffffff;
+       CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
+
+       for ( ;ring_prod < bp->rx_ring_size; ) {
+               if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
+                       break;
+               }
+               prod = NEXT_RX_BD(prod);
+               ring_prod = RX_RING_IDX(prod);
+       }
+       bp->rx_prod = prod;
+
+       REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
+
+       REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
+}
+
+static void
+bnx2_free_tx_skbs(struct bnx2 *bp)
+{
+       int i;
+
+       if (bp->tx_buf_ring == NULL)
+               return;
+
+       for (i = 0; i < TX_DESC_CNT; ) {
+               struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
+               struct sk_buff *skb = tx_buf->skb;
+               int j, last;
+
+               if (skb == NULL) {
+                       i++;
+                       continue;
+               }
+
+               pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
+                       skb_headlen(skb), PCI_DMA_TODEVICE);
+
+               tx_buf->skb = NULL;
+
+               last = skb_shinfo(skb)->nr_frags;
+               for (j = 0; j < last; j++) {
+                       tx_buf = &bp->tx_buf_ring[i + j + 1];
+                       pci_unmap_page(bp->pdev,
+                               pci_unmap_addr(tx_buf, mapping),
+                               skb_shinfo(skb)->frags[j].size,
+                               PCI_DMA_TODEVICE);
+               }
+               dev_kfree_skb_any(skb);
+               i += j + 1;
+       }
+
+}
+
+static void
+bnx2_free_rx_skbs(struct bnx2 *bp)
+{
+       int i;
+
+       if (bp->rx_buf_ring == NULL)
+               return;
+
+       for (i = 0; i < RX_DESC_CNT; i++) {
+               struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
+               struct sk_buff *skb = rx_buf->skb;
+
+               if (skb == 0)
+                       continue;
+
+               pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
+                       bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
+
+               rx_buf->skb = NULL;
+
+               dev_kfree_skb_any(skb);
+       }
+}
+
+static void
+bnx2_free_skbs(struct bnx2 *bp)
+{
+       bnx2_free_tx_skbs(bp);
+       bnx2_free_rx_skbs(bp);
+}
+
+static int
+bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
+{
+       int rc;
+
+       rc = bnx2_reset_chip(bp, reset_code);
+       bnx2_free_skbs(bp);
+       if (rc)
+               return rc;
+
+       bnx2_init_chip(bp);
+       bnx2_init_tx_ring(bp);
+       bnx2_init_rx_ring(bp);
+       return 0;
+}
+
+static int
+bnx2_init_nic(struct bnx2 *bp)
+{
+       int rc;
+
+       if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
+               return rc;
+
+       bnx2_init_phy(bp);
+       bnx2_set_link(bp);
+       return 0;
+}
+
+static int
+bnx2_test_registers(struct bnx2 *bp)
+{
+       int ret;
+       int i;
+       static struct {
+               u16   offset;
+               u16   flags;
+               u32   rw_mask;
+               u32   ro_mask;
+       } reg_tbl[] = {
+               { 0x006c, 0, 0x00000000, 0x0000003f },
+               { 0x0090, 0, 0xffffffff, 0x00000000 },
+               { 0x0094, 0, 0x00000000, 0x00000000 },
+
+               { 0x0404, 0, 0x00003f00, 0x00000000 },
+               { 0x0418, 0, 0x00000000, 0xffffffff },
+               { 0x041c, 0, 0x00000000, 0xffffffff },
+               { 0x0420, 0, 0x00000000, 0x80ffffff },
+               { 0x0424, 0, 0x00000000, 0x00000000 },
+               { 0x0428, 0, 0x00000000, 0x00000001 },
+               { 0x0450, 0, 0x00000000, 0x0000ffff },
+               { 0x0454, 0, 0x00000000, 0xffffffff },
+               { 0x0458, 0, 0x00000000, 0xffffffff },
+
+               { 0x0808, 0, 0x00000000, 0xffffffff },
+               { 0x0854, 0, 0x00000000, 0xffffffff },
+               { 0x0868, 0, 0x00000000, 0x77777777 },
+               { 0x086c, 0, 0x00000000, 0x77777777 },
+               { 0x0870, 0, 0x00000000, 0x77777777 },
+               { 0x0874, 0, 0x00000000, 0x77777777 },
+
+               { 0x0c00, 0, 0x00000000, 0x00000001 },
+               { 0x0c04, 0, 0x00000000, 0x03ff0001 },
+               { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
+               { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
+               { 0x0c30, 0, 0x00000000, 0xffffffff },
+               { 0x0c34, 0, 0x00000000, 0xffffffff },
+               { 0x0c38, 0, 0x00000000, 0xffffffff },
+               { 0x0c3c, 0, 0x00000000, 0xffffffff },
+               { 0x0c40, 0, 0x00000000, 0xffffffff },
+               { 0x0c44, 0, 0x00000000, 0xffffffff },
+               { 0x0c48, 0, 0x00000000, 0x0007ffff },
+               { 0x0c4c, 0, 0x00000000, 0xffffffff },
+               { 0x0c50, 0, 0x00000000, 0xffffffff },
+               { 0x0c54, 0, 0x00000000, 0xffffffff },
+               { 0x0c58, 0, 0x00000000, 0xffffffff },
+               { 0x0c5c, 0, 0x00000000, 0xffffffff },
+               { 0x0c60, 0, 0x00000000, 0xffffffff },
+               { 0x0c64, 0, 0x00000000, 0xffffffff },
+               { 0x0c68, 0, 0x00000000, 0xffffffff },
+               { 0x0c6c, 0, 0x00000000, 0xffffffff },
+               { 0x0c70, 0, 0x00000000, 0xffffffff },
+               { 0x0c74, 0, 0x00000000, 0xffffffff },
+               { 0x0c78, 0, 0x00000000, 0xffffffff },
+               { 0x0c7c, 0, 0x00000000, 0xffffffff },
+               { 0x0c80, 0, 0x00000000, 0xffffffff },
+               { 0x0c84, 0, 0x00000000, 0xffffffff },
+               { 0x0c88, 0, 0x00000000, 0xffffffff },
+               { 0x0c8c, 0, 0x00000000, 0xffffffff },
+               { 0x0c90, 0, 0x00000000, 0xffffffff },
+               { 0x0c94, 0, 0x00000000, 0xffffffff },
+               { 0x0c98, 0, 0x00000000, 0xffffffff },
+               { 0x0c9c, 0, 0x00000000, 0xffffffff },
+               { 0x0ca0, 0, 0x00000000, 0xffffffff },
+               { 0x0ca4, 0, 0x00000000, 0xffffffff },
+               { 0x0ca8, 0, 0x00000000, 0x0007ffff },
+               { 0x0cac, 0, 0x00000000, 0xffffffff },
+               { 0x0cb0, 0, 0x00000000, 0xffffffff },
+               { 0x0cb4, 0, 0x00000000, 0xffffffff },
+               { 0x0cb8, 0, 0x00000000, 0xffffffff },
+               { 0x0cbc, 0, 0x00000000, 0xffffffff },
+               { 0x0cc0, 0, 0x00000000, 0xffffffff },
+               { 0x0cc4, 0, 0x00000000, 0xffffffff },
+               { 0x0cc8, 0, 0x00000000, 0xffffffff },
+               { 0x0ccc, 0, 0x00000000, 0xffffffff },
+               { 0x0cd0, 0, 0x00000000, 0xffffffff },
+               { 0x0cd4, 0, 0x00000000, 0xffffffff },
+               { 0x0cd8, 0, 0x00000000, 0xffffffff },
+               { 0x0cdc, 0, 0x00000000, 0xffffffff },
+               { 0x0ce0, 0, 0x00000000, 0xffffffff },
+               { 0x0ce4, 0, 0x00000000, 0xffffffff },
+               { 0x0ce8, 0, 0x00000000, 0xffffffff },
+               { 0x0cec, 0, 0x00000000, 0xffffffff },
+               { 0x0cf0, 0, 0x00000000, 0xffffffff },
+               { 0x0cf4, 0, 0x00000000, 0xffffffff },
+               { 0x0cf8, 0, 0x00000000, 0xffffffff },
+               { 0x0cfc, 0, 0x00000000, 0xffffffff },
+               { 0x0d00, 0, 0x00000000, 0xffffffff },
+               { 0x0d04, 0, 0x00000000, 0xffffffff },
+
+               { 0x1000, 0, 0x00000000, 0x00000001 },
+               { 0x1004, 0, 0x00000000, 0x000f0001 },
+               { 0x1044, 0, 0x00000000, 0xffc003ff },
+               { 0x1080, 0, 0x00000000, 0x0001ffff },
+               { 0x1084, 0, 0x00000000, 0xffffffff },
+               { 0x1088, 0, 0x00000000, 0xffffffff },
+               { 0x108c, 0, 0x00000000, 0xffffffff },
+               { 0x1090, 0, 0x00000000, 0xffffffff },
+               { 0x1094, 0, 0x00000000, 0xffffffff },
+               { 0x1098, 0, 0x00000000, 0xffffffff },
+               { 0x109c, 0, 0x00000000, 0xffffffff },
+               { 0x10a0, 0, 0x00000000, 0xffffffff },
+
+               { 0x1408, 0, 0x01c00800, 0x00000000 },
+               { 0x149c, 0, 0x8000ffff, 0x00000000 },
+               { 0x14a8, 0, 0x00000000, 0x000001ff },
+               { 0x14ac, 0, 0x4fffffff, 0x10000000 },
+               { 0x14b0, 0, 0x00000002, 0x00000001 },
+               { 0x14b8, 0, 0x00000000, 0x00000000 },
+               { 0x14c0, 0, 0x00000000, 0x00000009 },
+               { 0x14c4, 0, 0x00003fff, 0x00000000 },
+               { 0x14cc, 0, 0x00000000, 0x00000001 },
+               { 0x14d0, 0, 0xffffffff, 0x00000000 },
+               { 0x1500, 0, 0x00000000, 0xffffffff },
+               { 0x1504, 0, 0x00000000, 0xffffffff },
+               { 0x1508, 0, 0x00000000, 0xffffffff },
+               { 0x150c, 0, 0x00000000, 0xffffffff },
+               { 0x1510, 0, 0x00000000, 0xffffffff },
+               { 0x1514, 0, 0x00000000, 0xffffffff },
+               { 0x1518, 0, 0x00000000, 0xffffffff },
+               { 0x151c, 0, 0x00000000, 0xffffffff },
+               { 0x1520, 0, 0x00000000, 0xffffffff },
+               { 0x1524, 0, 0x00000000, 0xffffffff },
+               { 0x1528, 0, 0x00000000, 0xffffffff },
+               { 0x152c, 0, 0x00000000, 0xffffffff },
+               { 0x1530, 0, 0x00000000, 0xffffffff },
+               { 0x1534, 0, 0x00000000, 0xffffffff },
+               { 0x1538, 0, 0x00000000, 0xffffffff },
+               { 0x153c, 0, 0x00000000, 0xffffffff },
+               { 0x1540, 0, 0x00000000, 0xffffffff },
+               { 0x1544, 0, 0x00000000, 0xffffffff },
+               { 0x1548, 0, 0x00000000, 0xffffffff },
+               { 0x154c, 0, 0x00000000, 0xffffffff },
+               { 0x1550, 0, 0x00000000, 0xffffffff },
+               { 0x1554, 0, 0x00000000, 0xffffffff },
+               { 0x1558, 0, 0x00000000, 0xffffffff },
+               { 0x1600, 0, 0x00000000, 0xffffffff },
+               { 0x1604, 0, 0x00000000, 0xffffffff },
+               { 0x1608, 0, 0x00000000, 0xffffffff },
+               { 0x160c, 0, 0x00000000, 0xffffffff },
+               { 0x1610, 0, 0x00000000, 0xffffffff },
+               { 0x1614, 0, 0x00000000, 0xffffffff },
+               { 0x1618, 0, 0x00000000, 0xffffffff },
+               { 0x161c, 0, 0x00000000, 0xffffffff },
+               { 0x1620, 0, 0x00000000, 0xffffffff },
+               { 0x1624, 0, 0x00000000, 0xffffffff },
+               { 0x1628, 0, 0x00000000, 0xffffffff },
+               { 0x162c, 0, 0x00000000, 0xffffffff },
+               { 0x1630, 0, 0x00000000, 0xffffffff },
+               { 0x1634, 0, 0x00000000, 0xffffffff },
+               { 0x1638, 0, 0x00000000, 0xffffffff },
+               { 0x163c, 0, 0x00000000, 0xffffffff },
+               { 0x1640, 0, 0x00000000, 0xffffffff },
+               { 0x1644, 0, 0x00000000, 0xffffffff },
+               { 0x1648, 0, 0x00000000, 0xffffffff },
+               { 0x164c, 0, 0x00000000, 0xffffffff },
+               { 0x1650, 0, 0x00000000, 0xffffffff },
+               { 0x1654, 0, 0x00000000, 0xffffffff },
+
+               { 0x1800, 0, 0x00000000, 0x00000001 },
+               { 0x1804, 0, 0x00000000, 0x00000003 },
+               { 0x1840, 0, 0x00000000, 0xffffffff },
+               { 0x1844, 0, 0x00000000, 0xffffffff },
+               { 0x1848, 0, 0x00000000, 0xffffffff },
+               { 0x184c, 0, 0x00000000, 0xffffffff },
+               { 0x1850, 0, 0x00000000, 0xffffffff },
+               { 0x1900, 0, 0x7ffbffff, 0x00000000 },
+               { 0x1904, 0, 0xffffffff, 0x00000000 },
+               { 0x190c, 0, 0xffffffff, 0x00000000 },
+               { 0x1914, 0, 0xffffffff, 0x00000000 },
+               { 0x191c, 0, 0xffffffff, 0x00000000 },
+               { 0x1924, 0, 0xffffffff, 0x00000000 },
+               { 0x192c, 0, 0xffffffff, 0x00000000 },
+               { 0x1934, 0, 0xffffffff, 0x00000000 },
+               { 0x193c, 0, 0xffffffff, 0x00000000 },
+               { 0x1944, 0, 0xffffffff, 0x00000000 },
+               { 0x194c, 0, 0xffffffff, 0x00000000 },
+               { 0x1954, 0, 0xffffffff, 0x00000000 },
+               { 0x195c, 0, 0xffffffff, 0x00000000 },
+               { 0x1964, 0, 0xffffffff, 0x00000000 },
+               { 0x196c, 0, 0xffffffff, 0x00000000 },
+               { 0x1974, 0, 0xffffffff, 0x00000000 },
+               { 0x197c, 0, 0xffffffff, 0x00000000 },
+               { 0x1980, 0, 0x0700ffff, 0x00000000 },
+
+               { 0x1c00, 0, 0x00000000, 0x00000001 },
+               { 0x1c04, 0, 0x00000000, 0x00000003 },
+               { 0x1c08, 0, 0x0000000f, 0x00000000 },
+               { 0x1c40, 0, 0x00000000, 0xffffffff },
+               { 0x1c44, 0, 0x00000000, 0xffffffff },
+               { 0x1c48, 0, 0x00000000, 0xffffffff },
+               { 0x1c4c, 0, 0x00000000, 0xffffffff },
+               { 0x1c50, 0, 0x00000000, 0xffffffff },
+               { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
+               { 0x1d04, 0, 0xffffffff, 0x00000000 },
+               { 0x1d0c, 0, 0xffffffff, 0x00000000 },
+               { 0x1d14, 0, 0xffffffff, 0x00000000 },
+               { 0x1d1c, 0, 0xffffffff, 0x00000000 },
+               { 0x1d24, 0, 0xffffffff, 0x00000000 },
+               { 0x1d2c, 0, 0xffffffff, 0x00000000 },
+               { 0x1d34, 0, 0xffffffff, 0x00000000 },
+               { 0x1d3c, 0, 0xffffffff, 0x00000000 },
+               { 0x1d44, 0, 0xffffffff, 0x00000000 },
+               { 0x1d4c, 0, 0xffffffff, 0x00000000 },
+               { 0x1d54, 0, 0xffffffff, 0x00000000 },
+               { 0x1d5c, 0, 0xffffffff, 0x00000000 },
+               { 0x1d64, 0, 0xffffffff, 0x00000000 },
+               { 0x1d6c, 0, 0xffffffff, 0x00000000 },
+               { 0x1d74, 0, 0xffffffff, 0x00000000 },
+               { 0x1d7c, 0, 0xffffffff, 0x00000000 },
+               { 0x1d80, 0, 0x0700ffff, 0x00000000 },
+
+               { 0x2004, 0, 0x00000000, 0x0337000f },
+               { 0x2008, 0, 0xffffffff, 0x00000000 },
+               { 0x200c, 0, 0xffffffff, 0x00000000 },
+               { 0x2010, 0, 0xffffffff, 0x00000000 },
+               { 0x2014, 0, 0x801fff80, 0x00000000 },
+               { 0x2018, 0, 0x000003ff, 0x00000000 },
+
+               { 0x2800, 0, 0x00000000, 0x00000001 },
+               { 0x2804, 0, 0x00000000, 0x00003f01 },
+               { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
+               { 0x2810, 0, 0xffff0000, 0x00000000 },
+               { 0x2814, 0, 0xffff0000, 0x00000000 },
+               { 0x2818, 0, 0xffff0000, 0x00000000 },
+               { 0x281c, 0, 0xffff0000, 0x00000000 },
+               { 0x2834, 0, 0xffffffff, 0x00000000 },
+               { 0x2840, 0, 0x00000000, 0xffffffff },
+               { 0x2844, 0, 0x00000000, 0xffffffff },
+               { 0x2848, 0, 0xffffffff, 0x00000000 },
+               { 0x284c, 0, 0xf800f800, 0x07ff07ff },
+
+               { 0x2c00, 0, 0x00000000, 0x00000011 },
+               { 0x2c04, 0, 0x00000000, 0x00030007 },
+
+               { 0x3000, 0, 0x00000000, 0x00000001 },
+               { 0x3004, 0, 0x00000000, 0x007007ff },
+               { 0x3008, 0, 0x00000003, 0x00000000 },
+               { 0x300c, 0, 0xffffffff, 0x00000000 },
+               { 0x3010, 0, 0xffffffff, 0x00000000 },
+               { 0x3014, 0, 0xffffffff, 0x00000000 },
+               { 0x3034, 0, 0xffffffff, 0x00000000 },
+               { 0x3038, 0, 0xffffffff, 0x00000000 },
+               { 0x3050, 0, 0x00000001, 0x00000000 },
+
+               { 0x3c00, 0, 0x00000000, 0x00000001 },
+               { 0x3c04, 0, 0x00000000, 0x00070000 },
+               { 0x3c08, 0, 0x00007f71, 0x07f00000 },
+               { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
+               { 0x3c10, 0, 0xffffffff, 0x00000000 },
+               { 0x3c14, 0, 0x00000000, 0xffffffff },
+               { 0x3c18, 0, 0x00000000, 0xffffffff },
+               { 0x3c1c, 0, 0xfffff000, 0x00000000 },
+               { 0x3c20, 0, 0xffffff00, 0x00000000 },
+               { 0x3c24, 0, 0xffffffff, 0x00000000 },
+               { 0x3c28, 0, 0xffffffff, 0x00000000 },
+               { 0x3c2c, 0, 0xffffffff, 0x00000000 },
+               { 0x3c30, 0, 0xffffffff, 0x00000000 },
+               { 0x3c34, 0, 0xffffffff, 0x00000000 },
+               { 0x3c38, 0, 0xffffffff, 0x00000000 },
+               { 0x3c3c, 0, 0xffffffff, 0x00000000 },
+               { 0x3c40, 0, 0xffffffff, 0x00000000 },
+               { 0x3c44, 0, 0xffffffff, 0x00000000 },
+               { 0x3c48, 0, 0xffffffff, 0x00000000 },
+               { 0x3c4c, 0, 0xffffffff, 0x00000000 },
+               { 0x3c50, 0, 0xffffffff, 0x00000000 },
+               { 0x3c54, 0, 0xffffffff, 0x00000000 },
+               { 0x3c58, 0, 0xffffffff, 0x00000000 },
+               { 0x3c5c, 0, 0xffffffff, 0x00000000 },
+               { 0x3c60, 0, 0xffffffff, 0x00000000 },
+               { 0x3c64, 0, 0xffffffff, 0x00000000 },
+               { 0x3c68, 0, 0xffffffff, 0x00000000 },
+               { 0x3c6c, 0, 0xffffffff, 0x00000000 },
+               { 0x3c70, 0, 0xffffffff, 0x00000000 },
+               { 0x3c74, 0, 0x0000003f, 0x00000000 },
+               { 0x3c78, 0, 0x00000000, 0x00000000 },
+               { 0x3c7c, 0, 0x00000000, 0x00000000 },
+               { 0x3c80, 0, 0x3fffffff, 0x00000000 },
+               { 0x3c84, 0, 0x0000003f, 0x00000000 },
+               { 0x3c88, 0, 0x00000000, 0xffffffff },
+               { 0x3c8c, 0, 0x00000000, 0xffffffff },
+
+               { 0x4000, 0, 0x00000000, 0x00000001 },
+               { 0x4004, 0, 0x00000000, 0x00030000 },
+               { 0x4008, 0, 0x00000ff0, 0x00000000 },
+               { 0x400c, 0, 0xffffffff, 0x00000000 },
+               { 0x4088, 0, 0x00000000, 0x00070303 },
+
+               { 0x4400, 0, 0x00000000, 0x00000001 },
+               { 0x4404, 0, 0x00000000, 0x00003f01 },
+               { 0x4408, 0, 0x7fff00ff, 0x00000000 },
+               { 0x440c, 0, 0xffffffff, 0x00000000 },
+               { 0x4410, 0, 0xffff,     0x0000 },
+               { 0x4414, 0, 0xffff,     0x0000 },
+               { 0x4418, 0, 0xffff,     0x0000 },
+               { 0x441c, 0, 0xffff,     0x0000 },
+               { 0x4428, 0, 0xffffffff, 0x00000000 },
+               { 0x442c, 0, 0xffffffff, 0x00000000 },
+               { 0x4430, 0, 0xffffffff, 0x00000000 },
+               { 0x4434, 0, 0xffffffff, 0x00000000 },
+               { 0x4438, 0, 0xffffffff, 0x00000000 },
+               { 0x443c, 0, 0xffffffff, 0x00000000 },
+               { 0x4440, 0, 0xffffffff, 0x00000000 },
+               { 0x4444, 0, 0xffffffff, 0x00000000 },
+
+               { 0x4c00, 0, 0x00000000, 0x00000001 },
+               { 0x4c04, 0, 0x00000000, 0x0000003f },
+               { 0x4c08, 0, 0xffffffff, 0x00000000 },
+               { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
+               { 0x4c10, 0, 0x80003fe0, 0x00000000 },
+               { 0x4c14, 0, 0xffffffff, 0x00000000 },
+               { 0x4c44, 0, 0x00000000, 0x9fff9fff },
+               { 0x4c48, 0, 0x00000000, 0xb3009fff },
+               { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
+               { 0x4c50, 0, 0x00000000, 0xffffffff },
+
+               { 0x5004, 0, 0x00000000, 0x0000007f },
+               { 0x5008, 0, 0x0f0007ff, 0x00000000 },
+               { 0x500c, 0, 0xf800f800, 0x07ff07ff },
+
+               { 0x5400, 0, 0x00000008, 0x00000001 },
+               { 0x5404, 0, 0x00000000, 0x0000003f },
+               { 0x5408, 0, 0x0000001f, 0x00000000 },
+               { 0x540c, 0, 0xffffffff, 0x00000000 },
+               { 0x5410, 0, 0xffffffff, 0x00000000 },
+               { 0x5414, 0, 0x0000ffff, 0x00000000 },
+               { 0x5418, 0, 0x0000ffff, 0x00000000 },
+               { 0x541c, 0, 0x0000ffff, 0x00000000 },
+               { 0x5420, 0, 0x0000ffff, 0x00000000 },
+               { 0x5428, 0, 0x000000ff, 0x00000000 },
+               { 0x542c, 0, 0xff00ffff, 0x00000000 },
+               { 0x5430, 0, 0x001fff80, 0x00000000 },
+               { 0x5438, 0, 0xffffffff, 0x00000000 },
+               { 0x543c, 0, 0xffffffff, 0x00000000 },
+               { 0x5440, 0, 0xf800f800, 0x07ff07ff },
+
+               { 0x5c00, 0, 0x00000000, 0x00000001 },
+               { 0x5c04, 0, 0x00000000, 0x0003000f },
+               { 0x5c08, 0, 0x00000003, 0x00000000 },
+               { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
+               { 0x5c10, 0, 0x00000000, 0xffffffff },
+               { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
+               { 0x5c84, 0, 0x00000000, 0x0000f333 },
+               { 0x5c88, 0, 0x00000000, 0x00077373 },
+               { 0x5c8c, 0, 0x00000000, 0x0007f737 },
+
+               { 0x6808, 0, 0x0000ff7f, 0x00000000 },
+               { 0x680c, 0, 0xffffffff, 0x00000000 },
+               { 0x6810, 0, 0xffffffff, 0x00000000 },
+               { 0x6814, 0, 0xffffffff, 0x00000000 },
+               { 0x6818, 0, 0xffffffff, 0x00000000 },
+               { 0x681c, 0, 0xffffffff, 0x00000000 },
+               { 0x6820, 0, 0x00ff00ff, 0x00000000 },
+               { 0x6824, 0, 0x00ff00ff, 0x00000000 },
+               { 0x6828, 0, 0x00ff00ff, 0x00000000 },
+               { 0x682c, 0, 0x03ff03ff, 0x00000000 },
+               { 0x6830, 0, 0x03ff03ff, 0x00000000 },
+               { 0x6834, 0, 0x03ff03ff, 0x00000000 },
+               { 0x6838, 0, 0x03ff03ff, 0x00000000 },
+               { 0x683c, 0, 0x0000ffff, 0x00000000 },
+               { 0x6840, 0, 0x00000ff0, 0x00000000 },
+               { 0x6844, 0, 0x00ffff00, 0x00000000 },
+               { 0x684c, 0, 0xffffffff, 0x00000000 },
+               { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
+               { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
+               { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
+               { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
+               { 0x6908, 0, 0x00000000, 0x0001ff0f },
+               { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
+
+               { 0xffff, 0, 0x00000000, 0x00000000 },
+       };
+
+       ret = 0;
+       for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
+               u32 offset, rw_mask, ro_mask, save_val, val;
+
+               offset = (u32) reg_tbl[i].offset;
+               rw_mask = reg_tbl[i].rw_mask;
+               ro_mask = reg_tbl[i].ro_mask;
+
+               save_val = readl((u8 *) bp->regview + offset);
+
+               writel(0, (u8 *) bp->regview + offset);
+
+               val = readl((u8 *) bp->regview + offset);
+               if ((val & rw_mask) != 0) {
+                       goto reg_test_err;
+               }
+
+               if ((val & ro_mask) != (save_val & ro_mask)) {
+                       goto reg_test_err;
+               }
+
+               writel(0xffffffff, (u8 *) bp->regview + offset);
+
+               val = readl((u8 *) bp->regview + offset);
+               if ((val & rw_mask) != rw_mask) {
+                       goto reg_test_err;
+               }
+
+               if ((val & ro_mask) != (save_val & ro_mask)) {
+                       goto reg_test_err;
+               }
+
+               writel(save_val, (u8 *) bp->regview + offset);
+               continue;
+
+reg_test_err:
+               writel(save_val, (u8 *) bp->regview + offset);
+               ret = -ENODEV;
+               break;
+       }
+       return ret;
+}
+
+static int
+bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
+{
+       static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
+               0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
+       int i;
+
+       for (i = 0; i < sizeof(test_pattern) / 4; i++) {
+               u32 offset;
+
+               for (offset = 0; offset < size; offset += 4) {
+
+                       REG_WR_IND(bp, start + offset, test_pattern[i]);
+
+                       if (REG_RD_IND(bp, start + offset) !=
+                               test_pattern[i]) {
+                               return -ENODEV;
+                       }
+               }
+       }
+       return 0;
+}
+
+static int
+bnx2_test_memory(struct bnx2 *bp)
+{
+       int ret = 0;
+       int i;
+       static struct {
+               u32   offset;
+               u32   len;
+       } mem_tbl[] = {
+               { 0x60000,  0x4000 },
+               { 0xa0000,  0x4000 },
+               { 0xe0000,  0x4000 },
+               { 0x120000, 0x4000 },
+               { 0x1a0000, 0x4000 },
+               { 0x160000, 0x4000 },
+               { 0xffffffff, 0    },
+       };
+
+       for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
+               if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
+                       mem_tbl[i].len)) != 0) {
+                       return ret;
+               }
+       }
+       
+       return ret;
+}
+
+static int
+bnx2_test_loopback(struct bnx2 *bp)
+{
+       unsigned int pkt_size, num_pkts, i;
+       struct sk_buff *skb, *rx_skb;
+       unsigned char *packet;
+       u16 rx_start_idx, rx_idx, send_idx;
+       u32 send_bseq, val;
+       dma_addr_t map;
+       struct tx_bd *txbd;
+       struct sw_bd *rx_buf;
+       struct l2_fhdr *rx_hdr;
+       int ret = -ENODEV;
+
+       if (!netif_running(bp->dev))
+               return -ENODEV;
+
+       bp->loopback = MAC_LOOPBACK;
+       bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
+       bnx2_set_mac_loopback(bp);
+
+       pkt_size = 1514;
+       skb = dev_alloc_skb(pkt_size);
+       packet = skb_put(skb, pkt_size);
+       memcpy(packet, bp->mac_addr, 6);
+       memset(packet + 6, 0x0, 8);
+       for (i = 14; i < pkt_size; i++)
+               packet[i] = (unsigned char) (i & 0xff);
+
+       map = pci_map_single(bp->pdev, skb->data, pkt_size,
+               PCI_DMA_TODEVICE);
+
+       val = REG_RD(bp, BNX2_HC_COMMAND);
+       REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+       REG_RD(bp, BNX2_HC_COMMAND);
+
+       udelay(5);
+       rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
+
+       send_idx = 0;
+       send_bseq = 0;
+       num_pkts = 0;
+
+       txbd = &bp->tx_desc_ring[send_idx];
+
+       txbd->tx_bd_haddr_hi = (u64) map >> 32;
+       txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
+       txbd->tx_bd_mss_nbytes = pkt_size;
+       txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
+
+       num_pkts++;
+       send_idx = NEXT_TX_BD(send_idx);
+
+       send_bseq += pkt_size;
+
+       REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
+       REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
+
+
+       udelay(100);
+
+       val = REG_RD(bp, BNX2_HC_COMMAND);
+       REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+       REG_RD(bp, BNX2_HC_COMMAND);
+
+       udelay(5);
+
+       pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
+       dev_kfree_skb_irq(skb);
+
+       if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
+               goto loopback_test_done;
+       }
+
+       rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
+       if (rx_idx != rx_start_idx + num_pkts) {
+               goto loopback_test_done;
+       }
+
+       rx_buf = &bp->rx_buf_ring[rx_start_idx];
+       rx_skb = rx_buf->skb;
+
+       rx_hdr = (struct l2_fhdr *) rx_skb->data;
+       skb_reserve(rx_skb, bp->rx_offset);
+
+       pci_dma_sync_single_for_cpu(bp->pdev,
+               pci_unmap_addr(rx_buf, mapping),
+               bp->rx_buf_size, PCI_DMA_FROMDEVICE);
+
+       if (rx_hdr->l2_fhdr_errors &
+               (L2_FHDR_ERRORS_BAD_CRC |
+               L2_FHDR_ERRORS_PHY_DECODE |
+               L2_FHDR_ERRORS_ALIGNMENT |
+               L2_FHDR_ERRORS_TOO_SHORT |
+               L2_FHDR_ERRORS_GIANT_FRAME)) {
+
+               goto loopback_test_done;
+       }
+
+       if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
+               goto loopback_test_done;
+       }
+
+       for (i = 14; i < pkt_size; i++) {
+               if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
+                       goto loopback_test_done;
+               }
+       }
+
+       ret = 0;
+
+loopback_test_done:
+       bp->loopback = 0;
+       return ret;
+}
+
+#define NVRAM_SIZE 0x200
+#define CRC32_RESIDUAL 0xdebb20e3
+
+static int
+bnx2_test_nvram(struct bnx2 *bp)
+{
+       u32 buf[NVRAM_SIZE / 4];
+       u8 *data = (u8 *) buf;
+       int rc = 0;
+       u32 magic, csum;
+
+       if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
+               goto test_nvram_done;
+
+        magic = be32_to_cpu(buf[0]);
+       if (magic != 0x669955aa) {
+               rc = -ENODEV;
+               goto test_nvram_done;
+       }
+
+       if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
+               goto test_nvram_done;
+
+       csum = ether_crc_le(0x100, data);
+       if (csum != CRC32_RESIDUAL) {
+               rc = -ENODEV;
+               goto test_nvram_done;
+       }
+
+       csum = ether_crc_le(0x100, data + 0x100);
+       if (csum != CRC32_RESIDUAL) {
+               rc = -ENODEV;
+       }
+
+test_nvram_done:
+       return rc;
+}
+
+static int
+bnx2_test_link(struct bnx2 *bp)
+{
+       u32 bmsr;
+
+       spin_lock_irq(&bp->phy_lock);
+       bnx2_read_phy(bp, MII_BMSR, &bmsr);
+       bnx2_read_phy(bp, MII_BMSR, &bmsr);
+       spin_unlock_irq(&bp->phy_lock);
+               
+       if (bmsr & BMSR_LSTATUS) {
+               return 0;
+       }
+       return -ENODEV;
+}
+
+static int
+bnx2_test_intr(struct bnx2 *bp)
+{
+       int i;
+       u32 val;
+       u16 status_idx;
+
+       if (!netif_running(bp->dev))
+               return -ENODEV;
+
+       status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
+
+       /* This register is not touched during run-time. */
+       val = REG_RD(bp, BNX2_HC_COMMAND);
+       REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
+       REG_RD(bp, BNX2_HC_COMMAND);
+
+       for (i = 0; i < 10; i++) {
+               if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
+                       status_idx) {
+
+                       break;
+               }
+
+               msleep_interruptible(10);
+       }
+       if (i < 10)
+               return 0;
+
+       return -ENODEV;
+}
+
+static void
+bnx2_timer(unsigned long data)
+{
+       struct bnx2 *bp = (struct bnx2 *) data;
+       u32 msg;
+
+       if (atomic_read(&bp->intr_sem) != 0)
+               goto bnx2_restart_timer;
+
+       msg = (u32) ++bp->fw_drv_pulse_wr_seq;
+       REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
+
+       if ((bp->phy_flags & PHY_SERDES_FLAG) &&
+           (CHIP_NUM(bp) == CHIP_NUM_5706)) {
+               unsigned long flags;
+
+               spin_lock_irqsave(&bp->phy_lock, flags);
+               if (bp->serdes_an_pending) {
+                       bp->serdes_an_pending--;
+               }
+               else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
+                       u32 bmcr;
+
+                       bnx2_read_phy(bp, MII_BMCR, &bmcr);
+
+                       if (bmcr & BMCR_ANENABLE) {
+                               u32 phy1, phy2;
+
+                               bnx2_write_phy(bp, 0x1c, 0x7c00);
+                               bnx2_read_phy(bp, 0x1c, &phy1);
+
+                               bnx2_write_phy(bp, 0x17, 0x0f01);
+                               bnx2_read_phy(bp, 0x15, &phy2);
+                               bnx2_write_phy(bp, 0x17, 0x0f01);
+                               bnx2_read_phy(bp, 0x15, &phy2);
+
+                               if ((phy1 & 0x10) &&    /* SIGNAL DETECT */
+                                       !(phy2 & 0x20)) {       /* no CONFIG */
+
+                                       bmcr &= ~BMCR_ANENABLE;
+                                       bmcr |= BMCR_SPEED1000 |
+                                               BMCR_FULLDPLX;
+                                       bnx2_write_phy(bp, MII_BMCR, bmcr);
+                                       bp->phy_flags |=
+                                               PHY_PARALLEL_DETECT_FLAG;
+                               }
+                       }
+               }
+               else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
+                       (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
+                       u32 phy2;
+
+                       bnx2_write_phy(bp, 0x17, 0x0f01);
+                       bnx2_read_phy(bp, 0x15, &phy2);
+                       if (phy2 & 0x20) {
+                               u32 bmcr;
+
+                               bnx2_read_phy(bp, MII_BMCR, &bmcr);
+                               bmcr |= BMCR_ANENABLE;
+                               bnx2_write_phy(bp, MII_BMCR, bmcr);
+
+                               bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
+
+                       }
+               }
+
+               spin_unlock_irqrestore(&bp->phy_lock, flags);
+       }
+
+bnx2_restart_timer:
+       bp->timer.expires = RUN_AT(bp->timer_interval);
+
+       add_timer(&bp->timer);
+}
+
+/* Called with rtnl_lock */
+static int
+bnx2_open(struct net_device *dev)
+{
+       struct bnx2 *bp = dev->priv;
+       int rc;
+
+       bnx2_set_power_state(bp, 0);
+       bnx2_disable_int(bp);
+
+       rc = bnx2_alloc_mem(bp);
+       if (rc)
+               return rc;
+
+       if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
+               (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
+               !disable_msi) {
+
+               if (pci_enable_msi(bp->pdev) == 0) {
+                       bp->flags |= USING_MSI_FLAG;
+                       rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
+                                       dev);
+               }
+               else {
+                       rc = request_irq(bp->pdev->irq, bnx2_interrupt,
+                                       SA_SHIRQ, dev->name, dev);
+               }
+       }
+       else {
+               rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
+                               dev->name, dev);
+       }
+       if (rc) {
+               bnx2_free_mem(bp);
+               return rc;
+       }
+
+       rc = bnx2_init_nic(bp);
+
+       if (rc) {
+               free_irq(bp->pdev->irq, dev);
+               if (bp->flags & USING_MSI_FLAG) {
+                       pci_disable_msi(bp->pdev);
+                       bp->flags &= ~USING_MSI_FLAG;
+               }
+               bnx2_free_skbs(bp);
+               bnx2_free_mem(bp);
+               return rc;
+       }
+       
+       init_timer(&bp->timer);
+
+       bp->timer.expires = RUN_AT(bp->timer_interval);
+       bp->timer.data = (unsigned long) bp;
+       bp->timer.function = bnx2_timer;
+       add_timer(&bp->timer);
+
+       atomic_set(&bp->intr_sem, 0);
+
+       bnx2_enable_int(bp);
+
+       if (bp->flags & USING_MSI_FLAG) {
+               /* Test MSI to make sure it is working
+                * If MSI test fails, go back to INTx mode
+                */
+               if (bnx2_test_intr(bp) != 0) {
+                       printk(KERN_WARNING PFX "%s: No interrupt was generated"
+                              " using MSI, switching to INTx mode. Please"
+                              " report this failure to the PCI maintainer"
+                              " and include system chipset information.\n",
+                              bp->dev->name);
+
+                       bnx2_disable_int(bp);
+                       free_irq(bp->pdev->irq, dev);
+                       pci_disable_msi(bp->pdev);
+                       bp->flags &= ~USING_MSI_FLAG;
+
+                       rc = bnx2_init_nic(bp);
+
+                       if (!rc) {
+                               rc = request_irq(bp->pdev->irq, bnx2_interrupt,
+                                       SA_SHIRQ, dev->name, dev);
+                       }
+                       if (rc) {
+                               bnx2_free_skbs(bp);
+                               bnx2_free_mem(bp);
+                               del_timer_sync(&bp->timer);
+                               return rc;
+                       }
+                       bnx2_enable_int(bp);
+               }
+       }
+       if (bp->flags & USING_MSI_FLAG) {
+               printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
+       }
+
+       netif_start_queue(dev);
+
+       return 0;
+}
+
+static void
+bnx2_reset_task(void *data)
+{
+       struct bnx2 *bp = data;
+
+       bnx2_netif_stop(bp);
+
+       bnx2_init_nic(bp);
+
+       atomic_set(&bp->intr_sem, 1);
+       bnx2_netif_start(bp);
+}
+
+static void
+bnx2_tx_timeout(struct net_device *dev)
+{
+       struct bnx2 *bp = dev->priv;
+
+       /* This allows the netif to be shutdown gracefully before resetting */
+       schedule_work(&bp->reset_task);
+}
+
+#ifdef BCM_VLAN
+/* Called with rtnl_lock */
+static void
+bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
+{
+       struct bnx2 *bp = dev->priv;
+
+       bnx2_netif_stop(bp);
+
+       bp->vlgrp = vlgrp;
+       bnx2_set_rx_mode(dev);
+
+       bnx2_netif_start(bp);
+}
+
+/* Called with rtnl_lock */
+static void
+bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
+{
+       struct bnx2 *bp = dev->priv;
+
+       bnx2_netif_stop(bp);
+
+       if (bp->vlgrp)
+               bp->vlgrp->vlan_devices[vid] = NULL;
+       bnx2_set_rx_mode(dev);
+
+       bnx2_netif_start(bp);
+}
+#endif
+
+/* Called with dev->xmit_lock.
+ * hard_start_xmit is pseudo-lockless - a lock is only required when
+ * the tx queue is full. This way, we get the benefit of lockless
+ * operations most of the time without the complexities to handle
+ * netif_stop_queue/wake_queue race conditions.
+ */
+static int
+bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+       struct bnx2 *bp = dev->priv;
+       dma_addr_t mapping;
+       struct tx_bd *txbd;
+       struct sw_bd *tx_buf;
+       u32 len, vlan_tag_flags, last_frag, mss;
+       u16 prod, ring_prod;
+       int i;
+
+       if (unlikely(atomic_read(&bp->tx_avail_bd) <
+               (skb_shinfo(skb)->nr_frags + 1))) {
+
+               netif_stop_queue(dev);
+               printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
+                       dev->name);
+
+               return NETDEV_TX_BUSY;
+       }
+       len = skb_headlen(skb);
+       prod = bp->tx_prod;
+       ring_prod = TX_RING_IDX(prod);
+
+       vlan_tag_flags = 0;
+       if (skb->ip_summed == CHECKSUM_HW) {
+               vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
+       }
+
+       if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
+               vlan_tag_flags |=
+                       (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
+       }
+#ifdef BCM_TSO 
+       if ((mss = skb_shinfo(skb)->tso_size) &&
+               (skb->len > (bp->dev->mtu + ETH_HLEN))) {
+               u32 tcp_opt_len, ip_tcp_len;
+
+               if (skb_header_cloned(skb) &&
+                   pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
+                       dev_kfree_skb(skb);
+                       return NETDEV_TX_OK;
+               }
+
+               tcp_opt_len = ((skb->h.th->doff - 5) * 4);
+               vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
+
+               tcp_opt_len = 0;
+               if (skb->h.th->doff > 5) {
+                       tcp_opt_len = (skb->h.th->doff - 5) << 2;
+               }
+               ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
+
+               skb->nh.iph->check = 0;
+               skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
+               skb->h.th->check =
+                       ~csum_tcpudp_magic(skb->nh.iph->saddr,
+                                           skb->nh.iph->daddr,
+                                           0, IPPROTO_TCP, 0);
+
+               if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
+                       vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
+                               (tcp_opt_len >> 2)) << 8;
+               }
+       }
+       else
+#endif
+       {
+               mss = 0;
+       }
+
+       mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
+       
+       tx_buf = &bp->tx_buf_ring[ring_prod];
+       tx_buf->skb = skb;
+       pci_unmap_addr_set(tx_buf, mapping, mapping);
+
+       txbd = &bp->tx_desc_ring[ring_prod];
+
+       txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
+       txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
+       txbd->tx_bd_mss_nbytes = len | (mss << 16);
+       txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
+
+       last_frag = skb_shinfo(skb)->nr_frags;
+
+       for (i = 0; i < last_frag; i++) {
+               skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+
+               prod = NEXT_TX_BD(prod);
+               ring_prod = TX_RING_IDX(prod);
+               txbd = &bp->tx_desc_ring[ring_prod];
+
+               len = frag->size;
+               mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
+                       len, PCI_DMA_TODEVICE);
+               pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
+                               mapping, mapping);
+
+               txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
+               txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
+               txbd->tx_bd_mss_nbytes = len | (mss << 16);
+               txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
+
+       }
+       txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
+
+       prod = NEXT_TX_BD(prod);
+       bp->tx_prod_bseq += skb->len;
+
+       atomic_sub(last_frag + 1, &bp->tx_avail_bd);
+
+       REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
+       REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
+
+       mmiowb();
+
+       bp->tx_prod = prod;
+       dev->trans_start = jiffies;
+
+       if (unlikely(atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS)) {
+               unsigned long flags;
+
+               spin_lock_irqsave(&bp->tx_lock, flags);
+               if (atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS) {
+                       netif_stop_queue(dev);
+
+                       if (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS)
+                               netif_wake_queue(dev);
+               }
+               spin_unlock_irqrestore(&bp->tx_lock, flags);
+       }
+
+       return NETDEV_TX_OK;
+}
+
+/* Called with rtnl_lock */
+static int
+bnx2_close(struct net_device *dev)
+{
+       struct bnx2 *bp = dev->priv;
+       u32 reset_code;
+
+       flush_scheduled_work();
+       bnx2_netif_stop(bp);
+       del_timer_sync(&bp->timer);
+       if (bp->wol)
+               reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
+       else
+               reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
+       bnx2_reset_chip(bp, reset_code);
+       free_irq(bp->pdev->irq, dev);
+       if (bp->flags & USING_MSI_FLAG) {
+               pci_disable_msi(bp->pdev);
+               bp->flags &= ~USING_MSI_FLAG;
+       }
+       bnx2_free_skbs(bp);
+       bnx2_free_mem(bp);
+       bp->link_up = 0;
+       netif_carrier_off(bp->dev);
+       bnx2_set_power_state(bp, 3);
+       return 0;
+}
+
+#define GET_NET_STATS64(ctr)                                   \
+       (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
+       (unsigned long) (ctr##_lo)
+
+#define GET_NET_STATS32(ctr)           \
+       (ctr##_lo)
+
+#if (BITS_PER_LONG == 64)
+#define GET_NET_STATS  GET_NET_STATS64
+#else
+#define GET_NET_STATS  GET_NET_STATS32
+#endif
+
+static struct net_device_stats *
+bnx2_get_stats(struct net_device *dev)
+{
+       struct bnx2 *bp = dev->priv;
+       struct statistics_block *stats_blk = bp->stats_blk;
+       struct net_device_stats *net_stats = &bp->net_stats;
+
+       if (bp->stats_blk == NULL) {
+               return net_stats;
+       }
+       net_stats->rx_packets =
+               GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
+               GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
+               GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
+
+       net_stats->tx_packets =
+               GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
+               GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
+               GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
+
+       net_stats->rx_bytes =
+               GET_NET_STATS(stats_blk->stat_IfHCInOctets);
+
+       net_stats->tx_bytes =
+               GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
+
+       net_stats->multicast = 
+               GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
+
+       net_stats->collisions = 
+               (unsigned long) stats_blk->stat_EtherStatsCollisions;
+
+       net_stats->rx_length_errors = 
+               (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
+               stats_blk->stat_EtherStatsOverrsizePkts);
+
+       net_stats->rx_over_errors = 
+               (unsigned long) stats_blk->stat_IfInMBUFDiscards;
+
+       net_stats->rx_frame_errors = 
+               (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
+
+       net_stats->rx_crc_errors = 
+               (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
+
+       net_stats->rx_errors = net_stats->rx_length_errors +
+               net_stats->rx_over_errors + net_stats->rx_frame_errors +
+               net_stats->rx_crc_errors;
+
+       net_stats->tx_aborted_errors =
+               (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
+               stats_blk->stat_Dot3StatsLateCollisions);
+
+       if (CHIP_NUM(bp) == CHIP_NUM_5706)
+               net_stats->tx_carrier_errors = 0;
+       else {
+               net_stats->tx_carrier_errors =
+                       (unsigned long)
+                       stats_blk->stat_Dot3StatsCarrierSenseErrors;
+       }
+
+       net_stats->tx_errors =
+               (unsigned long) 
+               stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
+               +
+               net_stats->tx_aborted_errors +
+               net_stats->tx_carrier_errors;
+
+       return net_stats;
+}
+
+/* All ethtool functions called with rtnl_lock */
+
+static int
+bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct bnx2 *bp = dev->priv;
+
+       cmd->supported = SUPPORTED_Autoneg;
+       if (bp->phy_flags & PHY_SERDES_FLAG) {
+               cmd->supported |= SUPPORTED_1000baseT_Full |
+                       SUPPORTED_FIBRE;
+
+               cmd->port = PORT_FIBRE;
+       }
+       else {
+               cmd->supported |= SUPPORTED_10baseT_Half |
+                       SUPPORTED_10baseT_Full |
+                       SUPPORTED_100baseT_Half |
+                       SUPPORTED_100baseT_Full |
+                       SUPPORTED_1000baseT_Full |
+                       SUPPORTED_TP;
+
+               cmd->port = PORT_TP;
+       }
+
+       cmd->advertising = bp->advertising;
+
+       if (bp->autoneg & AUTONEG_SPEED) {
+               cmd->autoneg = AUTONEG_ENABLE;
+       }
+       else {
+               cmd->autoneg = AUTONEG_DISABLE;
+       }
+
+       if (netif_carrier_ok(dev)) {
+               cmd->speed = bp->line_speed;
+               cmd->duplex = bp->duplex;
+       }
+       else {
+               cmd->speed = -1;
+               cmd->duplex = -1;
+       }
+
+       cmd->transceiver = XCVR_INTERNAL;
+       cmd->phy_address = bp->phy_addr;
+
+       return 0;
+}
+  
+static int
+bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct bnx2 *bp = dev->priv;
+       u8 autoneg = bp->autoneg;
+       u8 req_duplex = bp->req_duplex;
+       u16 req_line_speed = bp->req_line_speed;
+       u32 advertising = bp->advertising;
+
+       if (cmd->autoneg == AUTONEG_ENABLE) {
+               autoneg |= AUTONEG_SPEED;
+
+               cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED; 
+
+               /* allow advertising 1 speed */
+               if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
+                       (cmd->advertising == ADVERTISED_10baseT_Full) ||
+                       (cmd->advertising == ADVERTISED_100baseT_Half) ||
+                       (cmd->advertising == ADVERTISED_100baseT_Full)) {
+
+                       if (bp->phy_flags & PHY_SERDES_FLAG)
+                               return -EINVAL;
+
+                       advertising = cmd->advertising;
+
+               }
+               else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
+                       advertising = cmd->advertising;
+               }
+               else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
+                       return -EINVAL;
+               }
+               else {
+                       if (bp->phy_flags & PHY_SERDES_FLAG) {
+                               advertising = ETHTOOL_ALL_FIBRE_SPEED;
+                       }
+                       else {
+                               advertising = ETHTOOL_ALL_COPPER_SPEED;
+                       }
+               }
+               advertising |= ADVERTISED_Autoneg;
+       }
+       else {
+               if (bp->phy_flags & PHY_SERDES_FLAG) {
+                       if ((cmd->speed != SPEED_1000) ||
+                               (cmd->duplex != DUPLEX_FULL)) {
+                               return -EINVAL;
+                       }
+               }
+               else if (cmd->speed == SPEED_1000) {
+                       return -EINVAL;
+               }
+               autoneg &= ~AUTONEG_SPEED;
+               req_line_speed = cmd->speed;
+               req_duplex = cmd->duplex;
+               advertising = 0;
+       }
+
+       bp->autoneg = autoneg;
+       bp->advertising = advertising;
+       bp->req_line_speed = req_line_speed;
+       bp->req_duplex = req_duplex;
+
+       spin_lock_irq(&bp->phy_lock);
+
+       bnx2_setup_phy(bp);
+
+       spin_unlock_irq(&bp->phy_lock);
+
+       return 0;
+}
+
+static void
+bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
+{
+       struct bnx2 *bp = dev->priv;
+
+       strcpy(info->driver, DRV_MODULE_NAME);
+       strcpy(info->version, DRV_MODULE_VERSION);
+       strcpy(info->bus_info, pci_name(bp->pdev));
+       info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
+       info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
+       info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
+       info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
+       info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
+       info->fw_version[7] = 0;
+}
+
+static void
+bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+       struct bnx2 *bp = dev->priv;
+
+       if (bp->flags & NO_WOL_FLAG) {
+               wol->supported = 0;
+               wol->wolopts = 0;
+       }
+       else {
+               wol->supported = WAKE_MAGIC;
+               if (bp->wol)
+                       wol->wolopts = WAKE_MAGIC;
+               else
+                       wol->wolopts = 0;
+       }
+       memset(&wol->sopass, 0, sizeof(wol->sopass));
+}
+
+static int
+bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+       struct bnx2 *bp = dev->priv;
+
+       if (wol->wolopts & ~WAKE_MAGIC)
+               return -EINVAL;
+
+       if (wol->wolopts & WAKE_MAGIC) {
+               if (bp->flags & NO_WOL_FLAG)
+                       return -EINVAL;
+
+               bp->wol = 1;
+       }
+       else {
+               bp->wol = 0;
+       }
+       return 0;
+}
+
+static int
+bnx2_nway_reset(struct net_device *dev)
+{
+       struct bnx2 *bp = dev->priv;
+       u32 bmcr;
+
+       if (!(bp->autoneg & AUTONEG_SPEED)) {
+               return -EINVAL;
+       }
+
+       spin_lock_irq(&bp->phy_lock);
+
+       /* Force a link down visible on the other side */
+       if (bp->phy_flags & PHY_SERDES_FLAG) {
+               bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
+               spin_unlock_irq(&bp->phy_lock);
+
+               msleep(20);
+
+               spin_lock_irq(&bp->phy_lock);
+               if (CHIP_NUM(bp) == CHIP_NUM_5706) {
+                       bp->serdes_an_pending = SERDES_AN_TIMEOUT /
+                               bp->timer_interval;
+               }
+       }
+
+       bnx2_read_phy(bp, MII_BMCR, &bmcr);
+       bmcr &= ~BMCR_LOOPBACK;
+       bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
+
+       spin_unlock_irq(&bp->phy_lock);
+
+       return 0;
+}
+
+static int
+bnx2_get_eeprom_len(struct net_device *dev)
+{
+       struct bnx2 *bp = dev->priv;
+
+       if (bp->flash_info == 0)
+               return 0;
+
+       return (int) bp->flash_info->total_size;
+}
+
+static int
+bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
+               u8 *eebuf)
+{
+       struct bnx2 *bp = dev->priv;
+       int rc;
+
+       if (eeprom->offset > bp->flash_info->total_size)
+               return -EINVAL;
+
+       if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
+               eeprom->len = bp->flash_info->total_size - eeprom->offset;
+
+       rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
+
+       return rc;
+}
+
+static int
+bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
+               u8 *eebuf)
+{
+       struct bnx2 *bp = dev->priv;
+       int rc;
+
+       if (eeprom->offset > bp->flash_info->total_size)
+               return -EINVAL;
+
+       if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
+               eeprom->len = bp->flash_info->total_size - eeprom->offset;
+
+       rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
+
+       return rc;
+}
+
+static int
+bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
+{
+       struct bnx2 *bp = dev->priv;
+
+       memset(coal, 0, sizeof(struct ethtool_coalesce));
+
+       coal->rx_coalesce_usecs = bp->rx_ticks;
+       coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
+       coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
+       coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
+
+       coal->tx_coalesce_usecs = bp->tx_ticks;
+       coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
+       coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
+       coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
+
+       coal->stats_block_coalesce_usecs = bp->stats_ticks;
+
+       return 0;
+}
+
+static int
+bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
+{
+       struct bnx2 *bp = dev->priv;
+
+       bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
+       if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
+
+       bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; 
+       if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
+
+       bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
+       if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
+
+       bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
+       if (bp->rx_quick_cons_trip_int > 0xff)
+               bp->rx_quick_cons_trip_int = 0xff;
+
+       bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
+       if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
+
+       bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
+       if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
+
+       bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
+       if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
+
+       bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
+       if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
+               0xff;
+
+       bp->stats_ticks = coal->stats_block_coalesce_usecs;
+       if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
+       bp->stats_ticks &= 0xffff00;
+
+       if (netif_running(bp->dev)) {
+               bnx2_netif_stop(bp);
+               bnx2_init_nic(bp);
+               bnx2_netif_start(bp);
+       }
+
+       return 0;
+}
+
+static void
+bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
+{
+       struct bnx2 *bp = dev->priv;
+
+       ering->rx_max_pending = MAX_RX_DESC_CNT;
+       ering->rx_mini_max_pending = 0;
+       ering->rx_jumbo_max_pending = 0;
+
+       ering->rx_pending = bp->rx_ring_size;
+       ering->rx_mini_pending = 0;
+       ering->rx_jumbo_pending = 0;
+
+       ering->tx_max_pending = MAX_TX_DESC_CNT;
+       ering->tx_pending = bp->tx_ring_size;
+}
+
+static int
+bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
+{
+       struct bnx2 *bp = dev->priv;
+
+       if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
+               (ering->tx_pending > MAX_TX_DESC_CNT) ||
+               (ering->tx_pending <= MAX_SKB_FRAGS)) {
+
+               return -EINVAL;
+       }
+       bp->rx_ring_size = ering->rx_pending;
+       bp->tx_ring_size = ering->tx_pending;
+
+       if (netif_running(bp->dev)) {
+               bnx2_netif_stop(bp);
+               bnx2_init_nic(bp);
+               bnx2_netif_start(bp);
+       }
+
+       return 0;
+}
+
+static void
+bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
+{
+       struct bnx2 *bp = dev->priv;
+
+       epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
+       epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
+       epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
+}
+
+static int
+bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
+{
+       struct bnx2 *bp = dev->priv;
+
+       bp->req_flow_ctrl = 0;
+       if (epause->rx_pause)
+               bp->req_flow_ctrl |= FLOW_CTRL_RX;
+       if (epause->tx_pause)
+               bp->req_flow_ctrl |= FLOW_CTRL_TX;
+
+       if (epause->autoneg) {
+               bp->autoneg |= AUTONEG_FLOW_CTRL;
+       }
+       else {
+               bp->autoneg &= ~AUTONEG_FLOW_CTRL;
+       }
+
+       spin_lock_irq(&bp->phy_lock);
+
+       bnx2_setup_phy(bp);
+
+       spin_unlock_irq(&bp->phy_lock);
+
+       return 0;
+}
+
+static u32
+bnx2_get_rx_csum(struct net_device *dev)
+{
+       struct bnx2 *bp = dev->priv;
+
+       return bp->rx_csum;
+}
+
+static int
+bnx2_set_rx_csum(struct net_device *dev, u32 data)
+{
+       struct bnx2 *bp = dev->priv;
+
+       bp->rx_csum = data;
+       return 0;
+}
+
+#define BNX2_NUM_STATS 45
+
+struct {
+       char string[ETH_GSTRING_LEN];
+} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
+       { "rx_bytes" },
+       { "rx_error_bytes" },
+       { "tx_bytes" },
+       { "tx_error_bytes" },
+       { "rx_ucast_packets" },
+       { "rx_mcast_packets" },
+       { "rx_bcast_packets" },
+       { "tx_ucast_packets" },
+       { "tx_mcast_packets" },
+       { "tx_bcast_packets" },
+       { "tx_mac_errors" },
+       { "tx_carrier_errors" },
+       { "rx_crc_errors" },
+       { "rx_align_errors" },
+       { "tx_single_collisions" },
+       { "tx_multi_collisions" },
+       { "tx_deferred" },
+       { "tx_excess_collisions" },
+       { "tx_late_collisions" },
+       { "tx_total_collisions" },
+       { "rx_fragments" },
+       { "rx_jabbers" },
+       { "rx_undersize_packets" },
+       { "rx_oversize_packets" },
+       { "rx_64_byte_packets" },
+       { "rx_65_to_127_byte_packets" },
+       { "rx_128_to_255_byte_packets" },
+       { "rx_256_to_511_byte_packets" },
+       { "rx_512_to_1023_byte_packets" },
+       { "rx_1024_to_1522_byte_packets" },
+       { "rx_1523_to_9022_byte_packets" },
+       { "tx_64_byte_packets" },
+       { "tx_65_to_127_byte_packets" },
+       { "tx_128_to_255_byte_packets" },
+       { "tx_256_to_511_byte_packets" },
+       { "tx_512_to_1023_byte_packets" },
+       { "tx_1024_to_1522_byte_packets" },
+       { "tx_1523_to_9022_byte_packets" },
+       { "rx_xon_frames" },
+       { "rx_xoff_frames" },
+       { "tx_xon_frames" },
+       { "tx_xoff_frames" },
+       { "rx_mac_ctrl_frames" },
+       { "rx_filtered_packets" },
+       { "rx_discards" },
+};
+
+#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, 
offset_name) / 4)
+
+unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
+    STATS_OFFSET32(stat_IfHCInOctets_hi),
+    STATS_OFFSET32(stat_IfHCInBadOctets_hi),
+    STATS_OFFSET32(stat_IfHCOutOctets_hi),
+    STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
+    STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
+    STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
+    STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
+    STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
+    STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
+    STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
+    STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
+    STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),                 
+    STATS_OFFSET32(stat_Dot3StatsFCSErrors),                          
+    STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),                    
+    STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),              
+    STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),            
+    STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),              
+    STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),                
+    STATS_OFFSET32(stat_Dot3StatsLateCollisions),                     
+    STATS_OFFSET32(stat_EtherStatsCollisions),                        
+    STATS_OFFSET32(stat_EtherStatsFragments),                         
+    STATS_OFFSET32(stat_EtherStatsJabbers),                           
+    STATS_OFFSET32(stat_EtherStatsUndersizePkts),                     
+    STATS_OFFSET32(stat_EtherStatsOverrsizePkts),                     
+    STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),                    
+    STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),         
+    STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),        
+    STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),        
+    STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),       
+    STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),      
+    STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),      
+    STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),                    
+    STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),         
+    STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),        
+    STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),        
+    STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),       
+    STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),      
+    STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),      
+    STATS_OFFSET32(stat_XonPauseFramesReceived),                      
+    STATS_OFFSET32(stat_XoffPauseFramesReceived),                     
+    STATS_OFFSET32(stat_OutXonSent),                                  
+    STATS_OFFSET32(stat_OutXoffSent),                                 
+    STATS_OFFSET32(stat_MacControlFramesReceived),                    
+    STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),                  
+    STATS_OFFSET32(stat_IfInMBUFDiscards),                            
+};
+
+/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
+ * skipped because of errata.
+ */               
+u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
+       8,0,8,8,8,8,8,8,8,8,
+       4,0,4,4,4,4,4,4,4,4,
+       4,4,4,4,4,4,4,4,4,4,
+       4,4,4,4,4,4,4,4,4,4,
+       4,4,4,4,4,
+};
+
+#define BNX2_NUM_TESTS 6
+
+struct {
+       char string[ETH_GSTRING_LEN];
+} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
+       { "register_test (offline)" },
+       { "memory_test (offline)" },
+       { "loopback_test (offline)" },
+       { "nvram_test (online)" },
+       { "interrupt_test (online)" },
+       { "link_test (online)" },
+};
+
+static int
+bnx2_self_test_count(struct net_device *dev)
+{
+       return BNX2_NUM_TESTS;
+}
+
+static void
+bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
+{
+       struct bnx2 *bp = dev->priv;
+
+       memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
+       if (etest->flags & ETH_TEST_FL_OFFLINE) {
+               bnx2_netif_stop(bp);
+               bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
+               bnx2_free_skbs(bp);
+
+               if (bnx2_test_registers(bp) != 0) {
+                       buf[0] = 1;
+                       etest->flags |= ETH_TEST_FL_FAILED;
+               }
+               if (bnx2_test_memory(bp) != 0) {
+                       buf[1] = 1;
+                       etest->flags |= ETH_TEST_FL_FAILED;
+               }
+               if (bnx2_test_loopback(bp) != 0) {
+                       buf[2] = 1;
+                       etest->flags |= ETH_TEST_FL_FAILED;
+               }
+
+               if (!netif_running(bp->dev)) {
+                       bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
+               }
+               else {
+                       bnx2_init_nic(bp);
+                       bnx2_netif_start(bp);
+               }
+
+               /* wait for link up */
+               msleep_interruptible(3000);
+               if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
+                       msleep_interruptible(4000);
+       }
+
+       if (bnx2_test_nvram(bp) != 0) {
+               buf[3] = 1;
+               etest->flags |= ETH_TEST_FL_FAILED;
+       }
+       if (bnx2_test_intr(bp) != 0) {
+               buf[4] = 1;
+               etest->flags |= ETH_TEST_FL_FAILED;
+       }
+
+       if (bnx2_test_link(bp) != 0) {
+               buf[5] = 1;
+               etest->flags |= ETH_TEST_FL_FAILED;
+
+       }
+}
+
+static void
+bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
+{
+       switch (stringset) {
+       case ETH_SS_STATS:
+               memcpy(buf, bnx2_stats_str_arr,
+                       sizeof(bnx2_stats_str_arr));
+               break;
+       case ETH_SS_TEST:
+               memcpy(buf, bnx2_tests_str_arr,
+                       sizeof(bnx2_tests_str_arr));
+               break;
+       }
+}
+
+static int
+bnx2_get_stats_count(struct net_device *dev)
+{
+       return BNX2_NUM_STATS;
+}
+
+static void
+bnx2_get_ethtool_stats(struct net_device *dev,
+               struct ethtool_stats *stats, u64 *buf)
+{
+       struct bnx2 *bp = dev->priv;
+       int i;
+       u32 *hw_stats = (u32 *) bp->stats_blk;
+       u8 *stats_len_arr = 0;
+
+       if (hw_stats == NULL) {
+               memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
+               return;
+       }
+
+       if (CHIP_NUM(bp) == CHIP_NUM_5706)
+               stats_len_arr = bnx2_5706_stats_len_arr;
+
+       for (i = 0; i < BNX2_NUM_STATS; i++) {
+               if (stats_len_arr[i] == 0) {
+                       /* skip this counter */
+                       buf[i] = 0;
+                       continue;
+               }
+               if (stats_len_arr[i] == 4) {
+                       /* 4-byte counter */
+                       buf[i] = (u64)
+                               *(hw_stats + bnx2_stats_offset_arr[i]);
+                       continue;
+               }
+               /* 8-byte counter */
+               buf[i] = (((u64) *(hw_stats +
+                                       bnx2_stats_offset_arr[i])) << 32) +
+                               *(hw_stats + bnx2_stats_offset_arr[i] + 1);
+       }
+}
+
+static int
+bnx2_phys_id(struct net_device *dev, u32 data)
+{
+       struct bnx2 *bp = dev->priv;
+       int i;
+       u32 save;
+
+       if (data == 0)
+               data = 2;
+
+       save = REG_RD(bp, BNX2_MISC_CFG);
+       REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
+
+       for (i = 0; i < (data * 2); i++) {
+               if ((i % 2) == 0) {
+                       REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
+               }
+               else {
+                       REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
+                               BNX2_EMAC_LED_1000MB_OVERRIDE |
+                               BNX2_EMAC_LED_100MB_OVERRIDE |
+                               BNX2_EMAC_LED_10MB_OVERRIDE |
+                               BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
+                               BNX2_EMAC_LED_TRAFFIC);
+               }
+               msleep_interruptible(500);
+               if (signal_pending(current))
+                       break;
+       }
+       REG_WR(bp, BNX2_EMAC_LED, 0);
+       REG_WR(bp, BNX2_MISC_CFG, save);
+       return 0;
+}
+
+static struct ethtool_ops bnx2_ethtool_ops = {
+       .get_settings           = bnx2_get_settings,
+       .set_settings           = bnx2_set_settings,
+       .get_drvinfo            = bnx2_get_drvinfo,
+       .get_wol                = bnx2_get_wol,
+       .set_wol                = bnx2_set_wol,
+       .nway_reset             = bnx2_nway_reset,
+       .get_link               = ethtool_op_get_link,
+       .get_eeprom_len         = bnx2_get_eeprom_len,
+       .get_eeprom             = bnx2_get_eeprom,
+       .set_eeprom             = bnx2_set_eeprom,
+       .get_coalesce           = bnx2_get_coalesce,
+       .set_coalesce           = bnx2_set_coalesce,
+       .get_ringparam          = bnx2_get_ringparam,
+       .set_ringparam          = bnx2_set_ringparam,
+       .get_pauseparam         = bnx2_get_pauseparam,
+       .set_pauseparam         = bnx2_set_pauseparam,
+       .get_rx_csum            = bnx2_get_rx_csum,
+       .set_rx_csum            = bnx2_set_rx_csum,
+       .get_tx_csum            = ethtool_op_get_tx_csum,
+       .set_tx_csum            = ethtool_op_set_tx_csum,
+       .get_sg                 = ethtool_op_get_sg,
+       .set_sg                 = ethtool_op_set_sg,
+#ifdef BCM_TSO
+       .get_tso                = ethtool_op_get_tso,
+       .set_tso                = ethtool_op_set_tso,
+#endif
+       .self_test_count        = bnx2_self_test_count,
+       .self_test              = bnx2_self_test,
+       .get_strings            = bnx2_get_strings,
+       .phys_id                = bnx2_phys_id,
+       .get_stats_count        = bnx2_get_stats_count,
+       .get_ethtool_stats      = bnx2_get_ethtool_stats,
+};
+
+/* Called with rtnl_lock */
+static int
+bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+       struct mii_ioctl_data *data = (struct mii_ioctl_data *)&ifr->ifr_data;
+       struct bnx2 *bp = dev->priv;
+       int err;
+
+       switch(cmd) {
+       case SIOCGMIIPHY:
+               data->phy_id = bp->phy_addr;
+
+               /* fallthru */
+       case SIOCGMIIREG: {
+               u32 mii_regval;
+
+               spin_lock_irq(&bp->phy_lock);
+               err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
+               spin_unlock_irq(&bp->phy_lock);
+
+               data->val_out = mii_regval;
+
+               return err;
+       }
+
+       case SIOCSMIIREG:
+               if (!capable(CAP_NET_ADMIN))
+                       return -EPERM;
+
+               spin_lock_irq(&bp->phy_lock);
+               err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
+               spin_unlock_irq(&bp->phy_lock);
+
+               return err;
+
+       default:
+               /* do nothing */
+               break;
+       }
+       return -EOPNOTSUPP;
+}
+
+/* Called with rtnl_lock */
+static int
+bnx2_change_mac_addr(struct net_device *dev, void *p)
+{
+       struct sockaddr *addr = p;
+       struct bnx2 *bp = dev->priv;
+
+       memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+       if (netif_running(dev))
+               bnx2_set_mac_addr(bp);
+
+       return 0;
+}
+
+/* Called with rtnl_lock */
+static int
+bnx2_change_mtu(struct net_device *dev, int new_mtu)
+{
+       struct bnx2 *bp = dev->priv;
+
+       if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
+               ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
+               return -EINVAL;
+
+       dev->mtu = new_mtu;
+       if (netif_running(dev)) {
+               bnx2_netif_stop(bp);
+
+               bnx2_init_nic(bp);
+
+               bnx2_netif_start(bp);
+       }
+       return 0;
+}
+
+#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
+static void
+poll_bnx2(struct net_device *dev)
+{
+       struct bnx2 *bp = dev->priv;
+
+       disable_irq(bp->pdev->irq);
+       bnx2_interrupt(bp->pdev->irq, dev, NULL);
+       enable_irq(bp->pdev->irq);
+}
+#endif
+
+static int __devinit
+bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
+{
+       struct bnx2 *bp;
+       unsigned long mem_len;
+       int rc;
+       u32 reg;
+
+       SET_MODULE_OWNER(dev);
+       SET_NETDEV_DEV(dev, &pdev->dev);
+       bp = dev->priv;
+
+       bp->flags = 0;
+       bp->phy_flags = 0;
+
+       /* enable device (incl. PCI PM wakeup), and bus-mastering */
+       rc = pci_enable_device(pdev);
+       if (rc) {
+               printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
+               goto err_out;
+       }
+
+       if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
+               printk(KERN_ERR PFX "Cannot find PCI device base address, "
+                      "aborting.\n");
+               rc = -ENODEV;
+               goto err_out_disable;
+       }
+
+       rc = pci_request_regions(pdev, DRV_MODULE_NAME);
+       if (rc) {
+               printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
+               goto err_out_disable;
+       }
+
+       pci_set_master(pdev);
+
+       bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
+       if (bp->pm_cap == 0) {
+               printk(KERN_ERR PFX "Cannot find power management capability, "
+                              "aborting.\n");
+               rc = -EIO;
+               goto err_out_release;
+       }
+
+       bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
+       if (bp->pcix_cap == 0) {
+               printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
+               rc = -EIO;
+               goto err_out_release;
+       }
+
+       if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
+               bp->flags |= USING_DAC_FLAG;
+               if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
+                       printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
+                              "failed, aborting.\n");
+                       rc = -EIO;
+                       goto err_out_release;
+               }
+       }
+       else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
+               printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
+               rc = -EIO;
+               goto err_out_release;
+       }
+
+       bp->dev = dev;
+       bp->pdev = pdev;
+
+       spin_lock_init(&bp->phy_lock);
+       spin_lock_init(&bp->tx_lock);
+       INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
+
+       dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
+       mem_len = MB_GET_CID_ADDR(17);
+       dev->mem_end = dev->mem_start + mem_len;
+       dev->irq = pdev->irq;
+
+       bp->regview = ioremap_nocache(dev->base_addr, mem_len);
+
+       if (!bp->regview) {
+               printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
+               rc = -ENOMEM;
+               goto err_out_release;
+       }
+
+       /* Configure byte swap and enable write to the reg_window registers.
+        * Rely on CPU to do target byte swapping on big endian systems
+        * The chip's target access swapping will not swap all accesses
+        */
+       pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
+                              BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
+                              BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
+
+       bnx2_set_power_state(bp, 0);
+
+       bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
+
+       bp->phy_addr = 1;
+
+       /* Get bus information. */
+       reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
+       if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
+               u32 clkreg;
+
+               bp->flags |= PCIX_FLAG;
+
+               clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
+               
+               clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
+               switch (clkreg) {
+               case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
+                       bp->bus_speed_mhz = 133;
+                       break;
+
+               case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
+                       bp->bus_speed_mhz = 100;
+                       break;
+
+               case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
+               case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
+                       bp->bus_speed_mhz = 66;
+                       break;
+
+               case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
+               case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
+                       bp->bus_speed_mhz = 50;
+                       break;
+
+               case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
+               case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
+               case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
+                       bp->bus_speed_mhz = 33;
+                       break;
+               }
+       }
+       else {
+               if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
+                       bp->bus_speed_mhz = 66;
+               else
+                       bp->bus_speed_mhz = 33;
+       }
+
+       if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
+               bp->flags |= PCI_32BIT_FLAG;
+
+       /* 5706A0 may falsely detect SERR and PERR. */
+       if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
+               reg = REG_RD(bp, PCI_COMMAND);
+               reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
+               REG_WR(bp, PCI_COMMAND, reg);
+       }
+       else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
+               !(bp->flags & PCIX_FLAG)) {
+
+               printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
+                      "aborting.\n");
+               goto err_out_unmap;
+       }
+
+       bnx2_init_nvram(bp);
+
+       /* Get the permanent MAC address.  First we need to make sure the
+        * firmware is actually running.
+        */
+       reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
+
+       if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
+           BNX2_DEV_INFO_SIGNATURE_MAGIC) {
+               printk(KERN_ERR PFX "Firmware not running, aborting.\n");
+               rc = -ENODEV;
+               goto err_out_unmap;
+       }
+
+       bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
+                               BNX2_DEV_INFO_BC_REV);
+
+       reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
+       bp->mac_addr[0] = (u8) (reg >> 8);
+       bp->mac_addr[1] = (u8) reg;
+
+       reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
+       bp->mac_addr[2] = (u8) (reg >> 24);
+       bp->mac_addr[3] = (u8) (reg >> 16);
+       bp->mac_addr[4] = (u8) (reg >> 8);
+       bp->mac_addr[5] = (u8) reg;
+
+       bp->tx_ring_size = MAX_TX_DESC_CNT;
+       bp->rx_ring_size = 100;
+
+       bp->rx_csum = 1;
+
+       bp->rx_offset = sizeof(struct l2_fhdr) + 2;
+
+       bp->tx_quick_cons_trip_int = 20;
+       bp->tx_quick_cons_trip = 20;
+       bp->tx_ticks_int = 80;
+       bp->tx_ticks = 80;
+               
+       bp->rx_quick_cons_trip_int = 6;
+       bp->rx_quick_cons_trip = 6;
+       bp->rx_ticks_int = 18;
+       bp->rx_ticks = 18;
+
+       bp->stats_ticks = 1000000 & 0xffff00;
+
+       bp->timer_interval =  HZ;
+
+       /* Disable WOL support if we are running on a SERDES chip. */
+       if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
+               bp->phy_flags |= PHY_SERDES_FLAG;
+               bp->flags |= NO_WOL_FLAG;
+       }
+
+       if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
+               bp->tx_quick_cons_trip_int =
+                       bp->tx_quick_cons_trip;
+               bp->tx_ticks_int = bp->tx_ticks;
+               bp->rx_quick_cons_trip_int =
+                       bp->rx_quick_cons_trip;
+               bp->rx_ticks_int = bp->rx_ticks;
+               bp->comp_prod_trip_int = bp->comp_prod_trip;
+               bp->com_ticks_int = bp->com_ticks;
+               bp->cmd_ticks_int = bp->cmd_ticks;
+       }
+
+       bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
+       bp->req_line_speed = 0;
+       if (bp->phy_flags & PHY_SERDES_FLAG) {
+               bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
+       }
+       else {
+               bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
+       }
+
+       bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
+
+       return 0;
+
+err_out_unmap:
+       if (bp->regview) {
+               iounmap(bp->regview);
+       }
+
+err_out_release:
+       pci_release_regions(pdev);
+
+err_out_disable:
+       pci_disable_device(pdev);
+       pci_set_drvdata(pdev, NULL);
+
+err_out:
+       return rc;
+}
+
+static int __devinit
+bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+       static int version_printed = 0;
+       struct net_device *dev = NULL;
+       struct bnx2 *bp;
+       int rc, i;
+
+       if (version_printed++ == 0)
+               printk(KERN_INFO "%s", version);
+
+       /* dev zeroed in init_etherdev */
+       dev = alloc_etherdev(sizeof(*bp));
+
+       if (!dev)
+               return -ENOMEM;
+
+       rc = bnx2_init_board(pdev, dev);
+       if (rc < 0) {
+               free_netdev(dev);
+               return rc;
+       }
+
+       dev->open = bnx2_open;
+       dev->hard_start_xmit = bnx2_start_xmit;
+       dev->stop = bnx2_close;
+       dev->get_stats = bnx2_get_stats;
+       dev->set_multicast_list = bnx2_set_rx_mode;
+       dev->do_ioctl = bnx2_ioctl;
+       dev->set_mac_address = bnx2_change_mac_addr;
+       dev->change_mtu = bnx2_change_mtu;
+       dev->tx_timeout = bnx2_tx_timeout;
+       dev->watchdog_timeo = TX_TIMEOUT;
+#ifdef BCM_VLAN
+       dev->vlan_rx_register = bnx2_vlan_rx_register;
+       dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
+#endif
+       dev->poll = bnx2_poll;
+       dev->ethtool_ops = &bnx2_ethtool_ops;
+       dev->weight = 64;
+
+       bp = dev->priv;
+
+#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
+       dev->poll_controller = poll_bnx2;
+#endif
+
+       if ((rc = register_netdev(dev))) {
+               printk(KERN_ERR PFX "Cannot register net device\n");
+               if (bp->regview)
+                       iounmap(bp->regview);
+               pci_release_regions(pdev);
+               pci_disable_device(pdev);
+               pci_set_drvdata(pdev, NULL);
+               free_netdev(dev);
+               return rc;
+       }
+
+       pci_set_drvdata(pdev, dev);
+
+       memcpy(dev->dev_addr, bp->mac_addr, 6);
+       bp->name = board_info[ent->driver_data].name,
+       printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
+               "IRQ %d, ",
+               dev->name,
+               bp->name,
+               ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
+               ((CHIP_ID(bp) & 0x0ff0) >> 4),
+               ((bp->flags & PCIX_FLAG) ? "-X" : ""),
+               ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
+               bp->bus_speed_mhz,
+               dev->base_addr,
+               bp->pdev->irq);
+
+       printk("node addr ");
+       for (i = 0; i < 6; i++)
+               printk("%2.2x", dev->dev_addr[i]);
+       printk("\n");
+
+       dev->features |= NETIF_F_SG;
+       if (bp->flags & USING_DAC_FLAG)
+               dev->features |= NETIF_F_HIGHDMA;
+       dev->features |= NETIF_F_IP_CSUM;
+#ifdef BCM_VLAN
+       dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
+#endif
+#ifdef BCM_TSO
+       dev->features |= NETIF_F_TSO;
+#endif
+
+       netif_carrier_off(bp->dev);
+
+       return 0;
+}
+
+static void __devexit
+bnx2_remove_one(struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct bnx2 *bp = dev->priv;
+
+       unregister_netdev(dev);
+
+       if (bp->regview)
+               iounmap(bp->regview);
+
+       free_netdev(dev);
+       pci_release_regions(pdev);
+       pci_disable_device(pdev);
+       pci_set_drvdata(pdev, NULL);
+}
+
+static int
+bnx2_suspend(struct pci_dev *pdev, u32 state)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct bnx2 *bp = dev->priv;
+       u32 reset_code;
+
+       if (!netif_running(dev))
+               return 0;
+
+       bnx2_netif_stop(bp);
+       netif_device_detach(dev);
+       del_timer_sync(&bp->timer);
+       if (bp->wol)
+               reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
+       else
+               reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
+       bnx2_reset_chip(bp, reset_code);
+       bnx2_free_skbs(bp);
+       bnx2_set_power_state(bp, state);
+       return 0;
+}
+
+static int
+bnx2_resume(struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct bnx2 *bp = dev->priv;
+
+       if (!netif_running(dev))
+               return 0;
+
+       bnx2_set_power_state(bp, 0);
+       netif_device_attach(dev);
+       bnx2_init_nic(bp);
+       bnx2_netif_start(bp);
+       return 0;
+}
+
+static struct pci_driver bnx2_pci_driver = {
+       name:           DRV_MODULE_NAME,
+       id_table:       bnx2_pci_tbl,
+       probe:          bnx2_init_one,
+       remove:         __devexit_p(bnx2_remove_one),
+       suspend:        bnx2_suspend,
+       resume:         bnx2_resume,
+};
+
+static int __init bnx2_init(void)
+{
+       return pci_module_init(&bnx2_pci_driver);
+}
+
+static void __exit bnx2_cleanup(void)
+{
+       pci_unregister_driver(&bnx2_pci_driver);
+}
+
+module_init(bnx2_init);
+module_exit(bnx2_cleanup);
+
+
+
diff -urN linux/drivers/net/bnx2.h linux/drivers/net/bnx2.h
--- linux/drivers/net/bnx2.h    1970/01/01 00:00:00
+++ linux/drivers/net/bnx2.h    2005-06-07 14:45:34.321822000 +0100     1.1
@@ -0,0 +1,4352 @@
+/* bnx2.h: Broadcom NX2 network driver.
+ *
+ * Copyright (c) 2004, 2005 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Written by: Michael Chan  (mchan@broadcom.com)
+ */
+
+
+#ifndef BNX2_H
+#define BNX2_H
+
+#include <linux/config.h>
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+
+#include <linux/kernel.h>
+#include <linux/timer.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/dma-mapping.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <linux/delay.h>
+#include <asm/byteorder.h>
+#include <linux/time.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#ifdef NETIF_F_HW_VLAN_TX
+#include <linux/if_vlan.h>
+#define BCM_VLAN 1
+#endif
+#ifdef NETIF_F_TSO
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/checksum.h>
+#define BCM_TSO 1
+#endif
+#include <linux/workqueue.h>
+#include <linux/crc32.h>
+
+/* Hardware data structures and register definitions automatically
+ * generated from RTL code. Do not modify.
+ */
+
+/*
+ *  tx_bd definition
+ */
+struct tx_bd {
+       u32 tx_bd_haddr_hi;
+       u32 tx_bd_haddr_lo;                                   
+       u32 tx_bd_mss_nbytes;                                     
+       u32 tx_bd_vlan_tag_flags;                                      
+               #define TX_BD_FLAGS_CONN_FAULT          (1<<0)
+               #define TX_BD_FLAGS_TCP_UDP_CKSUM       (1<<1)
+               #define TX_BD_FLAGS_IP_CKSUM            (1<<2)
+               #define TX_BD_FLAGS_VLAN_TAG            (1<<3)
+               #define TX_BD_FLAGS_COAL_NOW            (1<<4)
+               #define TX_BD_FLAGS_DONT_GEN_CRC        (1<<5)
+               #define TX_BD_FLAGS_END                 (1<<6)
+               #define TX_BD_FLAGS_START               (1<<7)
+               #define TX_BD_FLAGS_SW_OPTION_WORD      (0x1f<<8)
+               #define TX_BD_FLAGS_SW_FLAGS            (1<<13)
+               #define TX_BD_FLAGS_SW_SNAP             (1<<14)
+               #define TX_BD_FLAGS_SW_LSO              (1<<15)
+
+};
+
+
+/*
+ *  rx_bd definition
+ */
+struct rx_bd {
+       u32 rx_bd_haddr_hi;
+       u32 rx_bd_haddr_lo;
+       u32 rx_bd_len;
+       u32 rx_bd_flags;
+               #define RX_BD_FLAGS_NOPUSH              (1<<0)
+               #define RX_BD_FLAGS_DUMMY               (1<<1)
+               #define RX_BD_FLAGS_END                 (1<<2)
+               #define RX_BD_FLAGS_START               (1<<3)
+
+};
+
+
+/*
+ *  status_block definition
+ */
+struct status_block {
+       u32 status_attn_bits;
+               #define STATUS_ATTN_BITS_LINK_STATE             (1L<<0)
+               #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT     (1L<<1)
+               #define STATUS_ATTN_BITS_TX_BD_READ_ABORT       (1L<<2)
+               #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT      (1L<<3)
+               #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT     (1L<<4)
+               #define STATUS_ATTN_BITS_TX_DMA_ABORT           (1L<<5)
+               #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT       (1L<<6)
+               #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT     (1L<<7)
+               #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT    (1L<<8)
+               #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT        (1L<<9)
+               #define STATUS_ATTN_BITS_RX_MBUF_ABORT          (1L<<10)
+               #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT        (1L<<11)
+               #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT     (1L<<12)
+               #define STATUS_ATTN_BITS_RX_V2P_ABORT           (1L<<13)
+               #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT      (1L<<14)
+               #define STATUS_ATTN_BITS_RX_DMA_ABORT           (1L<<15)
+               #define STATUS_ATTN_BITS_COMPLETION_ABORT       (1L<<16)
+               #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT    (1L<<17)
+               #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT    (1L<<18)
+               #define STATUS_ATTN_BITS_CONTEXT_ABORT          (1L<<19)
+               #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT    (1L<<20)
+               #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT    (1L<<21)
+               #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT   (1L<<22)
+               #define STATUS_ATTN_BITS_MAC_ABORT              (1L<<23)
+               #define STATUS_ATTN_BITS_TIMER_ABORT            (1L<<24)
+               #define STATUS_ATTN_BITS_DMAE_ABORT             (1L<<25)
+               #define STATUS_ATTN_BITS_FLSH_ABORT             (1L<<26)
+               #define STATUS_ATTN_BITS_GRC_ABORT              (1L<<27)
+               #define STATUS_ATTN_BITS_PARITY_ERROR           (1L<<31)
+
+       u32 status_attn_bits_ack;
+#if defined(__BIG_ENDIAN)
+       u16 status_tx_quick_consumer_index0;
+       u16 status_tx_quick_consumer_index1;
+       u16 status_tx_quick_consumer_index2;
+       u16 status_tx_quick_consumer_index3;
+       u16 status_rx_quick_consumer_index0;
+       u16 status_rx_quick_consumer_index1;
+       u16 status_rx_quick_consumer_index2;
+       u16 status_rx_quick_consumer_index3;
+       u16 status_rx_quick_consumer_index4;
+       u16 status_rx_quick_consumer_index5;
+       u16 status_rx_quick_consumer_index6;
+       u16 status_rx_quick_consumer_index7;
+       u16 status_rx_quick_consumer_index8;
+       u16 status_rx_quick_consumer_index9;
+       u16 status_rx_quick_consumer_index10;
+       u16 status_rx_quick_consumer_index11;
+       u16 status_rx_quick_consumer_index12;
+       u16 status_rx_quick_consumer_index13;
+       u16 status_rx_quick_consumer_index14;
+       u16 status_rx_quick_consumer_index15;
+       u16 status_completion_producer_index;
+       u16 status_cmd_consumer_index;
+       u16 status_idx;
+       u16 status_unused;
+#elif defined(__LITTLE_ENDIAN)
+       u16 status_tx_quick_consumer_index1;
+       u16 status_tx_quick_consumer_index0;
+       u16 status_tx_quick_consumer_index3;
+       u16 status_tx_quick_consumer_index2;
+       u16 status_rx_quick_consumer_index1;
+       u16 status_rx_quick_consumer_index0;
+       u16 status_rx_quick_consumer_index3;
+       u16 status_rx_quick_consumer_index2;
+       u16 status_rx_quick_consumer_index5;
+       u16 status_rx_quick_consumer_index4;
+       u16 status_rx_quick_consumer_index7;
+       u16 status_rx_quick_consumer_index6;
+       u16 status_rx_quick_consumer_index9;
+       u16 status_rx_quick_consumer_index8;
+       u16 status_rx_quick_consumer_index11;
+       u16 status_rx_quick_consumer_index10;
+       u16 status_rx_quick_consumer_index13;
+       u16 status_rx_quick_consumer_index12;
+       u16 status_rx_quick_consumer_index15;
+       u16 status_rx_quick_consumer_index14;
+       u16 status_cmd_consumer_index;
+       u16 status_completion_producer_index;
+       u16 status_unused;
+       u16 status_idx;
+#endif
+};
+
+
+/*
+ *  statistics_block definition
+ */
+struct statistics_block {
+       u32 stat_IfHCInOctets_hi;
+       u32 stat_IfHCInOctets_lo;
+       u32 stat_IfHCInBadOctets_hi;
+       u32 stat_IfHCInBadOctets_lo;
+       u32 stat_IfHCOutOctets_hi;
+       u32 stat_IfHCOutOctets_lo;
+       u32 stat_IfHCOutBadOctets_hi;
+       u32 stat_IfHCOutBadOctets_lo;
+       u32 stat_IfHCInUcastPkts_hi;
+       u32 stat_IfHCInUcastPkts_lo;
+       u32 stat_IfHCInMulticastPkts_hi;
+       u32 stat_IfHCInMulticastPkts_lo;
+       u32 stat_IfHCInBroadcastPkts_hi;
+       u32 stat_IfHCInBroadcastPkts_lo;
+       u32 stat_IfHCOutUcastPkts_hi;
+       u32 stat_IfHCOutUcastPkts_lo;
+       u32 stat_IfHCOutMulticastPkts_hi;
+       u32 stat_IfHCOutMulticastPkts_lo;
+       u32 stat_IfHCOutBroadcastPkts_hi;
+       u32 stat_IfHCOutBroadcastPkts_lo;
+       u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
+       u32 stat_Dot3StatsCarrierSenseErrors;
+       u32 stat_Dot3StatsFCSErrors;
+       u32 stat_Dot3StatsAlignmentErrors;
+       u32 stat_Dot3StatsSingleCollisionFrames;
+       u32 stat_Dot3StatsMultipleCollisionFrames;
+       u32 stat_Dot3StatsDeferredTransmissions;
+       u32 stat_Dot3StatsExcessiveCollisions;
+       u32 stat_Dot3StatsLateCollisions;
+       u32 stat_EtherStatsCollisions;
+       u32 stat_EtherStatsFragments;
+       u32 stat_EtherStatsJabbers;
+       u32 stat_EtherStatsUndersizePkts;
+       u32 stat_EtherStatsOverrsizePkts;
+       u32 stat_EtherStatsPktsRx64Octets;
+       u32 stat_EtherStatsPktsRx65Octetsto127Octets;
+       u32 stat_EtherStatsPktsRx128Octetsto255Octets;
+       u32 stat_EtherStatsPktsRx256Octetsto511Octets;
+       u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
+       u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
+       u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
+       u32 stat_EtherStatsPktsTx64Octets;
+       u32 stat_EtherStatsPktsTx65Octetsto127Octets;
+       u32 stat_EtherStatsPktsTx128Octetsto255Octets;
+       u32 stat_EtherStatsPktsTx256Octetsto511Octets;
+       u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
+       u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
+       u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
+       u32 stat_XonPauseFramesReceived;
+       u32 stat_XoffPauseFramesReceived;
+       u32 stat_OutXonSent;
+       u32 stat_OutXoffSent;
+       u32 stat_FlowControlDone;
+       u32 stat_MacControlFramesReceived;
+       u32 stat_XoffStateEntered;
+       u32 stat_IfInFramesL2FilterDiscards;
+       u32 stat_IfInRuleCheckerDiscards;
+       u32 stat_IfInFTQDiscards;
+       u32 stat_IfInMBUFDiscards;
+       u32 stat_IfInRuleCheckerP4Hit;
+       u32 stat_CatchupInRuleCheckerDiscards;
+       u32 stat_CatchupInFTQDiscards;
+       u32 stat_CatchupInMBUFDiscards;
+       u32 stat_CatchupInRuleCheckerP4Hit;
+       u32 stat_GenStat00;
+       u32 stat_GenStat01;
+       u32 stat_GenStat02;
+       u32 stat_GenStat03;
+       u32 stat_GenStat04;
+       u32 stat_GenStat05;
+       u32 stat_GenStat06;
+       u32 stat_GenStat07;
+       u32 stat_GenStat08;
+       u32 stat_GenStat09;
+       u32 stat_GenStat10;
+       u32 stat_GenStat11;
+       u32 stat_GenStat12;
+       u32 stat_GenStat13;
+       u32 stat_GenStat14;
+       u32 stat_GenStat15;
+};
+
+
+/*
+ *  l2_fhdr definition
+ */
+struct l2_fhdr {
+#if defined(__BIG_ENDIAN)
+       u16 l2_fhdr_errors;
+       u16 l2_fhdr_status;
+#elif defined(__LITTLE_ENDIAN)
+       u16 l2_fhdr_status;
+       u16 l2_fhdr_errors;
+#endif
+               #define L2_FHDR_ERRORS_BAD_CRC          (1<<1)
+               #define L2_FHDR_ERRORS_PHY_DECODE       (1<<2)
+               #define L2_FHDR_ERRORS_ALIGNMENT        (1<<3)
+               #define L2_FHDR_ERRORS_TOO_SHORT        (1<<4)
+               #define L2_FHDR_ERRORS_GIANT_FRAME      (1<<5)
+
+               #define L2_FHDR_STATUS_RULE_CLASS       (0x7<<0)
+               #define L2_FHDR_STATUS_RULE_P2          (1<<3)
+               #define L2_FHDR_STATUS_RULE_P3          (1<<4)
+               #define L2_FHDR_STATUS_RULE_P4          (1<<5)
+               #define L2_FHDR_STATUS_L2_VLAN_TAG      (1<<6)
+               #define L2_FHDR_STATUS_L2_LLC_SNAP      (1<<7)
+               #define L2_FHDR_STATUS_RSS_HASH         (1<<8)
+               #define L2_FHDR_STATUS_IP_DATAGRAM      (1<<13)
+               #define L2_FHDR_STATUS_TCP_SEGMENT      (1<<14)
+               #define L2_FHDR_STATUS_UDP_DATAGRAM     (1<<15)
+
+       u32 l2_fhdr_hash;
+#if defined(__BIG_ENDIAN)
+       u16 l2_fhdr_pkt_len;
+       u16 l2_fhdr_vlan_tag;
+       u16 l2_fhdr_ip_xsum;
+       u16 l2_fhdr_tcp_udp_xsum;
+#elif defined(__LITTLE_ENDIAN)
+       u16 l2_fhdr_vlan_tag;
+       u16 l2_fhdr_pkt_len;
+       u16 l2_fhdr_tcp_udp_xsum;
+       u16 l2_fhdr_ip_xsum;
+#endif
+};
+
+
+/*
+ *  l2_context definition
+ */
+#define BNX2_L2CTX_TYPE                                        0x00000000
+#define BNX2_L2CTX_TYPE_SIZE_L2                                 
((0xc0/0x20)<<16)
+#define BNX2_L2CTX_TYPE_TYPE                            (0xf<<28)
+#define BNX2_L2CTX_TYPE_TYPE_EMPTY                      (0<<28)
+#define BNX2_L2CTX_TYPE_TYPE_L2                                 (1<<28)
+
+#define BNX2_L2CTX_TX_HOST_BIDX                                0x00000088
+#define BNX2_L2CTX_EST_NBD                             0x00000088
+#define BNX2_L2CTX_CMD_TYPE                            0x00000088
+#define BNX2_L2CTX_CMD_TYPE_TYPE                        (0xf<<24)
+#define BNX2_L2CTX_CMD_TYPE_TYPE_L2                     (0<<24)
+#define BNX2_L2CTX_CMD_TYPE_TYPE_TCP                    (1<<24)
+
+#define BNX2_L2CTX_TX_HOST_BSEQ                                0x00000090
+#define BNX2_L2CTX_TSCH_BSEQ                           0x00000094
+#define BNX2_L2CTX_TBDR_BSEQ                           0x00000098
+#define BNX2_L2CTX_TBDR_BOFF                           0x0000009c
+#define BNX2_L2CTX_TBDR_BIDX                           0x0000009c
+#define BNX2_L2CTX_TBDR_BHADDR_HI                      0x000000a0
+#define BNX2_L2CTX_TBDR_BHADDR_LO                      0x000000a4
+#define BNX2_L2CTX_TXP_BOFF                            0x000000a8
+#define BNX2_L2CTX_TXP_BIDX                            0x000000a8
+#define BNX2_L2CTX_TXP_BSEQ                            0x000000ac
+
+
+/*
+ *  l2_bd_chain_context definition
+ */
+#define BNX2_L2CTX_BD_PRE_READ                         0x00000000
+#define BNX2_L2CTX_CTX_SIZE                            0x00000000
+#define BNX2_L2CTX_CTX_TYPE                            0x00000000
+#define BNX2_L2CTX_CTX_TYPE_SIZE_L2                     ((0x20/20)<<16)
+#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE             (0xf<<28)
+#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED   (0<<28)
+#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE       (1<<28)
+
+#define BNX2_L2CTX_HOST_BDIDX                          0x00000004
+#define BNX2_L2CTX_HOST_BSEQ                           0x00000008
+#define BNX2_L2CTX_NX_BSEQ                             0x0000000c
+#define BNX2_L2CTX_NX_BDHADDR_HI                       0x00000010
+#define BNX2_L2CTX_NX_BDHADDR_LO                       0x00000014
+#define BNX2_L2CTX_NX_BDIDX                            0x00000018
+
+
+/*
+ *  pci_config_l definition
+ *  offset: 0000
+ */
+#define BNX2_PCICFG_MISC_CONFIG                                0x00000068
+#define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP        (1L<<2)
+#define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP     (1L<<3)
+#define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA           (1L<<5)
+#define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP    (1L<<6)
+#define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA          (1L<<7)
+#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ            (1L<<8)
+#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY            (1L<<9)
+#define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV          (0xffL<<16)
+#define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV           (0xfL<<24)
+#define BNX2_PCICFG_MISC_CONFIG_ASIC_ID                         (0xfL<<28)
+
+#define BNX2_PCICFG_MISC_STATUS                                0x0000006c
+#define BNX2_PCICFG_MISC_STATUS_INTA_VALUE              (1L<<0)
+#define BNX2_PCICFG_MISC_STATUS_32BIT_DET               (1L<<1)
+#define BNX2_PCICFG_MISC_STATUS_M66EN                   (1L<<2)
+#define BNX2_PCICFG_MISC_STATUS_PCIX_DET                (1L<<3)
+#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED              (0x3L<<4)
+#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66           (0L<<4)
+#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100          (1L<<4)
+#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133          (2L<<4)
+#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE     (3L<<4)
+
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS             0x00000070
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET      (0xfL<<0)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ        (0L<<0)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ        (1L<<0)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ        (2L<<0)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ        (3L<<0)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ        (4L<<0)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ        (5L<<0)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ        (6L<<0)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ       (7L<<0)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW  (0xfL<<0)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE     (1L<<6)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT         (1L<<7)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC     (0x7L<<8)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF       (0L<<8)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12  (1L<<8)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6   (2L<<8)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62  (4L<<8)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD    (1L<<11)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED   (0xfL<<12)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100       
(0L<<12)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80        
(1L<<12)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50        
(2L<<12)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40        
(4L<<12)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25        
(8L<<12)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP    (1L<<16)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP         (1L<<17)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18  (1L<<18)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET  (1L<<19)
+#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED     (0xfffL<<20)
+
+#define BNX2_PCICFG_REG_WINDOW_ADDRESS                 0x00000078
+#define BNX2_PCICFG_REG_WINDOW                         0x00000080
+#define BNX2_PCICFG_INT_ACK_CMD                                0x00000084
+#define BNX2_PCICFG_INT_ACK_CMD_INDEX                   (0xffffL<<0)
+#define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID             (1L<<16)
+#define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM        (1L<<17)
+#define BNX2_PCICFG_INT_ACK_CMD_MASK_INT                (1L<<18)
+
+#define BNX2_PCICFG_STATUS_BIT_SET_CMD                 0x00000088
+#define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD               0x0000008c
+#define BNX2_PCICFG_MAILBOX_QUEUE_ADDR                 0x00000090
+#define BNX2_PCICFG_MAILBOX_QUEUE_DATA                 0x00000094
+
+
+/*
+ *  pci_reg definition
+ *  offset: 0x400
+ */
+#define BNX2_PCI_GRC_WINDOW_ADDR                       0x00000400
+#define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE      (0x3ffffL<<8)
+
+#define BNX2_PCI_CONFIG_1                              0x00000404
+#define BNX2_PCI_CONFIG_1_READ_BOUNDARY                         (0x7L<<8)
+#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF             (0L<<8)
+#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16              (1L<<8)
+#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32              (2L<<8)
+#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64              (3L<<8)
+#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128             (4L<<8)
+#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256             (5L<<8)
+#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512             (6L<<8)
+#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024            (7L<<8)
+#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY                (0x7L<<11)
+#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF            (0L<<11)
+#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16             (1L<<11)
+#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32             (2L<<11)
+#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64             (3L<<11)
+#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128            (4L<<11)
+#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256            (5L<<11)
+#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512            (6L<<11)
+#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024           (7L<<11)
+
+#define BNX2_PCI_CONFIG_2                              0x00000408
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE                     (0xfL<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED            (0L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K                         (1L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K                (2L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K                (3L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K                (4L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M                  (5L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M                  (6L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M                  (7L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M                  (8L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M                         (9L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M                         (10L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M                         (11L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M                (12L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M                (13L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M                (14L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G                  (15L<<0)
+#define BNX2_PCI_CONFIG_2_BAR1_64ENA                    (1L<<4)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY                         (1L<<5)
+#define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY               (1L<<6)
+#define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE                (1L<<7)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE                  (0xffL<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED                 (0L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K               (1L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K               (2L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K               (3L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K               (4L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K              (5L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K              (6L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K              (7L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K             (8L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K             (9L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K             (10L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M               (11L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M               (12L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M               (13L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M               (14L<<8)
+#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M              (15L<<8)
+#define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT               (0x1fL<<16)
+#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT                (0x3L<<21)
+#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512            (0L<<21)
+#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K             (1L<<21)
+#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K             (2L<<21)
+#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K             (3L<<21)
+#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR             (1L<<23)
+#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT              (1L<<24)
+#define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT               (1L<<25)
+
+#define BNX2_PCI_CONFIG_3                              0x0000040c
+#define BNX2_PCI_CONFIG_3_STICKY_BYTE                   (0xffL<<0)
+#define BNX2_PCI_CONFIG_3_FORCE_PME                     (1L<<24)
+#define BNX2_PCI_CONFIG_3_PME_STATUS                    (1L<<25)
+#define BNX2_PCI_CONFIG_3_PME_ENABLE                    (1L<<26)
+#define BNX2_PCI_CONFIG_3_PM_STATE                      (0x3L<<27)
+#define BNX2_PCI_CONFIG_3_VAUX_PRESET                   (1L<<30)
+#define BNX2_PCI_CONFIG_3_PCI_POWER                     (1L<<31)
+
+#define BNX2_PCI_PM_DATA_A                             0x00000410
+#define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG                (0xffL<<0)
+#define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG                (0xffL<<8)
+#define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG                (0xffL<<16)
+#define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG                (0xffL<<24)
+
+#define BNX2_PCI_PM_DATA_B                             0x00000414
+#define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG                (0xffL<<0)
+#define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG                (0xffL<<8)
+#define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG                (0xffL<<16)
+#define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG                (0xffL<<24)
+
+#define BNX2_PCI_SWAP_DIAG0                            0x00000418
+#define BNX2_PCI_SWAP_DIAG1                            0x0000041c
+#define BNX2_PCI_EXP_ROM_ADDR                          0x00000420
+#define BNX2_PCI_EXP_ROM_ADDR_ADDRESS                   (0x3fffffL<<2)
+#define BNX2_PCI_EXP_ROM_ADDR_REQ                       (1L<<31)
+
+#define BNX2_PCI_EXP_ROM_DATA                          0x00000424
+#define BNX2_PCI_VPD_INTF                              0x00000428
+#define BNX2_PCI_VPD_INTF_INTF_REQ                      (1L<<0)
+
+#define BNX2_PCI_VPD_ADDR_FLAG                         0x0000042c
+#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                  (0x1fff<<2)
+#define BNX2_PCI_VPD_ADDR_FLAG_WR                       (1<<15)
+
+#define BNX2_PCI_VPD_DATA                              0x00000430
+#define BNX2_PCI_ID_VAL1                               0x00000434
+#define BNX2_PCI_ID_VAL1_DEVICE_ID                      (0xffffL<<0)
+#define BNX2_PCI_ID_VAL1_VENDOR_ID                      (0xffffL<<16)
+
+#define BNX2_PCI_ID_VAL2                               0x00000438
+#define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID            (0xffffL<<0)
+#define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID                   (0xffffL<<16)
+
+#define BNX2_PCI_ID_VAL3                               0x0000043c
+#define BNX2_PCI_ID_VAL3_CLASS_CODE                     (0xffffffL<<0)
+#define BNX2_PCI_ID_VAL3_REVISION_ID                    (0xffL<<24)
+
+#define BNX2_PCI_ID_VAL4                               0x00000440
+#define BNX2_PCI_ID_VAL4_CAP_ENA                        (0xfL<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_0                      (0L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_1                      (1L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_2                      (2L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_3                      (3L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_4                      (4L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_5                      (5L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_6                      (6L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_7                      (7L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_8                      (8L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_9                      (9L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_10                     (10L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_11                     (11L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_12                     (12L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_13                     (13L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_14                     (14L<<0)
+#define BNX2_PCI_ID_VAL4_CAP_ENA_15                     (15L<<0)
+#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG                   (0x3L<<6)
+#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0                         (0L<<6)
+#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1                         (1L<<6)
+#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2                         (2L<<6)
+#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3                         (3L<<6)
+#define BNX2_PCI_ID_VAL4_MSI_LIMIT                      (0x7L<<9)
+#define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE                  (0x7L<<12)
+#define BNX2_PCI_ID_VAL4_MSI_ENABLE                     (1L<<15)
+#define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE               (1L<<16)
+#define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE              (1L<<17)
+#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE              (0x3L<<21)
+#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE                         (0x7L<<23)
+#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE            (0x7L<<26)
+
+#define BNX2_PCI_ID_VAL5                               0x00000444
+#define BNX2_PCI_ID_VAL5_D1_SUPPORT                     (1L<<0)
+#define BNX2_PCI_ID_VAL5_D2_SUPPORT                     (1L<<1)
+#define BNX2_PCI_ID_VAL5_PME_IN_D0                      (1L<<2)
+#define BNX2_PCI_ID_VAL5_PME_IN_D1                      (1L<<3)
+#define BNX2_PCI_ID_VAL5_PME_IN_D2                      (1L<<4)
+#define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT                  (1L<<5)
+
+#define BNX2_PCI_PCIX_EXTENDED_STATUS                  0x00000448
+#define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP          (1L<<8)
+#define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST        (1L<<9)
+#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS      (0xfL<<16)
+#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX        (0xffL<<24)
+
+#define BNX2_PCI_ID_VAL6                               0x0000044c
+#define BNX2_PCI_ID_VAL6_MAX_LAT                        (0xffL<<0)
+#define BNX2_PCI_ID_VAL6_MIN_GNT                        (0xffL<<8)
+#define BNX2_PCI_ID_VAL6_BIST                           (0xffL<<16)
+
+#define BNX2_PCI_MSI_DATA                              0x00000450
+#define BNX2_PCI_MSI_DATA_PCI_MSI_DATA                  (0xffffL<<0)
+
+#define BNX2_PCI_MSI_ADDR_H                            0x00000454
+#define BNX2_PCI_MSI_ADDR_L                            0x00000458
+
+
+/*
+ *  misc_reg definition
+ *  offset: 0x800
+ */
+#define BNX2_MISC_COMMAND                              0x00000800
+#define BNX2_MISC_COMMAND_ENABLE_ALL                    (1L<<0)
+#define BNX2_MISC_COMMAND_DISABLE_ALL                   (1L<<1)
+#define BNX2_MISC_COMMAND_CORE_RESET                    (1L<<4)
+#define BNX2_MISC_COMMAND_HARD_RESET                    (1L<<5)
+#define BNX2_MISC_COMMAND_PAR_ERROR                     (1L<<8)
+#define BNX2_MISC_COMMAND_PAR_ERR_RAM                   (0x7fL<<16)
+
+#define BNX2_MISC_CFG                                  0x00000804
+#define BNX2_MISC_CFG_PCI_GRC_TMOUT                     (1L<<0)
+#define BNX2_MISC_CFG_NVM_WR_EN                                 (0x3L<<1)
+#define BNX2_MISC_CFG_NVM_WR_EN_PROTECT                         (0L<<1)
+#define BNX2_MISC_CFG_NVM_WR_EN_PCI                     (1L<<1)
+#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW                   (2L<<1)
+#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2                  (3L<<1)
+#define BNX2_MISC_CFG_BIST_EN                           (1L<<3)
+#define BNX2_MISC_CFG_CK25_OUT_ALT_SRC                  (1L<<4)
+#define BNX2_MISC_CFG_BYPASS_BSCAN                      (1L<<5)
+#define BNX2_MISC_CFG_BYPASS_EJTAG                      (1L<<6)
+#define BNX2_MISC_CFG_CLK_CTL_OVERRIDE                  (1L<<7)
+#define BNX2_MISC_CFG_LEDMODE                           (0x3L<<8)
+#define BNX2_MISC_CFG_LEDMODE_MAC                       (0L<<8)
+#define BNX2_MISC_CFG_LEDMODE_GPHY1                     (1L<<8)
+#define BNX2_MISC_CFG_LEDMODE_GPHY2                     (2L<<8)
+
+#define BNX2_MISC_ID                                   0x00000808
+#define BNX2_MISC_ID_BOND_ID                            (0xfL<<0)
+#define BNX2_MISC_ID_CHIP_METAL                                 (0xffL<<4)
+#define BNX2_MISC_ID_CHIP_REV                           (0xfL<<12)
+#define BNX2_MISC_ID_CHIP_NUM                           (0xffffL<<16)
+
+#define BNX2_MISC_ENABLE_STATUS_BITS                   0x0000080c
+#define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE        (1L<<0)
+#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE  (1L<<1)
+#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE         (1L<<2)
+#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE        (1L<<3)
+#define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE      (1L<<4)
+#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE  (1L<<5)
+#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE        (1L<<6)
+#define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE         (1L<<7)
+#define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE        (1L<<8)
+#define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE        (1L<<9)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE       (1L<<10)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE   (1L<<11)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE     (1L<<12)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE   (1L<<13)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE        (1L<<14)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE      (1L<<15)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE         (1L<<16)
+#define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE      (1L<<17)
+#define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE  (1L<<18)
+#define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE       (1L<<19)
+#define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE       (1L<<20)
+#define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE     (1L<<21)
+#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE       (1L<<22)
+#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE       (1L<<23)
+#define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE      (1L<<24)
+#define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE       (1L<<25)
+#define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE  (1L<<26)
+#define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE                 (1L<<27)
+
+#define BNX2_MISC_ENABLE_SET_BITS                      0x00000810
+#define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE   (1L<<0)
+#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE     (1L<<1)
+#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE    (1L<<2)
+#define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE   (1L<<3)
+#define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE                 (1L<<4)
+#define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE     (1L<<5)
+#define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE   (1L<<6)
+#define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE    (1L<<7)
+#define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE   (1L<<8)
+#define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE           (1L<<9)
+#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE  (1L<<10)
+#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE      (1L<<11)
+#define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE        (1L<<12)
+#define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE      (1L<<13)
+#define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE   (1L<<14)
+#define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE                 (1L<<15)
+#define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE    (1L<<16)
+#define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE                 (1L<<17)
+#define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE     (1L<<18)
+#define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE  (1L<<19)
+#define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE  (1L<<20)
+#define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE        (1L<<21)
+#define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE  (1L<<22)
+#define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE  (1L<<23)
+#define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE         (1L<<24)
+#define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE          (1L<<25)
+#define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE     (1L<<26)
+#define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE            (1L<<27)
+
+#define BNX2_MISC_ENABLE_CLR_BITS                      0x00000814
+#define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE   (1L<<0)
+#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE     (1L<<1)
+#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE    (1L<<2)
+#define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE   (1L<<3)
+#define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE                 (1L<<4)
+#define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE     (1L<<5)
+#define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE   (1L<<6)
+#define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE    (1L<<7)
+#define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE   (1L<<8)
+#define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE           (1L<<9)
+#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE  (1L<<10)
+#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE      (1L<<11)
+#define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE        (1L<<12)
+#define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE      (1L<<13)
+#define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE   (1L<<14)
+#define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE                 (1L<<15)
+#define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE    (1L<<16)
+#define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE                 (1L<<17)
+#define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE     (1L<<18)
+#define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE  (1L<<19)
+#define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE  (1L<<20)
+#define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE        (1L<<21)
+#define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE  (1L<<22)
+#define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE  (1L<<23)
+#define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE         (1L<<24)
+#define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE          (1L<<25)
+#define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE     (1L<<26)
+#define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE            (1L<<27)
+
+#define BNX2_MISC_CLOCK_CONTROL_BITS                   0x00000818
+#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET    (0xfL<<0)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ      (0L<<0)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ      (1L<<0)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ      (2L<<0)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ      (3L<<0)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ      (4L<<0)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ      (5L<<0)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ      (6L<<0)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ     (7L<<0)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW        (0xfL<<0)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE   (1L<<6)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT       (1L<<7)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC   (0x7L<<8)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF     (0L<<8)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12        (1L<<8)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6         (2L<<8)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62        (4L<<8)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD          (1L<<11)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED         (0xfL<<12)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100     (0L<<12)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80      (1L<<12)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50      (2L<<12)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40      (4L<<12)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25      (8L<<12)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP  (1L<<16)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP       (1L<<17)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18        (1L<<18)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET        (1L<<19)
+#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED           (0xfffL<<20)
+
+#define BNX2_MISC_GPIO                                 0x0000081c
+#define BNX2_MISC_GPIO_VALUE                            (0xffL<<0)
+#define BNX2_MISC_GPIO_SET                              (0xffL<<8)
+#define BNX2_MISC_GPIO_CLR                              (0xffL<<16)
+#define BNX2_MISC_GPIO_FLOAT                            (0xffL<<24)
+
+#define BNX2_MISC_GPIO_INT                             0x00000820
+#define BNX2_MISC_GPIO_INT_INT_STATE                    (0xfL<<0)
+#define BNX2_MISC_GPIO_INT_OLD_VALUE                    (0xfL<<8)
+#define BNX2_MISC_GPIO_INT_OLD_SET                      (0xfL<<16)
+#define BNX2_MISC_GPIO_INT_OLD_CLR                      (0xfL<<24)
+
+#define BNX2_MISC_CONFIG_LFSR                          0x00000824
+#define BNX2_MISC_CONFIG_LFSR_DIV                       (0xffffL<<0)
+
+#define BNX2_MISC_LFSR_MASK_BITS                       0x00000828
+#define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
+#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE      (1L<<1)
+#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
+#define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
+#define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE          (1L<<4)
+#define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE      (1L<<5)
+#define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
+#define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
+#define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
+#define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE            (1L<<9)
+#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
+#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
+#define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE                 (1L<<12)
+#define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE       (1L<<13)
+#define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
+#define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE          (1L<<15)
+#define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
+#define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE          (1L<<17)
+#define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE      (1L<<18)
+#define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE   (1L<<19)
+#define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
+#define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE                 (1L<<21)
+#define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
+#define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
+#define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
+#define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE           (1L<<25)
+#define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE      (1L<<26)
+#define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE             (1L<<27)
+
+#define BNX2_MISC_ARB_REQ0                             0x0000082c
+#define BNX2_MISC_ARB_REQ1                             0x00000830
+#define BNX2_MISC_ARB_REQ2                             0x00000834
+#define BNX2_MISC_ARB_REQ3                             0x00000838
+#define BNX2_MISC_ARB_REQ4                             0x0000083c
+#define BNX2_MISC_ARB_FREE0                            0x00000840
+#define BNX2_MISC_ARB_FREE1                            0x00000844
+#define BNX2_MISC_ARB_FREE2                            0x00000848
+#define BNX2_MISC_ARB_FREE3                            0x0000084c
+#define BNX2_MISC_ARB_FREE4                            0x00000850
+#define BNX2_MISC_ARB_REQ_STATUS0                      0x00000854
+#define BNX2_MISC_ARB_REQ_STATUS1                      0x00000858
+#define BNX2_MISC_ARB_REQ_STATUS2                      0x0000085c
+#define BNX2_MISC_ARB_REQ_STATUS3                      0x00000860
+#define BNX2_MISC_ARB_REQ_STATUS4                      0x00000864
+#define BNX2_MISC_ARB_GNT0                             0x00000868
+#define BNX2_MISC_ARB_GNT0_0                            (0x7L<<0)
+#define BNX2_MISC_ARB_GNT0_1                            (0x7L<<4)
+#define BNX2_MISC_ARB_GNT0_2                            (0x7L<<8)
+#define BNX2_MISC_ARB_GNT0_3                            (0x7L<<12)
+#define BNX2_MISC_ARB_GNT0_4                            (0x7L<<16)
+#define BNX2_MISC_ARB_GNT0_5                            (0x7L<<20)
+#define BNX2_MISC_ARB_GNT0_6                            (0x7L<<24)
+#define BNX2_MISC_ARB_GNT0_7                            (0x7L<<28)
+
+#define BNX2_MISC_ARB_GNT1                             0x0000086c
+#define BNX2_MISC_ARB_GNT1_8                            (0x7L<<0)
+#define BNX2_MISC_ARB_GNT1_9                            (0x7L<<4)
+#define BNX2_MISC_ARB_GNT1_10                           (0x7L<<8)
+#define BNX2_MISC_ARB_GNT1_11                           (0x7L<<12)
+#define BNX2_MISC_ARB_GNT1_12                           (0x7L<<16)
+#define BNX2_MISC_ARB_GNT1_13                           (0x7L<<20)
+#define BNX2_MISC_ARB_GNT1_14                           (0x7L<<24)
+#define BNX2_MISC_ARB_GNT1_15                           (0x7L<<28)
+
+#define BNX2_MISC_ARB_GNT2                             0x00000870
+#define BNX2_MISC_ARB_GNT2_16                           (0x7L<<0)
+#define BNX2_MISC_ARB_GNT2_17                           (0x7L<<4)
+#define BNX2_MISC_ARB_GNT2_18                           (0x7L<<8)
+#define BNX2_MISC_ARB_GNT2_19                           (0x7L<<12)
+#define BNX2_MISC_ARB_GNT2_20                           (0x7L<<16)
+#define BNX2_MISC_ARB_GNT2_21                           (0x7L<<20)
+#define BNX2_MISC_ARB_GNT2_22                           (0x7L<<24)
+#define BNX2_MISC_ARB_GNT2_23                           (0x7L<<28)
+
+#define BNX2_MISC_ARB_GNT3                             0x00000874
+#define BNX2_MISC_ARB_GNT3_24                           (0x7L<<0)
+#define BNX2_MISC_ARB_GNT3_25                           (0x7L<<4)
+#define BNX2_MISC_ARB_GNT3_26                           (0x7L<<8)
+#define BNX2_MISC_ARB_GNT3_27                           (0x7L<<12)
+#define BNX2_MISC_ARB_GNT3_28                           (0x7L<<16)
+#define BNX2_MISC_ARB_GNT3_29                           (0x7L<<20)
+#define BNX2_MISC_ARB_GNT3_30                           (0x7L<<24)
+#define BNX2_MISC_ARB_GNT3_31                           (0x7L<<28)
+
+#define BNX2_MISC_PRBS_CONTROL                         0x00000878
+#define BNX2_MISC_PRBS_CONTROL_EN                       (1L<<0)
+#define BNX2_MISC_PRBS_CONTROL_RSTB                     (1L<<1)
+#define BNX2_MISC_PRBS_CONTROL_INV                      (1L<<2)
+#define BNX2_MISC_PRBS_CONTROL_ERR_CLR                  (1L<<3)
+#define BNX2_MISC_PRBS_CONTROL_ORDER                    (0x3L<<4)
+#define BNX2_MISC_PRBS_CONTROL_ORDER_7TH                (0L<<4)
+#define BNX2_MISC_PRBS_CONTROL_ORDER_15TH               (1L<<4)
+#define BNX2_MISC_PRBS_CONTROL_ORDER_23RD               (2L<<4)
+#define BNX2_MISC_PRBS_CONTROL_ORDER_31ST               (3L<<4)
+
+#define BNX2_MISC_PRBS_STATUS                          0x0000087c
+#define BNX2_MISC_PRBS_STATUS_LOCK                      (1L<<0)
+#define BNX2_MISC_PRBS_STATUS_STKY                      (1L<<1)
+#define BNX2_MISC_PRBS_STATUS_ERRORS                    (0x3fffL<<2)
+#define BNX2_MISC_PRBS_STATUS_STATE                     (0xfL<<16)
+
+#define BNX2_MISC_SM_ASF_CONTROL                       0x00000880
+#define BNX2_MISC_SM_ASF_CONTROL_ASF_RST                (1L<<0)
+#define BNX2_MISC_SM_ASF_CONTROL_TSC_EN                         (1L<<1)
+#define BNX2_MISC_SM_ASF_CONTROL_WG_TO                  (1L<<2)
+#define BNX2_MISC_SM_ASF_CONTROL_HB_TO                  (1L<<3)
+#define BNX2_MISC_SM_ASF_CONTROL_PA_TO                  (1L<<4)
+#define BNX2_MISC_SM_ASF_CONTROL_PL_TO                  (1L<<5)
+#define BNX2_MISC_SM_ASF_CONTROL_RT_TO                  (1L<<6)
+#define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT              (1L<<7)
+#define BNX2_MISC_SM_ASF_CONTROL_RES                    (0xfL<<8)
+#define BNX2_MISC_SM_ASF_CONTROL_SMB_EN                         (1L<<12)
+#define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN              (1L<<13)
+#define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT       (1L<<14)
+#define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD           (1L<<15)
+#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1          (0x3fL<<16)
+#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2          (0x3fL<<24)
+#define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0      (1L<<30)
+#define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN                 (1L<<31)
+
+#define BNX2_MISC_SMB_IN                               0x00000884
+#define BNX2_MISC_SMB_IN_DAT_IN                                 (0xffL<<0)
+#define BNX2_MISC_SMB_IN_RDY                            (1L<<8)
+#define BNX2_MISC_SMB_IN_DONE                           (1L<<9)
+#define BNX2_MISC_SMB_IN_FIRSTBYTE                      (1L<<10)
+#define BNX2_MISC_SMB_IN_STATUS                                 (0x7L<<11)
+#define BNX2_MISC_SMB_IN_STATUS_OK                      (0x0L<<11)
+#define BNX2_MISC_SMB_IN_STATUS_PEC                     (0x1L<<11)
+#define BNX2_MISC_SMB_IN_STATUS_OFLOW                   (0x2L<<11)
+#define BNX2_MISC_SMB_IN_STATUS_STOP                    (0x3L<<11)
+#define BNX2_MISC_SMB_IN_STATUS_TIMEOUT                         (0x4L<<11)
+
+#define BNX2_MISC_SMB_OUT                              0x00000888
+#define BNX2_MISC_SMB_OUT_DAT_OUT                       (0xffL<<0)
+#define BNX2_MISC_SMB_OUT_RDY                           (1L<<8)
+#define BNX2_MISC_SMB_OUT_START                                 (1L<<9)
+#define BNX2_MISC_SMB_OUT_LAST                          (1L<<10)
+#define BNX2_MISC_SMB_OUT_ACC_TYPE                      (1L<<11)
+#define BNX2_MISC_SMB_OUT_ENB_PEC                       (1L<<12)
+#define BNX2_MISC_SMB_OUT_GET_RX_LEN                    (1L<<13)
+#define BNX2_MISC_SMB_OUT_SMB_READ_LEN                  (0x3fL<<14)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS                (0xfL<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK             (0L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK     (1L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK       (9L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW          (2L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP           (3L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT        (4L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST     (5L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST       (0xdL<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK                 (0x6L<<20)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE             (1L<<24)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN                (1L<<25)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN                (1L<<26)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN                (1L<<27)
+#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN                (1L<<28)
+
+#define BNX2_MISC_SMB_WATCHDOG                         0x0000088c
+#define BNX2_MISC_SMB_WATCHDOG_WATCHDOG                         (0xffffL<<0)
+
+#define BNX2_MISC_SMB_HEARTBEAT                                0x00000890
+#define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT               (0xffffL<<0)
+
+#define BNX2_MISC_SMB_POLL_ASF                         0x00000894
+#define BNX2_MISC_SMB_POLL_ASF_POLL_ASF                         (0xffffL<<0)
+
+#define BNX2_MISC_SMB_POLL_LEGACY                      0x00000898
+#define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY           (0xffffL<<0)
+
+#define BNX2_MISC_SMB_RETRAN                           0x0000089c
+#define BNX2_MISC_SMB_RETRAN_RETRAN                     (0xffL<<0)
+
+#define BNX2_MISC_SMB_TIMESTAMP                                0x000008a0
+#define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP               (0xffffffffL<<0)
+
+#define BNX2_MISC_PERR_ENA0                            0x000008a4
+#define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC               (1L<<0)
+#define BNX2_MISC_PERR_ENA0_COM_MISC_REGF               (1L<<1)
+#define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD              (1L<<2)
+#define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC                (1L<<3)
+#define BNX2_MISC_PERR_ENA0_CP_MISC_REGF                (1L<<4)
+#define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD               (1L<<5)
+#define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM                (1L<<6)
+#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0              (1L<<7)
+#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1              (1L<<8)
+#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2              (1L<<9)
+#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3              (1L<<10)
+#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4              (1L<<11)
+#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5              (1L<<12)
+#define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL              (1L<<13)
+#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0               (1L<<14)
+#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1               (1L<<15)
+#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2               (1L<<16)
+#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3               (1L<<17)
+#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4               (1L<<18)
+#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0               (1L<<19)
+#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1               (1L<<20)
+#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2               (1L<<21)
+#define BNX2_MISC_PERR_ENA0_HC_MISC_DMA                         (1L<<22)
+#define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF               (1L<<23)
+#define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD              (1L<<24)
+#define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX                         (1L<<25)
+#define BNX2_MISC_PERR_ENA0_RBDC_MISC                   (1L<<26)
+#define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB                (1L<<27)
+#define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR               (1L<<28)
+#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC                (1L<<29)
+#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM                (1L<<30)
+#define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS           (1L<<31)
+
+#define BNX2_MISC_PERR_ENA1                            0x000008a8
+#define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS           (1L<<0)
+#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM            (1L<<1)
+#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM            (1L<<2)
+#define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC               (1L<<3)
+#define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF               (1L<<4)
+#define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD              (1L<<5)
+#define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC              (1L<<6)
+#define BNX2_MISC_PERR_ENA1_TBDC_MISC                   (1L<<7)
+#define BNX2_MISC_PERR_ENA1_TDMA_MISC                   (1L<<8)
+#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0              (1L<<9)
+#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1              (1L<<10)
+#define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF              (1L<<11)
+#define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD             (1L<<12)
+#define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB               (1L<<13)
+#define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR                (1L<<14)
+#define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC               (1L<<15)
+#define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF               (1L<<16)
+#define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD              (1L<<17)
+#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX              (1L<<18)
+#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX              (1L<<19)
+#define BNX2_MISC_PERR_ENA1_UMP_MISC_RX                         (1L<<20)
+#define BNX2_MISC_PERR_ENA1_UMP_MISC_TX                         (1L<<21)
+#define BNX2_MISC_PERR_ENA1_RDMAQ_MISC                  (1L<<22)
+#define BNX2_MISC_PERR_ENA1_CSQ_MISC                    (1L<<23)
+#define BNX2_MISC_PERR_ENA1_CPQ_MISC                    (1L<<24)
+#define BNX2_MISC_PERR_ENA1_MCPQ_MISC                   (1L<<25)
+#define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC                         (1L<<26)
+#define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC                         (1L<<27)
+#define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC                         (1L<<28)
+#define BNX2_MISC_PERR_ENA1_RXPQ_MISC                   (1L<<29)
+#define BNX2_MISC_PERR_ENA1_RXPCQ_MISC                  (1L<<30)
+#define BNX2_MISC_PERR_ENA1_RLUPQ_MISC                  (1L<<31)
+
+#define BNX2_MISC_PERR_ENA2                            0x000008ac
+#define BNX2_MISC_PERR_ENA2_COMQ_MISC                   (1L<<0)
+#define BNX2_MISC_PERR_ENA2_COMXQ_MISC                  (1L<<1)
+#define BNX2_MISC_PERR_ENA2_COMTQ_MISC                  (1L<<2)
+#define BNX2_MISC_PERR_ENA2_TSCHQ_MISC                  (1L<<3)
+#define BNX2_MISC_PERR_ENA2_TBDRQ_MISC                  (1L<<4)
+#define BNX2_MISC_PERR_ENA2_TXPQ_MISC                   (1L<<5)
+#define BNX2_MISC_PERR_ENA2_TDMAQ_MISC                  (1L<<6)
+#define BNX2_MISC_PERR_ENA2_TPATQ_MISC                  (1L<<7)
+#define BNX2_MISC_PERR_ENA2_TASQ_MISC                   (1L<<8)
+
+#define BNX2_MISC_DEBUG_VECTOR_SEL                     0x000008b0
+#define BNX2_MISC_DEBUG_VECTOR_SEL_0                    (0xfffL<<0)
+#define BNX2_MISC_DEBUG_VECTOR_SEL_1                    (0xfffL<<12)
+
+#define BNX2_MISC_VREG_CONTROL                         0x000008b4
+#define BNX2_MISC_VREG_CONTROL_1_2                      (0xfL<<0)
+#define BNX2_MISC_VREG_CONTROL_2_5                      (0xfL<<4)
+
+#define BNX2_MISC_FINAL_CLK_CTL_VAL                    0x000008b8
+#define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL      (0x3ffffffL<<6)
+
+#define BNX2_MISC_UNUSED0                              0x000008bc
+
+
+/*
+ *  nvm_reg definition
+ *  offset: 0x6400
+ */
+#define BNX2_NVM_COMMAND                               0x00006400
+#define BNX2_NVM_COMMAND_RST                            (1L<<0)
+#define BNX2_NVM_COMMAND_DONE                           (1L<<3)
+#define BNX2_NVM_COMMAND_DOIT                           (1L<<4)
+#define BNX2_NVM_COMMAND_WR                             (1L<<5)
+#define BNX2_NVM_COMMAND_ERASE                          (1L<<6)
+#define BNX2_NVM_COMMAND_FIRST                          (1L<<7)
+#define BNX2_NVM_COMMAND_LAST                           (1L<<8)
+#define BNX2_NVM_COMMAND_WREN                           (1L<<16)
+#define BNX2_NVM_COMMAND_WRDI                           (1L<<17)
+#define BNX2_NVM_COMMAND_EWSR                           (1L<<18)
+#define BNX2_NVM_COMMAND_WRSR                           (1L<<19)
+
+#define BNX2_NVM_STATUS                                        0x00006404
+#define BNX2_NVM_STATUS_PI_FSM_STATE                    (0xfL<<0)
+#define BNX2_NVM_STATUS_EE_FSM_STATE                    (0xfL<<4)
+#define BNX2_NVM_STATUS_EQ_FSM_STATE                    (0xfL<<8)
+
+#define BNX2_NVM_WRITE                                 0x00006408
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE                  (0xffffffffL<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG                 (0L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK            (1L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA           (2L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK             (4L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B             (8L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO               (16L<<0)
+#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI               (32L<<0)
+
+#define BNX2_NVM_ADDR                                  0x0000640c
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE                    (0xffffffL<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG           (0L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK              (1L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA             (2L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK               (4L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B               (8L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO                         (16L<<0)
+#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI                         (32L<<0)
+
+#define BNX2_NVM_READ                                  0x00006410
+#define BNX2_NVM_READ_NVM_READ_VALUE                    (0xffffffffL<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG           (0L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_EECLK              (1L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA             (2L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_SCLK               (4L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B               (8L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_SO                         (16L<<0)
+#define BNX2_NVM_READ_NVM_READ_VALUE_SI                         (32L<<0)
+
+#define BNX2_NVM_CFG1                                  0x00006414
+#define BNX2_NVM_CFG1_FLASH_MODE                        (1L<<0)
+#define BNX2_NVM_CFG1_BUFFER_MODE                       (1L<<1)
+#define BNX2_NVM_CFG1_PASS_MODE                                 (1L<<2)
+#define BNX2_NVM_CFG1_BITBANG_MODE                      (1L<<3)
+#define BNX2_NVM_CFG1_STATUS_BIT                        (0x7L<<4)
+#define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY              (0L<<4)
+#define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY             (7L<<4)
+#define BNX2_NVM_CFG1_SPI_CLK_DIV                       (0xfL<<7)
+#define BNX2_NVM_CFG1_SEE_CLK_DIV                       (0x7ffL<<11)
+#define BNX2_NVM_CFG1_PROTECT_MODE                      (1L<<24)
+#define BNX2_NVM_CFG1_FLASH_SIZE                        (1L<<25)
+#define BNX2_NVM_CFG1_COMPAT_BYPASSS                    (1L<<31)
+
+#define BNX2_NVM_CFG2                                  0x00006418
+#define BNX2_NVM_CFG2_ERASE_CMD                                 (0xffL<<0)
+#define BNX2_NVM_CFG2_DUMMY                             (0xffL<<8)
+#define BNX2_NVM_CFG2_STATUS_CMD                        (0xffL<<16)
+
+#define BNX2_NVM_CFG3                                  0x0000641c
+#define BNX2_NVM_CFG3_BUFFER_RD_CMD                     (0xffL<<0)
+#define BNX2_NVM_CFG3_WRITE_CMD                                 (0xffL<<8)
+#define BNX2_NVM_CFG3_BUFFER_WRITE_CMD                  (0xffL<<16)
+#define BNX2_NVM_CFG3_READ_CMD                          (0xffL<<24)
+
+#define BNX2_NVM_SW_ARB                                        0x00006420
+#define BNX2_NVM_SW_ARB_ARB_REQ_SET0                    (1L<<0)
+#define BNX2_NVM_SW_ARB_ARB_REQ_SET1                    (1L<<1)
+#define BNX2_NVM_SW_ARB_ARB_REQ_SET2                    (1L<<2)
+#define BNX2_NVM_SW_ARB_ARB_REQ_SET3                    (1L<<3)
+#define BNX2_NVM_SW_ARB_ARB_REQ_CLR0                    (1L<<4)
+#define BNX2_NVM_SW_ARB_ARB_REQ_CLR1                    (1L<<5)
+#define BNX2_NVM_SW_ARB_ARB_REQ_CLR2                    (1L<<6)
+#define BNX2_NVM_SW_ARB_ARB_REQ_CLR3                    (1L<<7)
+#define BNX2_NVM_SW_ARB_ARB_ARB0                        (1L<<8)
+#define BNX2_NVM_SW_ARB_ARB_ARB1                        (1L<<9)
+#define BNX2_NVM_SW_ARB_ARB_ARB2                        (1L<<10)
+#define BNX2_NVM_SW_ARB_ARB_ARB3                        (1L<<11)
+#define BNX2_NVM_SW_ARB_REQ0                            (1L<<12)
+#define BNX2_NVM_SW_ARB_REQ1                            (1L<<13)
+#define BNX2_NVM_SW_ARB_REQ2                            (1L<<14)
+#define BNX2_NVM_SW_ARB_REQ3                            (1L<<15)
+
+#define BNX2_NVM_ACCESS_ENABLE                         0x00006424
+#define BNX2_NVM_ACCESS_ENABLE_EN                       (1L<<0)
+#define BNX2_NVM_ACCESS_ENABLE_WR_EN                    (1L<<1)
+
+#define BNX2_NVM_WRITE1                                        0x00006428
+#define BNX2_NVM_WRITE1_WREN_CMD                        (0xffL<<0)
+#define BNX2_NVM_WRITE1_WRDI_CMD                        (0xffL<<8)
+#define BNX2_NVM_WRITE1_SR_DATA                                 (0xffL<<16)
+
+
+
+/*
+ *  dma_reg definition
+ *  offset: 0xc00
+ */
+#define BNX2_DMA_COMMAND                               0x00000c00
+#define BNX2_DMA_COMMAND_ENABLE                                 (1L<<0)
+
+#define BNX2_DMA_STATUS                                        0x00000c04
+#define BNX2_DMA_STATUS_PAR_ERROR_STATE                         (1L<<0)
+#define BNX2_DMA_STATUS_READ_TRANSFERS_STAT             (1L<<16)
+#define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT        (1L<<17)
+#define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT                 (1L<<18)
+#define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT    (1L<<19)
+#define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT  (1L<<20)
+#define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT            (1L<<21)
+#define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT       (1L<<22)
+#define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT        (1L<<23)
+#define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT   (1L<<24)
+#define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT         (1L<<25)
+
+#define BNX2_DMA_CONFIG                                        0x00000c08
+#define BNX2_DMA_CONFIG_DATA_BYTE_SWAP                  (1L<<0)
+#define BNX2_DMA_CONFIG_DATA_WORD_SWAP                  (1L<<1)
+#define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP                  (1L<<4)
+#define BNX2_DMA_CONFIG_CNTL_WORD_SWAP                  (1L<<5)
+#define BNX2_DMA_CONFIG_ONE_DMA                                 (1L<<6)
+#define BNX2_DMA_CONFIG_CNTL_TWO_DMA                    (1L<<7)
+#define BNX2_DMA_CONFIG_CNTL_FPGA_MODE                  (1L<<8)
+#define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA              (1L<<10)
+#define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY               (1L<<11)
+#define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE                (0xfL<<12)
+#define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE                (0xfL<<16)
+#define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS                (0x7L<<20)
+#define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP                (1L<<23)
+#define BNX2_DMA_CONFIG_BIG_SIZE                        (0xfL<<24)
+#define BNX2_DMA_CONFIG_BIG_SIZE_NONE                   (0x0L<<24)
+#define BNX2_DMA_CONFIG_BIG_SIZE_64                     (0x1L<<24)
+#define BNX2_DMA_CONFIG_BIG_SIZE_128                    (0x2L<<24)
+#define BNX2_DMA_CONFIG_BIG_SIZE_256                    (0x4L<<24)
+#define BNX2_DMA_CONFIG_BIG_SIZE_512                    (0x8L<<24)
+
+#define BNX2_DMA_BLACKOUT                              0x00000c0c
+#define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT             (0xffL<<0)
+#define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT                 (0xffL<<8)
+#define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT             (0xffL<<16)
+
+#define BNX2_DMA_RCHAN_STAT                            0x00000c30
+#define BNX2_DMA_RCHAN_STAT_COMP_CODE_0                         (0x7L<<0)
+#define BNX2_DMA_RCHAN_STAT_PAR_ERR_0                   (1L<<3)
+#define BNX2_DMA_RCHAN_STAT_COMP_CODE_1                         (0x7L<<4)
+#define BNX2_DMA_RCHAN_STAT_PAR_ERR_1                   (1L<<7)
+#define BNX2_DMA_RCHAN_STAT_COMP_CODE_2                         (0x7L<<8)
+#define BNX2_DMA_RCHAN_STAT_PAR_ERR_2                   (1L<<11)
+#define BNX2_DMA_RCHAN_STAT_COMP_CODE_3                         (0x7L<<12)
+#define BNX2_DMA_RCHAN_STAT_PAR_ERR_3                   (1L<<15)
+#define BNX2_DMA_RCHAN_STAT_COMP_CODE_4                         (0x7L<<16)
+#define BNX2_DMA_RCHAN_STAT_PAR_ERR_4                   (1L<<19)
+#define BNX2_DMA_RCHAN_STAT_COMP_CODE_5                         (0x7L<<20)
+#define BNX2_DMA_RCHAN_STAT_PAR_ERR_5                   (1L<<23)
+#define BNX2_DMA_RCHAN_STAT_COMP_CODE_6                         (0x7L<<24)
+#define BNX2_DMA_RCHAN_STAT_PAR_ERR_6                   (1L<<27)
+#define BNX2_DMA_RCHAN_STAT_COMP_CODE_7                         (0x7L<<28)
+#define BNX2_DMA_RCHAN_STAT_PAR_ERR_7                   (1L<<31)
+
+#define BNX2_DMA_WCHAN_STAT                            0x00000c34
+#define BNX2_DMA_WCHAN_STAT_COMP_CODE_0                         (0x7L<<0)
+#define BNX2_DMA_WCHAN_STAT_PAR_ERR_0                   (1L<<3)
+#define BNX2_DMA_WCHAN_STAT_COMP_CODE_1                         (0x7L<<4)
+#define BNX2_DMA_WCHAN_STAT_PAR_ERR_1                   (1L<<7)
+#define BNX2_DMA_WCHAN_STAT_COMP_CODE_2                         (0x7L<<8)
+#define BNX2_DMA_WCHAN_STAT_PAR_ERR_2                   (1L<<11)
+#define BNX2_DMA_WCHAN_STAT_COMP_CODE_3                         (0x7L<<12)
+#define BNX2_DMA_WCHAN_STAT_PAR_ERR_3                   (1L<<15)
+#define BNX2_DMA_WCHAN_STAT_COMP_CODE_4                         (0x7L<<16)
+#define BNX2_DMA_WCHAN_STAT_PAR_ERR_4                   (1L<<19)
+#define BNX2_DMA_WCHAN_STAT_COMP_CODE_5                         (0x7L<<20)
+#define BNX2_DMA_WCHAN_STAT_PAR_ERR_5                   (1L<<23)
+#define BNX2_DMA_WCHAN_STAT_COMP_CODE_6                         (0x7L<<24)
+#define BNX2_DMA_WCHAN_STAT_PAR_ERR_6                   (1L<<27)
+#define BNX2_DMA_WCHAN_STAT_COMP_CODE_7                         (0x7L<<28)
+#define BNX2_DMA_WCHAN_STAT_PAR_ERR_7                   (1L<<31)
+
+#define BNX2_DMA_RCHAN_ASSIGNMENT                      0x00000c38
+#define BNX2_DMA_RCHAN_ASSIGNMENT_0                     (0xfL<<0)
+#define BNX2_DMA_RCHAN_ASSIGNMENT_1                     (0xfL<<4)
+#define BNX2_DMA_RCHAN_ASSIGNMENT_2                     (0xfL<<8)
+#define BNX2_DMA_RCHAN_ASSIGNMENT_3                     (0xfL<<12)
+#define BNX2_DMA_RCHAN_ASSIGNMENT_4                     (0xfL<<16)
+#define BNX2_DMA_RCHAN_ASSIGNMENT_5                     (0xfL<<20)
+#define BNX2_DMA_RCHAN_ASSIGNMENT_6                     (0xfL<<24)
+#define BNX2_DMA_RCHAN_ASSIGNMENT_7                     (0xfL<<28)
+
+#define BNX2_DMA_WCHAN_ASSIGNMENT                      0x00000c3c
+#define BNX2_DMA_WCHAN_ASSIGNMENT_0                     (0xfL<<0)
+#define BNX2_DMA_WCHAN_ASSIGNMENT_1                     (0xfL<<4)
+#define BNX2_DMA_WCHAN_ASSIGNMENT_2                     (0xfL<<8)
+#define BNX2_DMA_WCHAN_ASSIGNMENT_3                     (0xfL<<12)
+#define BNX2_DMA_WCHAN_ASSIGNMENT_4                     (0xfL<<16)
+#define BNX2_DMA_WCHAN_ASSIGNMENT_5                     (0xfL<<20)
+#define BNX2_DMA_WCHAN_ASSIGNMENT_6                     (0xfL<<24)
+#define BNX2_DMA_WCHAN_ASSIGNMENT_7                     (0xfL<<28)
+
+#define BNX2_DMA_RCHAN_STAT_00                         0x00000c40
+#define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW  (0xffffffffL<<0)
+
+#define BNX2_DMA_RCHAN_STAT_01                         0x00000c44
+#define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH         
(0xffffffffL<<0)
+
+#define BNX2_DMA_RCHAN_STAT_02                         0x00000c48
+#define BNX2_DMA_RCHAN_STAT_02_LENGTH                   (0xffffL<<0)
+#define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP                (1L<<16)
+#define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP                (1L<<17)
+#define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL             (1L<<18)
+
+#define BNX2_DMA_RCHAN_STAT_10                         0x00000c4c
+#define BNX2_DMA_RCHAN_STAT_11                         0x00000c50
+#define BNX2_DMA_RCHAN_STAT_12                         0x00000c54
+#define BNX2_DMA_RCHAN_STAT_20                         0x00000c58
+#define BNX2_DMA_RCHAN_STAT_21                         0x00000c5c
+#define BNX2_DMA_RCHAN_STAT_22                         0x00000c60
+#define BNX2_DMA_RCHAN_STAT_30                         0x00000c64
+#define BNX2_DMA_RCHAN_STAT_31                         0x00000c68
+#define BNX2_DMA_RCHAN_STAT_32                         0x00000c6c
+#define BNX2_DMA_RCHAN_STAT_40                         0x00000c70
+#define BNX2_DMA_RCHAN_STAT_41                         0x00000c74
+#define BNX2_DMA_RCHAN_STAT_42                         0x00000c78
+#define BNX2_DMA_RCHAN_STAT_50                         0x00000c7c
+#define BNX2_DMA_RCHAN_STAT_51                         0x00000c80
+#define BNX2_DMA_RCHAN_STAT_52                         0x00000c84
+#define BNX2_DMA_RCHAN_STAT_60                         0x00000c88
+#define BNX2_DMA_RCHAN_STAT_61                         0x00000c8c
+#define BNX2_DMA_RCHAN_STAT_62                         0x00000c90
+#define BNX2_DMA_RCHAN_STAT_70                         0x00000c94
+#define BNX2_DMA_RCHAN_STAT_71                         0x00000c98
+#define BNX2_DMA_RCHAN_STAT_72                         0x00000c9c
+#define BNX2_DMA_WCHAN_STAT_00                         0x00000ca0
+#define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW  (0xffffffffL<<0)
+
+#define BNX2_DMA_WCHAN_STAT_01                         0x00000ca4
+#define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH         
(0xffffffffL<<0)
+
+#define BNX2_DMA_WCHAN_STAT_02                         0x00000ca8
+#define BNX2_DMA_WCHAN_STAT_02_LENGTH                   (0xffffL<<0)
+#define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP                (1L<<16)
+#define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP                (1L<<17)
+#define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL             (1L<<18)
+
+#define BNX2_DMA_WCHAN_STAT_10                         0x00000cac
+#define BNX2_DMA_WCHAN_STAT_11                         0x00000cb0
+#define BNX2_DMA_WCHAN_STAT_12                         0x00000cb4
+#define BNX2_DMA_WCHAN_STAT_20                         0x00000cb8
+#define BNX2_DMA_WCHAN_STAT_21                         0x00000cbc
+#define BNX2_DMA_WCHAN_STAT_22                         0x00000cc0
+#define BNX2_DMA_WCHAN_STAT_30                         0x00000cc4
+#define BNX2_DMA_WCHAN_STAT_31                         0x00000cc8
+#define BNX2_DMA_WCHAN_STAT_32                         0x00000ccc
+#define BNX2_DMA_WCHAN_STAT_40                         0x00000cd0
+#define BNX2_DMA_WCHAN_STAT_41                         0x00000cd4
+#define BNX2_DMA_WCHAN_STAT_42                         0x00000cd8
+#define BNX2_DMA_WCHAN_STAT_50                         0x00000cdc
+#define BNX2_DMA_WCHAN_STAT_51                         0x00000ce0
+#define BNX2_DMA_WCHAN_STAT_52                         0x00000ce4
+#define BNX2_DMA_WCHAN_STAT_60                         0x00000ce8
+#define BNX2_DMA_WCHAN_STAT_61                         0x00000cec
+#define BNX2_DMA_WCHAN_STAT_62                         0x00000cf0
+#define BNX2_DMA_WCHAN_STAT_70                         0x00000cf4
+#define BNX2_DMA_WCHAN_STAT_71                         0x00000cf8
+#define BNX2_DMA_WCHAN_STAT_72                         0x00000cfc
+#define BNX2_DMA_ARB_STAT_00                           0x00000d00
+#define BNX2_DMA_ARB_STAT_00_MASTER                     (0xffffL<<0)
+#define BNX2_DMA_ARB_STAT_00_MASTER_ENC                         (0xffL<<16)
+#define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR                (0xffL<<24)
+
+#define BNX2_DMA_ARB_STAT_01                           0x00000d04
+#define BNX2_DMA_ARB_STAT_01_LPR_RPTR                   (0xfL<<0)
+#define BNX2_DMA_ARB_STAT_01_LPR_WPTR                   (0xfL<<4)
+#define BNX2_DMA_ARB_STAT_01_LPB_RPTR                   (0xfL<<8)
+#define BNX2_DMA_ARB_STAT_01_LPB_WPTR                   (0xfL<<12)
+#define BNX2_DMA_ARB_STAT_01_HPR_RPTR                   (0xfL<<16)
+#define BNX2_DMA_ARB_STAT_01_HPR_WPTR                   (0xfL<<20)
+#define BNX2_DMA_ARB_STAT_01_HPB_RPTR                   (0xfL<<24)
+#define BNX2_DMA_ARB_STAT_01_HPB_WPTR                   (0xfL<<28)
+
+#define BNX2_DMA_FUSE_CTRL0_CMD                                0x00000f00
+#define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE              (1L<<0)
+#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE              (1L<<1)
+#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT                   (1L<<2)
+#define BNX2_DMA_FUSE_CTRL0_CMD_LOAD                    (1L<<3)
+#define BNX2_DMA_FUSE_CTRL0_CMD_SEL                     (0xfL<<8)
+
+#define BNX2_DMA_FUSE_CTRL0_DATA                       0x00000f04
+#define BNX2_DMA_FUSE_CTRL1_CMD                                0x00000f08
+#define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE              (1L<<0)
+#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE              (1L<<1)
+#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT                   (1L<<2)
+#define BNX2_DMA_FUSE_CTRL1_CMD_LOAD                    (1L<<3)
+#define BNX2_DMA_FUSE_CTRL1_CMD_SEL                     (0xfL<<8)
+
+#define BNX2_DMA_FUSE_CTRL1_DATA                       0x00000f0c
+#define BNX2_DMA_FUSE_CTRL2_CMD                                0x00000f10
+#define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE              (1L<<0)
+#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE              (1L<<1)
+#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT                   (1L<<2)
+#define BNX2_DMA_FUSE_CTRL2_CMD_LOAD                    (1L<<3)
+#define BNX2_DMA_FUSE_CTRL2_CMD_SEL                     (0xfL<<8)
+
+#define BNX2_DMA_FUSE_CTRL2_DATA                       0x00000f14
+
+
+/*
+ *  context_reg definition
+ *  offset: 0x1000
+ */
+#define BNX2_CTX_COMMAND                               0x00001000
+#define BNX2_CTX_COMMAND_ENABLED                        (1L<<0)
+
+#define BNX2_CTX_STATUS                                        0x00001004
+#define BNX2_CTX_STATUS_LOCK_WAIT                       (1L<<0)
+#define BNX2_CTX_STATUS_READ_STAT                       (1L<<16)
+#define BNX2_CTX_STATUS_WRITE_STAT                      (1L<<17)
+#define BNX2_CTX_STATUS_ACC_STALL_STAT                  (1L<<18)
+#define BNX2_CTX_STATUS_LOCK_STALL_STAT                         (1L<<19)
+
+#define BNX2_CTX_VIRT_ADDR                             0x00001008
+#define BNX2_CTX_VIRT_ADDR_VIRT_ADDR                    (0x7fffL<<6)
+
+#define BNX2_CTX_PAGE_TBL                              0x0000100c
+#define BNX2_CTX_PAGE_TBL_PAGE_TBL                      (0x3fffL<<6)
+
+#define BNX2_CTX_DATA_ADR                              0x00001010
+#define BNX2_CTX_DATA_ADR_DATA_ADR                      (0x7ffffL<<2)
+
+#define BNX2_CTX_DATA                                  0x00001014
+#define BNX2_CTX_LOCK                                  0x00001018
+#define BNX2_CTX_LOCK_TYPE                              (0x7L<<0)
+#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID               (0x0L<<0)
+#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE           (0x7L<<0)
+#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL           (0x1L<<0)
+#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX                         (0x2L<<0)
+#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER              (0x4L<<0)
+#define BNX2_CTX_LOCK_CID_VALUE                                 (0x3fffL<<7)
+#define BNX2_CTX_LOCK_GRANTED                           (1L<<26)
+#define BNX2_CTX_LOCK_MODE                              (0x7L<<27)
+#define BNX2_CTX_LOCK_MODE_UNLOCK                       (0x0L<<27)
+#define BNX2_CTX_LOCK_MODE_IMMEDIATE                    (0x1L<<27)
+#define BNX2_CTX_LOCK_MODE_SURE                                 (0x2L<<27)
+#define BNX2_CTX_LOCK_STATUS                            (1L<<30)
+#define BNX2_CTX_LOCK_REQ                               (1L<<31)
+
+#define BNX2_CTX_ACCESS_STATUS                         0x00001040
+#define BNX2_CTX_ACCESS_STATUS_MASTERENCODED            (0xfL<<0)
+#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM           (0x3L<<10)
+#define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM          (0x3L<<12)
+#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM       (0x3L<<14)
+#define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST        (0x7ffL<<17)
+
+#define BNX2_CTX_DBG_LOCK_STATUS                       0x00001044
+#define BNX2_CTX_DBG_LOCK_STATUS_SM                     (0x3ffL<<0)
+#define BNX2_CTX_DBG_LOCK_STATUS_MATCH                  (0x3ffL<<22)
+
+#define BNX2_CTX_CHNL_LOCK_STATUS_0                    0x00001080
+#define BNX2_CTX_CHNL_LOCK_STATUS_0_CID                         (0x3fffL<<0)
+#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE                (0x3L<<14)
+#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE                (1L<<16)
+
+#define BNX2_CTX_CHNL_LOCK_STATUS_1                    0x00001084
+#define BNX2_CTX_CHNL_LOCK_STATUS_2                    0x00001088
+#define BNX2_CTX_CHNL_LOCK_STATUS_3                    0x0000108c
+#define BNX2_CTX_CHNL_LOCK_STATUS_4                    0x00001090
+#define BNX2_CTX_CHNL_LOCK_STATUS_5                    0x00001094
+#define BNX2_CTX_CHNL_LOCK_STATUS_6                    0x00001098
+#define BNX2_CTX_CHNL_LOCK_STATUS_7                    0x0000109c
+#define BNX2_CTX_CHNL_LOCK_STATUS_8                    0x000010a0
+
+
+/*
+ *  emac_reg definition
+ *  offset: 0x1400
+ */
+#define BNX2_EMAC_MODE                                 0x00001400
+#define BNX2_EMAC_MODE_RESET                            (1L<<0)
+#define BNX2_EMAC_MODE_HALF_DUPLEX                      (1L<<1)
+#define BNX2_EMAC_MODE_PORT                             (0x3L<<2)
+#define BNX2_EMAC_MODE_PORT_NONE                        (0L<<2)
+#define BNX2_EMAC_MODE_PORT_MII                                 (1L<<2)
+#define BNX2_EMAC_MODE_PORT_GMII                        (2L<<2)
+#define BNX2_EMAC_MODE_PORT_UNDEF                       (3L<<2)
+#define BNX2_EMAC_MODE_MAC_LOOP                                 (1L<<4)
+#define BNX2_EMAC_MODE_TAGGED_MAC_CTL                   (1L<<7)
+#define BNX2_EMAC_MODE_TX_BURST                                 (1L<<8)
+#define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA               (1L<<9)
+#define BNX2_EMAC_MODE_EXT_LINK_POL                     (1L<<10)
+#define BNX2_EMAC_MODE_FORCE_LINK                       (1L<<11)
+#define BNX2_EMAC_MODE_MPKT                             (1L<<18)
+#define BNX2_EMAC_MODE_MPKT_RCVD                        (1L<<19)
+#define BNX2_EMAC_MODE_ACPI_RCVD                        (1L<<20)
+
+#define BNX2_EMAC_STATUS                               0x00001404
+#define BNX2_EMAC_STATUS_LINK                           (1L<<11)
+#define BNX2_EMAC_STATUS_LINK_CHANGE                    (1L<<12)
+#define BNX2_EMAC_STATUS_MI_COMPLETE                    (1L<<22)
+#define BNX2_EMAC_STATUS_MI_INT                                 (1L<<23)
+#define BNX2_EMAC_STATUS_AP_ERROR                       (1L<<24)
+#define BNX2_EMAC_STATUS_PARITY_ERROR_STATE             (1L<<31)
+
+#define BNX2_EMAC_ATTENTION_ENA                                0x00001408
+#define BNX2_EMAC_ATTENTION_ENA_LINK                    (1L<<11)
+#define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE             (1L<<22)
+#define BNX2_EMAC_ATTENTION_ENA_MI_INT                  (1L<<23)
+#define BNX2_EMAC_ATTENTION_ENA_AP_ERROR                (1L<<24)
+
+#define BNX2_EMAC_LED                                  0x0000140c
+#define BNX2_EMAC_LED_OVERRIDE                          (1L<<0)
+#define BNX2_EMAC_LED_1000MB_OVERRIDE                   (1L<<1)
+#define BNX2_EMAC_LED_100MB_OVERRIDE                    (1L<<2)
+#define BNX2_EMAC_LED_10MB_OVERRIDE                     (1L<<3)
+#define BNX2_EMAC_LED_TRAFFIC_OVERRIDE                  (1L<<4)
+#define BNX2_EMAC_LED_BLNK_TRAFFIC                      (1L<<5)
+#define BNX2_EMAC_LED_TRAFFIC                           (1L<<6)
+#define BNX2_EMAC_LED_1000MB                            (1L<<7)
+#define BNX2_EMAC_LED_100MB                             (1L<<8)
+#define BNX2_EMAC_LED_10MB                              (1L<<9)
+#define BNX2_EMAC_LED_TRAFFIC_STAT                      (1L<<10)
+#define BNX2_EMAC_LED_BLNK_RATE                                 (0xfffL<<19)
+#define BNX2_EMAC_LED_BLNK_RATE_ENA                     (1L<<31)
+
+#define BNX2_EMAC_MAC_MATCH0                           0x00001410
+#define BNX2_EMAC_MAC_MATCH1                           0x00001414
+#define BNX2_EMAC_MAC_MATCH2                           0x00001418
+#define BNX2_EMAC_MAC_MATCH3                           0x0000141c
+#define BNX2_EMAC_MAC_MATCH4                           0x00001420
+#define BNX2_EMAC_MAC_MATCH5                           0x00001424
+#define BNX2_EMAC_MAC_MATCH6                           0x00001428
+#define BNX2_EMAC_MAC_MATCH7                           0x0000142c
+#define BNX2_EMAC_MAC_MATCH8                           0x00001430
+#define BNX2_EMAC_MAC_MATCH9                           0x00001434
+#define BNX2_EMAC_MAC_MATCH10                          0x00001438
+#define BNX2_EMAC_MAC_MATCH11                          0x0000143c
+#define BNX2_EMAC_MAC_MATCH12                          0x00001440
+#define BNX2_EMAC_MAC_MATCH13                          0x00001444
+#define BNX2_EMAC_MAC_MATCH14                          0x00001448
+#define BNX2_EMAC_MAC_MATCH15                          0x0000144c
+#define BNX2_EMAC_MAC_MATCH16                          0x00001450
+#define BNX2_EMAC_MAC_MATCH17                          0x00001454
+#define BNX2_EMAC_MAC_MATCH18                          0x00001458
+#define BNX2_EMAC_MAC_MATCH19                          0x0000145c
+#define BNX2_EMAC_MAC_MATCH20                          0x00001460
+#define BNX2_EMAC_MAC_MATCH21                          0x00001464
+#define BNX2_EMAC_MAC_MATCH22                          0x00001468
+#define BNX2_EMAC_MAC_MATCH23                          0x0000146c
+#define BNX2_EMAC_MAC_MATCH24                          0x00001470
+#define BNX2_EMAC_MAC_MATCH25                          0x00001474
+#define BNX2_EMAC_MAC_MATCH26                          0x00001478
+#define BNX2_EMAC_MAC_MATCH27                          0x0000147c
+#define BNX2_EMAC_MAC_MATCH28                          0x00001480
+#define BNX2_EMAC_MAC_MATCH29                          0x00001484
+#define BNX2_EMAC_MAC_MATCH30                          0x00001488
+#define BNX2_EMAC_MAC_MATCH31                          0x0000148c
+#define BNX2_EMAC_BACKOFF_SEED                         0x00001498
+#define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED        (0x3ffL<<0)
+
+#define BNX2_EMAC_RX_MTU_SIZE                          0x0000149c
+#define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE                  (0xffffL<<0)
+#define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA                         (1L<<31)
+
+#define BNX2_EMAC_SERDES_CNTL                          0x000014a4
+#define BNX2_EMAC_SERDES_CNTL_RXR                       (0x7L<<0)
+#define BNX2_EMAC_SERDES_CNTL_RXG                       (0x3L<<3)
+#define BNX2_EMAC_SERDES_CNTL_RXCKSEL                   (1L<<6)
+#define BNX2_EMAC_SERDES_CNTL_TXBIAS                    (0x7L<<7)
+#define BNX2_EMAC_SERDES_CNTL_BGMAX                     (1L<<10)
+#define BNX2_EMAC_SERDES_CNTL_BGMIN                     (1L<<11)
+#define BNX2_EMAC_SERDES_CNTL_TXMODE                    (1L<<12)
+#define BNX2_EMAC_SERDES_CNTL_TXEDGE                    (1L<<13)
+#define BNX2_EMAC_SERDES_CNTL_SERDES_MODE               (1L<<14)
+#define BNX2_EMAC_SERDES_CNTL_PLLTEST                   (1L<<15)
+#define BNX2_EMAC_SERDES_CNTL_CDET_EN                   (1L<<16)
+#define BNX2_EMAC_SERDES_CNTL_TBI_LBK                   (1L<<17)
+#define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK                (1L<<18)
+#define BNX2_EMAC_SERDES_CNTL_REV_PHASE                         (1L<<19)
+#define BNX2_EMAC_SERDES_CNTL_REGCTL12                  (0x3L<<20)
+#define BNX2_EMAC_SERDES_CNTL_REGCTL25                  (0x3L<<22)
+
+#define BNX2_EMAC_SERDES_STATUS                                0x000014a8
+#define BNX2_EMAC_SERDES_STATUS_RX_STAT                         (0xffL<<0)
+#define BNX2_EMAC_SERDES_STATUS_COMMA_DET               (1L<<8)
+
+#define BNX2_EMAC_MDIO_COMM                            0x000014ac
+#define BNX2_EMAC_MDIO_COMM_DATA                        (0xffffL<<0)
+#define BNX2_EMAC_MDIO_COMM_REG_ADDR                    (0x1fL<<16)
+#define BNX2_EMAC_MDIO_COMM_PHY_ADDR                    (0x1fL<<21)
+#define BNX2_EMAC_MDIO_COMM_COMMAND                     (0x3L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0                 (0L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE               (1L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_READ                (2L<<26)
+#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3                 (3L<<26)
+#define BNX2_EMAC_MDIO_COMM_FAIL                        (1L<<28)
+#define BNX2_EMAC_MDIO_COMM_START_BUSY                  (1L<<29)
+#define BNX2_EMAC_MDIO_COMM_DISEXT                      (1L<<30)
+
+#define BNX2_EMAC_MDIO_STATUS                          0x000014b0
+#define BNX2_EMAC_MDIO_STATUS_LINK                      (1L<<0)
+#define BNX2_EMAC_MDIO_STATUS_10MB                      (1L<<1)
+
+#define BNX2_EMAC_MDIO_MODE                            0x000014b4
+#define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE              (1L<<1)
+#define BNX2_EMAC_MDIO_MODE_AUTO_POLL                   (1L<<4)
+#define BNX2_EMAC_MDIO_MODE_BIT_BANG                    (1L<<8)
+#define BNX2_EMAC_MDIO_MODE_MDIO                        (1L<<9)
+#define BNX2_EMAC_MDIO_MODE_MDIO_OE                     (1L<<10)
+#define BNX2_EMAC_MDIO_MODE_MDC                                 (1L<<11)
+#define BNX2_EMAC_MDIO_MODE_MDINT                       (1L<<12)
+#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT                   (0x1fL<<16)
+
+#define BNX2_EMAC_MDIO_AUTO_STATUS                     0x000014b8
+#define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR             (1L<<0)
+
+#define BNX2_EMAC_TX_MODE                              0x000014bc
+#define BNX2_EMAC_TX_MODE_RESET                                 (1L<<0)
+#define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN                  (1L<<3)
+#define BNX2_EMAC_TX_MODE_FLOW_EN                       (1L<<4)
+#define BNX2_EMAC_TX_MODE_BIG_BACKOFF                   (1L<<5)
+#define BNX2_EMAC_TX_MODE_LONG_PAUSE                    (1L<<6)
+#define BNX2_EMAC_TX_MODE_LINK_AWARE                    (1L<<7)
+
+#define BNX2_EMAC_TX_STATUS                            0x000014c0
+#define BNX2_EMAC_TX_STATUS_XOFFED                      (1L<<0)
+#define BNX2_EMAC_TX_STATUS_XOFF_SENT                   (1L<<1)
+#define BNX2_EMAC_TX_STATUS_XON_SENT                    (1L<<2)
+#define BNX2_EMAC_TX_STATUS_LINK_UP                     (1L<<3)
+#define BNX2_EMAC_TX_STATUS_UNDERRUN                    (1L<<4)
+
+#define BNX2_EMAC_TX_LENGTHS                           0x000014c4
+#define BNX2_EMAC_TX_LENGTHS_SLOT                       (0xffL<<0)
+#define BNX2_EMAC_TX_LENGTHS_IPG                        (0xfL<<8)
+#define BNX2_EMAC_TX_LENGTHS_IPG_CRS                    (0x3L<<12)
+
+#define BNX2_EMAC_RX_MODE                              0x000014c8
+#define BNX2_EMAC_RX_MODE_RESET                                 (1L<<0)
+#define BNX2_EMAC_RX_MODE_FLOW_EN                       (1L<<2)
+#define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL              (1L<<3)
+#define BNX2_EMAC_RX_MODE_KEEP_PAUSE                    (1L<<4)
+#define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE               (1L<<5)
+#define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS                  (1L<<6)
+#define BNX2_EMAC_RX_MODE_LLC_CHK                       (1L<<7)
+#define BNX2_EMAC_RX_MODE_PROMISCUOUS                   (1L<<8)
+#define BNX2_EMAC_RX_MODE_NO_CRC_CHK                    (1L<<9)
+#define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG                         (1L<<10)
+#define BNX2_EMAC_RX_MODE_FILT_BROADCAST                (1L<<11)
+#define BNX2_EMAC_RX_MODE_SORT_MODE                     (1L<<12)
+
+#define BNX2_EMAC_RX_STATUS                            0x000014cc
+#define BNX2_EMAC_RX_STATUS_FFED                        (1L<<0)
+#define BNX2_EMAC_RX_STATUS_FF_RECEIVED                         (1L<<1)
+#define BNX2_EMAC_RX_STATUS_N_RECEIVED                  (1L<<2)
+
+#define BNX2_EMAC_MULTICAST_HASH0                      0x000014d0
+#define BNX2_EMAC_MULTICAST_HASH1                      0x000014d4
+#define BNX2_EMAC_MULTICAST_HASH2                      0x000014d8
+#define BNX2_EMAC_MULTICAST_HASH3                      0x000014dc
+#define BNX2_EMAC_MULTICAST_HASH4                      0x000014e0
+#define BNX2_EMAC_MULTICAST_HASH5                      0x000014e4
+#define BNX2_EMAC_MULTICAST_HASH6                      0x000014e8
+#define BNX2_EMAC_MULTICAST_HASH7                      0x000014ec
+#define BNX2_EMAC_RX_STAT_IFHCINOCTETS                 0x00001500
+#define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS              0x00001504
+#define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS          0x00001508
+#define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS              0x0000150c
+#define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS          0x00001510
+#define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS          0x00001514
+#define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS           0x00001518
+#define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS     0x0000151c
+#define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS  0x00001520
+#define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED       0x00001524
+#define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED      0x00001528
+#define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED     0x0000152c
+#define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED             0x00001530
+#define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG       0x00001534
+#define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS            0x00001538
+#define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS      0x0000153c
+#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS       0x00001540
+#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS    0x00001544
+#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS   0x00001548
+#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS   0x0000154c
+#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS  0x00001550
+#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
+#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558
+#define BNX2_EMAC_RXMAC_DEBUG0                         0x0000155c
+#define BNX2_EMAC_RXMAC_DEBUG1                         0x00001560
+#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT     (1L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE                 (1L<<1)
+#define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC                  (1L<<2)
+#define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR                         (1L<<3)
+#define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR              (1L<<4)
+#define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA                (1L<<5)
+#define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START           (1L<<6)
+#define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT               (0xffffL<<7)
+#define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME                (0xffL<<23)
+
+#define BNX2_EMAC_RXMAC_DEBUG2                         0x00001564
+#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE                         (0x7L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE            (0x0L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD             (0x1L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA            (0x2L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP           (0x3L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT             (0x4L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP            (0x5L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP           (0x6L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC              (0x7L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE                (0xfL<<3)
+#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE           (0x0L<<3)
+#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0          (0x1L<<3)
+#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1          (0x2L<<3)
+#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2          (0x3L<<3)
+#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3          (0x4L<<3)
+#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT          (0x5L<<3)
+#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT           (0x6L<<3)
+#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS                 (0x7L<<3)
+#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST           (0x8L<<3)
+#define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN                  (0xffL<<7)
+#define BNX2_EMAC_RXMAC_DEBUG2_FALSEC                   (1L<<15)
+#define BNX2_EMAC_RXMAC_DEBUG2_TAGGED                   (1L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE              (1L<<18)
+#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE                 (0L<<18)
+#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED       (1L<<18)
+#define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER               (0xfL<<19)
+#define BNX2_EMAC_RXMAC_DEBUG2_QUANTA                   (0x1fL<<23)
+
+#define BNX2_EMAC_RXMAC_DEBUG3                         0x00001568
+#define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR                (0xffffL<<0)
+#define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR            (0xffffL<<16)
+
+#define BNX2_EMAC_RXMAC_DEBUG4                         0x0000156c
+#define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD               (0xffffL<<0)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE               (0x3fL<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE          (0x0L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2                 (0x1L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3                 (0x2L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI           (0x3L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2                 (0x7L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3                 (0x5L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1          (0x6L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2          (0x7L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3          (0x8L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2           (0x9L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3           (0xaL<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1        (0xeL<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2        (0xfL<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK        (0x10L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC            (0x11L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2           (0x12L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3           (0x13L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1          (0x14L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2          (0x15L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3          (0x16L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE                 (0x17L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC            (0x18L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE                 (0x19L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD           (0x1aL<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC           (0x1bL<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH                 (0x1cL<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF          (0x1dL<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON           (0x1eL<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED        (0x1fL<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED       (0x20L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE                 (0x21L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL          (0x22L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1          (0x23L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2          (0x24L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3          (0x25L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE                 (0x26L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE        (0x27L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL                 (0x28L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE                 (0x29L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP          (0x2aL<<16)
+#define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT                         (1L<<22)
+#define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED              (1L<<23)
+#define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER            (1L<<24)
+#define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA                (1L<<25)
+#define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND                (1L<<26)
+#define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE                  (1L<<27)
+#define BNX2_EMAC_RXMAC_DEBUG4_START                    (1L<<28)
+
+#define BNX2_EMAC_RXMAC_DEBUG5                         0x00001570
+#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM                         (0x7L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE            (0L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF        (1L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT       (2L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC    (3L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE     (4L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL     (5L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT   (6L<<0)
+#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1               (0x7L<<4)
+#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW           (0x0L<<4)
+#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT          (0x1L<<4)
+#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF          (0x2L<<4)
+#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF          (0x3L<<4)
+#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF           (0x4L<<4)
+#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF                 (0x6L<<4)
+#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF                 (0x7L<<4)
+#define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED             (1L<<7)
+#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0               (0x7L<<8)
+#define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL        (1L<<11)
+#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE               (1L<<12)
+#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA                (1L<<13)
+#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT                (1L<<14)
+#define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT                         (1L<<15)
+#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE            (0x3L<<16)
+#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT           (1L<<19)
+#define BNX2_EMAC_RXMAC_DEBUG5_FMLEN                    (0xfffL<<20)
+
+#define BNX2_EMAC_RX_STAT_AC0                          0x00001580
+#define BNX2_EMAC_RX_STAT_AC1                          0x00001584
+#define BNX2_EMAC_RX_STAT_AC2                          0x00001588
+#define BNX2_EMAC_RX_STAT_AC3                          0x0000158c
+#define BNX2_EMAC_RX_STAT_AC4                          0x00001590
+#define BNX2_EMAC_RX_STAT_AC5                          0x00001594
+#define BNX2_EMAC_RX_STAT_AC6                          0x00001598
+#define BNX2_EMAC_RX_STAT_AC7                          0x0000159c
+#define BNX2_EMAC_RX_STAT_AC8                          0x000015a0
+#define BNX2_EMAC_RX_STAT_AC9                          0x000015a4
+#define BNX2_EMAC_RX_STAT_AC10                         0x000015a8
+#define BNX2_EMAC_RX_STAT_AC11                         0x000015ac
+#define BNX2_EMAC_RX_STAT_AC12                         0x000015b0
+#define BNX2_EMAC_RX_STAT_AC13                         0x000015b4
+#define BNX2_EMAC_RX_STAT_AC14                         0x000015b8
+#define BNX2_EMAC_RX_STAT_AC15                         0x000015bc
+#define BNX2_EMAC_RX_STAT_AC16                         0x000015c0
+#define BNX2_EMAC_RX_STAT_AC17                         0x000015c4
+#define BNX2_EMAC_RX_STAT_AC18                         0x000015c8
+#define BNX2_EMAC_RX_STAT_AC19                         0x000015cc
+#define BNX2_EMAC_RX_STAT_AC20                         0x000015d0
+#define BNX2_EMAC_RX_STAT_AC21                         0x000015d4
+#define BNX2_EMAC_RX_STAT_AC22                         0x000015d8
+#define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC             0x000015dc
+#define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS                        0x00001600
+#define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS             0x00001604
+#define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS         0x00001608
+#define BNX2_EMAC_TX_STAT_OUTXONSENT                   0x0000160c
+#define BNX2_EMAC_TX_STAT_OUTXOFFSENT                  0x00001610
+#define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE              0x00001614
+#define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES       0x00001618
+#define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES     0x0000161c
+#define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS       0x00001620
+#define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
+#define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS      0x00001628
+#define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS             0x0000162c
+#define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS         0x00001630
+#define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS         0x00001634
+#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS       0x00001638
+#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS    0x0000163c
+#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS   0x00001640
+#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS   0x00001644
+#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS  0x00001648
+#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
+#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650
+#define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS   0x00001654
+#define BNX2_EMAC_TXMAC_DEBUG0                         0x00001658
+#define BNX2_EMAC_TXMAC_DEBUG1                         0x0000165c
+#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE                (0xfL<<0)
+#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE           (0x0L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0                 (0x1L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0          (0x4L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1          (0x5L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2          (0x6L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3          (0x7L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0          (0x8L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1          (0x9L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE               (1L<<4)
+#define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC                  (1L<<5)
+#define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER               (0xfL<<6)
+#define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE               (1L<<10)
+#define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION           (1L<<11)
+#define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER                (1L<<12)
+#define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED                         (1L<<13)
+#define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE                         (1L<<14)
+#define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME                         (0xfL<<15)
+#define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME                (0xffL<<19)
+
+#define BNX2_EMAC_TXMAC_DEBUG2                         0x00001660
+#define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF                         (0x3ffL<<0)
+#define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT               (0xffffL<<10)
+#define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT                (0x1fL<<26)
+#define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT                  (1L<<31)
+
+#define BNX2_EMAC_TXMAC_DEBUG3                         0x00001664
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE                         (0xfL<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE            (0x0L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1            (0x1L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2            (0x2L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD             (0x3L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA            (0x4L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1            (0x5L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2            (0x6L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT             (0x7L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB           (0x8L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG           (0x9L<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM             (0xaL<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM            (0xbL<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM            (0xcL<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT           (0xdL<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF                 (0xeL<<0)
+#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE               (0x7L<<4)
+#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE          (0x0L<<4)
+#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT          (0x1L<<4)
+#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI           (0x2L<<4)
+#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC            (0x3L<<4)
+#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2           (0x4L<<4)
+#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3           (0x5L<<4)
+#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC            (0x6L<<4)
+#define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE                         (1L<<7)
+#define BNX2_EMAC_TXMAC_DEBUG3_XOFF                     (1L<<8)
+#define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER               (0xfL<<9)
+#define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER           (0x1fL<<13)
+
+#define BNX2_EMAC_TXMAC_DEBUG4                         0x00001668
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER            (0xffffL<<0)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE              (0xfL<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE                 (0x0L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1                 (0x2L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2                 (0x3L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3                 (0x6L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1                 (0x7L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2                 (0x5L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3                 (0x4L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE                 (0xcL<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD          (0xeL<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME                 (0xaL<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1                 (0x8L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2                 (0x9L<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT                 (0xdL<<16)
+#define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID             (1L<<20)
+#define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC               (1L<<21)
+#define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED              (1L<<22)
+#define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER                (1L<<23)
+#define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND              (1L<<24)
+#define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING             (1L<<25)
+#define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC                  (1L<<26)
+#define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING                (1L<<27)
+#define BNX2_EMAC_TXMAC_DEBUG4_COL_IN                   (1L<<28)
+#define BNX2_EMAC_TXMAC_DEBUG4_BURSTING                         (1L<<29)
+#define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE                  (1L<<30)
+#define BNX2_EMAC_TXMAC_DEBUG4_GO                       (1L<<31)
+
+#define BNX2_EMAC_TX_STAT_AC0                          0x00001680
+#define BNX2_EMAC_TX_STAT_AC1                          0x00001684
+#define BNX2_EMAC_TX_STAT_AC2                          0x00001688
+#define BNX2_EMAC_TX_STAT_AC3                          0x0000168c
+#define BNX2_EMAC_TX_STAT_AC4                          0x00001690
+#define BNX2_EMAC_TX_STAT_AC5                          0x00001694
+#define BNX2_EMAC_TX_STAT_AC6                          0x00001698
+#define BNX2_EMAC_TX_STAT_AC7                          0x0000169c
+#define BNX2_EMAC_TX_STAT_AC8                          0x000016a0
+#define BNX2_EMAC_TX_STAT_AC9                          0x000016a4
+#define BNX2_EMAC_TX_STAT_AC10                         0x000016a8
+#define BNX2_EMAC_TX_STAT_AC11                         0x000016ac
+#define BNX2_EMAC_TX_STAT_AC12                         0x000016b0
+#define BNX2_EMAC_TX_STAT_AC13                         0x000016b4
+#define BNX2_EMAC_TX_STAT_AC14                         0x000016b8
+#define BNX2_EMAC_TX_STAT_AC15                         0x000016bc
+#define BNX2_EMAC_TX_STAT_AC16                         0x000016c0
+#define BNX2_EMAC_TX_STAT_AC17                         0x000016c4
+#define BNX2_EMAC_TX_STAT_AC18                         0x000016c8
+#define BNX2_EMAC_TX_STAT_AC19                         0x000016cc
+#define BNX2_EMAC_TX_STAT_AC20                         0x000016d0
+#define BNX2_EMAC_TX_STAT_AC21                         0x000016d4
+#define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC             0x000016d8
+
+
+/*
+ *  rpm_reg definition
+ *  offset: 0x1800
+ */
+#define BNX2_RPM_COMMAND                               0x00001800
+#define BNX2_RPM_COMMAND_ENABLED                        (1L<<0)
+#define BNX2_RPM_COMMAND_OVERRUN_ABORT                  (1L<<4)
+
+#define BNX2_RPM_STATUS                                        0x00001804
+#define BNX2_RPM_STATUS_MBUF_WAIT                       (1L<<0)
+#define BNX2_RPM_STATUS_FREE_WAIT                       (1L<<1)
+
+#define BNX2_RPM_CONFIG                                        0x00001808
+#define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM                (1L<<0)
+#define BNX2_RPM_CONFIG_ACPI_ENA                        (1L<<1)
+#define BNX2_RPM_CONFIG_ACPI_KEEP                       (1L<<2)
+#define BNX2_RPM_CONFIG_MP_KEEP                                 (1L<<3)
+#define BNX2_RPM_CONFIG_SORT_VECT_VAL                   (0xfL<<4)
+#define BNX2_RPM_CONFIG_IGNORE_VLAN                     (1L<<31)
+
+#define BNX2_RPM_VLAN_MATCH0                           0x00001810
+#define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE       (0xfffL<<0)
+
+#define BNX2_RPM_VLAN_MATCH1                           0x00001814
+#define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE       (0xfffL<<0)
+
+#define BNX2_RPM_VLAN_MATCH2                           0x00001818
+#define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE       (0xfffL<<0)
+
+#define BNX2_RPM_VLAN_MATCH3                           0x0000181c
+#define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE       (0xfffL<<0)
+
+#define BNX2_RPM_SORT_USER0                            0x00001820
+#define BNX2_RPM_SORT_USER0_PM_EN                       (0xffffL<<0)
+#define BNX2_RPM_SORT_USER0_BC_EN                       (1L<<16)
+#define BNX2_RPM_SORT_USER0_MC_EN                       (1L<<17)
+#define BNX2_RPM_SORT_USER0_MC_HSH_EN                   (1L<<18)
+#define BNX2_RPM_SORT_USER0_PROM_EN                     (1L<<19)
+#define BNX2_RPM_SORT_USER0_VLAN_EN                     (0xfL<<20)
+#define BNX2_RPM_SORT_USER0_PROM_VLAN                   (1L<<24)
+#define BNX2_RPM_SORT_USER0_ENA                                 (1L<<31)
+
+#define BNX2_RPM_SORT_USER1                            0x00001824
+#define BNX2_RPM_SORT_USER1_PM_EN                       (0xffffL<<0)
+#define BNX2_RPM_SORT_USER1_BC_EN                       (1L<<16)
+#define BNX2_RPM_SORT_USER1_MC_EN                       (1L<<17)
+#define BNX2_RPM_SORT_USER1_MC_HSH_EN                   (1L<<18)
+#define BNX2_RPM_SORT_USER1_PROM_EN                     (1L<<19)
+#define BNX2_RPM_SORT_USER1_VLAN_EN                     (0xfL<<20)
+#define BNX2_RPM_SORT_USER1_PROM_VLAN                   (1L<<24)
+#define BNX2_RPM_SORT_USER1_ENA                                 (1L<<31)
+
+#define BNX2_RPM_SORT_USER2                            0x00001828
+#define BNX2_RPM_SORT_USER2_PM_EN                       (0xffffL<<0)
+#define BNX2_RPM_SORT_USER2_BC_EN                       (1L<<16)
+#define BNX2_RPM_SORT_USER2_MC_EN                       (1L<<17)
+#define BNX2_RPM_SORT_USER2_MC_HSH_EN                   (1L<<18)
+#define BNX2_RPM_SORT_USER2_PROM_EN                     (1L<<19)
+#define BNX2_RPM_SORT_USER2_VLAN_EN                     (0xfL<<20)
+#define BNX2_RPM_SORT_USER2_PROM_VLAN                   (1L<<24)
+#define BNX2_RPM_SORT_USER2_ENA                                 (1L<<31)
+
+#define BNX2_RPM_SORT_USER3                            0x0000182c
+#define BNX2_RPM_SORT_USER3_PM_EN                       (0xffffL<<0)
+#define BNX2_RPM_SORT_USER3_BC_EN                       (1L<<16)
+#define BNX2_RPM_SORT_USER3_MC_EN                       (1L<<17)
+#define BNX2_RPM_SORT_USER3_MC_HSH_EN                   (1L<<18)
+#define BNX2_RPM_SORT_USER3_PROM_EN                     (1L<<19)
+#define BNX2_RPM_SORT_USER3_VLAN_EN                     (0xfL<<20)
+#define BNX2_RPM_SORT_USER3_PROM_VLAN                   (1L<<24)
+#define BNX2_RPM_SORT_USER3_ENA                                 (1L<<31)
+
+#define BNX2_RPM_STAT_L2_FILTER_DISCARDS               0x00001840
+#define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS            0x00001844
+#define BNX2_RPM_STAT_IFINFTQDISCARDS                  0x00001848
+#define BNX2_RPM_STAT_IFINMBUFDISCARD                  0x0000184c
+#define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT              0x00001850
+#define BNX2_RPM_STAT_AC0                              0x00001880
+#define BNX2_RPM_STAT_AC1                              0x00001884
+#define BNX2_RPM_STAT_AC2                              0x00001888
+#define BNX2_RPM_STAT_AC3                              0x0000188c
+#define BNX2_RPM_STAT_AC4                              0x00001890
+#define BNX2_RPM_RC_CNTL_0                             0x00001900
+#define BNX2_RPM_RC_CNTL_0_OFFSET                       (0xffL<<0)
+#define BNX2_RPM_RC_CNTL_0_CLASS                        (0x7L<<8)
+#define BNX2_RPM_RC_CNTL_0_PRIORITY                     (1L<<11)
+#define BNX2_RPM_RC_CNTL_0_P4                           (1L<<12)
+#define BNX2_RPM_RC_CNTL_0_HDR_TYPE                     (0x7L<<13)
+#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START               (0L<<13)
+#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP                  (1L<<13)
+#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP                         (2L<<13)
+#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP                         (3L<<13)
+#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA                (4L<<13)
+#define BNX2_RPM_RC_CNTL_0_COMP                                 (0x3L<<16)
+#define BNX2_RPM_RC_CNTL_0_COMP_EQUAL                   (0L<<16)
+#define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL                  (1L<<16)
+#define BNX2_RPM_RC_CNTL_0_COMP_GREATER                         (2L<<16)
+#define BNX2_RPM_RC_CNTL_0_COMP_LESS                    (3L<<16)
+#define BNX2_RPM_RC_CNTL_0_SBIT                                 (1L<<19)
+#define BNX2_RPM_RC_CNTL_0_CMDSEL                       (0xfL<<20)
+#define BNX2_RPM_RC_CNTL_0_MAP                          (1L<<24)
+#define BNX2_RPM_RC_CNTL_0_DISCARD                      (1L<<25)
+#define BNX2_RPM_RC_CNTL_0_MASK                                 (1L<<26)
+#define BNX2_RPM_RC_CNTL_0_P1                           (1L<<27)
+#define BNX2_RPM_RC_CNTL_0_P2                           (1L<<28)
+#define BNX2_RPM_RC_CNTL_0_P3                           (1L<<29)
+#define BNX2_RPM_RC_CNTL_0_NBIT                                 (1L<<30)
+
+#define BNX2_RPM_RC_VALUE_MASK_0                       0x00001904
+#define BNX2_RPM_RC_VALUE_MASK_0_VALUE                  (0xffffL<<0)
+#define BNX2_RPM_RC_VALUE_MASK_0_MASK                   (0xffffL<<16)
+
+#define BNX2_RPM_RC_CNTL_1                             0x00001908
+#define BNX2_RPM_RC_CNTL_1_A                            (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_1_B                            (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_1                       0x0000190c
+#define BNX2_RPM_RC_CNTL_2                             0x00001910
+#define BNX2_RPM_RC_CNTL_2_A                            (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_2_B                            (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_2                       0x00001914
+#define BNX2_RPM_RC_CNTL_3                             0x00001918
+#define BNX2_RPM_RC_CNTL_3_A                            (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_3_B                            (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_3                       0x0000191c
+#define BNX2_RPM_RC_CNTL_4                             0x00001920
+#define BNX2_RPM_RC_CNTL_4_A                            (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_4_B                            (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_4                       0x00001924
+#define BNX2_RPM_RC_CNTL_5                             0x00001928
+#define BNX2_RPM_RC_CNTL_5_A                            (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_5_B                            (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_5                       0x0000192c
+#define BNX2_RPM_RC_CNTL_6                             0x00001930
+#define BNX2_RPM_RC_CNTL_6_A                            (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_6_B                            (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_6                       0x00001934
+#define BNX2_RPM_RC_CNTL_7                             0x00001938
+#define BNX2_RPM_RC_CNTL_7_A                            (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_7_B                            (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_7                       0x0000193c
+#define BNX2_RPM_RC_CNTL_8                             0x00001940
+#define BNX2_RPM_RC_CNTL_8_A                            (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_8_B                            (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_8                       0x00001944
+#define BNX2_RPM_RC_CNTL_9                             0x00001948
+#define BNX2_RPM_RC_CNTL_9_A                            (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_9_B                            (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_9                       0x0000194c
+#define BNX2_RPM_RC_CNTL_10                            0x00001950
+#define BNX2_RPM_RC_CNTL_10_A                           (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_10_B                           (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_10                      0x00001954
+#define BNX2_RPM_RC_CNTL_11                            0x00001958
+#define BNX2_RPM_RC_CNTL_11_A                           (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_11_B                           (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_11                      0x0000195c
+#define BNX2_RPM_RC_CNTL_12                            0x00001960
+#define BNX2_RPM_RC_CNTL_12_A                           (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_12_B                           (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_12                      0x00001964
+#define BNX2_RPM_RC_CNTL_13                            0x00001968
+#define BNX2_RPM_RC_CNTL_13_A                           (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_13_B                           (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_13                      0x0000196c
+#define BNX2_RPM_RC_CNTL_14                            0x00001970
+#define BNX2_RPM_RC_CNTL_14_A                           (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_14_B                           (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_14                      0x00001974
+#define BNX2_RPM_RC_CNTL_15                            0x00001978
+#define BNX2_RPM_RC_CNTL_15_A                           (0x3ffffL<<0)
+#define BNX2_RPM_RC_CNTL_15_B                           (0xfffL<<19)
+
+#define BNX2_RPM_RC_VALUE_MASK_15                      0x0000197c
+#define BNX2_RPM_RC_CONFIG                             0x00001980
+#define BNX2_RPM_RC_CONFIG_RULE_ENABLE                  (0xffffL<<0)
+#define BNX2_RPM_RC_CONFIG_DEF_CLASS                    (0x7L<<24)
+
+#define BNX2_RPM_DEBUG0                                        0x00001984
+#define BNX2_RPM_DEBUG0_FM_BCNT                                 (0xffffL<<0)
+#define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD                         (1L<<16)
+#define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD                  (1L<<17)
+#define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD                  (1L<<18)
+#define BNX2_RPM_DEBUG0_T_IP_OFST_VLD                   (1L<<19)
+#define BNX2_RPM_DEBUG0_IP_MORE_FRGMT                   (1L<<20)
+#define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR             (1L<<21)
+#define BNX2_RPM_DEBUG0_LLC_SNAP                        (1L<<22)
+#define BNX2_RPM_DEBUG0_FM_STARTED                      (1L<<23)
+#define BNX2_RPM_DEBUG0_DONE                            (1L<<24)
+#define BNX2_RPM_DEBUG0_WAIT_4_DONE                     (1L<<25)
+#define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM                         (1L<<26)
+#define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM             (1L<<27)
+#define BNX2_RPM_DEBUG0_IGNORE_VLAN                     (1L<<28)
+#define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE                   (1L<<31)
+
+#define BNX2_RPM_DEBUG1                                        0x00001988
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST                      (0xffffL<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE                         (0L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL                 (1L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC       (2L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP          (4L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP          (8L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START             (16L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP                   (32L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP                  (64L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP                  (128L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH                   (256L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP                  (512L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD          (1024L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA                         (2048L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY            (0x2000L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT                 (0x4000L<<0)
+#define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT                 (0x8000L<<0)
+#define BNX2_RPM_DEBUG1_HDR_BCNT                        (0x7ffL<<16)
+#define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D                         (1L<<28)
+#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2                         (1L<<29)
+#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1                         (1L<<30)
+#define BNX2_RPM_DEBUG1_EOF_0XTRA_WD                    (1L<<31)
+
+#define BNX2_RPM_DEBUG2                                        0x0000198c
+#define BNX2_RPM_DEBUG2_CMD_HIT_VEC                     (0xffffL<<0)
+#define BNX2_RPM_DEBUG2_IP_BCNT                                 (0xffL<<16)
+#define BNX2_RPM_DEBUG2_THIS_CMD_M4                     (1L<<24)
+#define BNX2_RPM_DEBUG2_THIS_CMD_M3                     (1L<<25)
+#define BNX2_RPM_DEBUG2_THIS_CMD_M2                     (1L<<26)
+#define BNX2_RPM_DEBUG2_THIS_CMD_M1                     (1L<<27)
+#define BNX2_RPM_DEBUG2_IPIPE_EMPTY                     (1L<<28)
+#define BNX2_RPM_DEBUG2_FM_DISCARD                      (1L<<29)
+#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2              (1L<<30)
+#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1              (1L<<31)
+
+#define BNX2_RPM_DEBUG3                                        0x00001990
+#define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR                  (0x1ffL<<0)
+#define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT            (1L<<9)
+#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT            (1L<<10)
+#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT             (1L<<11)
+#define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ               (1L<<12)
+#define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ              (1L<<13)
+#define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL              (1L<<14)
+#define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP               (1L<<15)
+#define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT              (0xfL<<16)
+#define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL            (1L<<21)
+#define BNX2_RPM_DEBUG3_DROP_NXT_VLD                    (1L<<22)
+#define BNX2_RPM_DEBUG3_DROP_NXT                        (1L<<23)
+#define BNX2_RPM_DEBUG3_FTQ_FSM                                 (0x3L<<24)
+#define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE                    (0x0L<<24)
+#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK                (0x1L<<24)
+#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE               (0x2L<<24)
+#define BNX2_RPM_DEBUG3_MBWRITE_FSM                     (0x3L<<26)
+#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF            (0x0L<<26)
+#define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF            (0x1L<<26)
+#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA            (0x2L<<26)
+#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA           (0x3L<<26)
+#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF            (0x4L<<26)
+#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK                 (0x5L<<26)
+#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD   (0x6L<<26)
+#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE                (0x7L<<26)
+#define BNX2_RPM_DEBUG3_MBFREE_FSM                      (1L<<29)
+#define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE                         (0L<<29)
+#define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK             (1L<<29)
+#define BNX2_RPM_DEBUG3_MBALLOC_FSM                     (1L<<30)
+#define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF             (0x0L<<30)
+#define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF            (0x1L<<30)
+#define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR                         (1L<<31)
+
+#define BNX2_RPM_DEBUG4                                        0x00001994
+#define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER               (0x1ffffffL<<0)
+#define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE                         (0x7L<<25)
+#define BNX2_RPM_DEBUG4_MBWRITE_FSM                     (0x7L<<28)
+#define BNX2_RPM_DEBUG4_DFIFO_EMPTY                     (1L<<31)
+
+#define BNX2_RPM_DEBUG5                                        0x00001998
+#define BNX2_RPM_DEBUG5_RDROP_WPTR                      (0x1fL<<0)
+#define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR                         (0x1fL<<5)
+#define BNX2_RPM_DEBUG5_RDROP_MC_RPTR                   (0x1fL<<10)
+#define BNX2_RPM_DEBUG5_RDROP_RC_RPTR                   (0x1fL<<15)
+#define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY                (1L<<20)
+#define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY                  (1L<<21)
+#define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR         (1L<<22)
+#define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT            (1L<<23)
+#define BNX2_RPM_DEBUG5_HOLDREG_DISCARD                         (1L<<24)
+#define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL           (1L<<25)
+#define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY                (1L<<26)
+#define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY                (1L<<27)
+#define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY                (1L<<28)
+#define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY              (1L<<29)
+#define BNX2_RPM_DEBUG5_HOLDREG_FULL_T                  (1L<<30)
+#define BNX2_RPM_DEBUG5_HOLDREG_RD                      (1L<<31)
+
+#define BNX2_RPM_DEBUG6                                        0x0000199c
+#define BNX2_RPM_DEBUG6_ACPI_VEC                        (0xffffL<<0)
+#define BNX2_RPM_DEBUG6_VEC                             (0xffffL<<16)
+
+#define BNX2_RPM_DEBUG7                                        0x000019a0
+#define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC               (0xffffffffL<<0)
+
+#define BNX2_RPM_DEBUG8                                        0x000019a4
+#define BNX2_RPM_DEBUG8_PS_ACPI_FSM                     (0xfL<<0)
+#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE                (0L<<0)
+#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR                 (1L<<0)
+#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR                 (2L<<0)
+#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR                 (3L<<0)
+#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF      (4L<<0)
+#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA             (5L<<0)
+#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR             (6L<<0)
+#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR             (7L<<0)
+#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR             (8L<<0)
+#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR             (9L<<0)
+#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF          (10L<<0)
+#define BNX2_RPM_DEBUG8_COMPARE_AT_W0                   (1L<<4)
+#define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA              (1L<<5)
+#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT             (1L<<6)
+#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3               (1L<<7)
+#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2               (1L<<8)
+#define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES            (1L<<9)
+#define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES            (1L<<10)
+#define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES           (1L<<11)
+#define BNX2_RPM_DEBUG8_EOF_DET                                 (1L<<12)
+#define BNX2_RPM_DEBUG8_SOF_DET                                 (1L<<13)
+#define BNX2_RPM_DEBUG8_WAIT_4_SOF                      (1L<<14)
+#define BNX2_RPM_DEBUG8_ALL_DONE                        (1L<<15)
+#define BNX2_RPM_DEBUG8_THBUF_ADDR                      (0x7fL<<16)
+#define BNX2_RPM_DEBUG8_BYTE_CTR                        (0xffL<<24)
+
+#define BNX2_RPM_DEBUG9                                        0x000019a8
+#define BNX2_RPM_DEBUG9_OUTFIFO_COUNT                   (0x7L<<0)
+#define BNX2_RPM_DEBUG9_RDE_ACPI_RDY                    (1L<<3)
+#define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT                         (0x7L<<4)
+#define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED        (1L<<28)
+#define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED                 (1L<<29)
+#define BNX2_RPM_DEBUG9_ACPI_MATCH_INT                  (1L<<30)
+#define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN                         (1L<<31)
+
+#define BNX2_RPM_ACPI_DBG_BUF_W00                      0x000019c0
+#define BNX2_RPM_ACPI_DBG_BUF_W01                      0x000019c4
+#define BNX2_RPM_ACPI_DBG_BUF_W02                      0x000019c8
+#define BNX2_RPM_ACPI_DBG_BUF_W03                      0x000019cc
+#define BNX2_RPM_ACPI_DBG_BUF_W10                      0x000019d0
+#define BNX2_RPM_ACPI_DBG_BUF_W11                      0x000019d4
+#define BNX2_RPM_ACPI_DBG_BUF_W12                      0x000019d8
+#define BNX2_RPM_ACPI_DBG_BUF_W13                      0x000019dc
+#define BNX2_RPM_ACPI_DBG_BUF_W20                      0x000019e0
+#define BNX2_RPM_ACPI_DBG_BUF_W21                      0x000019e4
+#define BNX2_RPM_ACPI_DBG_BUF_W22                      0x000019e8
+#define BNX2_RPM_ACPI_DBG_BUF_W23                      0x000019ec
+#define BNX2_RPM_ACPI_DBG_BUF_W30                      0x000019f0
+#define BNX2_RPM_ACPI_DBG_BUF_W31                      0x000019f4
+#define BNX2_RPM_ACPI_DBG_BUF_W32                      0x000019f8
+#define BNX2_RPM_ACPI_DBG_BUF_W33                      0x000019fc
+
+
+/*
+ *  rbuf_reg definition
+ *  offset: 0x200000
+ */
+#define BNX2_RBUF_COMMAND                              0x00200000
+#define BNX2_RBUF_COMMAND_ENABLED                       (1L<<0)
+#define BNX2_RBUF_COMMAND_FREE_INIT                     (1L<<1)
+#define BNX2_RBUF_COMMAND_RAM_INIT                      (1L<<2)
+#define BNX2_RBUF_COMMAND_OVER_FREE                     (1L<<4)
+#define BNX2_RBUF_COMMAND_ALLOC_REQ                     (1L<<5)
+
+#define BNX2_RBUF_STATUS1                              0x00200004
+#define BNX2_RBUF_STATUS1_FREE_COUNT                    (0x3ffL<<0)
+
+#define BNX2_RBUF_STATUS2                              0x00200008
+#define BNX2_RBUF_STATUS2_FREE_TAIL                     (0x3ffL<<0)
+#define BNX2_RBUF_STATUS2_FREE_HEAD                     (0x3ffL<<16)
+
+#define BNX2_RBUF_CONFIG                               0x0020000c
+#define BNX2_RBUF_CONFIG_XOFF_TRIP                      (0x3ffL<<0)
+#define BNX2_RBUF_CONFIG_XON_TRIP                       (0x3ffL<<16)
+
+#define BNX2_RBUF_FW_BUF_ALLOC                         0x00200010
+#define BNX2_RBUF_FW_BUF_ALLOC_VALUE                    (0x1ffL<<7)
+
+#define BNX2_RBUF_FW_BUF_FREE                          0x00200014
+#define BNX2_RBUF_FW_BUF_FREE_COUNT                     (0x7fL<<0)
+#define BNX2_RBUF_FW_BUF_FREE_TAIL                      (0x1ffL<<7)
+#define BNX2_RBUF_FW_BUF_FREE_HEAD                      (0x1ffL<<16)
+
+#define BNX2_RBUF_FW_BUF_SEL                           0x00200018
+#define BNX2_RBUF_FW_BUF_SEL_COUNT                      (0x7fL<<0)
+#define BNX2_RBUF_FW_BUF_SEL_TAIL                       (0x1ffL<<7)
+#define BNX2_RBUF_FW_BUF_SEL_HEAD                       (0x1ffL<<16)
+
+#define BNX2_RBUF_CONFIG2                              0x0020001c
+#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP                         (0x3ffL<<0)
+#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP                         (0x3ffL<<16)
+
+#define BNX2_RBUF_CONFIG3                              0x00200020
+#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP                  (0x3ffL<<0)
+#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP                  (0x3ffL<<16)
+
+#define BNX2_RBUF_PKT_DATA                             0x00208000
+#define BNX2_RBUF_CLIST_DATA                           0x00210000
+#define BNX2_RBUF_BUF_DATA                             0x00220000
+
+
+/*
+ *  rv2p_reg definition
+ *  offset: 0x2800
+ */
+#define BNX2_RV2P_COMMAND                              0x00002800
+#define BNX2_RV2P_COMMAND_ENABLED                       (1L<<0)
+#define BNX2_RV2P_COMMAND_PROC1_INTRPT                  (1L<<1)
+#define BNX2_RV2P_COMMAND_PROC2_INTRPT                  (1L<<2)
+#define BNX2_RV2P_COMMAND_ABORT0                        (1L<<4)
+#define BNX2_RV2P_COMMAND_ABORT1                        (1L<<5)
+#define BNX2_RV2P_COMMAND_ABORT2                        (1L<<6)
+#define BNX2_RV2P_COMMAND_ABORT3                        (1L<<7)
+#define BNX2_RV2P_COMMAND_ABORT4                        (1L<<8)
+#define BNX2_RV2P_COMMAND_ABORT5                        (1L<<9)
+#define BNX2_RV2P_COMMAND_PROC1_RESET                   (1L<<16)
+#define BNX2_RV2P_COMMAND_PROC2_RESET                   (1L<<17)
+#define BNX2_RV2P_COMMAND_CTXIF_RESET                   (1L<<18)
+
+#define BNX2_RV2P_STATUS                               0x00002804
+#define BNX2_RV2P_STATUS_ALWAYS_0                       (1L<<0)
+#define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT             (1L<<8)
+#define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT             (1L<<9)
+#define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT             (1L<<10)
+#define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT             (1L<<11)
+#define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT             (1L<<12)
+#define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT             (1L<<13)
+
+#define BNX2_RV2P_CONFIG                               0x00002808
+#define BNX2_RV2P_CONFIG_STALL_PROC1                    (1L<<0)
+#define BNX2_RV2P_CONFIG_STALL_PROC2                    (1L<<1)
+#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0          (1L<<8)
+#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1          (1L<<9)
+#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2          (1L<<10)
+#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3          (1L<<11)
+#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4          (1L<<12)
+#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5          (1L<<13)
+#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0          (1L<<16)
+#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1          (1L<<17)
+#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2          (1L<<18)
+#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3          (1L<<19)
+#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4          (1L<<20)
+#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5          (1L<<21)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE                      (0xfL<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_256                  (0L<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_512                  (1L<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_1K                   (2L<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_2K                   (3L<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_4K                   (4L<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_8K                   (5L<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_16K                  (6L<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_32K                  (7L<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_64K                  (8L<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_128K                         (9L<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_256K                         (10L<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_512K                         (11L<<24)
+#define BNX2_RV2P_CONFIG_PAGE_SIZE_1M                   (12L<<24)
+
+#define BNX2_RV2P_GEN_BFR_ADDR_0                       0x00002810
+#define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE                  (0xffffL<<16)
+
+#define BNX2_RV2P_GEN_BFR_ADDR_1                       0x00002814
+#define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE                  (0xffffL<<16)
+
+#define BNX2_RV2P_GEN_BFR_ADDR_2                       0x00002818
+#define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE                  (0xffffL<<16)
+
+#define BNX2_RV2P_GEN_BFR_ADDR_3                       0x0000281c
+#define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE                  (0xffffL<<16)
+
+#define BNX2_RV2P_INSTR_HIGH                           0x00002830
+#define BNX2_RV2P_INSTR_HIGH_HIGH                       (0x1fL<<0)
+
+#define BNX2_RV2P_INSTR_LOW                            0x00002834
+#define BNX2_RV2P_PROC1_ADDR_CMD                       0x00002838
+#define BNX2_RV2P_PROC1_ADDR_CMD_ADD                    (0x3ffL<<0)
+#define BNX2_RV2P_PROC1_ADDR_CMD_RDWR                   (1L<<31)
+
+#define BNX2_RV2P_PROC2_ADDR_CMD                       0x0000283c
+#define BNX2_RV2P_PROC2_ADDR_CMD_ADD                    (0x3ffL<<0)
+#define BNX2_RV2P_PROC2_ADDR_CMD_RDWR                   (1L<<31)
+
+#define BNX2_RV2P_PROC1_GRC_DEBUG                      0x00002840
+#define BNX2_RV2P_PROC2_GRC_DEBUG                      0x00002844
+#define BNX2_RV2P_GRC_PROC_DEBUG                       0x00002848
+#define BNX2_RV2P_DEBUG_VECT_PEEK                      0x0000284c
+#define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE               (0x7ffL<<0)
+#define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN             (1L<<11)
+#define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL                         (0xfL<<12)
+#define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE               (0x7ffL<<16)
+#define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN             (1L<<27)
+#define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL                         (0xfL<<28)
+
+#define BNX2_RV2P_PFTQ_DATA                            0x00002b40
+#define BNX2_RV2P_PFTQ_CMD                             0x00002b78
+#define BNX2_RV2P_PFTQ_CMD_OFFSET                       (0x3ffL<<0)
+#define BNX2_RV2P_PFTQ_CMD_WR_TOP                       (1L<<10)
+#define BNX2_RV2P_PFTQ_CMD_WR_TOP_0                     (0L<<10)
+#define BNX2_RV2P_PFTQ_CMD_WR_TOP_1                     (1L<<10)
+#define BNX2_RV2P_PFTQ_CMD_SFT_RESET                    (1L<<25)
+#define BNX2_RV2P_PFTQ_CMD_RD_DATA                      (1L<<26)
+#define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN                         (1L<<27)
+#define BNX2_RV2P_PFTQ_CMD_ADD_DATA                     (1L<<28)
+#define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR                (1L<<29)
+#define BNX2_RV2P_PFTQ_CMD_POP                          (1L<<30)
+#define BNX2_RV2P_PFTQ_CMD_BUSY                                 (1L<<31)
+
+#define BNX2_RV2P_PFTQ_CTL                             0x00002b7c
+#define BNX2_RV2P_PFTQ_CTL_INTERVENE                    (1L<<0)
+#define BNX2_RV2P_PFTQ_CTL_OVERFLOW                     (1L<<1)
+#define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE              (1L<<2)
+#define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH                    (0x3ffL<<12)
+#define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH                    (0x3ffL<<22)
+
+#define BNX2_RV2P_TFTQ_DATA                            0x00002b80
+#define BNX2_RV2P_TFTQ_CMD                             0x00002bb8
+#define BNX2_RV2P_TFTQ_CMD_OFFSET                       (0x3ffL<<0)
+#define BNX2_RV2P_TFTQ_CMD_WR_TOP                       (1L<<10)
+#define BNX2_RV2P_TFTQ_CMD_WR_TOP_0                     (0L<<10)
+#define BNX2_RV2P_TFTQ_CMD_WR_TOP_1                     (1L<<10)
+#define BNX2_RV2P_TFTQ_CMD_SFT_RESET                    (1L<<25)
+#define BNX2_RV2P_TFTQ_CMD_RD_DATA                      (1L<<26)
+#define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN                         (1L<<27)
+#define BNX2_RV2P_TFTQ_CMD_ADD_DATA                     (1L<<28)
+#define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR                (1L<<29)
+#define BNX2_RV2P_TFTQ_CMD_POP                          (1L<<30)
+#define BNX2_RV2P_TFTQ_CMD_BUSY                                 (1L<<31)
+
+#define BNX2_RV2P_TFTQ_CTL                             0x00002bbc
+#define BNX2_RV2P_TFTQ_CTL_INTERVENE                    (1L<<0)
+#define BNX2_RV2P_TFTQ_CTL_OVERFLOW                     (1L<<1)
+#define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE              (1L<<2)
+#define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH                    (0x3ffL<<12)
+#define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH                    (0x3ffL<<22)
+
+#define BNX2_RV2P_MFTQ_DATA                            0x00002bc0
+#define BNX2_RV2P_MFTQ_CMD                             0x00002bf8
+#define BNX2_RV2P_MFTQ_CMD_OFFSET                       (0x3ffL<<0)
+#define BNX2_RV2P_MFTQ_CMD_WR_TOP                       (1L<<10)
+#define BNX2_RV2P_MFTQ_CMD_WR_TOP_0                     (0L<<10)
+#define BNX2_RV2P_MFTQ_CMD_WR_TOP_1                     (1L<<10)
+#define BNX2_RV2P_MFTQ_CMD_SFT_RESET                    (1L<<25)
+#define BNX2_RV2P_MFTQ_CMD_RD_DATA                      (1L<<26)
+#define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN                         (1L<<27)
+#define BNX2_RV2P_MFTQ_CMD_ADD_DATA                     (1L<<28)
+#define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR                (1L<<29)
+#define BNX2_RV2P_MFTQ_CMD_POP                          (1L<<30)
+#define BNX2_RV2P_MFTQ_CMD_BUSY                                 (1L<<31)
+
+#define BNX2_RV2P_MFTQ_CTL                             0x00002bfc
+#define BNX2_RV2P_MFTQ_CTL_INTERVENE                    (1L<<0)
+#define BNX2_RV2P_MFTQ_CTL_OVERFLOW                     (1L<<1)
+#define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE              (1L<<2)
+#define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH                    (0x3ffL<<12)
+#define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH                    (0x3ffL<<22)
+
+
+
+/*
+ *  mq_reg definition
+ *  offset: 0x3c00
+ */
+#define BNX2_MQ_COMMAND                                        0x00003c00
+#define BNX2_MQ_COMMAND_ENABLED                                 (1L<<0)
+#define BNX2_MQ_COMMAND_OVERFLOW                        (1L<<4)
+#define BNX2_MQ_COMMAND_WR_ERROR                        (1L<<5)
+#define BNX2_MQ_COMMAND_RD_ERROR                        (1L<<6)
+
+#define BNX2_MQ_STATUS                                 0x00003c04
+#define BNX2_MQ_STATUS_CTX_ACCESS_STAT                  (1L<<16)
+#define BNX2_MQ_STATUS_CTX_ACCESS64_STAT                (1L<<17)
+#define BNX2_MQ_STATUS_PCI_STALL_STAT                   (1L<<18)
+
+#define BNX2_MQ_CONFIG                                 0x00003c08
+#define BNX2_MQ_CONFIG_TX_HIGH_PRI                      (1L<<0)
+#define BNX2_MQ_CONFIG_HALT_DIS                                 (1L<<1)
+#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE                         (0x7L<<4)
+#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256             (0L<<4)
+#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512             (1L<<4)
+#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K              (2L<<4)
+#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K              (3L<<4)
+#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K              (4L<<4)
+#define BNX2_MQ_CONFIG_MAX_DEPTH                        (0x7fL<<8)
+#define BNX2_MQ_CONFIG_CUR_DEPTH                        (0x7fL<<20)
+
+#define BNX2_MQ_ENQUEUE1                               0x00003c0c
+#define BNX2_MQ_ENQUEUE1_OFFSET                                 (0x3fL<<2)
+#define BNX2_MQ_ENQUEUE1_CID                            (0x3fffL<<8)
+#define BNX2_MQ_ENQUEUE1_BYTE_MASK                      (0xfL<<24)
+#define BNX2_MQ_ENQUEUE1_KNL_MODE                       (1L<<28)
+
+#define BNX2_MQ_ENQUEUE2                               0x00003c10
+#define BNX2_MQ_BAD_WR_ADDR                            0x00003c14
+#define BNX2_MQ_BAD_RD_ADDR                            0x00003c18
+#define BNX2_MQ_KNL_BYP_WIND_START                     0x00003c1c
+#define BNX2_MQ_KNL_BYP_WIND_START_VALUE                (0xfffffL<<12)
+
+#define BNX2_MQ_KNL_WIND_END                           0x00003c20
+#define BNX2_MQ_KNL_WIND_END_VALUE                      (0xffffffL<<8)
+
+#define BNX2_MQ_KNL_WRITE_MASK1                                0x00003c24
+#define BNX2_MQ_KNL_TX_MASK1                           0x00003c28
+#define BNX2_MQ_KNL_CMD_MASK1                          0x00003c2c
+#define BNX2_MQ_KNL_COND_ENQUEUE_MASK1                 0x00003c30
+#define BNX2_MQ_KNL_RX_V2P_MASK1                       0x00003c34
+#define BNX2_MQ_KNL_WRITE_MASK2                                0x00003c38
+#define BNX2_MQ_KNL_TX_MASK2                           0x00003c3c
+#define BNX2_MQ_KNL_CMD_MASK2                          0x00003c40
+#define BNX2_MQ_KNL_COND_ENQUEUE_MASK2                 0x00003c44
+#define BNX2_MQ_KNL_RX_V2P_MASK2                       0x00003c48
+#define BNX2_MQ_KNL_BYP_WRITE_MASK1                    0x00003c4c
+#define BNX2_MQ_KNL_BYP_TX_MASK1                       0x00003c50
+#define BNX2_MQ_KNL_BYP_CMD_MASK1                      0x00003c54
+#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1             0x00003c58
+#define BNX2_MQ_KNL_BYP_RX_V2P_MASK1                   0x00003c5c
+#define BNX2_MQ_KNL_BYP_WRITE_MASK2                    0x00003c60
+#define BNX2_MQ_KNL_BYP_TX_MASK2                       0x00003c64
+#define BNX2_MQ_KNL_BYP_CMD_MASK2                      0x00003c68
+#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2             0x00003c6c
+#define BNX2_MQ_KNL_BYP_RX_V2P_MASK2                   0x00003c70
+#define BNX2_MQ_MEM_WR_ADDR                            0x00003c74
+#define BNX2_MQ_MEM_WR_ADDR_VALUE                       (0x3fL<<0)
+
+#define BNX2_MQ_MEM_WR_DATA0                           0x00003c78
+#define BNX2_MQ_MEM_WR_DATA0_VALUE                      (0xffffffffL<<0)
+
+#define BNX2_MQ_MEM_WR_DATA1                           0x00003c7c
+#define BNX2_MQ_MEM_WR_DATA1_VALUE                      (0xffffffffL<<0)
+
+#define BNX2_MQ_MEM_WR_DATA2                           0x00003c80
+#define BNX2_MQ_MEM_WR_DATA2_VALUE                      (0x3fffffffL<<0)
+
+#define BNX2_MQ_MEM_RD_ADDR                            0x00003c84
+#define BNX2_MQ_MEM_RD_ADDR_VALUE                       (0x3fL<<0)
+
+#define BNX2_MQ_MEM_RD_DATA0                           0x00003c88
+#define BNX2_MQ_MEM_RD_DATA0_VALUE                      (0xffffffffL<<0)
+
+#define BNX2_MQ_MEM_RD_DATA1                           0x00003c8c
+#define BNX2_MQ_MEM_RD_DATA1_VALUE                      (0xffffffffL<<0)
+
+#define BNX2_MQ_MEM_RD_DATA2                           0x00003c90
+#define BNX2_MQ_MEM_RD_DATA2_VALUE                      (0x3fffffffL<<0)
+
+
+
+/*
+ *  tbdr_reg definition
+ *  offset: 0x5000
+ */
+#define BNX2_TBDR_COMMAND                              0x00005000
+#define BNX2_TBDR_COMMAND_ENABLE                        (1L<<0)
+#define BNX2_TBDR_COMMAND_SOFT_RST                      (1L<<1)
+#define BNX2_TBDR_COMMAND_MSTR_ABORT                    (1L<<4)
+
+#define BNX2_TBDR_STATUS                               0x00005004
+#define BNX2_TBDR_STATUS_DMA_WAIT                       (1L<<0)
+#define BNX2_TBDR_STATUS_FTQ_WAIT                       (1L<<1)
+#define BNX2_TBDR_STATUS_FIFO_OVERFLOW                  (1L<<2)
+#define BNX2_TBDR_STATUS_FIFO_UNDERFLOW                         (1L<<3)
+#define BNX2_TBDR_STATUS_SEARCHMISS_ERROR               (1L<<4)
+#define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT                  (1L<<5)
+#define BNX2_TBDR_STATUS_BURST_CNT                      (1L<<6)
+
+#define BNX2_TBDR_CONFIG                               0x00005008
+#define BNX2_TBDR_CONFIG_MAX_BDS                        (0xffL<<0)
+#define BNX2_TBDR_CONFIG_SWAP_MODE                      (1L<<8)
+#define BNX2_TBDR_CONFIG_PRIORITY                       (1L<<9)
+#define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS           (1L<<10)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE                      (0xfL<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_256                  (0L<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_512                  (1L<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_1K                   (2L<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_2K                   (3L<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_4K                   (4L<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_8K                   (5L<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_16K                  (6L<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_32K                  (7L<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_64K                  (8L<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_128K                         (9L<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_256K                         (10L<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_512K                         (11L<<24)
+#define BNX2_TBDR_CONFIG_PAGE_SIZE_1M                   (12L<<24)
+
+#define BNX2_TBDR_DEBUG_VECT_PEEK                      0x0000500c
+#define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE               (0x7ffL<<0)
+#define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN             (1L<<11)
+#define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL                         (0xfL<<12)
+#define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE               (0x7ffL<<16)
+#define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN             (1L<<27)
+#define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL                         (0xfL<<28)
+
+#define BNX2_TBDR_FTQ_DATA                             0x000053c0
+#define BNX2_TBDR_FTQ_CMD                              0x000053f8
+#define BNX2_TBDR_FTQ_CMD_OFFSET                        (0x3ffL<<0)
+#define BNX2_TBDR_FTQ_CMD_WR_TOP                        (1L<<10)
+#define BNX2_TBDR_FTQ_CMD_WR_TOP_0                      (0L<<10)
+#define BNX2_TBDR_FTQ_CMD_WR_TOP_1                      (1L<<10)
+#define BNX2_TBDR_FTQ_CMD_SFT_RESET                     (1L<<25)
+#define BNX2_TBDR_FTQ_CMD_RD_DATA                       (1L<<26)
+#define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN                  (1L<<27)
+#define BNX2_TBDR_FTQ_CMD_ADD_DATA                      (1L<<28)
+#define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR                         (1L<<29)
+#define BNX2_TBDR_FTQ_CMD_POP                           (1L<<30)
+#define BNX2_TBDR_FTQ_CMD_BUSY                          (1L<<31)
+
+#define BNX2_TBDR_FTQ_CTL                              0x000053fc
+#define BNX2_TBDR_FTQ_CTL_INTERVENE                     (1L<<0)
+#define BNX2_TBDR_FTQ_CTL_OVERFLOW                      (1L<<1)
+#define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE               (1L<<2)
+#define BNX2_TBDR_FTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
+#define BNX2_TBDR_FTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
+
+
+
+/*
+ *  tdma_reg definition
+ *  offset: 0x5c00
+ */
+#define BNX2_TDMA_COMMAND                              0x00005c00
+#define BNX2_TDMA_COMMAND_ENABLED                       (1L<<0)
+#define BNX2_TDMA_COMMAND_MASTER_ABORT                  (1L<<4)
+#define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT           (1L<<7)
+
+#define BNX2_TDMA_STATUS                               0x00005c04
+#define BNX2_TDMA_STATUS_DMA_WAIT                       (1L<<0)
+#define BNX2_TDMA_STATUS_PAYLOAD_WAIT                   (1L<<1)
+#define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT                         (1L<<2)
+#define BNX2_TDMA_STATUS_LOCK_WAIT                      (1L<<3)
+#define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT                  (1L<<16)
+#define BNX2_TDMA_STATUS_BURST_CNT                      (1L<<17)
+
+#define BNX2_TDMA_CONFIG                               0x00005c08
+#define BNX2_TDMA_CONFIG_ONE_DMA                        (1L<<0)
+#define BNX2_TDMA_CONFIG_ONE_RECORD                     (1L<<1)
+#define BNX2_TDMA_CONFIG_LIMIT_SZ                       (0xfL<<4)
+#define BNX2_TDMA_CONFIG_LIMIT_SZ_64                    (0L<<4)
+#define BNX2_TDMA_CONFIG_LIMIT_SZ_128                   (0x4L<<4)
+#define BNX2_TDMA_CONFIG_LIMIT_SZ_256                   (0x6L<<4)
+#define BNX2_TDMA_CONFIG_LIMIT_SZ_512                   (0x8L<<4)
+#define BNX2_TDMA_CONFIG_LINE_SZ                        (0xfL<<8)
+#define BNX2_TDMA_CONFIG_LINE_SZ_64                     (0L<<8)
+#define BNX2_TDMA_CONFIG_LINE_SZ_128                    (4L<<8)
+#define BNX2_TDMA_CONFIG_LINE_SZ_256                    (6L<<8)
+#define BNX2_TDMA_CONFIG_LINE_SZ_512                    (8L<<8)
+#define BNX2_TDMA_CONFIG_ALIGN_ENA                      (1L<<15)
+#define BNX2_TDMA_CONFIG_CHK_L2_BD                      (1L<<16)
+#define BNX2_TDMA_CONFIG_FIFO_CMP                       (0xfL<<20)
+
+#define BNX2_TDMA_PAYLOAD_PROD                         0x00005c0c
+#define BNX2_TDMA_PAYLOAD_PROD_VALUE                    (0x1fffL<<3)
+
+#define BNX2_TDMA_DBG_WATCHDOG                         0x00005c10
+#define BNX2_TDMA_DBG_TRIGGER                          0x00005c14
+#define BNX2_TDMA_DMAD_FSM                             0x00005c80
+#define BNX2_TDMA_DMAD_FSM_BD_INVLD                     (1L<<0)
+#define BNX2_TDMA_DMAD_FSM_PUSH                                 (0xfL<<4)
+#define BNX2_TDMA_DMAD_FSM_ARB_TBDC                     (0x3L<<8)
+#define BNX2_TDMA_DMAD_FSM_ARB_CTX                      (1L<<12)
+#define BNX2_TDMA_DMAD_FSM_DR_INTF                      (1L<<16)
+#define BNX2_TDMA_DMAD_FSM_DMAD                                 (0x7L<<20)
+#define BNX2_TDMA_DMAD_FSM_BD                           (0xfL<<24)
+
+#define BNX2_TDMA_DMAD_STATUS                          0x00005c84
+#define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY          (0x3L<<0)
+#define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY          (0x3L<<4)
+#define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY            (0x3L<<8)
+#define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM                         (0xfL<<12)
+
+#define BNX2_TDMA_DR_INTF_FSM                          0x00005c88
+#define BNX2_TDMA_DR_INTF_FSM_L2_COMP                   (0x3L<<0)
+#define BNX2_TDMA_DR_INTF_FSM_TPATQ                     (0x7L<<4)
+#define BNX2_TDMA_DR_INTF_FSM_TPBUF                     (0x3L<<8)
+#define BNX2_TDMA_DR_INTF_FSM_DR_BUF                    (0x7L<<12)
+#define BNX2_TDMA_DR_INTF_FSM_DMAD                      (0x7L<<16)
+
+#define BNX2_TDMA_DR_INTF_STATUS                       0x00005c8c
+#define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE             (0x7L<<0)
+#define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL             (0x3L<<4)
+#define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR             (0x7L<<8)
+#define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR               (0xfL<<12)
+#define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT             (0x7L<<16)
+
+#define BNX2_TDMA_FTQ_DATA                             0x00005fc0
+#define BNX2_TDMA_FTQ_CMD                              0x00005ff8
+#define BNX2_TDMA_FTQ_CMD_OFFSET                        (0x3ffL<<0)
+#define BNX2_TDMA_FTQ_CMD_WR_TOP                        (1L<<10)
+#define BNX2_TDMA_FTQ_CMD_WR_TOP_0                      (0L<<10)
+#define BNX2_TDMA_FTQ_CMD_WR_TOP_1                      (1L<<10)
+#define BNX2_TDMA_FTQ_CMD_SFT_RESET                     (1L<<25)
+#define BNX2_TDMA_FTQ_CMD_RD_DATA                       (1L<<26)
+#define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN                  (1L<<27)
+#define BNX2_TDMA_FTQ_CMD_ADD_DATA                      (1L<<28)
+#define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR                         (1L<<29)
+#define BNX2_TDMA_FTQ_CMD_POP                           (1L<<30)
+#define BNX2_TDMA_FTQ_CMD_BUSY                          (1L<<31)
+
+#define BNX2_TDMA_FTQ_CTL                              0x00005ffc
+#define BNX2_TDMA_FTQ_CTL_INTERVENE                     (1L<<0)
+#define BNX2_TDMA_FTQ_CTL_OVERFLOW                      (1L<<1)
+#define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE               (1L<<2)
+#define BNX2_TDMA_FTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
+#define BNX2_TDMA_FTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
+
+
+
+/*
+ *  hc_reg definition
+ *  offset: 0x6800
+ */
+#define BNX2_HC_COMMAND                                        0x00006800
+#define BNX2_HC_COMMAND_ENABLE                          (1L<<0)
+#define BNX2_HC_COMMAND_SKIP_ABORT                      (1L<<4)
+#define BNX2_HC_COMMAND_COAL_NOW                        (1L<<16)
+#define BNX2_HC_COMMAND_COAL_NOW_WO_INT                         (1L<<17)
+#define BNX2_HC_COMMAND_STATS_NOW                       (1L<<18)
+#define BNX2_HC_COMMAND_FORCE_INT                       (0x3L<<19)
+#define BNX2_HC_COMMAND_FORCE_INT_NULL                  (0L<<19)
+#define BNX2_HC_COMMAND_FORCE_INT_HIGH                  (1L<<19)
+#define BNX2_HC_COMMAND_FORCE_INT_LOW                   (2L<<19)
+#define BNX2_HC_COMMAND_FORCE_INT_FREE                  (3L<<19)
+#define BNX2_HC_COMMAND_CLR_STAT_NOW                    (1L<<21)
+
+#define BNX2_HC_STATUS                                 0x00006804
+#define BNX2_HC_STATUS_MASTER_ABORT                     (1L<<0)
+#define BNX2_HC_STATUS_PARITY_ERROR_STATE               (1L<<1)
+#define BNX2_HC_STATUS_PCI_CLK_CNT_STAT                         (1L<<16)
+#define BNX2_HC_STATUS_CORE_CLK_CNT_STAT                (1L<<17)
+#define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT           (1L<<18)
+#define BNX2_HC_STATUS_NUM_INT_GEN_STAT                         (1L<<19)
+#define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT             (1L<<20)
+#define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT      (1L<<23)
+#define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT      (1L<<24)
+#define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT  (1L<<25)
+
+#define BNX2_HC_CONFIG                                 0x00006808
+#define BNX2_HC_CONFIG_COLLECT_STATS                    (1L<<0)
+#define BNX2_HC_CONFIG_RX_TMR_MODE                      (1L<<1)
+#define BNX2_HC_CONFIG_TX_TMR_MODE                      (1L<<2)
+#define BNX2_HC_CONFIG_COM_TMR_MODE                     (1L<<3)
+#define BNX2_HC_CONFIG_CMD_TMR_MODE                     (1L<<4)
+#define BNX2_HC_CONFIG_STATISTIC_PRIORITY               (1L<<5)
+#define BNX2_HC_CONFIG_STATUS_PRIORITY                  (1L<<6)
+#define BNX2_HC_CONFIG_STAT_MEM_ADDR                    (0xffL<<8)
+
+#define BNX2_HC_ATTN_BITS_ENABLE                       0x0000680c
+#define BNX2_HC_STATUS_ADDR_L                          0x00006810
+#define BNX2_HC_STATUS_ADDR_H                          0x00006814
+#define BNX2_HC_STATISTICS_ADDR_L                      0x00006818
+#define BNX2_HC_STATISTICS_ADDR_H                      0x0000681c
+#define BNX2_HC_TX_QUICK_CONS_TRIP                     0x00006820
+#define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE                (0xffL<<0)
+#define BNX2_HC_TX_QUICK_CONS_TRIP_INT                  (0xffL<<16)
+
+#define BNX2_HC_COMP_PROD_TRIP                         0x00006824
+#define BNX2_HC_COMP_PROD_TRIP_VALUE                    (0xffL<<0)
+#define BNX2_HC_COMP_PROD_TRIP_INT                      (0xffL<<16)
+
+#define BNX2_HC_RX_QUICK_CONS_TRIP                     0x00006828
+#define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE                (0xffL<<0)
+#define BNX2_HC_RX_QUICK_CONS_TRIP_INT                  (0xffL<<16)
+
+#define BNX2_HC_RX_TICKS                               0x0000682c
+#define BNX2_HC_RX_TICKS_VALUE                          (0x3ffL<<0)
+#define BNX2_HC_RX_TICKS_INT                            (0x3ffL<<16)
+
+#define BNX2_HC_TX_TICKS                               0x00006830
+#define BNX2_HC_TX_TICKS_VALUE                          (0x3ffL<<0)
+#define BNX2_HC_TX_TICKS_INT                            (0x3ffL<<16)
+
+#define BNX2_HC_COM_TICKS                              0x00006834
+#define BNX2_HC_COM_TICKS_VALUE                                 (0x3ffL<<0)
+#define BNX2_HC_COM_TICKS_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_CMD_TICKS                              0x00006838
+#define BNX2_HC_CMD_TICKS_VALUE                                 (0x3ffL<<0)
+#define BNX2_HC_CMD_TICKS_INT                           (0x3ffL<<16)
+
+#define BNX2_HC_PERIODIC_TICKS                         0x0000683c
+#define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS        (0xffffL<<0)
+
+#define BNX2_HC_STAT_COLLECT_TICKS                     0x00006840
+#define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS   (0xffL<<4)
+
+#define BNX2_HC_STATS_TICKS                            0x00006844
+#define BNX2_HC_STATS_TICKS_HC_STAT_TICKS               (0xffffL<<8)
+
+#define BNX2_HC_STAT_MEM_DATA                          0x0000684c
+#define BNX2_HC_STAT_GEN_SEL_0                         0x00006850
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0                (0x7fL<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0      (0L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1      (1L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2      (2L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3      (3L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4      (4L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5      (5L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6      (6L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7      (7L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8      (8L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9      (9L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10     (10L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11     (11L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0      (12L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1      (13L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2      (14L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3      (15L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4      (16L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5      (17L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6      (18L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7      (19L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0      (20L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1      (21L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2      (22L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3      (23L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4      (24L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5      (25L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6      (26L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7      (27L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8      (28L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9      (29L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10     (30L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11     (31L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0     (32L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1     (33L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2     (34L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3     (35L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0       (36L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1       (37L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2       (38L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3       (39L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4       (40L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5       (41L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6       (42L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7       (43L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0      (44L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1      (45L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2      (46L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3      (47L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4      (48L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5      (49L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6      (50L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7      (51L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT    (52L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT   (53L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS   (54L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN         (55L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR     (56L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK      
(59L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK      
(60L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK  
(61L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT   (62L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT  (63L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT   (64L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT  (65L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT        (66L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT         (67L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT        (68L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT       (69L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT       (70L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT       (71L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT        (72L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT        (73L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT        (74L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT         (75L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT        (76L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT        (77L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT         (78L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT  (79L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT  (80L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT        (81L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT        (82L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT         (83L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT         (84L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT        
(85L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT   
(86L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT    
(87L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT      
 (88L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT    
 (89L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT       
(90L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT  
(91L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT   
(92L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT     
 (93L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT   
 (94L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64   (95L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64   (96L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS     (97L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS    (98L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT    (99L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT  (100L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT     (101L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT     (102L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT         (103L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT     (104L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT         (105L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT     (106L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT         (107L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT         (108L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT      (109L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT   (110L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT   (111L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT   (112L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT   (113L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT   (114L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0     (115L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1     (116L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2     (117L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3     (118L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4     (119L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5     (120L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS        (121L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS        (122L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT         (127L<<0)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1                (0x7fL<<8)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2                (0x7fL<<16)
+#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3                (0x7fL<<24)
+
+#define BNX2_HC_STAT_GEN_SEL_1                         0x00006854
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4                (0x7fL<<0)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5                (0x7fL<<8)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6                (0x7fL<<16)
+#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7                (0x7fL<<24)
+
+#define BNX2_HC_STAT_GEN_SEL_2                         0x00006858
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8                (0x7fL<<0)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9                (0x7fL<<8)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10               (0x7fL<<16)
+#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11               (0x7fL<<24)
+
+#define BNX2_HC_STAT_GEN_SEL_3                         0x0000685c
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12               (0x7fL<<0)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13               (0x7fL<<8)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14               (0x7fL<<16)
+#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15               (0x7fL<<24)
+
+#define BNX2_HC_STAT_GEN_STAT0                         0x00006888
+#define BNX2_HC_STAT_GEN_STAT1                         0x0000688c
+#define BNX2_HC_STAT_GEN_STAT2                         0x00006890
+#define BNX2_HC_STAT_GEN_STAT3                         0x00006894
+#define BNX2_HC_STAT_GEN_STAT4                         0x00006898
+#define BNX2_HC_STAT_GEN_STAT5                         0x0000689c
+#define BNX2_HC_STAT_GEN_STAT6                         0x000068a0
+#define BNX2_HC_STAT_GEN_STAT7                         0x000068a4
+#define BNX2_HC_STAT_GEN_STAT8                         0x000068a8
+#define BNX2_HC_STAT_GEN_STAT9                         0x000068ac
+#define BNX2_HC_STAT_GEN_STAT10                                0x000068b0
+#define BNX2_HC_STAT_GEN_STAT11                                0x000068b4
+#define BNX2_HC_STAT_GEN_STAT12                                0x000068b8
+#define BNX2_HC_STAT_GEN_STAT13                                0x000068bc
+#define BNX2_HC_STAT_GEN_STAT14                                0x000068c0
+#define BNX2_HC_STAT_GEN_STAT15                                0x000068c4
+#define BNX2_HC_STAT_GEN_STAT_AC0                      0x000068c8
+#define BNX2_HC_STAT_GEN_STAT_AC1                      0x000068cc
+#define BNX2_HC_STAT_GEN_STAT_AC2                      0x000068d0
+#define BNX2_HC_STAT_GEN_STAT_AC3                      0x000068d4
+#define BNX2_HC_STAT_GEN_STAT_AC4                      0x000068d8
+#define BNX2_HC_STAT_GEN_STAT_AC5                      0x000068dc
+#define BNX2_HC_STAT_GEN_STAT_AC6                      0x000068e0
+#define BNX2_HC_STAT_GEN_STAT_AC7                      0x000068e4
+#define BNX2_HC_STAT_GEN_STAT_AC8                      0x000068e8
+#define BNX2_HC_STAT_GEN_STAT_AC9                      0x000068ec
+#define BNX2_HC_STAT_GEN_STAT_AC10                     0x000068f0
+#define BNX2_HC_STAT_GEN_STAT_AC11                     0x000068f4
+#define BNX2_HC_STAT_GEN_STAT_AC12                     0x000068f8
+#define BNX2_HC_STAT_GEN_STAT_AC13                     0x000068fc
+#define BNX2_HC_STAT_GEN_STAT_AC14                     0x00006900
+#define BNX2_HC_STAT_GEN_STAT_AC15                     0x00006904
+#define BNX2_HC_VIS                                    0x00006908
+#define BNX2_HC_VIS_STAT_BUILD_STATE                    (0xfL<<0)
+#define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE               (0L<<0)
+#define BNX2_HC_VIS_STAT_BUILD_STATE_START              (1L<<0)
+#define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST            (2L<<0)
+#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64           (3L<<0)
+#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32           (4L<<0)
+#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE        (5L<<0)
+#define BNX2_HC_VIS_STAT_BUILD_STATE_DMA                (6L<<0)
+#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL        (7L<<0)
+#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW            (8L<<0)
+#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH           (9L<<0)
+#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA           (10L<<0)
+#define BNX2_HC_VIS_DMA_STAT_STATE                      (0xfL<<8)
+#define BNX2_HC_VIS_DMA_STAT_STATE_IDLE                         (0L<<8)
+#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM                 (1L<<8)
+#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA           (2L<<8)
+#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP           (3L<<8)
+#define BNX2_HC_VIS_DMA_STAT_STATE_COMP                         (4L<<8)
+#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM      (5L<<8)
+#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA        (6L<<8)
+#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1                 (7L<<8)
+#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2                 (8L<<8)
+#define BNX2_HC_VIS_DMA_STAT_STATE_WAIT                         (9L<<8)
+#define BNX2_HC_VIS_DMA_STAT_STATE_ABORT                (15L<<8)
+#define BNX2_HC_VIS_DMA_MSI_STATE                       (0x7L<<12)
+#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE              (0x3L<<15)
+#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE                 (0L<<15)
+#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT        (1L<<15)
+#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START        (2L<<15)
+
+#define BNX2_HC_VIS_1                                  0x0000690c
+#define BNX2_HC_VIS_1_HW_INTACK_STATE                   (1L<<4)
+#define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE              (0L<<4)
+#define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT             (1L<<4)
+#define BNX2_HC_VIS_1_SW_INTACK_STATE                   (1L<<5)
+#define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE              (0L<<5)
+#define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT             (1L<<5)
+#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE            (1L<<6)
+#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE       (0L<<6)
+#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT      (1L<<6)
+#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE               (1L<<7)
+#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE          (0L<<7)
+#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT                 (1L<<7)
+#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE                  (0xfL<<17)
+#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE             (0L<<17)
+#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA              (1L<<17)
+#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE           (2L<<17)
+#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN           (3L<<17)
+#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT             (4L<<17)
+#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE       (5L<<17)
+#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN       (6L<<17)
+#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT                 (7L<<17)
+#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE                  (0x3L<<21)
+#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL           (0L<<21)
+#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR            (1L<<21)
+#define BNX2_HC_VIS_1_INT_GEN_STATE                     (1L<<23)
+#define BNX2_HC_VIS_1_INT_GEN_STATE_DLE                         (0L<<23)
+#define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT            (1L<<23)
+#define BNX2_HC_VIS_1_STAT_CHAN_ID                      (0x7L<<24)
+#define BNX2_HC_VIS_1_INT_B                             (1L<<27)
+
+#define BNX2_HC_DEBUG_VECT_PEEK                                0x00006910
+#define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE                         (0x7ffL<<0)
+#define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN               (1L<<11)
+#define BNX2_HC_DEBUG_VECT_PEEK_1_SEL                   (0xfL<<12)
+#define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE                         (0x7ffL<<16)
+#define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN               (1L<<27)
+#define BNX2_HC_DEBUG_VECT_PEEK_2_SEL                   (0xfL<<28)
+
+
+
+/*
+ *  txp_reg definition
+ *  offset: 0x40000
+ */
+#define BNX2_TXP_CPU_MODE                              0x00045000
+#define BNX2_TXP_CPU_MODE_LOCAL_RST                     (1L<<0)
+#define BNX2_TXP_CPU_MODE_STEP_ENA                      (1L<<1)
+#define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA               (1L<<2)
+#define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA               (1L<<3)
+#define BNX2_TXP_CPU_MODE_MSG_BIT1                      (1L<<6)
+#define BNX2_TXP_CPU_MODE_INTERRUPT_ENA                         (1L<<7)
+#define BNX2_TXP_CPU_MODE_SOFT_HALT                     (1L<<10)
+#define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA             (1L<<11)
+#define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA             (1L<<12)
+#define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA            (1L<<13)
+#define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA       (1L<<15)
+
+#define BNX2_TXP_CPU_STATE                             0x00045004
+#define BNX2_TXP_CPU_STATE_BREAKPOINT                   (1L<<0)
+#define BNX2_TXP_CPU_STATE_BAD_INST_HALTED              (1L<<2)
+#define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED           (1L<<3)
+#define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED           (1L<<4)
+#define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED                 (1L<<5)
+#define BNX2_TXP_CPU_STATE_BAD_pc_HALTED                (1L<<6)
+#define BNX2_TXP_CPU_STATE_ALIGN_HALTED                         (1L<<7)
+#define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED             (1L<<8)
+#define BNX2_TXP_CPU_STATE_SOFT_HALTED                  (1L<<10)
+#define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW               (1L<<11)
+#define BNX2_TXP_CPU_STATE_INTERRRUPT                   (1L<<12)
+#define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL            (1L<<14)
+#define BNX2_TXP_CPU_STATE_INST_FETCH_STALL             (1L<<15)
+#define BNX2_TXP_CPU_STATE_BLOCKED_READ                         (1L<<31)
+
+#define BNX2_TXP_CPU_EVENT_MASK                                0x00045008
+#define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK                 (1L<<0)
+#define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK    (1L<<2)
+#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK         (1L<<3)
+#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK         (1L<<4)
+#define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK       (1L<<5)
+#define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK      (1L<<6)
+#define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK       (1L<<7)
+#define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK          (1L<<8)
+#define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK        (1L<<10)
+#define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK     (1L<<11)
+#define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK          (1L<<12)
+
+#define BNX2_TXP_CPU_PROGRAM_COUNTER                   0x0004501c
+#define BNX2_TXP_CPU_INSTRUCTION                       0x00045020
+#define BNX2_TXP_CPU_DATA_ACCESS                       0x00045024
+#define BNX2_TXP_CPU_INTERRUPT_ENABLE                  0x00045028
+#define BNX2_TXP_CPU_INTERRUPT_VECTOR                  0x0004502c
+#define BNX2_TXP_CPU_INTERRUPT_SAVED_PC                        0x00045030
+#define BNX2_TXP_CPU_HW_BREAKPOINT                     0x00045034
+#define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE              (1L<<0)
+#define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS              (0x3fffffffL<<2)
+
+#define BNX2_TXP_CPU_DEBUG_VECT_PEEK                   0x00045038
+#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE            (0x7ffL<<0)
+#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN          (1L<<11)
+#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL              (0xfL<<12)
+#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE            (0x7ffL<<16)
+#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN          (1L<<27)
+#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL              (0xfL<<28)
+
+#define BNX2_TXP_CPU_LAST_BRANCH_ADDR                  0x00045048
+#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE              (1L<<1)
+#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP                 (0L<<1)
+#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH       (1L<<1)
+#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA               (0x3fffffffL<<2)
+
+#define BNX2_TXP_CPU_REG_FILE                          0x00045200
+#define BNX2_TXP_FTQ_DATA                              0x000453c0
+#define BNX2_TXP_FTQ_CMD                               0x000453f8
+#define BNX2_TXP_FTQ_CMD_OFFSET                                 (0x3ffL<<0)
+#define BNX2_TXP_FTQ_CMD_WR_TOP                                 (1L<<10)
+#define BNX2_TXP_FTQ_CMD_WR_TOP_0                       (0L<<10)
+#define BNX2_TXP_FTQ_CMD_WR_TOP_1                       (1L<<10)
+#define BNX2_TXP_FTQ_CMD_SFT_RESET                      (1L<<25)
+#define BNX2_TXP_FTQ_CMD_RD_DATA                        (1L<<26)
+#define BNX2_TXP_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
+#define BNX2_TXP_FTQ_CMD_ADD_DATA                       (1L<<28)
+#define BNX2_TXP_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
+#define BNX2_TXP_FTQ_CMD_POP                            (1L<<30)
+#define BNX2_TXP_FTQ_CMD_BUSY                           (1L<<31)
+
+#define BNX2_TXP_FTQ_CTL                               0x000453fc
+#define BNX2_TXP_FTQ_CTL_INTERVENE                      (1L<<0)
+#define BNX2_TXP_FTQ_CTL_OVERFLOW                       (1L<<1)
+#define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
+#define BNX2_TXP_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
+#define BNX2_TXP_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
+
+#define BNX2_TXP_SCRATCH                               0x00060000
+
+
+/*
+ *  tpat_reg definition
+ *  offset: 0x80000
+ */
+#define BNX2_TPAT_CPU_MODE                             0x00085000
+#define BNX2_TPAT_CPU_MODE_LOCAL_RST                    (1L<<0)
+#define BNX2_TPAT_CPU_MODE_STEP_ENA                     (1L<<1)
+#define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA              (1L<<2)
+#define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA              (1L<<3)
+#define BNX2_TPAT_CPU_MODE_MSG_BIT1                     (1L<<6)
+#define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA                (1L<<7)
+#define BNX2_TPAT_CPU_MODE_SOFT_HALT                    (1L<<10)
+#define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA            (1L<<11)
+#define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA            (1L<<12)
+#define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA           (1L<<13)
+#define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA      (1L<<15)
+
+#define BNX2_TPAT_CPU_STATE                            0x00085004
+#define BNX2_TPAT_CPU_STATE_BREAKPOINT                  (1L<<0)
+#define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED             (1L<<2)
+#define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED          (1L<<3)
+#define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED          (1L<<4)
+#define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED        (1L<<5)
+#define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED               (1L<<6)
+#define BNX2_TPAT_CPU_STATE_ALIGN_HALTED                (1L<<7)
+#define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED            (1L<<8)
+#define BNX2_TPAT_CPU_STATE_SOFT_HALTED                         (1L<<10)
+#define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW              (1L<<11)
+#define BNX2_TPAT_CPU_STATE_INTERRRUPT                  (1L<<12)
+#define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL           (1L<<14)
+#define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL            (1L<<15)
+#define BNX2_TPAT_CPU_STATE_BLOCKED_READ                (1L<<31)
+
+#define BNX2_TPAT_CPU_EVENT_MASK                       0x00085008
+#define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK        (1L<<0)
+#define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK   (1L<<2)
+#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK        (1L<<3)
+#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK        (1L<<4)
+#define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK      (1L<<5)
+#define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK     (1L<<6)
+#define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK      (1L<<7)
+#define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK                 (1L<<8)
+#define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK       (1L<<10)
+#define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK    (1L<<11)
+#define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK                 (1L<<12)
+
+#define BNX2_TPAT_CPU_PROGRAM_COUNTER                  0x0008501c
+#define BNX2_TPAT_CPU_INSTRUCTION                      0x00085020
+#define BNX2_TPAT_CPU_DATA_ACCESS                      0x00085024
+#define BNX2_TPAT_CPU_INTERRUPT_ENABLE                 0x00085028
+#define BNX2_TPAT_CPU_INTERRUPT_VECTOR                 0x0008502c
+#define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC               0x00085030
+#define BNX2_TPAT_CPU_HW_BREAKPOINT                    0x00085034
+#define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE             (1L<<0)
+#define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS             (0x3fffffffL<<2)
+
+#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK                  0x00085038
+#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE           (0x7ffL<<0)
+#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN                 (1L<<11)
+#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL             (0xfL<<12)
+#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE           (0x7ffL<<16)
+#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN                 (1L<<27)
+#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL             (0xfL<<28)
+
+#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR                 0x00085048
+#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE             (1L<<1)
+#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP        (0L<<1)
+#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH      (1L<<1)
+#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA              (0x3fffffffL<<2)
+
+#define BNX2_TPAT_CPU_REG_FILE                         0x00085200
+#define BNX2_TPAT_FTQ_DATA                             0x000853c0
+#define BNX2_TPAT_FTQ_CMD                              0x000853f8
+#define BNX2_TPAT_FTQ_CMD_OFFSET                        (0x3ffL<<0)
+#define BNX2_TPAT_FTQ_CMD_WR_TOP                        (1L<<10)
+#define BNX2_TPAT_FTQ_CMD_WR_TOP_0                      (0L<<10)
+#define BNX2_TPAT_FTQ_CMD_WR_TOP_1                      (1L<<10)
+#define BNX2_TPAT_FTQ_CMD_SFT_RESET                     (1L<<25)
+#define BNX2_TPAT_FTQ_CMD_RD_DATA                       (1L<<26)
+#define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN                  (1L<<27)
+#define BNX2_TPAT_FTQ_CMD_ADD_DATA                      (1L<<28)
+#define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR                         (1L<<29)
+#define BNX2_TPAT_FTQ_CMD_POP                           (1L<<30)
+#define BNX2_TPAT_FTQ_CMD_BUSY                          (1L<<31)
+
+#define BNX2_TPAT_FTQ_CTL                              0x000853fc
+#define BNX2_TPAT_FTQ_CTL_INTERVENE                     (1L<<0)
+#define BNX2_TPAT_FTQ_CTL_OVERFLOW                      (1L<<1)
+#define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE               (1L<<2)
+#define BNX2_TPAT_FTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
+#define BNX2_TPAT_FTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
+
+#define BNX2_TPAT_SCRATCH                              0x000a0000
+
+
+/*
+ *  rxp_reg definition
+ *  offset: 0xc0000
+ */
+#define BNX2_RXP_CPU_MODE                              0x000c5000
+#define BNX2_RXP_CPU_MODE_LOCAL_RST                     (1L<<0)
+#define BNX2_RXP_CPU_MODE_STEP_ENA                      (1L<<1)
+#define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA               (1L<<2)
+#define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA               (1L<<3)
+#define BNX2_RXP_CPU_MODE_MSG_BIT1                      (1L<<6)
+#define BNX2_RXP_CPU_MODE_INTERRUPT_ENA                         (1L<<7)
+#define BNX2_RXP_CPU_MODE_SOFT_HALT                     (1L<<10)
+#define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA             (1L<<11)
+#define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA             (1L<<12)
+#define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA            (1L<<13)
+#define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA       (1L<<15)
+
+#define BNX2_RXP_CPU_STATE                             0x000c5004
+#define BNX2_RXP_CPU_STATE_BREAKPOINT                   (1L<<0)
+#define BNX2_RXP_CPU_STATE_BAD_INST_HALTED              (1L<<2)
+#define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED           (1L<<3)
+#define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED           (1L<<4)
+#define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED                 (1L<<5)
+#define BNX2_RXP_CPU_STATE_BAD_pc_HALTED                (1L<<6)
+#define BNX2_RXP_CPU_STATE_ALIGN_HALTED                         (1L<<7)
+#define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED             (1L<<8)
+#define BNX2_RXP_CPU_STATE_SOFT_HALTED                  (1L<<10)
+#define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW               (1L<<11)
+#define BNX2_RXP_CPU_STATE_INTERRRUPT                   (1L<<12)
+#define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL            (1L<<14)
+#define BNX2_RXP_CPU_STATE_INST_FETCH_STALL             (1L<<15)
+#define BNX2_RXP_CPU_STATE_BLOCKED_READ                         (1L<<31)
+
+#define BNX2_RXP_CPU_EVENT_MASK                                0x000c5008
+#define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK                 (1L<<0)
+#define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK    (1L<<2)
+#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK         (1L<<3)
+#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK         (1L<<4)
+#define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK       (1L<<5)
+#define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK      (1L<<6)
+#define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK       (1L<<7)
+#define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK          (1L<<8)
+#define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK        (1L<<10)
+#define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK     (1L<<11)
+#define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK          (1L<<12)
+
+#define BNX2_RXP_CPU_PROGRAM_COUNTER                   0x000c501c
+#define BNX2_RXP_CPU_INSTRUCTION                       0x000c5020
+#define BNX2_RXP_CPU_DATA_ACCESS                       0x000c5024
+#define BNX2_RXP_CPU_INTERRUPT_ENABLE                  0x000c5028
+#define BNX2_RXP_CPU_INTERRUPT_VECTOR                  0x000c502c
+#define BNX2_RXP_CPU_INTERRUPT_SAVED_PC                        0x000c5030
+#define BNX2_RXP_CPU_HW_BREAKPOINT                     0x000c5034
+#define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE              (1L<<0)
+#define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS              (0x3fffffffL<<2)
+
+#define BNX2_RXP_CPU_DEBUG_VECT_PEEK                   0x000c5038
+#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE            (0x7ffL<<0)
+#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN          (1L<<11)
+#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL              (0xfL<<12)
+#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE            (0x7ffL<<16)
+#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN          (1L<<27)
+#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL              (0xfL<<28)
+
+#define BNX2_RXP_CPU_LAST_BRANCH_ADDR                  0x000c5048
+#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE              (1L<<1)
+#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP                 (0L<<1)
+#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH       (1L<<1)
+#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA               (0x3fffffffL<<2)
+
+#define BNX2_RXP_CPU_REG_FILE                          0x000c5200
+#define BNX2_RXP_CFTQ_DATA                             0x000c5380
+#define BNX2_RXP_CFTQ_CMD                              0x000c53b8
+#define BNX2_RXP_CFTQ_CMD_OFFSET                        (0x3ffL<<0)
+#define BNX2_RXP_CFTQ_CMD_WR_TOP                        (1L<<10)
+#define BNX2_RXP_CFTQ_CMD_WR_TOP_0                      (0L<<10)
+#define BNX2_RXP_CFTQ_CMD_WR_TOP_1                      (1L<<10)
+#define BNX2_RXP_CFTQ_CMD_SFT_RESET                     (1L<<25)
+#define BNX2_RXP_CFTQ_CMD_RD_DATA                       (1L<<26)
+#define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN                  (1L<<27)
+#define BNX2_RXP_CFTQ_CMD_ADD_DATA                      (1L<<28)
+#define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR                         (1L<<29)
+#define BNX2_RXP_CFTQ_CMD_POP                           (1L<<30)
+#define BNX2_RXP_CFTQ_CMD_BUSY                          (1L<<31)
+
+#define BNX2_RXP_CFTQ_CTL                              0x000c53bc
+#define BNX2_RXP_CFTQ_CTL_INTERVENE                     (1L<<0)
+#define BNX2_RXP_CFTQ_CTL_OVERFLOW                      (1L<<1)
+#define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE               (1L<<2)
+#define BNX2_RXP_CFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
+#define BNX2_RXP_CFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
+
+#define BNX2_RXP_FTQ_DATA                              0x000c53c0
+#define BNX2_RXP_FTQ_CMD                               0x000c53f8
+#define BNX2_RXP_FTQ_CMD_OFFSET                                 (0x3ffL<<0)
+#define BNX2_RXP_FTQ_CMD_WR_TOP                                 (1L<<10)
+#define BNX2_RXP_FTQ_CMD_WR_TOP_0                       (0L<<10)
+#define BNX2_RXP_FTQ_CMD_WR_TOP_1                       (1L<<10)
+#define BNX2_RXP_FTQ_CMD_SFT_RESET                      (1L<<25)
+#define BNX2_RXP_FTQ_CMD_RD_DATA                        (1L<<26)
+#define BNX2_RXP_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
+#define BNX2_RXP_FTQ_CMD_ADD_DATA                       (1L<<28)
+#define BNX2_RXP_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
+#define BNX2_RXP_FTQ_CMD_POP                            (1L<<30)
+#define BNX2_RXP_FTQ_CMD_BUSY                           (1L<<31)
+
+#define BNX2_RXP_FTQ_CTL                               0x000c53fc
+#define BNX2_RXP_FTQ_CTL_INTERVENE                      (1L<<0)
+#define BNX2_RXP_FTQ_CTL_OVERFLOW                       (1L<<1)
+#define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
+#define BNX2_RXP_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
+#define BNX2_RXP_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
+
+#define BNX2_RXP_SCRATCH                               0x000e0000
+
+
+/*
+ *  com_reg definition
+ *  offset: 0x100000
+ */
+#define BNX2_COM_CPU_MODE                              0x00105000
+#define BNX2_COM_CPU_MODE_LOCAL_RST                     (1L<<0)
+#define BNX2_COM_CPU_MODE_STEP_ENA                      (1L<<1)
+#define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA               (1L<<2)
+#define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA               (1L<<3)
+#define BNX2_COM_CPU_MODE_MSG_BIT1                      (1L<<6)
+#define BNX2_COM_CPU_MODE_INTERRUPT_ENA                         (1L<<7)
+#define BNX2_COM_CPU_MODE_SOFT_HALT                     (1L<<10)
+#define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA             (1L<<11)
+#define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA             (1L<<12)
+#define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA            (1L<<13)
+#define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA       (1L<<15)
+
+#define BNX2_COM_CPU_STATE                             0x00105004
+#define BNX2_COM_CPU_STATE_BREAKPOINT                   (1L<<0)
+#define BNX2_COM_CPU_STATE_BAD_INST_HALTED              (1L<<2)
+#define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED           (1L<<3)
+#define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED           (1L<<4)
+#define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED                 (1L<<5)
+#define BNX2_COM_CPU_STATE_BAD_pc_HALTED                (1L<<6)
+#define BNX2_COM_CPU_STATE_ALIGN_HALTED                         (1L<<7)
+#define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED             (1L<<8)
+#define BNX2_COM_CPU_STATE_SOFT_HALTED                  (1L<<10)
+#define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW               (1L<<11)
+#define BNX2_COM_CPU_STATE_INTERRRUPT                   (1L<<12)
+#define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL            (1L<<14)
+#define BNX2_COM_CPU_STATE_INST_FETCH_STALL             (1L<<15)
+#define BNX2_COM_CPU_STATE_BLOCKED_READ                         (1L<<31)
+
+#define BNX2_COM_CPU_EVENT_MASK                                0x00105008
+#define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK                 (1L<<0)
+#define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK    (1L<<2)
+#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK         (1L<<3)
+#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK         (1L<<4)
+#define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK       (1L<<5)
+#define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK      (1L<<6)
+#define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK       (1L<<7)
+#define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK          (1L<<8)
+#define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK        (1L<<10)
+#define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK     (1L<<11)
+#define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK          (1L<<12)
+
+#define BNX2_COM_CPU_PROGRAM_COUNTER                   0x0010501c
+#define BNX2_COM_CPU_INSTRUCTION                       0x00105020
+#define BNX2_COM_CPU_DATA_ACCESS                       0x00105024
+#define BNX2_COM_CPU_INTERRUPT_ENABLE                  0x00105028
+#define BNX2_COM_CPU_INTERRUPT_VECTOR                  0x0010502c
+#define BNX2_COM_CPU_INTERRUPT_SAVED_PC                        0x00105030
+#define BNX2_COM_CPU_HW_BREAKPOINT                     0x00105034
+#define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE              (1L<<0)
+#define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS              (0x3fffffffL<<2)
+
+#define BNX2_COM_CPU_DEBUG_VECT_PEEK                   0x00105038
+#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE            (0x7ffL<<0)
+#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN          (1L<<11)
+#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL              (0xfL<<12)
+#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE            (0x7ffL<<16)
+#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN          (1L<<27)
+#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL              (0xfL<<28)
+
+#define BNX2_COM_CPU_LAST_BRANCH_ADDR                  0x00105048
+#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE              (1L<<1)
+#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP                 (0L<<1)
+#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH       (1L<<1)
+#define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA               (0x3fffffffL<<2)
+
+#define BNX2_COM_CPU_REG_FILE                          0x00105200
+#define BNX2_COM_COMXQ_FTQ_DATA                                0x00105340
+#define BNX2_COM_COMXQ_FTQ_CMD                         0x00105378
+#define BNX2_COM_COMXQ_FTQ_CMD_OFFSET                   (0x3ffL<<0)
+#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP                   (1L<<10)
+#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0                         (0L<<10)
+#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1                         (1L<<10)
+#define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET                (1L<<25)
+#define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA                  (1L<<26)
+#define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN             (1L<<27)
+#define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA                         (1L<<28)
+#define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR            (1L<<29)
+#define BNX2_COM_COMXQ_FTQ_CMD_POP                      (1L<<30)
+#define BNX2_COM_COMXQ_FTQ_CMD_BUSY                     (1L<<31)
+
+#define BNX2_COM_COMXQ_FTQ_CTL                         0x0010537c
+#define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE                (1L<<0)
+#define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW                         (1L<<1)
+#define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE          (1L<<2)
+#define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH                (0x3ffL<<12)
+#define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH                (0x3ffL<<22)
+
+#define BNX2_COM_COMTQ_FTQ_DATA                                0x00105380
+#define BNX2_COM_COMTQ_FTQ_CMD                         0x001053b8
+#define BNX2_COM_COMTQ_FTQ_CMD_OFFSET                   (0x3ffL<<0)
+#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP                   (1L<<10)
+#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0                         (0L<<10)
+#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1                         (1L<<10)
+#define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET                (1L<<25)
+#define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA                  (1L<<26)
+#define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN             (1L<<27)
+#define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA                         (1L<<28)
+#define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR            (1L<<29)
+#define BNX2_COM_COMTQ_FTQ_CMD_POP                      (1L<<30)
+#define BNX2_COM_COMTQ_FTQ_CMD_BUSY                     (1L<<31)
+
+#define BNX2_COM_COMTQ_FTQ_CTL                         0x001053bc
+#define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE                (1L<<0)
+#define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW                         (1L<<1)
+#define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE          (1L<<2)
+#define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH                (0x3ffL<<12)
+#define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH                (0x3ffL<<22)
+
+#define BNX2_COM_COMQ_FTQ_DATA                         0x001053c0
+#define BNX2_COM_COMQ_FTQ_CMD                          0x001053f8
+#define BNX2_COM_COMQ_FTQ_CMD_OFFSET                    (0x3ffL<<0)
+#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP                    (1L<<10)
+#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0                  (0L<<10)
+#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1                  (1L<<10)
+#define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET                         (1L<<25)
+#define BNX2_COM_COMQ_FTQ_CMD_RD_DATA                   (1L<<26)
+#define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN              (1L<<27)
+#define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA                  (1L<<28)
+#define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR             (1L<<29)
+#define BNX2_COM_COMQ_FTQ_CMD_POP                       (1L<<30)
+#define BNX2_COM_COMQ_FTQ_CMD_BUSY                      (1L<<31)
+
+#define BNX2_COM_COMQ_FTQ_CTL                          0x001053fc
+#define BNX2_COM_COMQ_FTQ_CTL_INTERVENE                         (1L<<0)
+#define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW                  (1L<<1)
+#define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE           (1L<<2)
+#define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH                         (0x3ffL<<12)
+#define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH                         (0x3ffL<<22)
+
+#define BNX2_COM_SCRATCH                               0x00120000
+
+
+/*
+ *  cp_reg definition
+ *  offset: 0x180000
+ */
+#define BNX2_CP_CPU_MODE                               0x00185000
+#define BNX2_CP_CPU_MODE_LOCAL_RST                      (1L<<0)
+#define BNX2_CP_CPU_MODE_STEP_ENA                       (1L<<1)
+#define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA                (1L<<2)
+#define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA                (1L<<3)
+#define BNX2_CP_CPU_MODE_MSG_BIT1                       (1L<<6)
+#define BNX2_CP_CPU_MODE_INTERRUPT_ENA                  (1L<<7)
+#define BNX2_CP_CPU_MODE_SOFT_HALT                      (1L<<10)
+#define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA              (1L<<11)
+#define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA              (1L<<12)
+#define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA             (1L<<13)
+#define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA        (1L<<15)
+
+#define BNX2_CP_CPU_STATE                              0x00185004
+#define BNX2_CP_CPU_STATE_BREAKPOINT                    (1L<<0)
+#define BNX2_CP_CPU_STATE_BAD_INST_HALTED               (1L<<2)
+#define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
+#define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
+#define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED          (1L<<5)
+#define BNX2_CP_CPU_STATE_BAD_pc_HALTED                         (1L<<6)
+#define BNX2_CP_CPU_STATE_ALIGN_HALTED                  (1L<<7)
+#define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
+#define BNX2_CP_CPU_STATE_SOFT_HALTED                   (1L<<10)
+#define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW                (1L<<11)
+#define BNX2_CP_CPU_STATE_INTERRRUPT                    (1L<<12)
+#define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL             (1L<<14)
+#define BNX2_CP_CPU_STATE_INST_FETCH_STALL              (1L<<15)
+#define BNX2_CP_CPU_STATE_BLOCKED_READ                  (1L<<31)
+
+#define BNX2_CP_CPU_EVENT_MASK                         0x00185008
+#define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK          (1L<<0)
+#define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK     (1L<<2)
+#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK  (1L<<3)
+#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK  (1L<<4)
+#define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK        (1L<<5)
+#define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK       (1L<<6)
+#define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK        (1L<<7)
+#define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK           (1L<<8)
+#define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK                 (1L<<10)
+#define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK      (1L<<11)
+#define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK           (1L<<12)
+
+#define BNX2_CP_CPU_PROGRAM_COUNTER                    0x0018501c
+#define BNX2_CP_CPU_INSTRUCTION                                0x00185020
+#define BNX2_CP_CPU_DATA_ACCESS                                0x00185024
+#define BNX2_CP_CPU_INTERRUPT_ENABLE                   0x00185028
+#define BNX2_CP_CPU_INTERRUPT_VECTOR                   0x0018502c
+#define BNX2_CP_CPU_INTERRUPT_SAVED_PC                 0x00185030
+#define BNX2_CP_CPU_HW_BREAKPOINT                      0x00185034
+#define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE               (1L<<0)
+#define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS               (0x3fffffffL<<2)
+
+#define BNX2_CP_CPU_DEBUG_VECT_PEEK                    0x00185038
+#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE             (0x7ffL<<0)
+#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN           (1L<<11)
+#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL               (0xfL<<12)
+#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE             (0x7ffL<<16)
+#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN           (1L<<27)
+#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL               (0xfL<<28)
+
+#define BNX2_CP_CPU_LAST_BRANCH_ADDR                   0x00185048
+#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE               (1L<<1)
+#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP          (0L<<1)
+#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH        (1L<<1)
+#define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
+
+#define BNX2_CP_CPU_REG_FILE                           0x00185200
+#define BNX2_CP_CPQ_FTQ_DATA                           0x001853c0
+#define BNX2_CP_CPQ_FTQ_CMD                            0x001853f8
+#define BNX2_CP_CPQ_FTQ_CMD_OFFSET                      (0x3ffL<<0)
+#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP                      (1L<<10)
+#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0                    (0L<<10)
+#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1                    (1L<<10)
+#define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET                   (1L<<25)
+#define BNX2_CP_CPQ_FTQ_CMD_RD_DATA                     (1L<<26)
+#define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN                (1L<<27)
+#define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA                    (1L<<28)
+#define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR               (1L<<29)
+#define BNX2_CP_CPQ_FTQ_CMD_POP                                 (1L<<30)
+#define BNX2_CP_CPQ_FTQ_CMD_BUSY                        (1L<<31)
+
+#define BNX2_CP_CPQ_FTQ_CTL                            0x001853fc
+#define BNX2_CP_CPQ_FTQ_CTL_INTERVENE                   (1L<<0)
+#define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW                    (1L<<1)
+#define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE             (1L<<2)
+#define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH                   (0x3ffL<<12)
+#define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH                   (0x3ffL<<22)
+
+#define BNX2_CP_SCRATCH                                        0x001a0000
+
+
+/*
+ *  mcp_reg definition
+ *  offset: 0x140000
+ */
+#define BNX2_MCP_CPU_MODE                              0x00145000
+#define BNX2_MCP_CPU_MODE_LOCAL_RST                     (1L<<0)
+#define BNX2_MCP_CPU_MODE_STEP_ENA                      (1L<<1)
+#define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA               (1L<<2)
+#define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA               (1L<<3)
+#define BNX2_MCP_CPU_MODE_MSG_BIT1                      (1L<<6)
+#define BNX2_MCP_CPU_MODE_INTERRUPT_ENA                         (1L<<7)
+#define BNX2_MCP_CPU_MODE_SOFT_HALT                     (1L<<10)
+#define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA             (1L<<11)
+#define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA             (1L<<12)
+#define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA            (1L<<13)
+#define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA       (1L<<15)
+
+#define BNX2_MCP_CPU_STATE                             0x00145004
+#define BNX2_MCP_CPU_STATE_BREAKPOINT                   (1L<<0)
+#define BNX2_MCP_CPU_STATE_BAD_INST_HALTED              (1L<<2)
+#define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED           (1L<<3)
+#define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED           (1L<<4)
+#define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED                 (1L<<5)
+#define BNX2_MCP_CPU_STATE_BAD_pc_HALTED                (1L<<6)
+#define BNX2_MCP_CPU_STATE_ALIGN_HALTED                         (1L<<7)
+#define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED             (1L<<8)
+#define BNX2_MCP_CPU_STATE_SOFT_HALTED                  (1L<<10)
+#define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW               (1L<<11)
+#define BNX2_MCP_CPU_STATE_INTERRRUPT                   (1L<<12)
+#define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL            (1L<<14)
+#define BNX2_MCP_CPU_STATE_INST_FETCH_STALL             (1L<<15)
+#define BNX2_MCP_CPU_STATE_BLOCKED_READ                         (1L<<31)
+
+#define BNX2_MCP_CPU_EVENT_MASK                                0x00145008
+#define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK                 (1L<<0)
+#define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK    (1L<<2)
+#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK         (1L<<3)
+#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK         (1L<<4)
+#define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK       (1L<<5)
+#define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK      (1L<<6)
+#define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK       (1L<<7)
+#define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK          (1L<<8)
+#define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK        (1L<<10)
+#define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK     (1L<<11)
+#define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK          (1L<<12)
+
+#define BNX2_MCP_CPU_PROGRAM_COUNTER                   0x0014501c
+#define BNX2_MCP_CPU_INSTRUCTION                       0x00145020
+#define BNX2_MCP_CPU_DATA_ACCESS                       0x00145024
+#define BNX2_MCP_CPU_INTERRUPT_ENABLE                  0x00145028
+#define BNX2_MCP_CPU_INTERRUPT_VECTOR                  0x0014502c
+#define BNX2_MCP_CPU_INTERRUPT_SAVED_PC                        0x00145030
+#define BNX2_MCP_CPU_HW_BREAKPOINT                     0x00145034
+#define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE              (1L<<0)
+#define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS              (0x3fffffffL<<2)
+
+#define BNX2_MCP_CPU_DEBUG_VECT_PEEK                   0x00145038
+#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE            (0x7ffL<<0)
+#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN          (1L<<11)
+#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL              (0xfL<<12)
+#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE            (0x7ffL<<16)
+#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN          (1L<<27)
+#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL              (0xfL<<28)
+
+#define BNX2_MCP_CPU_LAST_BRANCH_ADDR                  0x00145048
+#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE              (1L<<1)
+#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP                 (0L<<1)
+#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH       (1L<<1)
+#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA               (0x3fffffffL<<2)
+
+#define BNX2_MCP_CPU_REG_FILE                          0x00145200
+#define BNX2_MCP_MCPQ_FTQ_DATA                         0x001453c0
+#define BNX2_MCP_MCPQ_FTQ_CMD                          0x001453f8
+#define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET                    (0x3ffL<<0)
+#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP                    (1L<<10)
+#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0                  (0L<<10)
+#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1                  (1L<<10)
+#define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET                         (1L<<25)
+#define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA                   (1L<<26)
+#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN              (1L<<27)
+#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA                  (1L<<28)
+#define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR             (1L<<29)
+#define BNX2_MCP_MCPQ_FTQ_CMD_POP                       (1L<<30)
+#define BNX2_MCP_MCPQ_FTQ_CMD_BUSY                      (1L<<31)
+
+#define BNX2_MCP_MCPQ_FTQ_CTL                          0x001453fc
+#define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE                         (1L<<0)
+#define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW                  (1L<<1)
+#define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE           (1L<<2)
+#define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH                         (0x3ffL<<12)
+#define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH                         (0x3ffL<<22)
+
+#define BNX2_MCP_ROM                                   0x00150000
+#define BNX2_MCP_SCRATCH                               0x00160000
+
+
+#define NUM_MC_HASH_REGISTERS   8
+
+
+/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0.  */
+#define PHY_BCM5706_PHY_ID                          0x00206160
+
+#define PHY_ID(id)                                  ((id) & 0xfffffff0)
+#define PHY_REV_ID(id)                              ((id) & 0xf)
+
+#define MIN_ETHERNET_PACKET_SIZE       60
+#define MAX_ETHERNET_PACKET_SIZE       1514
+#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
+
+#define RX_COPY_THRESH                 92
+
+#define DMA_READ_CHANS 5
+#define DMA_WRITE_CHANS        3
+
+#define BCM_PAGE_BITS  12
+#define BCM_PAGE_SIZE  (1 << BCM_PAGE_BITS)
+
+#define TX_DESC_CNT  (BCM_PAGE_SIZE / sizeof(struct tx_bd))
+#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
+
+#define RX_DESC_CNT  (BCM_PAGE_SIZE / sizeof(struct rx_bd))
+#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
+
+#define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) ==                        
\
+               (MAX_TX_DESC_CNT - 1)) ?                                \
+       (x) + 2 : (x) + 1
+
+#define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT)
+
+#define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) ==                        
\
+               (MAX_RX_DESC_CNT - 1)) ?                                \
+       (x) + 2 : (x) + 1
+
+#define RX_RING_IDX(x) ((x) & MAX_RX_DESC_CNT)
+
+
+/* Context size. */
+#define CTX_SHIFT                   7
+#define CTX_SIZE                    (1 << CTX_SHIFT)
+#define CTX_MASK                    (CTX_SIZE - 1)
+#define GET_CID_ADDR(_cid)          ((_cid) << CTX_SHIFT)
+#define GET_CID(_cid_addr)          ((_cid_addr) >> CTX_SHIFT)
+
+#define PHY_CTX_SHIFT               6
+#define PHY_CTX_SIZE                (1 << PHY_CTX_SHIFT)
+#define PHY_CTX_MASK                (PHY_CTX_SIZE - 1)
+#define GET_PCID_ADDR(_pcid)        ((_pcid) << PHY_CTX_SHIFT)
+#define GET_PCID(_pcid_addr)        ((_pcid_addr) >> PHY_CTX_SHIFT)
+
+#define MB_KERNEL_CTX_SHIFT         8
+#define MB_KERNEL_CTX_SIZE          (1 << MB_KERNEL_CTX_SHIFT)
+#define MB_KERNEL_CTX_MASK          (MB_KERNEL_CTX_SIZE - 1)
+#define MB_GET_CID_ADDR(_cid)       (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
+
+#define MAX_CID_CNT                 0x4000
+#define MAX_CID_ADDR                (GET_CID_ADDR(MAX_CID_CNT))
+#define INVALID_CID_ADDR            0xffffffff
+
+#define TX_CID         16
+#define RX_CID         0
+
+#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
+#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
+
+struct sw_bd {
+       struct sk_buff          *skb;
+       DECLARE_PCI_UNMAP_ADDR(mapping)
+};
+
+/* Buffered flash (Atmel: AT45DB011B) specific information */
+#define SEEPROM_PAGE_BITS                      2
+#define SEEPROM_PHY_PAGE_SIZE                  (1 << SEEPROM_PAGE_BITS)
+#define SEEPROM_BYTE_ADDR_MASK                 (SEEPROM_PHY_PAGE_SIZE-1)
+#define SEEPROM_PAGE_SIZE                      4
+#define SEEPROM_TOTAL_SIZE                     65536
+
+#define BUFFERED_FLASH_PAGE_BITS               9
+#define BUFFERED_FLASH_PHY_PAGE_SIZE           (1 << BUFFERED_FLASH_PAGE_BITS)
+#define BUFFERED_FLASH_BYTE_ADDR_MASK          (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
+#define BUFFERED_FLASH_PAGE_SIZE               264
+#define BUFFERED_FLASH_TOTAL_SIZE              131072
+
+#define SAIFUN_FLASH_PAGE_BITS                 8
+#define SAIFUN_FLASH_PHY_PAGE_SIZE             (1 << SAIFUN_FLASH_PAGE_BITS)
+#define SAIFUN_FLASH_BYTE_ADDR_MASK            (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
+#define SAIFUN_FLASH_PAGE_SIZE                 256
+#define SAIFUN_FLASH_BASE_TOTAL_SIZE           65536
+
+#define NVRAM_TIMEOUT_COUNT                    30000
+
+
+#define FLASH_STRAP_MASK                       (BNX2_NVM_CFG1_FLASH_MODE   | \
+                                                BNX2_NVM_CFG1_BUFFER_MODE  | \
+                                                BNX2_NVM_CFG1_PROTECT_MODE | \
+                                                BNX2_NVM_CFG1_FLASH_SIZE)
+
+struct flash_spec {
+       u32 strapping;
+       u32 config1;
+       u32 config2;
+       u32 config3;
+       u32 write1;
+       u32 buffered;
+       u32 page_bits;
+       u32 page_size;
+       u32 addr_mask;
+       u32 total_size;
+       u8  *name;
+};
+
+struct bnx2 {
+       /* Fields used in the tx and intr/napi performance paths are grouped */
+       /* together in the beginning of the structure. */
+       void __iomem            *regview;
+
+       struct net_device       *dev;
+       struct pci_dev          *pdev;
+
+       atomic_t                intr_sem;
+
+       struct status_block     *status_blk;
+       u32                     last_status_idx;
+
+       atomic_t                tx_avail_bd;
+       struct tx_bd            *tx_desc_ring;
+       struct sw_bd            *tx_buf_ring;
+       u32                     tx_prod_bseq;
+       u16                     tx_prod;
+       u16                     tx_cons;
+
+#ifdef BCM_VLAN 
+       struct                  vlan_group *vlgrp;
+#endif
+
+       u32                     rx_offset;
+       u32                     rx_buf_use_size;        /* useable size */
+       u32                     rx_buf_size;            /* with alignment */
+       struct rx_bd            *rx_desc_ring;
+       struct sw_bd            *rx_buf_ring;
+       u32                     rx_prod_bseq;
+       u16                     rx_prod;
+       u16                     rx_cons;
+
+       u32                     rx_csum;
+
+       /* Only used to synchronize netif_stop_queue/wake_queue when tx */
+       /* ring is full */
+       spinlock_t              tx_lock;
+
+       /* End of fileds used in the performance code paths. */
+
+       char                    *name;
+
+       int                     timer_interval;
+       struct                  timer_list timer;
+       struct work_struct      reset_task;
+
+       /* Used to synchronize phy accesses. */
+       spinlock_t              phy_lock;
+
+       u32                     flags;
+#define PCIX_FLAG                      1
+#define PCI_32BIT_FLAG                 2
+#define ONE_TDMA_FLAG                  4       /* no longer used */
+#define NO_WOL_FLAG                    8
+#define USING_DAC_FLAG                 0x10
+#define USING_MSI_FLAG                 0x20
+
+       u32                     phy_flags;
+#define PHY_SERDES_FLAG                        1
+#define PHY_CRC_FIX_FLAG               2
+#define PHY_PARALLEL_DETECT_FLAG       4
+#define PHY_INT_MODE_MASK_FLAG         0x300
+#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
+#define PHY_INT_MODE_LINK_READY_FLAG   0x200
+
+       u32                     chip_id;
+       /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
+#define CHIP_NUM(bp)                   (((bp)->chip_id) & 0xffff0000)
+#define CHIP_NUM_5706                  0x57060000
+
+#define CHIP_REV(bp)                   (((bp)->chip_id) & 0x0000f000)
+#define CHIP_REV_Ax                    0x00000000
+#define CHIP_REV_Bx                    0x00001000
+#define CHIP_REV_Cx                    0x00002000
+    
+#define CHIP_METAL(bp)                 (((bp)->chip_id) & 0x00000ff0)
+#define CHIP_BONDING(bp)               (((bp)->chip_id) & 0x0000000f)
+
+#define CHIP_ID(bp)                    (((bp)->chip_id) & 0xfffffff0)
+#define CHIP_ID_5706_A0                        0x57060000
+#define CHIP_ID_5706_A1                        0x57060010
+
+#define CHIP_BOND_ID(bp)               (((bp)->chip_id) & 0xf)
+
+/* A serdes chip will have the first bit of the bond id set. */
+#define CHIP_BOND_ID_SERDES_BIT                0x01
+
+       u32                     phy_addr;
+       u32                     phy_id;
+       
+       u16                     bus_speed_mhz;
+       u8                      wol;
+
+       u8                      fw_timed_out;
+
+       u16                     fw_wr_seq;
+       u16                     fw_drv_pulse_wr_seq;
+
+       int                     tx_ring_size;
+       dma_addr_t              tx_desc_mapping;
+
+
+       int                     rx_ring_size;
+       dma_addr_t              rx_desc_mapping;
+
+       u16                     tx_quick_cons_trip;
+       u16                     tx_quick_cons_trip_int;
+       u16                     rx_quick_cons_trip;
+       u16                     rx_quick_cons_trip_int;
+       u16                     comp_prod_trip;
+       u16                     comp_prod_trip_int;
+       u16                     tx_ticks;
+       u16                     tx_ticks_int;
+       u16                     com_ticks;
+       u16                     com_ticks_int;
+       u16                     cmd_ticks;
+       u16                     cmd_ticks_int;
+       u16                     rx_ticks;
+       u16                     rx_ticks_int;
+
+       u32                     stats_ticks;
+
+       dma_addr_t              status_blk_mapping;
+
+       struct statistics_block *stats_blk;
+       dma_addr_t              stats_blk_mapping;
+
+       u32                     rx_mode;
+
+       u16                     req_line_speed;
+       u8                      req_duplex;
+
+       u8                      link_up;
+
+       u16                     line_speed;
+       u8                      duplex;
+       u8                      flow_ctrl;      /* actual flow ctrl settings */
+                                               /* may be different from     */
+                                               /* req_flow_ctrl if autoneg  */
+#define FLOW_CTRL_TX           1
+#define FLOW_CTRL_RX           2
+
+       u32                     advertising;
+
+       u8                      req_flow_ctrl;  /* flow ctrl advertisement */ 
+                                               /* settings or forced      */
+                                               /* settings                */
+       u8                      autoneg;
+#define AUTONEG_SPEED          1
+#define AUTONEG_FLOW_CTRL      2
+
+       u8                      loopback;
+#define MAC_LOOPBACK           1
+#define PHY_LOOPBACK           2
+
+       u8                      serdes_an_pending;
+#define SERDES_AN_TIMEOUT      (2 * HZ)
+
+       u8                      mac_addr[8];
+
+       u32                     fw_ver;
+
+       int                     pm_cap;
+       int                     pcix_cap;
+
+       struct net_device_stats net_stats;
+
+       struct flash_spec       *flash_info;
+};
+
+static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
+static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
+
+#define REG_RD(bp, offset)                                     \
+       readl(bp->regview + offset)
+
+#define REG_WR(bp, offset, val)                                        \
+       writel(val, bp->regview + offset)
+
+#define REG_WR16(bp, offset, val)                              \
+       writew(val, bp->regview + offset)
+
+#define REG_RD_IND(bp, offset)                                 \
+       bnx2_reg_rd_ind(bp, offset)
+
+#define REG_WR_IND(bp, offset, val)                            \
+       bnx2_reg_wr_ind(bp, offset, val)
+
+/* Indirect context access.  Unlike the MBQ_WR, these macros will not
+ * trigger a chip event. */
+static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
+
+#define CTX_WR(bp, cid_addr, offset, val)                      \
+       bnx2_ctx_wr(bp, cid_addr, offset, val)
+
+struct cpu_reg {
+       u32 mode;
+       u32 mode_value_halt;
+       u32 mode_value_sstep;
+
+       u32 state;
+       u32 state_value_clear;
+
+       u32 gpr0;
+       u32 evmask;
+       u32 pc;
+       u32 inst;
+       u32 bp;
+
+       u32 spad_base;
+
+       u32 mips_view_base;
+};
+
+struct fw_info {
+       u32 ver_major;
+       u32 ver_minor;
+       u32 ver_fix;
+
+       u32 start_addr;
+
+       /* Text section. */
+       u32 text_addr;
+       u32 text_len;
+       u32 text_index;
+       u32 *text;
+
+       /* Data section. */
+       u32 data_addr;
+       u32 data_len;
+       u32 data_index;
+       u32 *data;
+
+       /* SBSS section. */
+       u32 sbss_addr;
+       u32 sbss_len;
+       u32 sbss_index;
+       u32 *sbss;
+
+       /* BSS section. */
+       u32 bss_addr;
+       u32 bss_len;
+       u32 bss_index;
+       u32 *bss;
+
+       /* Read-only section. */
+       u32 rodata_addr;
+       u32 rodata_len;
+       u32 rodata_index;
+       u32 *rodata;
+};
+
+#define RV2P_PROC1                              0
+#define RV2P_PROC2                              1
+
+
+/* This value (in milliseconds) determines the frequency of the driver
+ * issuing the PULSE message code.  The firmware monitors this periodic
+ * pulse to determine when to switch to an OS-absent mode. */
+#define DRV_PULSE_PERIOD_MS                 250
+
+/* This value (in milliseconds) determines how long the driver should
+ * wait for an acknowledgement from the firmware before timing out.  Once
+ * the firmware has timed out, the driver will assume there is no firmware
+ * running and there won't be any firmware-driver synchronization during a
+ * driver reset. */
+#define FW_ACK_TIME_OUT_MS                  50
+
+
+#define BNX2_DRV_RESET_SIGNATURE               0x00000000
+#define BNX2_DRV_RESET_SIGNATURE_MAGIC          0x4841564b /* HAVK */
+//#define DRV_RESET_SIGNATURE_MAGIC             0x47495352 /* RSIG */
+
+#define BNX2_DRV_MB                            0x00000004
+#define BNX2_DRV_MSG_CODE                       0xff000000
+#define BNX2_DRV_MSG_CODE_RESET                         0x01000000
+#define BNX2_DRV_MSG_CODE_UNLOAD                0x02000000
+#define BNX2_DRV_MSG_CODE_SHUTDOWN              0x03000000
+#define BNX2_DRV_MSG_CODE_SUSPEND_WOL           0x04000000
+#define BNX2_DRV_MSG_CODE_FW_TIMEOUT            0x05000000
+#define BNX2_DRV_MSG_CODE_PULSE                         0x06000000
+#define BNX2_DRV_MSG_CODE_DIAG                  0x07000000
+#define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL        0x09000000
+
+#define BNX2_DRV_MSG_DATA                       0x00ff0000
+#define BNX2_DRV_MSG_DATA_WAIT0                         0x00010000
+#define BNX2_DRV_MSG_DATA_WAIT1                         0x00020000
+#define BNX2_DRV_MSG_DATA_WAIT2                         0x00030000
+#define BNX2_DRV_MSG_DATA_WAIT3                         0x00040000
+        
+#define BNX2_DRV_MSG_SEQ                        0x0000ffff
+
+#define BNX2_FW_MB                             0x00000008
+#define BNX2_FW_MSG_ACK                                 0x0000ffff
+#define BNX2_FW_MSG_STATUS_MASK                         0x00ff0000
+#define BNX2_FW_MSG_STATUS_OK                   0x00000000
+#define BNX2_FW_MSG_STATUS_FAILURE              0x00ff0000
+
+#define BNX2_LINK_STATUS                       0x0000000c
+
+#define BNX2_DRV_PULSE_MB                      0x00000010
+#define BNX2_DRV_PULSE_SEQ_MASK                         0x0000ffff
+
+/* Indicate to the firmware not to go into the
+ * OS absent when it is not getting driver pulse.
+ * This is used for debugging. */
+#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE       0x00010000
+
+#define BNX2_DEV_INFO_SIGNATURE                        0x00000020
+#define BNX2_DEV_INFO_SIGNATURE_MAGIC           0x44564900
+#define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK      0xffffff00
+#define BNX2_DEV_INFO_FEATURE_CFG_VALID                 0x01
+#define BNX2_DEV_INFO_SECONDARY_PORT            0x80
+#define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE          0x40
+
+#define BNX2_SHARED_HW_CFG_PART_NUM            0x00000024
+
+#define BNX2_SHARED_HW_CFG_POWER_DISSIPATED    0x00000034
+#define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK  0xff000000
+#define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK  0xff0000
+#define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK  0xff00
+#define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK  0xff
+
+#define BNX2_SHARED_HW_CFG POWER_CONSUMED      0x00000038
+#define BNX2_SHARED_HW_CFG_CONFIG              0x0000003c
+#define BNX2_SHARED_HW_CFG_DESIGN_NIC           0
+#define BNX2_SHARED_HW_CFG_DESIGN_LOM           0x1
+#define BNX2_SHARED_HW_CFG_PHY_COPPER           0
+#define BNX2_SHARED_HW_CFG_PHY_FIBER            0x2
+#define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS  8
+#define BNX2_SHARED_HW_CFG_LED_MODE_MASK        0x300
+#define BNX2_SHARED_HW_CFG_LED_MODE_MAC                 0
+#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1       0x100
+#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2       0x200
+
+#define BNX2_DEV_INFO_BC_REV                   0x0000004c
+
+#define BNX2_PORT_HW_CFG_MAC_UPPER             0x00000050
+#define BNX2_PORT_HW_CFG_UPPERMAC_MASK          0xffff
+
+#define BNX2_PORT_HW_CFG_MAC_LOWER             0x00000054
+#define BNX2_PORT_HW_CFG_CONFIG                        0x00000058
+
+#define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER       0x00000068
+#define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER       0x0000006c
+#define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER       0x00000070
+#define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER       0x00000074
+#define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER       0x00000078
+#define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER       0x0000007c
+
+#define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2      0x000000b4
+
+#define BNX2_DEV_INFO_FORMAT_REV               0x000000c4
+#define BNX2_DEV_INFO_FORMAT_REV_MASK           0xff000000
+#define BNX2_DEV_INFO_FORMAT_REV_ID             ('A' << 24)
+
+#define BNX2_SHARED_FEATURE                    0x000000c8
+#define BNX2_SHARED_FEATURE_MASK                0xffffffff
+
+#define BNX2_PORT_FEATURE                      0x000000d8
+#define BNX2_PORT2_FEATURE                     0x00000014c
+#define BNX2_PORT_FEATURE_WOL_ENABLED           0x01000000
+#define BNX2_PORT_FEATURE_MBA_ENABLED           0x02000000
+#define BNX2_PORT_FEATURE_ASF_ENABLED           0x04000000
+#define BNX2_PORT_FEATURE_IMD_ENABLED           0x08000000
+#define BNX2_PORT_FEATURE_BAR1_SIZE_MASK        0xf
+#define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED    0x0
+#define BNX2_PORT_FEATURE_BAR1_SIZE_64K                 0x1
+#define BNX2_PORT_FEATURE_BAR1_SIZE_128K        0x2
+#define BNX2_PORT_FEATURE_BAR1_SIZE_256K        0x3
+#define BNX2_PORT_FEATURE_BAR1_SIZE_512K        0x4
+#define BNX2_PORT_FEATURE_BAR1_SIZE_1M          0x5
+#define BNX2_PORT_FEATURE_BAR1_SIZE_2M          0x6
+#define BNX2_PORT_FEATURE_BAR1_SIZE_4M          0x7
+#define BNX2_PORT_FEATURE_BAR1_SIZE_8M          0x8
+#define BNX2_PORT_FEATURE_BAR1_SIZE_16M                 0x9
+#define BNX2_PORT_FEATURE_BAR1_SIZE_32M                 0xa
+#define BNX2_PORT_FEATURE_BAR1_SIZE_64M                 0xb
+#define BNX2_PORT_FEATURE_BAR1_SIZE_128M        0xc
+#define BNX2_PORT_FEATURE_BAR1_SIZE_256M        0xd
+#define BNX2_PORT_FEATURE_BAR1_SIZE_512M        0xe
+#define BNX2_PORT_FEATURE_BAR1_SIZE_1G          0xf
+
+#define BNX2_PORT_FEATURE_WOL                  0xdc
+#define BNX2_PORT2_FEATURE_WOL                 0x150
+#define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS        4
+#define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK      0x30
+#define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE   0
+#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC     0x10
+#define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI      0x20
+#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI    0x30
+#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK   0xf
+#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG        0
+#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF         1
+#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL         2
+#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
+#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
+#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF       5
+#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL       6
+#define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000    0x40
+#define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
+#define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP   0x800
+
+#define BNX2_PORT_FEATURE_MBA                  0xe0
+#define BNX2_PORT2_FEATURE_MBA                 0x154
+#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS        0
+#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK      0x3
+#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE       0
+#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL       1
+#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP     2
+#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS     2
+#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK   0x3c
+#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG        0
+#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF         0x4
+#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL         0x8
+#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF        0xc
+#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL        0x10
+#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF       0x14
+#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL       0x18
+#define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE       0x40
+#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S     0
+#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B     0x80
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS   8
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK         0xff00
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED     0
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K   0x100
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K   0x200
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K   0x300
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K   0x400
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K  0x500
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K  0x600
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K  0x700
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K         0x800
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K         0x900
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K         0xa00
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M   0xb00
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M   0xc00
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M   0xd00
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M   0xe00
+#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M  0xf00
+#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS    16
+#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK  0xf0000
+#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS         20
+#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK       0x300000
+#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO       0
+#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS        0x100000
+#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H     0x200000
+#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H     0x300000
+
+#define BNX2_PORT_FEATURE_IMD                  0xe4
+#define BNX2_PORT2_FEATURE_IMD                 0x158
+#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT     0
+#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE      1
+
+#define BNX2_PORT_FEATURE_VLAN                 0xe8
+#define BNX2_PORT2_FEATURE_VLAN                        0x15c
+#define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK     0xffff
+#define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE       0x10000
+
+#define BNX2_BC_STATE_RESET_TYPE               0x000001c0
+#define BNX2_BC_STATE_RESET_TYPE_SIG            0x00005254
+#define BNX2_BC_STATE_RESET_TYPE_SIG_MASK       0x0000ffff
+#define BNX2_BC_STATE_RESET_TYPE_NONE   (BNX2_BC_STATE_RESET_TYPE_SIG | \
+                                         0x00010000)
+#define BNX2_BC_STATE_RESET_TYPE_PCI    (BNX2_BC_STATE_RESET_TYPE_SIG | \
+                                         0x00020000)
+#define BNX2_BC_STATE_RESET_TYPE_VAUX   (BNX2_BC_STATE_RESET_TYPE_SIG | \
+                                         0x00030000)
+#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK       DRV_MSG_CODE         
+#define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \
+                                           DRV_MSG_CODE_RESET)
+#define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \
+                                            DRV_MSG_CODE_UNLOAD)
+#define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \
+                                              DRV_MSG_CODE_SHUTDOWN)
+#define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \
+                                         DRV_MSG_CODE_WOL)
+#define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \
+                                          DRV_MSG_CODE_DIAG)
+#define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \
+                                            (msg))
+
+#define BNX2_BC_STATE                          0x000001c4
+#define BNX2_BC_STATE_ERR_MASK                  0x0000ff00
+#define BNX2_BC_STATE_SIGN                      0x42530000
+#define BNX2_BC_STATE_SIGN_MASK                         0xffff0000
+#define BNX2_BC_STATE_BC1_START                         (BNX2_BC_STATE_SIGN | 
0x1)
+#define BNX2_BC_STATE_GET_NVM_CFG1              (BNX2_BC_STATE_SIGN | 0x2)
+#define BNX2_BC_STATE_PROG_BAR                  (BNX2_BC_STATE_SIGN | 0x3)
+#define BNX2_BC_STATE_INIT_VID                  (BNX2_BC_STATE_SIGN | 0x4)
+#define BNX2_BC_STATE_GET_NVM_CFG2              (BNX2_BC_STATE_SIGN | 0x5)
+#define BNX2_BC_STATE_APPLY_WKARND              (BNX2_BC_STATE_SIGN | 0x6)
+#define BNX2_BC_STATE_LOAD_BC2                  (BNX2_BC_STATE_SIGN | 0x7)
+#define BNX2_BC_STATE_GOING_BC2                         (BNX2_BC_STATE_SIGN | 
0x8)
+#define BNX2_BC_STATE_GOING_DIAG                (BNX2_BC_STATE_SIGN | 0x9)
+#define BNX2_BC_STATE_RT_FINAL_INIT             (BNX2_BC_STATE_SIGN | 0x81)
+#define BNX2_BC_STATE_RT_WKARND                         (BNX2_BC_STATE_SIGN | 
0x82)
+#define BNX2_BC_STATE_RT_DRV_PULSE              (BNX2_BC_STATE_SIGN | 0x83)
+#define BNX2_BC_STATE_RT_FIOEVTS                (BNX2_BC_STATE_SIGN | 0x84)
+#define BNX2_BC_STATE_RT_DRV_CMD                (BNX2_BC_STATE_SIGN | 0x85)
+#define BNX2_BC_STATE_RT_LOW_POWER              (BNX2_BC_STATE_SIGN | 0x86)
+#define BNX2_BC_STATE_RT_SET_WOL                (BNX2_BC_STATE_SIGN | 0x87)
+#define BNX2_BC_STATE_RT_OTHER_FW               (BNX2_BC_STATE_SIGN | 0x88)
+#define BNX2_BC_STATE_RT_GOING_D3               (BNX2_BC_STATE_SIGN | 0x89)
+#define BNX2_BC_STATE_ERR_BAD_VERSION           (BNX2_BC_STATE_SIGN | 0x0100)
+#define BNX2_BC_STATE_ERR_BAD_BC2_CRC           (BNX2_BC_STATE_SIGN | 0x0200)
+#define BNX2_BC_STATE_ERR_BC1_LOOP              (BNX2_BC_STATE_SIGN | 0x0300)
+#define BNX2_BC_STATE_ERR_UNKNOWN_CMD           (BNX2_BC_STATE_SIGN | 0x0400)
+#define BNX2_BC_STATE_ERR_DRV_DEAD              (BNX2_BC_STATE_SIGN | 0x0500)
+#define BNX2_BC_STATE_ERR_NO_RXP                (BNX2_BC_STATE_SIGN | 0x0600)
+#define BNX2_BC_STATE_ERR_TOO_MANY_RBUF                 (BNX2_BC_STATE_SIGN | 
0x0700)
+       
+#define BNX2_BC_STATE_DEBUG_CMD                        0x1dc
+#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE      0x42440000
+#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK         0xffff0000
+#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK  0xffff
+#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE  0xffff
+
+#define HOST_VIEW_SHMEM_BASE                   0x167c00
+
+#endif
diff -urN linux/drivers/net/bnx2_fw.h linux/drivers/net/bnx2_fw.h
--- linux/drivers/net/bnx2_fw.h 1970/01/01 00:00:00
+++ linux/drivers/net/bnx2_fw.h 2005-06-07 14:45:34.383652000 +0100     1.1
@@ -0,0 +1,2468 @@
+/* bnx2_fw.h: Broadcom NX2 network driver.
+ *
+ * Copyright (c) 2004, 2005 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, except as noted below.
+ *
+ * This file contains firmware data derived from proprietary unpublished
+ * source code, Copyright (c) 2004, 2005 Broadcom Corporation.
+ *
+ * Permission is hereby granted for the distribution of this firmware data
+ * in hexadecimal or equivalent format, provided this copyright notice is
+ * accompanying it.
+ */
+
+
+static int bnx2_COM_b06FwReleaseMajor = 0x0;
+static int bnx2_COM_b06FwReleaseMinor = 0x0;
+static int bnx2_COM_b06FwReleaseFix = 0x0;
+static u32 bnx2_COM_b06FwStartAddr = 0x080004a0;
+static u32 bnx2_COM_b06FwTextAddr = 0x08000000;
+static int bnx2_COM_b06FwTextLen = 0x4594;
+static u32 bnx2_COM_b06FwDataAddr = 0x080045e0;
+static int bnx2_COM_b06FwDataLen = 0x0;
+static u32 bnx2_COM_b06FwRodataAddr = 0x08004598;
+static int bnx2_COM_b06FwRodataLen = 0x18;
+static u32 bnx2_COM_b06FwBssAddr = 0x08004600;
+static int bnx2_COM_b06FwBssLen = 0x88;
+static u32 bnx2_COM_b06FwSbssAddr = 0x080045e0;
+static int bnx2_COM_b06FwSbssLen = 0x1c;
+static u32 bnx2_COM_b06FwText[(0x4594/4) + 1] = {
+       0x0a000128, 0x00000000, 0x00000000, 0x0000000d, 0x636f6d20, 0x302e362e,
+       0x39000000, 0x00060902, 0x00000000, 0x00000003, 0x00000014, 0x00000032,
+       0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000010, 0x000003e8, 0x0000ea60, 0x00000001, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x0000ffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000002, 0x00000020, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x10000003, 0x00000000, 0x0000000d,
+       0x0000000d, 0x3c020800, 0x244245e0, 0x3c030800, 0x24634688, 0xac400000,
+       0x0043202b, 0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd7ffc, 0x03a0f021,
+       0x3c100800, 0x261004a0, 0x3c1c0800, 0x279c45e0, 0x0e0001f2, 0x00000000,
+       0x0000000d, 0x27bdffe8, 0x3c1a8000, 0x3c020008, 0x0342d825, 0x3c036010,
+       0xafbf0010, 0x8c655000, 0x3c020800, 0x24470ac8, 0x3c040800, 0x24864600,
+       0x2402ff7f, 0x00a22824, 0x34a5380c, 0xac655000, 0x00002821, 0x24020037,
+       0x24030c80, 0xaf420008, 0xaf430024, 0xacc70000, 0x24a50001, 0x2ca20016,
+       0x1440fffc, 0x24c60004, 0x24844600, 0x3c020800, 0x24420ad4, 0x3c030800,
+       0x246309d4, 0xac820004, 0x3c020800, 0x24420618, 0x3c050800, 0x24a50ca0,
+       0xac82000c, 0x3c020800, 0x24423100, 0xac830008, 0x3c030800, 0x246325c8,
+       0xac820014, 0x3c020800, 0x24422b0c, 0xac830018, 0xac83001c, 0x3c030800,
+       0x24630adc, 0xac820024, 0x3c020800, 0x24423040, 0xac83002c, 0x3c030800,
+       0x24633060, 0xac820030, 0x3c020800, 0x24422f6c, 0xac830034, 0x3c030800,
+       0x24632c60, 0xac82003c, 0x3c020800, 0x24420b6c, 0xac850010, 0xac850020,
+       0xac830040, 0x0e000bd6, 0xac820050, 0x8fbf0010, 0x03e00008, 0x27bd0018,
+       0x27bdffe0, 0xafb00010, 0x27500100, 0xafbf0018, 0xafb10014, 0x9203000b,
+       0x24020003, 0x1462005b, 0x96110008, 0x32220001, 0x10400009, 0x27430080,
+       0x8e020000, 0x96040014, 0x000211c2, 0x00021040, 0x00621821, 0xa4640000,
+       0x0a0001cb, 0x3c020800, 0x3c020800, 0x8c430020, 0x1060002a, 0x3c030800,
+       0x0e001006, 0x00000000, 0x97420108, 0x8f850018, 0x9743010c, 0x3042003e,
+       0x00021400, 0x00621825, 0xaca30000, 0x8f840018, 0x8f420100, 0xac820004,
+       0x97430116, 0x9742010e, 0x8f840018, 0x00031c00, 0x00431025, 0xac820008,
+       0x97430110, 0x97440112, 0x8f850018, 0x00031c00, 0x00832025, 0xaca4000c,
+       0x97420114, 0x8f840018, 0x3042ffff, 0xac820010, 0x8f830018, 0xac600014,
+       0x8f820018, 0x3c030800, 0xac400018, 0x9462466e, 0x8f840018, 0x3c032000,
+       0x00431025, 0xac82001c, 0x0e001044, 0x24040001, 0x3c030800, 0x8c620040,
+       0x24420001, 0xac620040, 0x3c020800, 0x8c430044, 0x32240004, 0x24630001,
+       0x10800017, 0xac430044, 0x8f4202b8, 0x04430007, 0x8e020020, 0x3c040800,
+       0x8c830060, 0x24020001, 0x24630001, 0x0a0001ed, 0xac830060, 0x3c060800,
+       0x8cc4005c, 0xaf420280, 0x96030016, 0x00001021, 0xa7430284, 0x8e050004,
+       0x24840001, 0x3c031000, 0xaf450288, 0xaf4302b8, 0x0a0001ed, 0xacc4005c,
+       0x32220002, 0x0a0001ed, 0x0002102b, 0x3c026000, 0xac400808, 0x0000000d,
+       0x00001021, 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
+       0x27bdffc8, 0xafbf0034, 0xafbe0030, 0xafb7002c, 0xafb60028, 0xafb50024,
+       0xafb40020, 0xafb3001c, 0xafb20018, 0xafb10014, 0x0e00013f, 0xafb00010,
+       0x24110020, 0x24150030, 0x2794000c, 0x27930008, 0x3c124000, 0x3c1e0800,
+       0x3c170800, 0x3c160800, 0x8f820004, 0x3c040800, 0x8c830020, 0x10430004,
+       0x00000000, 0xaf830004, 0x0e00110b, 0x00000000, 0x8f500000, 0x32020007,
+       0x1040fff5, 0x32020001, 0x1040002b, 0x32020002, 0x8f420100, 0xaf420020,
+       0x8f430104, 0xaf4300a8, 0x9342010b, 0x93630000, 0x306300ff, 0x10710005,
+       0x304400ff, 0x10750006, 0x2c820016, 0x0a000227, 0x00000000, 0xaf940000,
+       0x0a000228, 0x2c820016, 0xaf930000, 0x0a000228, 0x00000000, 0xaf800000,
+       0x14400005, 0x00041880, 0x0e0002b2, 0x00000000, 0x0a000234, 0x00000000,
+       0x3c020800, 0x24424600, 0x00621821, 0x8c620000, 0x0040f809, 0x00000000,
+       0x10400005, 0x8fc20034, 0x8f420104, 0x3c016020, 0xac220014, 0x8fc20034,
+       0xaf520138, 0x24420001, 0xafc20034, 0x32020002, 0x10400019, 0x32020004,
+       0x8f420140, 0xaf420020, 0x93630000, 0x306300ff, 0x10710005, 0x00000000,
+       0x10750006, 0x00000000, 0x0a000250, 0x00000000, 0xaf940000, 0x0a000251,
+       0x00000000, 0xaf930000, 0x0a000251, 0x00000000, 0xaf800000, 0x0e0008b9,
+       0x00000000, 0x8ee20038, 0xaf520178, 0x24420001, 0xaee20038, 0x32020004,
+       0x1040ffad, 0x00000000, 0x8f420180, 0xaf420020, 0x93630000, 0x306300ff,
+       0x10710005, 0x00000000, 0x10750006, 0x00000000, 0x0a00026a, 0x00000000,
+       0xaf940000, 0x0a00026b, 0x00000000, 0xaf930000, 0x0a00026b, 0x00000000,
+       0xaf800000, 0x93620000, 0x14510004, 0x8ec2003c, 0x0e000835, 0x00000000,
+       0x8ec2003c, 0xaf5201b8, 0x24420001, 0x0a000206, 0xaec2003c, 0x27bdffe8,
+       0xafbf0010, 0x97420108, 0x24033000, 0x30447000, 0x10830012, 0x28823001,
+       0x10400007, 0x24024000, 0x1080000b, 0x24022000, 0x1082001a, 0x24020001,
+       0x0a000299, 0x00000000, 0x1082000c, 0x24025000, 0x1082000e, 0x00000000,
+       0x0a000299, 0x00000000, 0x0000000d, 0x0a00029b, 0x00001021, 0x0e000300,
+       0x00000000, 0x0a00029b, 0x00001021, 0x0e00048f, 0x00000000, 0x0a00029b,
+       0x00001021, 0x0e000fdf, 0x00000000, 0x0a00029b, 0x00001021, 0x0000000d,
+       0x00001021, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x93620000, 0x24030020,
+       0x304400ff, 0x10830005, 0x24020030, 0x10820007, 0x00000000, 0x0a0002af,
+       0x00000000, 0x2782000c, 0xaf820000, 0x03e00008, 0x00000000, 0x27820008,
+       0xaf820000, 0x03e00008, 0x00000000, 0xaf800000, 0x03e00008, 0x00000000,
+       0x0000000d, 0x03e00008, 0x00001021, 0x03e00008, 0x00001021, 0x27440100,
+       0x94830008, 0x30620004, 0x10400017, 0x30620002, 0x8f4202b8, 0x04430007,
+       0x8c820020, 0x3c040800, 0x8c830060, 0x24020001, 0x24630001, 0x03e00008,
+       0xac830060, 0xaf420280, 0x94830016, 0x3c060800, 0xa7430284, 0x8c850004,
+       0x8cc4005c, 0x00001021, 0x3c031000, 0x24840001, 0xaf450288, 0xaf4302b8,
+       0x03e00008, 0xacc4005c, 0x14400003, 0x3c040800, 0x03e00008, 0x00001021,
+       0x8c830084, 0x24020001, 0x24630001, 0x03e00008, 0xac830084, 0x27450100,
+       0x3c040800, 0x8c820088, 0x94a3000c, 0x24420001, 0x007a1821, 0xac820088,
+       0x8ca40018, 0x90664000, 0xaf440038, 0x8ca2001c, 0x2403fff8, 0x00063600,
+       0x00431024, 0x34420004, 0x3c030005, 0xaf42003c, 0xaf430030, 0x00000000,
+       0x00000000, 0x00000000, 0xaf460404, 0x00000000, 0x00000000, 0x00000000,
+       0x3c020006, 0x34420001, 0xaf420030, 0x00000000, 0x00000000, 0x00000000,
+       0x8f420000, 0x30420010, 0x1040fffd, 0x00001021, 0x03e00008, 0x00000000,
+       0x3c020800, 0x8c430020, 0x27bdffe8, 0xafb00010, 0x27500100, 0x1060001e,
+       0xafbf0014, 0x0e001006, 0x00000000, 0x8f830018, 0x8e020018, 0xac620000,
+       0x8f840018, 0x9602000c, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018,
+       0xac40000c, 0x8f830018, 0xac600010, 0x8f820018, 0xac400014, 0x8f840018,
+       0x3c026000, 0x8c434448, 0xac830018, 0x96020008, 0x3c030800, 0x9464466e,
+       0x8f850018, 0x00021400, 0x00441025, 0x24040001, 0x0e001044, 0xaca2001c,
+       0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdffc8, 0xafb3001c,
+       0x00009821, 0xafb7002c, 0x0000b821, 0xafbe0030, 0x0000f021, 0xafb50024,
+       0x27550100, 0xafbf0034, 0xafb60028, 0xafb40020, 0xafb20018, 0xafb10014,
+       0xafb00010, 0x96a20008, 0x8f540100, 0x8eb20018, 0x30420001, 0x10400037,
+       0x02a0b021, 0x8f630054, 0x2642ffff, 0x00431023, 0x18400006, 0x00000000,
+       0x0000000d, 0x00000000, 0x24000128, 0x0a000372, 0x00002021, 0x8f62004c,
+       0x02421023, 0x18400028, 0x00002021, 0x93650120, 0x93640121, 0x3c030800,
+       0x8c62008c, 0x308400ff, 0x24420001, 0x30a500ff, 0x00803821, 0x1485000b,
+       0xac62008c, 0x3c040800, 0x8c830090, 0x24630001, 0xac830090, 0x93620122,
+       0x30420001, 0x00021023, 0x30420005, 0x0a000372, 0x34440004, 0x27660100,
+       0x00041080, 0x00c21021, 0x8c430000, 0x02431823, 0x04600004, 0x24820001,
+       0x30440007, 0x1485fff9, 0x00041080, 0x10870007, 0x3c030800, 0xa3640121,
+       0x8c620094, 0x24040005, 0x24420001, 0x0a000372, 0xac620094, 0x24040004,
+       0x00809821, 0x9362003f, 0x304400ff, 0x38830016, 0x2c630001, 0x38820010,
+       0x2c420001, 0x00621825, 0x1460000c, 0x24020001, 0x38830008, 0x2c630001,
+       0x38820014, 0x2c420001, 0x00621825, 0x14600005, 0x24020001, 0x24020012,
+       0x14820002, 0x00001021, 0x24020001, 0x50400007, 0x8eb10020, 0x8ea20020,
+       0x8f630040, 0x00408821, 0x00431023, 0x5c400001, 0x8f710040, 0x9343010b,
+       0x24020004, 0x54620005, 0x36730080, 0x96a20008, 0x36730002, 0x24170001,
+       0x305e0020, 0x2402fffb, 0x02628024, 0x1200002a, 0x3c030800, 0x8c620030,
+       0x02021024, 0x10400026, 0x3c020800, 0x8c430020, 0x10600024, 0x32620004,
+       0x0e001006, 0x00000000, 0x8f830018, 0x8f420100, 0xac620000, 0x8f840018,
+       0x02201821, 0x32620002, 0xac900004, 0x8f840018, 0x50400001, 0x8ec30014,
+       0xac830008, 0x8f830018, 0x8ec20020, 0xac62000c, 0x8f840018, 0x8f620040,
+       0xac820010, 0x8f830018, 0x8ec20018, 0xac620014, 0x8f840018, 0x3c026000,
+       0x8c434448, 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c024010,
+       0x00621825, 0xac83001c, 0x0e001044, 0x24040001, 0x32620004, 0x10400076,
+       0x00003821, 0x3c029000, 0x34420001, 0x3c038000, 0x02821025, 0xa360007c,
+       0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620023,
+       0x30420080, 0x10400011, 0x00000000, 0x8f65005c, 0x8f63004c, 0x9764003c,
+       0x8f620064, 0x00a32823, 0x00852821, 0x00a2102b, 0x54400006, 0x3c023fff,
+       0x93620023, 0x3042007f, 0xa3620023, 0xaf720064, 0x3c023fff, 0x0a0003f1,
+       0x3442ffff, 0x8f62005c, 0x02421023, 0x04400011, 0x00000000, 0x8f65005c,
+       0x8f630064, 0x9764003c, 0x3c023fff, 0x3442ffff, 0xaf720064, 0x00a32823,
+       0x00852821, 0x0045102b, 0x10400004, 0x02451021, 0x3c053fff, 0x34a5ffff,
+       0x02451021, 0xaf62005c, 0x24070001, 0xaf72004c, 0x8f620054, 0x16420005,
+       0x00000000, 0x93620023, 0x30420040, 0x10400017, 0x24020001, 0x9762006a,
+       0x00022880, 0x50a00001, 0x24050001, 0x97630068, 0x93640081, 0x3c020800,
+       0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021,
+       0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, 0x8f420074,
+       0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, 0x34420001,
+       0x02821025, 0xa3600081, 0xaf420020, 0x9363007e, 0x9362007a, 0x10620004,
+       0x00000000, 0x0e000f2a, 0x00000000, 0x00403821, 0x10e00017, 0x3c029000,
+       0x34420001, 0x02821025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024,
+       0x1440fffd, 0x3c028000, 0x9363007d, 0x34420001, 0x3c048000, 0x02821025,
+       0xa363007d, 0xaf420020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002,
+       0x3c031000, 0xaf5401c0, 0xa34201c4, 0xaf4301f8, 0x8ea30014, 0x8f620040,
+       0x14430003, 0x00431023, 0x0a000443, 0x00001021, 0x28420001, 0x10400034,
+       0x00000000, 0x8f620040, 0xaf630040, 0x9362003e, 0x30420001, 0x1440000b,
+       0x3c029000, 0x93620022, 0x24420001, 0xa3620022, 0x93630022, 0x3c020800,
+       0x8c440098, 0x0064182b, 0x1460001e, 0x3c020800, 0x3c029000, 0x34420001,
+       0x02821025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd,
+       0x00000000, 0x3c038000, 0x9362007d, 0x34630001, 0x3c048000, 0x02831825,
+       0x34420001, 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd,
+       0x24020002, 0x3c031000, 0xaf5401c0, 0xa34201c4, 0x24020001, 0xaf4301f8,
+       0xa7620012, 0x0a000476, 0xa3600022, 0x9743007a, 0x9444002a, 0x00641821,
+       0x3063fffe, 0xa7630012, 0x0e000b68, 0x00000000, 0x12e00003, 0x00000000,
+       0x0e000f27, 0x00000000, 0x53c00004, 0x96a20008, 0x0e000c10, 0x00000000,
+       0x96a20008, 0x8fbf0034, 0x8fbe0030, 0x8fb7002c, 0x8fb60028, 0x8fb50024,
+       0x8fb40020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x00021042,
+       0x30420001, 0x03e00008, 0x27bd0038, 0x27bdffe8, 0xafbf0010, 0x97420108,
+       0x2403000b, 0x304400ff, 0x1083004e, 0x2882000c, 0x10400011, 0x24020006,
+       0x1082003e, 0x28820007, 0x10400007, 0x28820008, 0x1080002b, 0x24020001,
+       0x1082002e, 0x3c026000, 0x0a000504, 0x00000000, 0x14400061, 0x2882000a,
+       0x1440002b, 0x00000000, 0x0a0004ec, 0x00000000, 0x2402001c, 0x1082004e,
+       0x2882001d, 0x1040000e, 0x24020019, 0x10820041, 0x2882001a, 0x10400005,
+       0x2402000e, 0x10820036, 0x00000000, 0x0a000504, 0x00000000, 0x2402001b,
+       0x1082003c, 0x00000000, 0x0a000504, 0x00000000, 0x240200c1, 0x10820040,
+       0x288200c2, 0x10400005, 0x24020080, 0x1082001f, 0x00000000, 0x0a000504,
+       0x00000000, 0x240200c2, 0x1082003b, 0x00000000, 0x0a000504, 0x00000000,
+       0x3c026000, 0x0e000c7d, 0xac400808, 0x0a000506, 0x8fbf0010, 0x8c444448,
+       0x3c030800, 0xac640064, 0x0e000c7d, 0x00000000, 0x3c026000, 0x8c444448,
+       0x3c030800, 0x0a000505, 0xac640068, 0x8f440100, 0x0e000508, 0x00000000,
+       0x3c026000, 0x8c444448, 0x3c030800, 0x0a000505, 0xac64006c, 0x0e000cab,
+       0x00000000, 0x0a000506, 0x8fbf0010, 0x8f440100, 0x0e000cd5, 0x00000000,
+       0x0a000506, 0x8fbf0010, 0x0e000d1c, 0x00000000, 0x0a000506, 0x8fbf0010,
+       0x0000000d, 0x0a000506, 0x8fbf0010, 0x0e0005d7, 0x00000000, 0x0a000506,
+       0x8fbf0010, 0x8f440100, 0x0e000d7e, 0x00000000, 0x0a000506, 0x8fbf0010,
+       0x0e000e95, 0x00000000, 0x0a000506, 0x8fbf0010, 0x0e000626, 0x00000000,
+       0x0a000506, 0x8fbf0010, 0x0e000b68, 0x00000000, 0x0a000506, 0x8fbf0010,
+       0x0000000d, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0x3c029000,
+       0x34420001, 0xafb00010, 0x00808021, 0x02021025, 0x3c038000, 0xafbf0014,
+       0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005,
+       0x34420001, 0xa3620005, 0x8f63004c, 0x8f620054, 0x10620019, 0x3c028000,
+       0x9762006a, 0x00022880, 0x50a00001, 0x24050001, 0x97630068, 0x93640081,
+       0x3c020800, 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001,
+       0x00a03021, 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021,
+       0x8f420074, 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000,
+       0x34420001, 0x02021025, 0x0e000c7d, 0xaf420020, 0x3c029000, 0x34420001,
+       0x3c038000, 0x02021025, 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd,
+       0x3c028000, 0x9363007d, 0x34420001, 0x3c048000, 0x02021025, 0xa363007d,
+       0xaf420020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x8fbf0014, 0xaf5001c0,
+       0x8fb00010, 0x24020002, 0x3c031000, 0xa34201c4, 0xaf4301f8, 0x03e00008,
+       0x27bd0018, 0x27bdffd8, 0xafbf0020, 0xafb3001c, 0xafb20018, 0xafb10014,
+       0xafb00010, 0x93630005, 0x00809021, 0x24020030, 0x30630030, 0x14620072,
+       0x00a09821, 0x3c020800, 0x8c430020, 0x1060006c, 0x00000000, 0x0e001006,
+       0x00000000, 0x8f820018, 0xac520000, 0x9363003e, 0x9362003f, 0x8f840018,
+       0x00031a00, 0x00431025, 0xac820004, 0x93630081, 0x93620082, 0x8f850018,
+       0x00031e00, 0x00021400, 0x00621825, 0xaca30008, 0x8f840018, 0x8f620040,
+       0xac82000c, 0x8f830018, 0x8f620048, 0xac620010, 0x8f840018, 0x8f62004c,
+       0x3c110800, 0xac820014, 0x8f830018, 0x8f620050, 0x26304660, 0x00002021,
+       0xac620018, 0x9602000e, 0x8f850018, 0x3c03c00b, 0x00431025, 0x0e001044,
+       0xaca2001c, 0x8f830018, 0x8f620054, 0xac620000, 0x8f840018, 0x8f620058,
+       0xac820004, 0x8f830018, 0x8f62005c, 0xac620008, 0x8f840018, 0x8f620060,
+       0xac82000c, 0x8f850018, 0x8f620064, 0xaca20010, 0x97630068, 0x9762006a,
+       0x8f840018, 0x00031c00, 0x00431025, 0xac820014, 0x8f830018, 0x00002021,
+       0xac600018, 0x9602000e, 0x8f850018, 0x3c03c00c, 0x00431025, 0x0e001044,
+       0xaca2001c, 0x8f840018, 0x8f630018, 0xac830000, 0x936200c4, 0x30420002,
+       0x10400006, 0x00000000, 0x976200c8, 0x8f830018, 0x3042ffff, 0x0a0005b5,
+       0xac620004, 0x8f820018, 0xac400004, 0x8f830018, 0x8f62006c, 0xac620008,
+       0x8f840018, 0x8f6200dc, 0xac82000c, 0x8f830018, 0xac600010, 0x93620005,
+       0x8f830018, 0x00021600, 0x00531025, 0xac620014, 0x8f850018, 0x3c026000,
+       0x8c434448, 0x24040001, 0x26224660, 0xaca30018, 0x9443000e, 0x8f850018,
+       0x3c02400d, 0x00621825, 0x0e001044, 0xaca3001c, 0x0e000d48, 0x02402021,
+       0x8fbf0020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
+       0x27bd0028, 0x27bdffe0, 0xafb00010, 0x27500100, 0xafbf0018, 0xafb10014,
+       0x9603000c, 0x240200c1, 0x5462001d, 0x8e040000, 0x3c029000, 0x8f440100,
+       0x34420001, 0x3c038000, 0x00821025, 0xaf420020, 0x8f420020, 0x00431024,
+       0x1440fffd, 0x00000000, 0x3c038000, 0x9362007d, 0x34630001, 0x3c058000,
+       0x00831825, 0x34420004, 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00451024,
+       0x1440fffd, 0x24020002, 0x3c031000, 0xaf4401c0, 0xa34201c4, 0xaf4301f8,
+       0x0a000622, 0x8fbf0018, 0x8f65004c, 0x24060001, 0x0e000db5, 0x2407049f,
+       0x3c020800, 0x8c430020, 0x9611000c, 0x1060001d, 0x8e100000, 0x0e001006,
+       0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x00111400, 0xac820004,
+       0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010,
+       0x8f840018, 0x240204a2, 0xac820014, 0x8f850018, 0x3c026000, 0x8c434448,
+       0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024019,
+       0x00621825, 0x0e001044, 0xaca3001c, 0x8fbf0018, 0x8fb10014, 0x8fb00010,
+       0x03e00008, 0x27bd0020, 0x27bdffb0, 0xafb1002c, 0x27510100, 0xafbf004c,
+       0xafbe0048, 0xafb70044, 0xafb60040, 0xafb5003c, 0xafb40038, 0xafb30034,
+       0xafb20030, 0xafb00028, 0x8e350000, 0x9634000c, 0x3c026000, 0x8c434448,
+       0x0000f021, 0xaf630170, 0x8f620040, 0x8e230014, 0x0000b821, 0x00431023,
+       0x044001ec, 0x0000b021, 0x32820010, 0x1040002e, 0x3c026000, 0x9363003f,
+       0x9222000e, 0x10430006, 0x2402000c, 0x9223000f, 0x10620003, 0x24020014,
+       0x14620025, 0x3c026000, 0x32820004, 0x10400007, 0x241e0001, 0x8f620050,
+       0x24420001, 0xaf620050, 0x8f630054, 0x24630001, 0xaf630054, 0x32830102,
+       0x24020002, 0x5462000d, 0x9222000f, 0x8f620040, 0x24420001, 0xaf620040,
+       0x8f630048, 0x8f620040, 0x24630001, 0x54620005, 0x9222000f, 0x8f620048,
+       0x24420001, 0xaf620048, 0x9222000f, 0xa362003f, 0x9223000f, 0x24020012,
+       0x14620007, 0x3c026000, 0x3c030800, 0x8c620074, 0x24420001, 0x0e000f6e,
+       0xac620074, 0x3c026000, 0x8c434448, 0x32820040, 0xaf630174, 0x32830020,
+       0xafa30010, 0x32830080, 0xafa30014, 0x32830001, 0xafa3001c, 0x32830008,
+       0xafa30020, 0x32830100, 0x104000bb, 0xafa30018, 0x8e260010, 0x8f630054,
+       0x24c2ffff, 0x00431023, 0x18400006, 0x00000000, 0x0000000d, 0x00000000,
+       0x24000128, 0x0a0006b2, 0x00009021, 0x8f62004c, 0x00c21023, 0x18400028,
+       0x00009021, 0x93650120, 0x93640121, 0x3c030800, 0x8c62008c, 0x308400ff,
+       0x24420001, 0x30a500ff, 0x00804021, 0x1485000b, 0xac62008c, 0x3c040800,
+       0x8c830090, 0x24630001, 0xac830090, 0x93620122, 0x30420001, 0x00021023,
+       0x30420005, 0x0a0006b2, 0x34520004, 0x27670100, 0x00041080, 0x00e21021,
+       0x8c430000, 0x00c31823, 0x04600004, 0x24820001, 0x30440007, 0x1485fff9,
+       0x00041080, 0x10880007, 0x3c030800, 0xa3640121, 0x8c620094, 0x24120005,
+       0x24420001, 0x0a0006b2, 0xac620094, 0x24120004, 0x32420001, 0x10400020,
+       0x3c020800, 0x8c430020, 0x8e300000, 0x1060001c, 0x8e330010, 0x0e001006,
+       0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x24020001, 0xac820004,
+       0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010,
+       0x8f820018, 0xac530014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001,
+       0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024010, 0x00621825,
+       0x0e001044, 0xaca3001c, 0x32420004, 0x10400060, 0x00003821, 0x3c029000,
+       0x8e260010, 0x34420001, 0x3c038000, 0x02a21025, 0xa360007c, 0xaf420020,
+       0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620023, 0x30420080,
+       0x10400011, 0x00000000, 0x8f65005c, 0x8f63004c, 0x9764003c, 0x8f620064,
+       0x00a32823, 0x00852821, 0x00a2102b, 0x54400006, 0x3c023fff, 0x93620023,
+       0x3042007f, 0xa3620023, 0xaf660064, 0x3c023fff, 0x0a000702, 0x3442ffff,
+       0x8f62005c, 0x00c21023, 0x04400011, 0x00000000, 0x8f65005c, 0x8f630064,
+       0x9764003c, 0x3c023fff, 0x3442ffff, 0xaf660064, 0x00a32823, 0x00852821,
+       0x0045102b, 0x10400004, 0x00c51021, 0x3c053fff, 0x34a5ffff, 0x00c51021,
+       0xaf62005c, 0x24070001, 0xaf66004c, 0x8f620054, 0x14c20005, 0x00000000,
+       0x93620023, 0x30420040, 0x10400017, 0x24020001, 0x9762006a, 0x00022880,
+       0x50a00001, 0x24050001, 0x97630068, 0x93640081, 0x3c020800, 0x8c46004c,
+       0x00652821, 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021, 0x3c020800,
+       0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, 0x8f420074, 0x2403fffe,
+       0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, 0x34420001, 0x02a21025,
+       0xa3600081, 0xaf420020, 0x9363007e, 0x9362007a, 0x10620005, 0x00e0b021,
+       0x0e000f2a, 0x00000000, 0x00403821, 0x00e0b021, 0x8fa20010, 0x10400008,
+       0x00000000, 0x8e220018, 0xaf620018, 0x8e23001c, 0xaf63001c, 0x8e220020,
+       0x24160001, 0xaf620058, 0x13c00036, 0x32820004, 0x10400035, 0x8fa30014,
+       0x93620023, 0x30420040, 0x10400031, 0x3c020800, 0x8c430020, 0x1060001c,
+       0x8e300000, 0x0e001006, 0x00000000, 0x8f820018, 0xac500000, 0x8f830018,
+       0xac600004, 0x8f820018, 0xac400008, 0x8f830018, 0xac60000c, 0x8f820018,
+       0xac400010, 0x8f830018, 0x24020587, 0xac620014, 0x8f850018, 0x3c026000,
+       0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018,
+       0x3c024019, 0x00621825, 0x0e001044, 0xaca3001c, 0x3c029000, 0x34420001,
+       0x02a21025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd,
+       0x24020001, 0xaf62000c, 0x93630023, 0x3c028000, 0x34420001, 0x02a21025,
+       0x306300bf, 0xa3630023, 0xaf420020, 0x8fa30014, 0x10600012, 0x8fa3001c,
+       0x9362007c, 0x24420001, 0xa362007c, 0x9363007e, 0x9362007a, 0x1462000b,
+       0x8fa3001c, 0x9362007c, 0x3c030800, 0x8c640024, 0x0044102b, 0x14400005,
+       0x8fa3001c, 0x0e000f2a, 0x00000000, 0x02c2b025, 0x8fa3001c, 0x3062ffff,
+       0x10400003, 0x32820200, 0x0a000793, 0x24170004, 0x10400003, 0x00000000,
+       0x24170040, 0x24160001, 0x13c0005d, 0x32820002, 0x1040005c, 0x8fa20020,
+       0x9222000a, 0x30420020, 0x10400033, 0x3c100800, 0x93620023, 0x30420040,
+       0x1040002f, 0x8e020020, 0x1040001e, 0x3c029000, 0x0e001006, 0x00000000,
+       0x8f820018, 0xac550000, 0x8f840018, 0x3c02008d, 0xac820004, 0x8f830018,
+       0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f840018,
+       0x240205bf, 0xac820014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001,
+       0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024019, 0x00621825,
+       0x0e001044, 0xaca3001c, 0x3c029000, 0x34420001, 0x02a21025, 0xaf420020,
+       0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93630023,
+       0x3c028000, 0x34420001, 0x02a21025, 0x306300bf, 0xa3630023, 0xaf420020,
+       0x8e020020, 0x10400023, 0x8fa20020, 0x0e001006, 0x00000000, 0x8f840018,
+       0x8e230000, 0xac830000, 0x9222000a, 0x8f830018, 0x00021600, 0xac620004,
+       0x8f840018, 0x8f620040, 0xac820008, 0x8f850018, 0x8f63004c, 0xaca3000c,
+       0x9362003f, 0x8f840018, 0x304200ff, 0xac820010, 0x8f830018, 0x3c026000,
+       0xac600014, 0x8f850018, 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018,
+       0x9443466e, 0x8f850018, 0x3c02401a, 0x00621825, 0x0e001044, 0xaca3001c,
+       0x8fa20020, 0x1040000e, 0x8fa20018, 0x9222000a, 0xa3620082, 0x56e00005,
+       0x36f70008, 0x8fa30018, 0x10600004, 0x00000000, 0x36f70008, 0x0a000801,
+       0x24160001, 0x0e000de1, 0x02a02021, 0x8fa20018, 0x10400003, 0x00000000,
+       0x36f70010, 0x24160001, 0x12c00019, 0x3c029000, 0x34420001, 0x02a21025,
+       0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000,
+       0x3c038000, 0x9362007d, 0x34630001, 0x3c048000, 0x02a31825, 0x02e21025,
+       0xa362007d, 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002,
+       0x3c031000, 0xaf5501c0, 0xa34201c4, 0xaf4301f8, 0x9363003f, 0x24020012,
+       0x14620004, 0x3c026000, 0x0e000f6e, 0x00000000, 0x3c026000, 0x8c434448,
+       0xaf630178, 0x8fbf004c, 0x8fbe0048, 0x8fb70044, 0x8fb60040, 0x8fb5003c,
+       0x8fb40038, 0x8fb30034, 0x8fb20030, 0x8fb1002c, 0x8fb00028, 0x03e00008,
+       0x27bd0050, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f500180, 0x97420184,
+       0x30420200, 0x14400015, 0x00000000, 0x8f430188, 0x3c02ff00, 0x00621824,
+       0x3c020200, 0x10620031, 0x0043102b, 0x14400007, 0x3c020300, 0x1060000b,
+       0x3c020100, 0x1062000d, 0x00000000, 0x0a0008b4, 0x00000000, 0x10620027,
+       0x3c020400, 0x1062003e, 0x02002021, 0x0a0008b4, 0x00000000, 0x0e000e1e,
+       0x02002021, 0x0a0008b6, 0x8fbf0014, 0x93620005, 0x30420020, 0x1440005e,
+       0x8fbf0014, 0x3c029000, 0x34420001, 0x02021025, 0xaf420020, 0x3c038000,
+       0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005, 0x3c038000,
+       0x34630001, 0x02031825, 0x34420020, 0xa3620005, 0xaf430020, 0x93620005,
+       0x30420020, 0x14400003, 0x02002021, 0x0000000d, 0x02002021, 0x0e000553,
+       0x24055854, 0x0a0008b6, 0x8fbf0014, 0x93620005, 0x30420001, 0x1040003f,
+       0x3c029000, 0x34420001, 0x02021025, 0xaf420020, 0x3c038000, 0x8f420020,
+       0x00431024, 0x1440fffd, 0x00000000, 0x93620005, 0x3c048000, 0x3c030800,
+       0x304200fe, 0xa3620005, 0x8c620020, 0x34840001, 0x02042025, 0xaf440020,
+       0x1040002d, 0x8fbf0014, 0x0a000894, 0x00000000, 0x00002821, 0x00003021,
+       0x0e000f78, 0x240706a4, 0x3c020800, 0x8c430020, 0x10600023, 0x8fbf0014,
+       0x0e001006, 0x00000000, 0x8f820018, 0xac500000, 0x93630082, 0x9362003f,
+       0x8f840018, 0x00031a00, 0x00431025, 0xac820004, 0x8f830018, 0xac600008,
+       0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018, 0xac400014,
+       0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018,
+       0x9443466e, 0x8f850018, 0x3c02400a, 0x00621825, 0x0e001044, 0xaca3001c,
+       0x0a0008b6, 0x8fbf0014, 0x0000000d, 0x8fbf0014, 0x8fb00010, 0x03e00008,
+       0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x93420148, 0x2444ffff, 0x2c830005,
+       0x10600047, 0x3c020800, 0x24424598, 0x00041880, 0x00621821, 0x8c640000,
+       0x00800008, 0x00000000, 0x8f430144, 0x8f62000c, 0x14620006, 0x24020001,
+       0xaf62000c, 0x0e000909, 0x00000000, 0x0a000907, 0x8fbf0010, 0x8f62000c,
+       0x0a000900, 0x00000000, 0x97630010, 0x8f420144, 0x14430006, 0x24020001,
+       0xa7620010, 0x0e000eeb, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620010,
+       0x0a000900, 0x00000000, 0x97630012, 0x8f420144, 0x14430006, 0x24020001,
+       0xa7620012, 0x0e000f06, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620012,
+       0x0a000900, 0x00000000, 0x97630014, 0x8f420144, 0x14430006, 0x24020001,
+       0xa7620014, 0x0e000f21, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620014,
+       0x0a000900, 0x00000000, 0x97630016, 0x8f420144, 0x14430006, 0x24020001,
+       0xa7620016, 0x0e000f24, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620016,
+       0x14400006, 0x8fbf0010, 0x3c030800, 0x8c620070, 0x24420001, 0xac620070,
+       0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x93620081,
+       0x3c030800, 0x8c640048, 0x0044102b, 0x14400028, 0x3c029000, 0x8f460140,
+       0x34420001, 0x3c038000, 0x00c21025, 0xaf420020, 0x8f420020, 0x00431024,
+       0x1440fffd, 0x3c048000, 0x34840001, 0x3c059000, 0x34a50001, 0x3c078000,
+       0x24020012, 0x24030080, 0x00c42025, 0x00c52825, 0xa362003f, 0xa3630082,
+       0xaf440020, 0xaf450020, 0x8f420020, 0x00471024, 0x1440fffd, 0x3c038000,
+       0x9362007d, 0x34630001, 0x3c048000, 0x00c31825, 0x34420020, 0xa362007d,
+       0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000,
+       0x0a00096d, 0xaf4601c0, 0x93620081, 0x24420001, 0x0e000f2a, 0xa3620081,
+       0x9763006a, 0x00032880, 0x14a00002, 0x00403821, 0x24050001, 0x97630068,
+       0x93640081, 0x3c020800, 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b,
+       0x54400001, 0x00a03021, 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001,
+       0x00c02021, 0x8f420074, 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c,
+       0x10e0001a, 0x3c029000, 0x8f440140, 0x34420001, 0x3c038000, 0x00821025,
+       0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000,
+       0x9362007d, 0x34630001, 0x3c058000, 0x00831825, 0x34420004, 0xa362007d,
+       0xaf430020, 0x8f4201f8, 0x00451024, 0x1440fffd, 0x24020002, 0x3c031000,
+       0xaf4401c0, 0xa34201c4, 0xaf4301f8, 0x8fbf0010, 0x03e00008, 0x27bd0018,
+       0x27bdffd8, 0xafb3001c, 0x27530100, 0xafbf0024, 0xafb40020, 0xafb20018,
+       0xafb10014, 0xafb00010, 0x96620008, 0x3c140800, 0x8f520100, 0x30420001,
+       0x104000cf, 0x00000000, 0x8e700018, 0x8f630054, 0x2602ffff, 0x00431023,
+       0x18400006, 0x00000000, 0x0000000d, 0x00000000, 0x24000128, 0x0a0009b6,
+       0x00008821, 0x8f62004c, 0x02021023, 0x18400028, 0x00008821, 0x93650120,
+       0x93640121, 0x3c030800, 0x8c62008c, 0x308400ff, 0x24420001, 0x30a500ff,
+       0x00803821, 0x1485000b, 0xac62008c, 0x3c040800, 0x8c830090, 0x24630001,
+       0xac830090, 0x93620122, 0x30420001, 0x00021023, 0x30420005, 0x0a0009b6,
+       0x34510004, 0x27660100, 0x00041080, 0x00c21021, 0x8c430000, 0x02031823,
+       0x04600004, 0x24820001, 0x30440007, 0x1485fff9, 0x00041080, 0x10870007,
+       0x3c030800, 0xa3640121, 0x8c620094, 0x24110005, 0x24420001, 0x0a0009b6,
+       0xac620094, 0x24110004, 0x32220001, 0x1040001e, 0x8e820020, 0x1040001d,
+       0x32220004, 0x0e001006, 0x00000000, 0x8f820018, 0xac520000, 0x8f840018,
+       0x24020001, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c,
+       0x8f830018, 0xac600010, 0x8f820018, 0xac500014, 0x8f850018, 0x3c026000,
+       0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018,
+       0x3c024010, 0x00621825, 0x0e001044, 0xaca3001c, 0x32220004, 0x10400076,
+       0x00003821, 0x3c029000, 0x34420001, 0x3c038000, 0x02421025, 0xa360007c,
+       0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620023,
+       0x30420080, 0x10400011, 0x00000000, 0x8f65005c, 0x8f63004c, 0x9764003c,
+       0x8f620064, 0x00a32823, 0x00852821, 0x00a2102b, 0x54400006, 0x3c023fff,
+       0x93620023, 0x3042007f, 0xa3620023, 0xaf700064, 0x3c023fff, 0x0a000a03,
+       0x3442ffff, 0x8f62005c, 0x02021023, 0x04400011, 0x00000000, 0x8f65005c,
+       0x8f630064, 0x9764003c, 0x3c023fff, 0x3442ffff, 0xaf700064, 0x00a32823,
+       0x00852821, 0x0045102b, 0x10400004, 0x02051021, 0x3c053fff, 0x34a5ffff,
+       0x02051021, 0xaf62005c, 0x24070001, 0xaf70004c, 0x8f620054, 0x16020005,
+       0x00000000, 0x93620023, 0x30420040, 0x10400017, 0x24020001, 0x9762006a,
+       0x00022880, 0x50a00001, 0x24050001, 0x97630068, 0x93640081, 0x3c020800,
+       0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021,
+       0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, 0x8f420074,
+       0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, 0x34420001,
+       0x02421025, 0xa3600081, 0xaf420020, 0x9363007e, 0x9362007a, 0x10620004,
+       0x00000000, 0x0e000f2a, 0x00000000, 0x00403821, 0x10e00017, 0x3c029000,
+       0x34420001, 0x02421025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024,
+       0x1440fffd, 0x3c028000, 0x9363007d, 0x34420001, 0x3c048000, 0x02421025,
+       0xa363007d, 0xaf420020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002,
+       0x3c031000, 0xaf5201c0, 0xa34201c4, 0xaf4301f8, 0x9342010b, 0x8e830020,
+       0x27500100, 0x38420006, 0x10600029, 0x2c510001, 0x0e001006, 0x00000000,
+       0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, 0x96020008, 0xac820004,
+       0x8f830018, 0x8e020014, 0xac620008, 0x8f850018, 0x3c026000, 0x8c434448,
+       0xaca3000c, 0x8f840018, 0x96020012, 0xac820010, 0x8f850018, 0x8e030020,
+       0xaca30014, 0x9602000c, 0x9603000e, 0x8f840018, 0x00021400, 0x00431025,
+       0xac820018, 0x12200005, 0x3c020800, 0x9443466e, 0x8f840018, 0x0a000a78,
+       0x3c024013, 0x9443466e, 0x8f840018, 0x3c024014, 0x00621825, 0xac83001c,
+       0x0e001044, 0x24040001, 0x8e630014, 0x8f620040, 0x14430003, 0x00431023,
+       0x0a000a83, 0x00001021, 0x28420001, 0x10400034, 0x00000000, 0x8f620040,
+       0xaf630040, 0x9362003e, 0x30420001, 0x1440000b, 0x3c029000, 0x93620022,
+       0x24420001, 0xa3620022, 0x93630022, 0x3c020800, 0x8c440098, 0x0064182b,
+       0x1460001e, 0x3c020800, 0x3c029000, 0x34420001, 0x02421025, 0xaf420020,
+       0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000,
+       0x9362007d, 0x34630001, 0x3c048000, 0x02431825, 0x34420001, 0xa362007d,
+       0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000,
+       0xaf5201c0, 0xa34201c4, 0x24020001, 0xaf4301f8, 0xa7620012, 0x0a000ab6,
+       0xa3600022, 0x9743007a, 0x9444002a, 0x00641821, 0x3063fffe, 0xa7630012,
+       0x0e000b68, 0x00000000, 0x97420108, 0x8fbf0024, 0x8fb40020, 0x8fb3001c,
+       0x8fb20018, 0x8fb10014, 0x8fb00010, 0x00021042, 0x30420001, 0x03e00008,
+       0x27bd0028, 0x27bdffe0, 0xafb20018, 0x3c120800, 0x8e420020, 0xafb00010,
+       0x27500100, 0xafbf001c, 0x10400046, 0xafb10014, 0x0e001006, 0x00000000,
+       0x8f840018, 0x8e020000, 0xac820000, 0x936300b1, 0x936200c5, 0x8f850018,
+       0x00031e00, 0x00021400, 0x34420100, 0x00621825, 0xaca30004, 0x8f840018,
+       0x8e02001c, 0xac820008, 0x8f830018, 0x8f620048, 0xac62000c, 0x8f840018,
+       0x96020012, 0xac820010, 0x8f830018, 0x8f620040, 0x24040001, 0xac620014,
+       0x8f850018, 0x3c026000, 0x8c434448, 0x3c020800, 0x24514660, 0xaca30018,
+       0x9623000e, 0x8f850018, 0x3c024016, 0x00621825, 0x0e001044, 0xaca3001c,
+       0x96030008, 0x30630010, 0x1060001c, 0x8e420020, 0x1040001a, 0x8e100000,
+       0x0e001006, 0x00000000, 0x8f820018, 0xac500000, 0x8f830018, 0xac600004,
+       0x8f820018, 0xac400008, 0x8f830018, 0xac60000c, 0x8f820018, 0xac400010,
+       0x8f830018, 0xac600014, 0x8f850018, 0x3c036000, 0x8c634448, 0x24040001,
+       0xaca30018, 0x9622000e, 0x8f850018, 0x3c034015, 0x00431025, 0x0e001044,
+       0xaca2001c, 0x00001021, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010,
+       0x03e00008, 0x27bd0020, 0x27bdffe0, 0xafb20018, 0x3c120800, 0x8e420020,
+       0xafb00010, 0x27500100, 0xafbf001c, 0x10400041, 0xafb10014, 0x0e001006,
+       0x00000000, 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, 0x24020100,
+       0xac820004, 0x8f830018, 0x8e02001c, 0xac620008, 0x8f840018, 0x8e020018,
+       0xac82000c, 0x8f830018, 0x96020012, 0xac620010, 0x8f840018, 0x96020008,
+       0xac820014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, 0x3c020800,
+       0x24514660, 0xaca30018, 0x9623000e, 0x8f850018, 0x3c024017, 0x00621825,
+       0x0e001044, 0xaca3001c, 0x96030008, 0x30630010, 0x1060001c, 0x8e420020,
+       0x1040001a, 0x8e100000, 0x0e001006, 0x00000000, 0x8f820018, 0xac500000,
+       0x8f830018, 0xac600004, 0x8f820018, 0xac400008, 0x8f830018, 0xac60000c,
+       0x8f820018, 0xac400010, 0x8f830018, 0xac600014, 0x8f850018, 0x3c036000,
+       0x8c634448, 0x24040001, 0xaca30018, 0x9622000e, 0x8f850018, 0x3c034015,
+       0x00431025, 0x0e001044, 0xaca2001c, 0x00001021, 0x8fbf001c, 0x8fb20018,
+       0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x27bdffe8, 0xafbf0010,
+       0x936200c4, 0x30420002, 0x10400019, 0x00000000, 0x936200c5, 0x936300b1,
+       0x00431023, 0x304400ff, 0x30830080, 0x10600004, 0x00000000, 0x0000000d,
+       0x00000000, 0x24000a6a, 0x93620004, 0x00441023, 0x304400ff, 0x30830080,
+       0x10600004, 0x2482ffff, 0x8f650024, 0x0a000b82, 0x00000000, 0x00022b00,
+       0x8f620024, 0x0045102b, 0x10400002, 0x00000000, 0x8f650024, 0x8f620048,
+       0x8f630040, 0x00431823, 0x0065202b, 0x10800004, 0x00000000, 0x8f620040,
+       0x00451021, 0xaf620048, 0x9762003c, 0x0062102b, 0x10400041, 0x8fbf0010,
+       0x10a0003f, 0x3c029000, 0x34420001, 0x3c040800, 0x8c830080, 0x8f450100,
+       0x3c068000, 0x24630001, 0x00a21025, 0xac830080, 0xaf420020, 0x8f420020,
+       0x00461024, 0x1440fffd, 0x3c038000, 0x9362007d, 0x34630001, 0x3c048000,
+       0x00a31825, 0x34420004, 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00441024,
+       0x1440fffd, 0x24020002, 0x3c030800, 0xaf4501c0, 0xa34201c4, 0x8c640020,
+       0x3c021000, 0xaf4201f8, 0x1080001f, 0x8fbf0010, 0x0e001006, 0x00000000,
+       0x8f830018, 0x8f420100, 0xac620000, 0x8f840018, 0x8f620040, 0xac820004,
+       0x8f850018, 0x8f620048, 0xaca20008, 0x8f830018, 0xac60000c, 0x8f820018,
+       0xac400010, 0x8f830018, 0x3c026000, 0xac600014, 0x8f840018, 0x8c434448,
+       0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c0240c2, 0x00621825,
+       0xac83001c, 0x0e001044, 0x24040001, 0x8fbf0010, 0x03e00008, 0x27bd0018,
+       0x3c020800, 0x24423958, 0xaf82000c, 0x03e00008, 0x00000000, 0x27bdffe8,
+       0xafb00010, 0x27500100, 0xafbf0014, 0x8e02001c, 0x14400003, 0x3c020800,
+       0x0000000d, 0x3c020800, 0x8c430020, 0x10600026, 0x00001021, 0x0e001006,
+       0x00000000, 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, 0x8e02001c,
+       0xac820004, 0x8f830018, 0xac600008, 0x8f840018, 0x8e020018, 0xac82000c,
+       0x8f850018, 0x96020012, 0xaca20010, 0x8f830018, 0x3c106000, 0xac600014,
+       0x8f840018, 0x8e024448, 0x3c030800, 0xac820018, 0x9462466e, 0x8f840018,
+       0x3c034012, 0x00431025, 0xac82001c, 0x0e001044, 0x24040001, 0x8e036800,
+       0x00001021, 0x3c040001, 0x00641825, 0xae036800, 0x0a000c0d, 0x8fbf0014,
+       0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c020800, 0x97430078,
+       0x9444002e, 0x00001021, 0x00641821, 0x3063fffe, 0x03e00008, 0xa7630010,
+       0x27450100, 0x8f640048, 0x8ca30018, 0x00641023, 0x18400021, 0x00000000,
+       0xaf630048, 0x8f620040, 0x9763003c, 0x00821023, 0x0043102a, 0x1040001a,
+       0x3c029000, 0x8ca40000, 0x34420001, 0x3c038000, 0x00821025, 0xaf420020,
+       0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, 0x9362007d,
+       0x34630001, 0x3c058000, 0x00831825, 0x34420004, 0xa362007d, 0xaf430020,
+       0x8f4201f8, 0x00451024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4401c0,
+       0xa34201c4, 0xaf4301f8, 0x03e00008, 0x00001021, 0x8f420100, 0x34420001,
+       0xaf4200a4, 0x03e00008, 0x00001021, 0x27bdffe0, 0xafbf0018, 0xafb10014,
+       0xafb00010, 0x9362007e, 0x30d000ff, 0x16020029, 0x00808821, 0x93620080,
+       0x16020026, 0x00000000, 0x9362007f, 0x16020023, 0x00000000, 0x9362007a,
+       0x16020004, 0x00000000, 0x0000000d, 0x00000000, 0x24000771, 0x0e000f49,
+       0x00000000, 0x3c039000, 0x34630001, 0x3c048000, 0x02231825, 0xa370007a,
+       0xaf430020, 0x8f420020, 0x00441024, 0x1440fffd, 0x3c028000, 0x9363007d,
+       0x34420001, 0x3c048000, 0x02221025, 0xa363007d, 0xaf420020, 0x8f4201f8,
+       0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf5101c0, 0xa34201c4,
+       0xaf4301f8, 0x0a000c79, 0x8fbf0018, 0x0000000d, 0x00000000, 0x24000781,
+       0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c020800,
+       0x8c430020, 0x27bdffe8, 0xafb00010, 0x27500100, 0x10600024, 0xafbf0014,
+       0x0e001006, 0x00000000, 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018,
+       0x8e020004, 0xac820004, 0x8f830018, 0x8e020018, 0xac620008, 0x8f840018,
+       0x8e03001c, 0xac83000c, 0x9602000c, 0x9203000a, 0x8f840018, 0x00021400,
+       0x00431025, 0xac820010, 0x8f830018, 0x3c026000, 0xac600014, 0x8f840018,
+       0x8c434448, 0xac830018, 0x96020008, 0x3c030800, 0x9464466e, 0x8f850018,
+       0x00021400, 0x00441025, 0x24040001, 0x0e001044, 0xaca2001c, 0x8fbf0014,
+       0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c020800, 0x8c430020, 0x27bdffe8,
+       0xafb00010, 0x27500100, 0x10600020, 0xafbf0014, 0x0e001006, 0x00000000,
+       0x8f820018, 0xac400000, 0x8f830018, 0xac600004, 0x8f820018, 0xac400008,
+       0x8f830018, 0xac60000c, 0x9602000c, 0x9603000e, 0x8f840018, 0x00021400,
+       0x00431025, 0xac820010, 0x8f830018, 0x3c026000, 0xac600014, 0x8f840018,
+       0x8c434448, 0xac830018, 0x96020008, 0x3c030800, 0x9464466e, 0x8f850018,
+       0x00021400, 0x00441025, 0x24040001, 0x0e001044, 0xaca2001c, 0x8fbf0014,
+       0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0xafb00010, 0x27500100,
+       0xafbf0014, 0x9602000c, 0x10400024, 0x00802821, 0x3c020800, 0x8c430020,
+       0x1060003a, 0x8fbf0014, 0x0e001006, 0x00000000, 0x8f840018, 0x8e030000,
+       0xac830000, 0x9602000c, 0x8f840018, 0x00021400, 0xac820004, 0x8f830018,
+       0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018,
+       0xac400014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, 0x3c020800,
+       0xaca30018, 0x9443466e, 0x8f850018, 0x3c02400b, 0x00621825, 0x0e001044,
+       0xaca3001c, 0x0a000d19, 0x8fbf0014, 0x93620005, 0x30420010, 0x14400015,
+       0x3c029000, 0x34420001, 0x00a21025, 0xaf420020, 0x3c038000, 0x8f420020,
+       0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, 0x93620005, 0x34630001,
+       0x00a02021, 0x00a31825, 0x24055852, 0x34420010, 0xa3620005, 0x0e000553,
+       0xaf430020, 0x0a000d19, 0x8fbf0014, 0x0000000d, 0x8fbf0014, 0x8fb00010,
+       0x03e00008, 0x27bd0018, 0x3c020800, 0x8c430020, 0x27bdffe8, 0xafb00010,
+       0x27500100, 0x10600022, 0xafbf0014, 0x0e001006, 0x00000000, 0x8f840018,
+       0x8e020004, 0xac820000, 0x9603000c, 0x9762002c, 0x8f840018, 0x00031c00,
+       0x00431025, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c,
+       0x8f830018, 0xac600010, 0x8f820018, 0xac400014, 0x8f850018, 0x3c026000,
+       0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018,
+       0x3c02400e, 0x00621825, 0x0e001044, 0xaca3001c, 0x0e000d48, 0x8e040000,
+       0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c038000, 0x8f420278,
+       0x00431024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf440240, 0xa3420244,
+       0x03e00008, 0xaf430278, 0x3c020800, 0x8c430020, 0x27bdffe0, 0xafb10014,
+       0x00808821, 0xafb20018, 0x00c09021, 0xafb00010, 0x30b0ffff, 0x1060001c,
+       0xafbf001c, 0x0e001006, 0x00000000, 0x8f820018, 0xac510000, 0x8f840018,
+       0x00101400, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c,
+       0x8f830018, 0xac600010, 0x8f820018, 0xac520014, 0x8f840018, 0x3c026000,
+       0x8c434448, 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c024019,
+       0x00621825, 0xac83001c, 0x0e001044, 0x24040001, 0x8fbf001c, 0x8fb20018,
+       0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x27bdffe8, 0x27450100,
+       0xafbf0010, 0x94a3000c, 0x240200c1, 0x14620029, 0x00803021, 0x3c029000,
+       0x34420001, 0x00c21025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024,
+       0x1440fffd, 0x3c028000, 0x34420001, 0x3c049000, 0x34840001, 0x3c058000,
+       0x24030012, 0x00c21025, 0x00c42025, 0xa363003f, 0xaf420020, 0xaf440020,
+       0x8f420020, 0x00451024, 0x1440fffd, 0x3c038000, 0x9362007d, 0x34630001,
+       0x3c048000, 0x00c31825, 0x34420020, 0xa362007d, 0xaf430020, 0x8f4201f8,
+       0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4601c0, 0xa34201c4,
+       0xaf4301f8, 0x0a000db3, 0x8fbf0010, 0x00c02021, 0x94a5000c, 0x24060001,
+       0x0e000f78, 0x240706d8, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x3c020800,
+       0x8c430020, 0x27bdffe0, 0xafb00010, 0x00808021, 0xafb20018, 0x00a09021,
+       0xafb10014, 0x30d100ff, 0x1060001c, 0xafbf001c, 0x0e001006, 0x00000000,
+       0x8f820018, 0xac500000, 0x8f840018, 0x24020001, 0xac820004, 0x8f830018,
+       0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018,
+       0xac520014, 0x8f840018, 0x3c026000, 0x8c434448, 0x3c020800, 0xac830018,
+       0x9443466e, 0x8f840018, 0x3c024010, 0x00621825, 0xac83001c, 0x0e001044,
+       0x02202021, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
+       0x27bd0020, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x93620005, 0x30420001,
+       0x10400033, 0x00808021, 0x3c029000, 0x34420001, 0x02021025, 0xaf420020,
+       0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005,
+       0x3c048000, 0x3c030800, 0x304200fe, 0xa3620005, 0x8c620020, 0x34840001,
+       0x02042025, 0xaf440020, 0x10400020, 0x8fbf0014, 0x0e001006, 0x00000000,
+       0x8f820018, 0xac500000, 0x93630082, 0x9362003f, 0x8f840018, 0x00031a00,
+       0x00431025, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c,
+       0x8f830018, 0xac600010, 0x8f820018, 0xac400014, 0x8f840018, 0x3c026000,
+       0x8c434448, 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c02400a,
+       0x00621825, 0xac83001c, 0x0e001044, 0x24040001, 0x8fbf0014, 0x8fb00010,
+       0x03e00008, 0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x8f420188, 0x00803021,
+       0x9364003f, 0x24030012, 0x00021402, 0x1483001c, 0x304500ff, 0x3c029000,
+       0x34420001, 0x3c038000, 0x00c21025, 0xa3650080, 0xa365007a, 0xaf420020,
+       0x8f420020, 0x00431024, 0x1440fffd, 0x3c028000, 0x9363007d, 0x34420001,
+       0x3c048000, 0x00c21025, 0xa363007d, 0xaf420020, 0x8f4201f8, 0x00441024,
+       0x1440fffd, 0x24020002, 0x3c031000, 0xaf4601c0, 0xa34201c4, 0xaf4301f8,
+       0x0a000e54, 0x8fbf0010, 0x9362007e, 0x1445000e, 0x00000000, 0x93620080,
+       0x1045000b, 0x00000000, 0xa3650080, 0x8f820000, 0x93660080, 0x8f440180,
+       0x8f65004c, 0x8c430000, 0x0060f809, 0x00000000, 0x0a000e54, 0x8fbf0010,
+       0xa3650080, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x3c020800, 0x8c430020,
+       0x27bdffe0, 0xafb10014, 0x00808821, 0xafb20018, 0x00a09021, 0xafb00010,
+       0x30d000ff, 0x1060002f, 0xafbf001c, 0x0e001006, 0x00000000, 0x8f820018,
+       0xac510000, 0x8f830018, 0xac700004, 0x8f820018, 0xac520008, 0x8f830018,
+       0xac60000c, 0x8f820018, 0xac400010, 0x9763006a, 0x00032880, 0x50a00001,
+       0x24050001, 0x97630068, 0x93640081, 0x3c020800, 0x8c46004c, 0x00652821,
+       0x00852804, 0x00c5102b, 0x54400001, 0x00a03021, 0x3c020800, 0x8c440050,
+       0x00c4182b, 0x54600001, 0x00c02021, 0x8f830018, 0x2402fffe, 0x00822824,
+       0x3c026000, 0xac650014, 0x8f840018, 0x8c434448, 0x3c020800, 0xac830018,
+       0x9443466e, 0x8f840018, 0x3c024011, 0x00621825, 0xac83001c, 0x0e001044,
+       0x24040001, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
+       0x27bd0020, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f440100, 0x27500100,
+       0x8f650050, 0x0e000c45, 0x9206001b, 0x3c020800, 0x8c430020, 0x1060001d,
+       0x8e100018, 0x0e001006, 0x00000000, 0x8f840018, 0x8f420100, 0xac820000,
+       0x8f830018, 0xac700004, 0x8f840018, 0x8f620050, 0xac820008, 0x8f830018,
+       0xac60000c, 0x8f820018, 0xac400010, 0x8f830018, 0x3c026000, 0xac600014,
+       0x8f850018, 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e,
+       0x8f850018, 0x3c02401c, 0x00621825, 0x0e001044, 0xaca3001c, 0x8fbf0014,
+       0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c029000, 0x8f460140, 0x34420001,
+       0x3c038000, 0x00c21025, 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd,
+       0x3c048000, 0x34840001, 0x3c059000, 0x34a50001, 0x3c078000, 0x24020012,
+       0x24030080, 0x00c42025, 0x00c52825, 0xa362003f, 0xa3630082, 0xaf440020,
+       0xaf450020, 0x8f420020, 0x00471024, 0x1440fffd, 0x3c038000, 0x9362007d,
+       0x34630001, 0x3c048000, 0x00c31825, 0x34420020, 0xa362007d, 0xaf430020,
+       0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4601c0,
+       0xa34201c4, 0x03e00008, 0xaf4301f8, 0x8f430238, 0x3c020800, 0x04610013,
+       0x8c44009c, 0x2406fffe, 0x3c050800, 0x3c038000, 0x2484ffff, 0x14800009,
+       0x00000000, 0x97420078, 0x8ca3007c, 0x24420001, 0x00461024, 0x24630001,
+       0xa7620010, 0x03e00008, 0xaca3007c, 0x8f420238, 0x00431024, 0x1440fff3,
+       0x2484ffff, 0x8f420140, 0x3c031000, 0xaf420200, 0x03e00008, 0xaf430238,
+       0x3c029000, 0x8f440140, 0x34420001, 0x3c038000, 0x00821025, 0xaf420020,
+       0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, 0x9362007d,
+       0x34630001, 0x3c058000, 0x00831825, 0x34420001, 0xa362007d, 0xaf430020,
+       0x8f4201f8, 0x00451024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4401c0,
+       0xa34201c4, 0x03e00008, 0xaf4301f8, 0x0000000d, 0x03e00008, 0x00000000,
+       0x0000000d, 0x03e00008, 0x00000000, 0x24020001, 0x03e00008, 0xa7620010,
+       0x9362003f, 0x304400ff, 0x3883000e, 0x2c630001, 0x38820010, 0x2c420001,
+       0x00621825, 0x14600003, 0x24020012, 0x14820003, 0x00000000, 0x03e00008,
+       0x00001021, 0x9363007e, 0x9362007a, 0x14620006, 0x00000000, 0x9363007e,
+       0x24020001, 0x24630001, 0x03e00008, 0xa363007e, 0x9363007e, 0x93620080,
+       0x14620004, 0x24020001, 0xa362000b, 0x03e00008, 0x24020001, 0x03e00008,
+       0x00001021, 0x9362000b, 0x10400021, 0x00001021, 0xa360000b, 0x9362003f,
+       0x304400ff, 0x3883000e, 0x2c630001, 0x38820010, 0x2c420001, 0x00621825,
+       0x14600015, 0x00001821, 0x24020012, 0x10820012, 0x00000000, 0x9363007e,
+       0x9362007a, 0x14620007, 0x00000000, 0x9362007e, 0x24030001, 0x24420001,
+       0xa362007e, 0x03e00008, 0x00601021, 0x9363007e, 0x93620080, 0x14620004,
+       0x00001821, 0x24020001, 0xa362000b, 0x24030001, 0x03e00008, 0x00601021,
+       0x03e00008, 0x00000000, 0x24040001, 0xaf64000c, 0x8f6300dc, 0x8f6200cc,
+       0x50620001, 0xa7640010, 0xa7640012, 0xa7640014, 0x03e00008, 0xa7640016,
+       0x27bdffd8, 0xafb00010, 0x00808021, 0xafb3001c, 0x00c09821, 0xafbf0020,
+       0xafb20018, 0xafb10014, 0x93620023, 0x00e09021, 0x30420040, 0x10400020,
+       0x30b1ffff, 0x3c020800, 0x8c430020, 0x1060001c, 0x00000000, 0x0e001006,
+       0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x3c02008d, 0xac820004,
+       0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010,
+       0x8f820018, 0xac520014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001,
+       0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024019, 0x00621825,
+       0x0e001044, 0xaca3001c, 0x93620023, 0x30420020, 0x14400003, 0x3c020800,
+       0x52600020, 0x3c029000, 0x8c430020, 0x1060001d, 0x3c029000, 0x0e001006,
+       0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x00111400, 0xac820004,
+       0x8f830018, 0xac720008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010,
+       0x8f820018, 0xac400014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001,
+       0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c02401b, 0x00621825,
+       0x0e001044, 0xaca3001c, 0x3c029000, 0x34420001, 0x02021025, 0xaf420020,
+       0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93630023,
+       0x3c028000, 0x34420001, 0x02021025, 0x8fbf0020, 0x8fb3001c, 0x8fb20018,
+       0x8fb10014, 0x8fb00010, 0x3063009f, 0xa3630023, 0xaf420020, 0x03e00008,
+       0x27bd0028, 0x3c020800, 0x8c430020, 0x27bdffe8, 0xafb00010, 0x27500100,
+       0x1060001d, 0xafbf0014, 0x0e001006, 0x00000000, 0x8f830018, 0x8e020004,
+       0xac620000, 0x8f840018, 0x8e020018, 0xac820004, 0x8f850018, 0x8e020000,
+       0xaca20008, 0x8f830018, 0xac60000c, 0x8f820018, 0xac400010, 0x8f830018,
+       0xac600014, 0x8f820018, 0xac400018, 0x96030008, 0x3c020800, 0x9444466e,
+       0x8f850018, 0x00031c00, 0x00641825, 0x24040001, 0x0e001044, 0xaca3001c,
+       0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c060800, 0x24c54660,
+       0x3c02000a, 0x03421821, 0x94640006, 0x94a2000a, 0x00441023, 0x00021400,
+       0x00021c03, 0x04610006, 0xa4a40006, 0x0000000d, 0x00000000, 0x2400005a,
+       0x0a00101b, 0x24020001, 0x8f820014, 0x0062102b, 0x14400002, 0x00001021,
+       0x24020001, 0x304200ff, 0x1040001c, 0x274a0400, 0x3c07000a, 0x3c020800,
+       0x24454660, 0x94a9000a, 0x8f880014, 0x03471021, 0x94430006, 0x00402021,
+       0xa4a30006, 0x94820006, 0xa4a20006, 0x01221023, 0x00021400, 0x00021403,
+       0x04410006, 0x0048102b, 0x0000000d, 0x00000000, 0x2400005a, 0x0a001036,
+       0x24020001, 0x14400002, 0x00001021, 0x24020001, 0x304200ff, 0x1440ffec,
+       0x03471021, 0x24c44660, 0x8c820010, 0xaf420038, 0x8c830014, 0x3c020005,
+       0xaf43003c, 0xaf420030, 0xaf800010, 0xaf8a0018, 0x03e00008, 0x00000000,
+       0x27bdffe0, 0x8f820010, 0x8f850018, 0x3c070800, 0x24e84660, 0xafbf001c,
+       0xafb20018, 0xafb10014, 0xafb00010, 0x9503000a, 0x8d060014, 0x00009021,
+       0x309000ff, 0x00e08821, 0x24420001, 0x24a50020, 0x24630001, 0xaf820010,
+       0xaf850018, 0xa503000a, 0x24c30020, 0x3c028000, 0x04c10007, 0xad030014,
+       0x00621024, 0x14400005, 0x26224660, 0x8d020010, 0x24420001, 0xad020010,
+       0x26224660, 0x9444000a, 0x94450018, 0x0010102b, 0x00a41826, 0x2c630001,
+       0x00621825, 0x1060001c, 0x3c030006, 0x8f820010, 0x24120001, 0x00021140,
+       0x00431025, 0xaf420030, 0x00000000, 0x00000000, 0x00000000, 0x27450400,
+       0x8f420000, 0x30420010, 0x1040fffd, 0x26224660, 0x9444000a, 0x94430018,
+       0xaf800010, 0xaf850018, 0x14830012, 0x26274660, 0x0e0010d2, 0x00000000,
+       0x1600000e, 0x26274660, 0x0e001006, 0x00000000, 0x0a00108f, 0x26274660,
+       0x00041c00, 0x00031c03, 0x00051400, 0x00021403, 0x00621823, 0x18600002,
+       0x3c026000, 0xac400808, 0x26274660, 0x94e2000e, 0x94e3000c, 0x24420001,
+       0xa4e2000e, 0x3042ffff, 0x50430001, 0xa4e0000e, 0x12000005, 0x3c02000a,
+       0x94e2000a, 0xa74200a2, 0x0a0010cc, 0x02401021, 0x03421821, 0x94640006,
+       0x94e2000a, 0x00441023, 0x00021400, 0x00021c03, 0x04610006, 0xa4e40006,
+       0x0000000d, 0x00000000, 0x2400005a, 0x0a0010ae, 0x24020001, 0x8f820014,
+       0x0062102b, 0x14400002, 0x00001021, 0x24020001, 0x304200ff, 0x1040001b,
+       0x3c020800, 0x3c06000a, 0x24454660, 0x94a8000a, 0x8f870014, 0x03461021,
+       0x94430006, 0x00402021, 0xa4a30006, 0x94820006, 0xa4a20006, 0x01021023,
+       0x00021400, 0x00021403, 0x04410006, 0x0047102b, 0x0000000d, 0x00000000,
+       0x2400005a, 0x0a0010c8, 0x24020001, 0x14400002, 0x00001021, 0x24020001,
+       0x304200ff, 0x1440ffec, 0x03461021, 0x02401021, 0x8fbf001c, 0x8fb20018,
+       0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c020800, 0x24454660,
+       0x94a3001a, 0x8ca40024, 0x00403021, 0x000318c0, 0x00832021, 0xaf44003c,
+       0x8ca20020, 0xaf420038, 0x3c020050, 0x34420008, 0xaf420030, 0x00000000,
+       0x00000000, 0x00000000, 0x8f420000, 0x30420020, 0x1040fffd, 0x00000000,
+       0x8f430400, 0x24c64660, 0xacc30010, 0x8f420404, 0x3c030020, 0xacc20014,
+       0xaf430030, 0x94c40018, 0x94c3001c, 0x94c2001a, 0x94c5001e, 0x00832021,
+       0x24420001, 0xa4c2001a, 0x3042ffff, 0x14450002, 0xa4c40018, 0xa4c0001a,
+       0x03e00008, 0x00000000, 0x8f820010, 0x3c030006, 0x00021140, 0x00431025,
+       0xaf420030, 0x00000000, 0x00000000, 0x00000000, 0x27430400, 0x8f420000,
+       0x30420010, 0x1040fffd, 0x00000000, 0xaf800010, 0xaf830018, 0x03e00008,
+       0x00000000, 0x27bdffe8, 0xafb00010, 0x3c100800, 0x26104660, 0x3c05000a,
+       0x02002021, 0x03452821, 0xafbf0014, 0x0e001128, 0x2406000a, 0x96020002,
+       0x9603001e, 0x3042000f, 0x24420003, 0x00431804, 0x24027fff, 0x0043102b,
+       0xaf830014, 0x10400004, 0x00000000, 0x0000000d, 0x00000000, 0x24000043,
+       0x0e0010d2, 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018,
+       0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000,
+       0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a001137, 0x00a01021,
+       0xac860000, 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, 0x03e00008,
+       0x00000000, 0x3c036000, 0x8c642b7c, 0x3c036010, 0x8c6553fc, 0x00041582,
+       0x00042302, 0x308403ff, 0x00052d82, 0x00441026, 0x0002102b, 0x0005282b,
+       0x00451025, 0x1440000d, 0x3c020050, 0x34420004, 0xaf400038, 0xaf40003c,
+       0xaf420030, 0x00000000, 0x00000000, 0x8f420000, 0x30420020, 0x1040fffd,
+       0x3c020020, 0xaf420030, 0x0000000d, 0x03e00008, 0x00000000, 0x3c020050,
+       0x34420004, 0xaf440038, 0xaf45003c, 0xaf420030, 0x00000000, 0x00000000,
+       0x8f420000, 0x30420020, 0x1040fffd, 0x3c020020, 0xaf420030, 0x03e00008,
+       0x00000000, 0x00000000 };
+
+static u32 bnx2_COM_b06FwData[(0x0/4) + 1] = { 0x00000000 };
+static u32 bnx2_COM_b06FwRodata[(0x18/4) + 1] = {
+       0x08002318, 0x08002348, 0x08002378, 0x080023a8, 0x080023d8, 0x00000000,
+       0x00000000 };
+
+static u32 bnx2_COM_b06FwBss[(0x88/4) + 1] = { 0x00000000 };
+static u32 bnx2_COM_b06FwSbss[(0x1c/4) + 1] = { 0x00000000 };
+
+static int bnx2_RXP_b06FwReleaseMajor = 0x0;
+static int bnx2_RXP_b06FwReleaseMinor = 0x0;
+static int bnx2_RXP_b06FwReleaseFix = 0x0;
+static u32 bnx2_RXP_b06FwStartAddr = 0x08000060;
+static u32 bnx2_RXP_b06FwTextAddr = 0x08000000;
+static int bnx2_RXP_b06FwTextLen = 0x20b8;
+static u32 bnx2_RXP_b06FwDataAddr = 0x080020e0;
+static int bnx2_RXP_b06FwDataLen = 0x0;
+static u32 bnx2_RXP_b06FwRodataAddr = 0x00000000;
+static int bnx2_RXP_b06FwRodataLen = 0x0;
+static u32 bnx2_RXP_b06FwBssAddr = 0x08002100;
+static int bnx2_RXP_b06FwBssLen = 0x239c;
+static u32 bnx2_RXP_b06FwSbssAddr = 0x080020e0;
+static int bnx2_RXP_b06FwSbssLen = 0x14;
+
+static u32 bnx2_RXP_b06FwText[(0x20b8/4) + 1] = {
+       0x0a000018, 0x00000000, 0x00000000, 0x0000000d, 0x72787020, 0x302e362e,
+       0x39000000, 0x00060903, 0x00000000, 0x0000000d, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c020800,
+       0x244220e0, 0x3c030800, 0x2463449c, 0xac400000, 0x0043202b, 0x1480fffd,
+       0x24420004, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100060,
+       0x3c1c0800, 0x279c20e0, 0x0e000329, 0x00000000, 0x0000000d, 0x8f870008,
+       0x2ce20080, 0x10400018, 0x3c030800, 0x24633490, 0x8f460100, 0x00072140,
+       0x00831021, 0xac460000, 0x8f450104, 0x00641021, 0xac450004, 0x8f460108,
+       0xac460008, 0x8f45010c, 0xac45000c, 0x8f460114, 0xac460010, 0x8f450118,
+       0xac450014, 0x8f460124, 0xac460018, 0x8f450128, 0x00641821, 0x24e20001,
+       0xaf820008, 0xac65001c, 0x03e00008, 0x00000000, 0x00804021, 0x8f830000,
+       0x24070001, 0x3c020001, 0x00621024, 0x10400037, 0x00603021, 0x9742010e,
+       0x3c038000, 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003,
+       0xa342018b, 0x8f840004, 0x24020080, 0x24030002, 0xaf420180, 0xa743018c,
+       0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000069, 0x00021400,
+       0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
+       0x24020003, 0x30838000, 0x1060000d, 0xa7420188, 0x93420116, 0x304200fc,
+       0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, 0x14600005, 0x00000000,
+       0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c,
+       0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6,
+       0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x03e00008, 0x00001021, 0x30c21000,
+       0x1040000f, 0x00000000, 0x9742010c, 0x3042fc00, 0x5440000b, 0x24070005,
+       0x3c021000, 0x00c21024, 0x10400007, 0x3c030dff, 0x3463ffff, 0x3c020e00,
+       0x00c21024, 0x0062182b, 0x54600001, 0x24070005, 0x8f82000c, 0x30434000,
+       0x10600016, 0x00404821, 0x3c020f00, 0x00c21024, 0x14400012, 0x00000000,
+       0x93420116, 0x34424000, 0x03421821, 0x94650002, 0x2ca21389, 0x1040000b,
+       0x3c020800, 0x24422100, 0x00051942, 0x00031880, 0x00621821, 0x30a5001f,
+       0x8c640000, 0x24020001, 0x00a21004, 0x00822024, 0x01044025, 0x11000037,
+       0x3c021000, 0x9742010e, 0x34e60002, 0x3c038000, 0x24420004, 0x3045ffff,
+       0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, 0xa342018b, 0x8f840004,
+       0x24020180, 0x24030002, 0xaf420180, 0xa743018c, 0x10800005, 0xa745018e,
+       0x9743011c, 0x9742011e, 0x0a0000cd, 0x00021400, 0x9743011e, 0x9742011c,
+       0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, 0x30828000, 0x1040000c,
+       0xa7460188, 0x93420116, 0x304200fc, 0x005a1021, 0x24424004, 0x8c430000,
+       0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c,
+       0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff,
+       0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x03e00008,
+       0x00001021, 0x00c21024, 0x104000ba, 0x3c020800, 0x8c430030, 0x1060003e,
+       0x31224000, 0x1040003c, 0x3c030f00, 0x00c31824, 0x3c020100, 0x0043102b,
+       0x14400038, 0x3c030800, 0x9742010e, 0x34e60002, 0x3c038000, 0x24420004,
+       0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, 0xa342018b,
+       0x8f840004, 0x24020080, 0x24030002, 0xaf420180, 0xa743018c, 0x10800005,
+       0xa745018e, 0x9743011c, 0x9742011e, 0x0a000110, 0x00021400, 0x9743011e,
+       0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, 0x30828000,
+       0x1040000c, 0xa7460188, 0x93420116, 0x304200fc, 0x005a1021, 0x24424004,
+       0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, 0x00821024,
+       0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, 0x00031c00,
+       0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, 0xaf4201b8,
+       0x03e00008, 0x00001021, 0x3c030800, 0x8c620024, 0x30420008, 0x1040003d,
+       0x34e80002, 0x3c020f00, 0x00c21024, 0x5440003a, 0x3107ffff, 0x9742010c,
+       0x30420200, 0x50400036, 0x3107ffff, 0x9742010e, 0x30e6fffb, 0x3c038000,
+       0x24420004, 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003,
+       0xa342018b, 0x8f840004, 0x24020180, 0x24030002, 0xaf420180, 0xa743018c,
+       0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000153, 0x00021400,
+       0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
+       0x30828000, 0x1040000c, 0xa7460188, 0x93420116, 0x304200fc, 0x005a1021,
+       0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
+       0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
+       0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
+       0xaf4201b8, 0x3107ffff, 0x8f820000, 0x3c068000, 0x9743010e, 0x00021442,
+       0x30440780, 0x24630004, 0x3065ffff, 0x8f4201b8, 0x00461024, 0x1440fffd,
+       0x24020003, 0xa342018b, 0x8f830004, 0x24020002, 0xaf440180, 0xa742018c,
+       0x10600005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000189, 0x00021400,
+       0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
+       0x30828000, 0x1040000c, 0xa7470188, 0x93420116, 0x304200fc, 0x005a1021,
+       0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
+       0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
+       0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
+       0xaf4201b8, 0x03e00008, 0x00001021, 0x8f424000, 0x30420100, 0x104000ef,
+       0x3c020800, 0x8c440024, 0x24030001, 0x14830036, 0x00404021, 0x9742010e,
+       0x34e50002, 0x3c038000, 0x24420004, 0x3044ffff, 0x8f4201b8, 0x00431024,
+       0x1440fffd, 0x24020003, 0xa342018b, 0x8f830004, 0x24020002, 0xaf400180,
+       0xa742018c, 0x10600005, 0xa744018e, 0x9743011c, 0x9742011e, 0x0a0001c6,
+       0x00021400, 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8,
+       0x8f84000c, 0x30828000, 0x1040000c, 0xa7450188, 0x93420116, 0x304200fc,
+       0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff,
+       0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104,
+       0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac,
+       0x3c021000, 0xaf4201b8, 0x03e00008, 0x00001021, 0x30820001, 0x10400035,
+       0x30e90004, 0x9742010e, 0x30e6fffb, 0x3c038000, 0x24420004, 0x3044ffff,
+       0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, 0xa342018b, 0x8f830004,
+       0x24020002, 0xaf400180, 0xa742018c, 0x10600005, 0xa744018e, 0x9743011c,
+       0x9742011e, 0x0a0001fe, 0x00021400, 0x9743011e, 0x9742011c, 0x00021400,
+       0x00621825, 0xaf4301a8, 0x8f84000c, 0x30828000, 0x1040000c, 0xa7470188,
+       0x93420116, 0x304200fc, 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff,
+       0x14600004, 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e,
+       0x9743010c, 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825,
+       0xa74201a6, 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x30c7ffff, 0x8d020024,
+       0x30420004, 0x10400037, 0x8d020024, 0x9742010e, 0x30e6fffb, 0x3c038000,
+       0x24420004, 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003,
+       0xa342018b, 0x8f840004, 0x24020100, 0x24030002, 0xaf420180, 0xa743018c,
+       0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000237, 0x00021400,
+       0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
+       0x30828000, 0x1040000c, 0xa7470188, 0x93420116, 0x304200fc, 0x005a1021,
+       0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
+       0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
+       0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
+       0xaf4201b8, 0x30c7ffff, 0x8d020024, 0x30420008, 0x10400034, 0x00000000,
+       0x9742010e, 0x3c038000, 0x24420004, 0x3045ffff, 0x8f4201b8, 0x00431024,
+       0x1440fffd, 0x24020003, 0xa342018b, 0x8f840004, 0x24020180, 0x24030002,
+       0xaf420180, 0xa743018c, 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e,
+       0x0a00026f, 0x00021400, 0x9743011e, 0x9742011c, 0x00021400, 0x00621825,
+       0xaf4301a8, 0x8f84000c, 0x30828000, 0x1040000c, 0xa7470188, 0x93420116,
+       0x304200fc, 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004,
+       0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c,
+       0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6,
+       0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x15200046, 0x00001021, 0x3c038000,
+       0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020002, 0x24032000, 0xa342018b,
+       0xa7430188, 0x3c021000, 0xaf4201b8, 0x03e00008, 0x00001021, 0x3c030800,
+       0x8c620024, 0x30420001, 0x10400035, 0x00001021, 0x9742010e, 0x34e50002,
+       0x3c038000, 0x24420004, 0x3044ffff, 0x8f4201b8, 0x00431024, 0x1440fffd,
+       0x24020003, 0xa342018b, 0x8f830004, 0x24020002, 0xaf400180, 0xa742018c,
+       0x10600005, 0xa744018e, 0x9743011c, 0x9742011e, 0x0a0002b5, 0x00021400,
+       0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
+       0x30828000, 0x1040000c, 0xa7450188, 0x93420116, 0x304200fc, 0x005a1021,
+       0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
+       0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
+       0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
+       0xaf4201b8, 0x00001021, 0x03e00008, 0x00000000, 0x27bdffe0, 0xafbf0018,
+       0xafb10014, 0xafb00010, 0x8f420140, 0xaf420020, 0x8f430148, 0x3c027000,
+       0x00621824, 0x3c024000, 0x1062000c, 0x0043102b, 0x14400006, 0x3c025000,
+       0x3c023000, 0x1062000b, 0x3c024000, 0x0a00031f, 0x00000000, 0x10620034,
+       0x3c024000, 0x0a00031f, 0x00000000, 0x0e00067c, 0x00000000, 0x0a00031f,
+       0x3c024000, 0x8f420148, 0x24030002, 0x3044ffff, 0x00021402, 0x305000ff,
+       0x1203000c, 0x27510180, 0x2a020003, 0x10400005, 0x24020003, 0x0600001d,
+       0x36053000, 0x0a00030a, 0x3c038000, 0x12020007, 0x00000000, 0x0a000317,
+       0x00000000, 0x0e000423, 0x00000000, 0x0a000308, 0x00402021, 0x0e000435,
+       0x00000000, 0x00402021, 0x36053000, 0x3c038000, 0x8f4201b8, 0x00431024,
+       0x1440fffd, 0x24020002, 0xa6250008, 0xa222000b, 0xa6240010, 0x8f420144,
+       0x3c031000, 0xae220024, 0xaf4301b8, 0x0a00031f, 0x3c024000, 0x0000000d,
+       0x00000000, 0x240001c3, 0x0a00031f, 0x3c024000, 0x0e0007f7, 0x00000000,
+       0x3c024000, 0xaf420178, 0x00000000, 0x8fbf0018, 0x8fb10014, 0x8fb00010,
+       0x03e00008, 0x27bd0020, 0x24020800, 0x03e00008, 0xaf4201b8, 0x27bdffe8,
+       0x3c04600c, 0xafbf0014, 0xafb00010, 0x8c825000, 0x3c1a8000, 0x2403ff7f,
+       0x3c106000, 0x00431024, 0x3442380c, 0x24030003, 0xac825000, 0x3c040008,
+       0xaf430008, 0x8e020808, 0x3c030800, 0xac600020, 0x3042fff0, 0x2c420001,
+       0xaf820004, 0x0e000819, 0x0344d825, 0x0e000781, 0x00000000, 0x3c020400,
+       0x3442000c, 0x3c03ffff, 0x34630806, 0xae021948, 0xae03194c, 0x8e021980,
+       0x34420200, 0xae021980, 0x8f500000, 0x32020003, 0x1040fffd, 0x32020001,
+       0x10400004, 0x32020002, 0x0e0003bd, 0x00000000, 0x32020002, 0x1040fff6,
+       0x00000000, 0x0e0002d4, 0x00000000, 0x0a00034a, 0x00000000, 0x27bdffe8,
+       0x3c04600c, 0xafbf0014, 0xafb00010, 0x8c825000, 0x3c1a8000, 0x2403ff7f,
+       0x3c106000, 0x00431024, 0x3442380c, 0x24030003, 0xac825000, 0x3c040008,
+       0xaf430008, 0x8e020808, 0x3c030800, 0xac600020, 0x3042fff0, 0x2c420001,
+       0xaf820004, 0x0e000819, 0x0344d825, 0x0e000781, 0x00000000, 0x3c020400,
+       0x3442000c, 0x3c03ffff, 0x34630806, 0xae021948, 0xae03194c, 0x8e021980,
+       0x8fbf0014, 0x34420200, 0xae021980, 0x8fb00010, 0x03e00008, 0x27bd0018,
+       0x30a5ffff, 0x30c6ffff, 0x30e7ffff, 0x3c038000, 0x8f4201b8, 0x00431024,
+       0x1440fffd, 0x24020003, 0xa342018b, 0x8f830004, 0xaf440180, 0xa745018c,
+       0x10600005, 0xa746018e, 0x9743011c, 0x9742011e, 0x0a000393, 0x00021400,
+       0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
+       0x30828000, 0x1040000c, 0xa7470188, 0x93420116, 0x304200fc, 0x005a1021,
+       0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
+       0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
+       0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
+       0xaf4201b8, 0x03e00008, 0x00000000, 0x3c038000, 0x8f4201b8, 0x00431024,
+       0x1440fffd, 0x24020002, 0x24032000, 0xa342018b, 0xa7430188, 0x3c021000,
+       0xaf4201b8, 0x03e00008, 0x00000000, 0x27bdffe8, 0xafbf0010, 0x8f460128,
+       0xaf460020, 0x8f420104, 0x8f450100, 0x24030800, 0x3c040010, 0xaf820000,
+       0x00441024, 0xaf85000c, 0xaf4301b8, 0x14400005, 0x3c02001f, 0x3c030800,
+       0x8c620020, 0x0a0003d5, 0x00002021, 0x3442ff00, 0x14c20009, 0x2402bfff,
+       0x3c030800, 0x8c620020, 0x24040001, 0x24420001, 0x0e00004c, 0xac620020,
+       0x0a0003e4, 0x00000000, 0x00a21024, 0x14400006, 0x00000000, 0xaf400048,
+       0x0e000448, 0xaf400040, 0x0a0003e4, 0x00000000, 0x0e000783, 0x00000000,
+       0x10400005, 0x3c024000, 0x8f430124, 0x3c026020, 0xac430014, 0x3c024000,
+       0xaf420138, 0x00000000, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe0,
+       0xafbf0018, 0xafb10014, 0xafb00010, 0x8f420148, 0x24030002, 0x3044ffff,
+       0x00021402, 0x305000ff, 0x1203000c, 0x27510180, 0x2a020003, 0x10400005,
+       0x24020003, 0x0600001d, 0x36053000, 0x0a00040e, 0x3c038000, 0x12020007,
+       0x00000000, 0x0a00041b, 0x00000000, 0x0e000423, 0x00000000, 0x0a00040c,
+       0x00402021, 0x0e000435, 0x00000000, 0x00402021, 0x36053000, 0x3c038000,
+       0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020002, 0xa6250008, 0xa222000b,
+       0xa6240010, 0x8f420144, 0x3c031000, 0xae220024, 0xaf4301b8, 0x0a00041f,
+       0x8fbf0018, 0x0000000d, 0x00000000, 0x240001c3, 0x8fbf0018, 0x8fb10014,
+       0x8fb00010, 0x03e00008, 0x27bd0020, 0x3084ffff, 0x2c821389, 0x1040000d,
+       0x00001021, 0x3c030800, 0x24632100, 0x00042942, 0x00052880, 0x00a32821,
+       0x3086001f, 0x8ca40000, 0x24030001, 0x00c31804, 0x00832025, 0x03e00008,
+       0xaca40000, 0x03e00008, 0x24020091, 0x3084ffff, 0x2c821389, 0x1040000e,
+       0x00001021, 0x3c030800, 0x24632100, 0x00042942, 0x00052880, 0x00a32821,
+       0x3086001f, 0x24030001, 0x8ca40000, 0x00c31804, 0x00031827, 0x00832024,
+       0x03e00008, 0xaca40000, 0x03e00008, 0x24020091, 0x27bdffb0, 0x3c026000,
+       0xafbf0048, 0x8c434448, 0xaf630140, 0x93620005, 0x30420001, 0x14400005,
+       0x00000000, 0x0e0007ed, 0x00000000, 0x0a00067a, 0x8fbf0048, 0x93420116,
+       0x93430112, 0x8f430104, 0x3c040020, 0x34424000, 0x00641824, 0x1060000d,
+       0x03426021, 0x8f430128, 0x27420180, 0xac430000, 0x8f650040, 0x24040008,
+       0x240340c1, 0xa4430008, 0x24030002, 0xa043000b, 0x3c031000, 0x0a000563,
+       0xa044000a, 0x8f420104, 0x3c030040, 0x00431024, 0x10400007, 0x00000000,
+       0x8f430128, 0x27420180, 0xac430000, 0x8f650040, 0x0a00055c, 0x24040010,
+       0xaf400048, 0xaf400054, 0xaf400040, 0x8f630048, 0x8f620040, 0x00624823,
+       0x05210004, 0x00000000, 0x0000000d, 0x00000000, 0x24000132, 0x9742011a,
+       0x3046ffff, 0x10c00004, 0x8d880004, 0x01061021, 0x0a000487, 0x2445ffff,
+       0x01002821, 0x918a000d, 0xa7a00020, 0xafa00028, 0x9364003f, 0x3c026000,
+       0x8c434448, 0x308700ff, 0x31420004, 0x10400033, 0xaf630144, 0x24090012,
+       0x14e90006, 0x3c040800, 0x8c830028, 0x24020001, 0x24630001, 0x0a00054e,
+       0xac830028, 0x8f620044, 0x15020012, 0x97a20020, 0x27a60010, 0x27450180,
+       0x3442001a, 0xa7a20020, 0x8f630040, 0x3c048000, 0x24020020, 0xa3a70022,
+       0xa3a90023, 0xa3a2001a, 0xafa30028, 0x8f4201b8, 0x00441024, 0x1440fffd,
+       0x00000000, 0x0a000533, 0x00000000, 0x8f620044, 0x01021023, 0x0440009e,
+       0x24020001, 0x8f620048, 0x01021023, 0x0441009a, 0x24020001, 0x97a20020,
+       0x27a60010, 0x34420001, 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000,
+       0xafa30028, 0x8f4201b8, 0x00441024, 0x1440fffd, 0x00000000, 0x0a000533,
+       0x00000000, 0x3c026000, 0x8c424448, 0xaf620148, 0x8f630040, 0x00685823,
+       0x19600013, 0x00cb102a, 0x54400007, 0x314a00fe, 0x5566000c, 0x010b4021,
+       0x31420001, 0x54400009, 0x010b4021, 0x314a00fe, 0x24020001, 0xa7a20020,
+       0x8f630040, 0x00c05821, 0x00003021, 0x0a0004dd, 0xafa30028, 0x00cb1023,
+       0x0a0004dd, 0x3046ffff, 0x00005821, 0x8f620048, 0x2442ffff, 0x00a21823,
+       0x18600019, 0x0066102a, 0x14400013, 0x24020001, 0xa7a20020, 0x8f630040,
+       0xafa30028, 0x8f620040, 0x55020005, 0x27a60010, 0x55200003, 0x27a60010,
+       0x0a0004f6, 0x00c01821, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024,
+       0x1440fffd, 0x00000000, 0x0a000533, 0x00000000, 0x8f650048, 0x00c31023,
+       0x3046ffff, 0x314a00f6, 0x3c046000, 0x8c824448, 0x31430002, 0x1060001e,
+       0xaf62014c, 0x8f620044, 0x1502000e, 0x97a20020, 0x27a60010, 0x34420200,
+       0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000, 0xafa30028, 0x8f4201b8,
+       0x00441024, 0x1440fffd, 0x00000000, 0x0a000533, 0x00000000, 0x27a60010,
+       0x34420001, 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000, 0xafa30028,
+       0x8f4201b8, 0x00441024, 0x1440fffd, 0x00000000, 0x0a000533, 0x00000000,
+       0x3c026000, 0x8c424448, 0x31430010, 0xaf620150, 0x54600003, 0x8d890008,
+       0x0a00054e, 0x24020001, 0x8f630054, 0x2522ffff, 0x00431023, 0x1840002a,
+       0x24020001, 0x27a60010, 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000,
+       0xafa30028, 0x8f4201b8, 0x00441024, 0x1440fffd, 0x00000000, 0x8f420128,
+       0xaca20000, 0x8cc30018, 0x240240c1, 0xa4a20008, 0xaca30018, 0x90c4000a,
+       0x24020002, 0xa0a2000b, 0xa0a4000a, 0x94c20010, 0xa4a20010, 0x90c30012,
+       0xa0a30012, 0x90c20013, 0xa0a20013, 0x8cc30014, 0xaca30014, 0x8cc20024,
+       0xaca20024, 0x8cc30028, 0xaca30028, 0x8cc4002c, 0x24020001, 0x3c031000,
+       0xaca4002c, 0xaf4301b8, 0xaf400044, 0xaf400050, 0x0a00067a, 0x8fbf0048,
+       0x3c026000, 0x8c424448, 0x31430020, 0x10600019, 0xaf620154, 0x8f430128,
+       0x27420180, 0xac430000, 0x8f650040, 0x24040004, 0x240340c1, 0xa4430008,
+       0x24030002, 0xa044000a, 0x24040008, 0xa043000b, 0x3c031000, 0xa4440010,
+       0xa0400012, 0xa0400013, 0xac400014, 0xac400024, 0xac400028, 0xac40002c,
+       0xac450018, 0x0e0007ed, 0xaf4301b8, 0x0a00067a, 0x8fbf0048, 0x8f430104,
+       0x8c824448, 0x38e3000a, 0x2c630001, 0xaf620158, 0x38e2000c, 0x2c420001,
+       0x00621825, 0x14600003, 0x2402000e, 0x14e2002a, 0x00000000, 0x50c00008,
+       0x9584000e, 0x10c00004, 0xa7a60040, 0x01061021, 0x0a000583, 0x2445ffff,
+       0x01002821, 0x9584000e, 0x93630035, 0x8f62004c, 0x00642004, 0x00892021,
+       0x00821023, 0x1840001f, 0x3c026000, 0x8f620018, 0x01021023, 0x1c40000f,
+       0x97a20020, 0x8f620018, 0x15020018, 0x3c026000, 0x8f62001c, 0x01221023,
+       0x1c400008, 0x97a20020, 0x8f62001c, 0x15220011, 0x3c026000, 0x8f620058,
+       0x00821023, 0x1840000c, 0x97a20020, 0xafa50028, 0xafa80034, 0xafa90038,
+       0xafa4003c, 0x34420020, 0x0a0005a8, 0xa7a20020, 0x8f680040, 0x00003021,
+       0x8f640058, 0x01002821, 0x3c026000, 0x8c434448, 0xaf63015c, 0x8f62004c,
+       0x01221023, 0x18400009, 0x00000000, 0x8f620054, 0x01221023, 0x1c400005,
+       0x97a20020, 0xafa50028, 0xafa90024, 0x0a0005c3, 0x34420040, 0x9742011a,
+       0x1440000c, 0x24020014, 0x8f620058, 0x14820009, 0x24020014, 0x8f63004c,
+       0x8f620054, 0x10620004, 0x97a20020, 0xafa50028, 0x34420080, 0xa7a20020,
+       0x24020014, 0x10e2000a, 0x28e20015, 0x10400005, 0x2402000c, 0x10e20006,
+       0x3c026000, 0x0a000600, 0x00000000, 0x24020016, 0x14e20031, 0x3c026000,
+       0x8f620054, 0x24420001, 0x1522002d, 0x3c026000, 0x24020014, 0x10e2001e,
+       0x28e20015, 0x10400005, 0x2402000c, 0x10e20008, 0x3c026000, 0x0a000600,
+       0x00000000, 0x24020016, 0x10e2000c, 0x97a20020, 0x0a000600, 0x3c026000,
+       0x97a30020, 0x2402000e, 0xafa50028, 0xa3a70022, 0xa3a20023, 0xafa90024,
+       0x34630054, 0x0a0005ff, 0xa7a30020, 0x24030010, 0x24040002, 0xafa50028,
+       0xa3a70022, 0xa3a30023, 0xa3a4001a, 0xafa90024, 0x0a0005fe, 0x3442005d,
+       0x97a20020, 0x24030012, 0x24040002, 0xafa50028, 0xa3a70022, 0xa3a30023,
+       0xa3a4001a, 0xafa90024, 0x3042fffe, 0x3442005c, 0xa7a20020, 0x3c026000,
+       0x8c434448, 0x31420001, 0xaf630160, 0x1040002c, 0x2402000c, 0x10e20014,
+       0x28e2000d, 0x10400005, 0x2402000a, 0x10e20008, 0x97a20020, 0x0a000631,
+       0x3c026000, 0x2402000e, 0x10e20018, 0x3c026000, 0x0a000631, 0x00000000,
+       0x24030008, 0x24040002, 0xafa50028, 0xa3a70022, 0xa3a30023, 0xa3a4001a,
+       0x0a00062f, 0x34420013, 0x97a30020, 0x30620004, 0x1440000b, 0x97a20020,
+       0x3462001b, 0xa7a20020, 0x24020016, 0x24030002, 0xafa50028, 0xa3a70022,
+       0xa3a20023, 0x0a000630, 0xa3a3001a, 0x97a20020, 0x24030010, 0x24040002,
+       0xafa50028, 0xa3a70022, 0xa3a30023, 0xa3a4001a, 0x3442001b, 0xa7a20020,
+       0x3c026000, 0x8c434448, 0x31420009, 0x0002102b, 0x00021023, 0x30420007,
+       0x34440003, 0xaf630164, 0x10c00016, 0x24030800, 0x8f820010, 0x27450180,
+       0x24420001, 0xaf820010, 0x24020004, 0xaf4301b8, 0xa4a40008, 0xa0a2000b,
+       0x93440120, 0x3c031000, 0xa4a6000e, 0xaca90024, 0xaca80028, 0x008b2021,
+       0xa4a4000c, 0xaf4301b8, 0x97a20020, 0x00003021, 0x3042ffbf, 0x0a000650,
+       0xa7a20020, 0x24060001, 0x3c026000, 0x8c434448, 0xaf630168, 0x97a20020,
+       0x10400020, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd,
+       0x00000000, 0x8f420128, 0xaca20000, 0x8fa30028, 0x240240c1, 0xa4a20008,
+       0xaca30018, 0x93a4001a, 0x24020002, 0xa0a2000b, 0xa0a4000a, 0x97a20020,
+       0xa4a20010, 0x93a30022, 0xa0a30012, 0x93a20023, 0xa0a20013, 0x8fa30024,
+       0xaca30014, 0x8fa20034, 0xaca20024, 0x8fa30038, 0xaca30028, 0x8fa2003c,
+       0x3c031000, 0xaca2002c, 0xaf4301b8, 0x3c026000, 0x8c434448, 0x00c01021,
+       0xaf63016c, 0x8fbf0048, 0x03e00008, 0x27bd0050, 0x8f460140, 0x8f470148,
+       0x3c028000, 0x00e24024, 0x00072c02, 0x30a300ff, 0x2402000b, 0x1062008f,
+       0x27440180, 0x2862000c, 0x10400011, 0x24020006, 0x1062005a, 0x28620007,
+       0x10400007, 0x24020008, 0x10600024, 0x24020001, 0x10620037, 0x00000000,
+       0x0a00077e, 0x00000000, 0x106200a9, 0x24020009, 0x106200bb, 0x00071c02,
+       0x0a00077e, 0x00000000, 0x2402001b, 0x106200c7, 0x2862001c, 0x10400007,
+       0x2402000e, 0x106200b1, 0x24020019, 0x106200c2, 0x00071c02, 0x0a00077e,
+       0x00000000, 0x24020080, 0x10620060, 0x28620081, 0x10400005, 0x2402001c,
+       0x10620094, 0x00071c02, 0x0a00077e, 0x00000000, 0x240200c2, 0x106200c5,
+       0x00a01821, 0x0a00077e, 0x00000000, 0x00a01821, 0x3c058000, 0x8f4201b8,
+       0x00451024, 0x1440fffd, 0x24020001, 0xa4830008, 0x24030002, 0xac860000,
+       0xac800004, 0xa082000a, 0xa083000b, 0xa4870010, 0x8f430144, 0x3c021000,
+       0xac800028, 0xac830024, 0x3c036000, 0xaf4201b8, 0x03e00008, 0xac600808,
+       0x11000009, 0x00a01821, 0x3c020800, 0x24030002, 0xa0434490, 0x24424490,
+       0xac460008, 0x8f430144, 0x03e00008, 0xac430004, 0x3c058000, 0x8f4201b8,
+       0x00451024, 0x1440fffd, 0x24020002, 0xac800000, 0xac860004, 0xa4830008,
+       0xa082000a, 0xa082000b, 0xa4870010, 0xac800024, 0x8f420144, 0x3c031000,
+       0xac820028, 0x3c026000, 0xaf4301b8, 0x03e00008, 0xac400808, 0x00a01821,
+       0x3c080800, 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x00000000,
+       0xac860000, 0x91024490, 0x00002821, 0x10400002, 0x25064490, 0x8cc50008,
+       0xac850004, 0xa4830008, 0x91034490, 0x24020002, 0xa082000b, 0xa4870010,
+       0x34630001, 0xa083000a, 0x8f420144, 0xac820024, 0x91034490, 0x10600002,
+       0x00001021, 0x8cc20004, 0xac820028, 0x3c021000, 0xaf4201b8, 0x3c026000,
+       0xa1004490, 0x03e00008, 0xac400808, 0x00a01821, 0x3c058000, 0x8f4201b8,
+       0x00451024, 0x1440fffd, 0x24020002, 0xa082000b, 0xa4830008, 0xa4870010,
+       0x8f420144, 0x3c031000, 0xa4820012, 0x03e00008, 0xaf4301b8, 0x30e2ffff,
+       0x14400028, 0x00071c02, 0x93620005, 0x30420004, 0x14400020, 0x3c029000,
+       0x34420001, 0x00c21025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024,
+       0x1440fffd, 0x00000000, 0x93620005, 0x3c038000, 0x34630001, 0x00c31825,
+       0x34420004, 0xa3620005, 0xaf430020, 0x93620005, 0x30420004, 0x14400003,
+       0x3c038000, 0x0000000d, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd,
+       0x24020005, 0x3c031000, 0xac860000, 0xa082000b, 0xaf4301b8, 0x0a00073d,
+       0x00071c02, 0x0000000d, 0x03e00008, 0x00000000, 0x00071c02, 0x3c058000,
+       0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020001, 0xa4830008, 0x24030002,
+       0xac860000, 0xac800004, 0xa082000a, 0xa083000b, 0xa4870010, 0x8f430144,
+       0x3c021000, 0xac800028, 0xac830024, 0x03e00008, 0xaf4201b8, 0x00071c02,
+       0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020002, 0xac800000,
+       0xac860004, 0xa4830008, 0xa082000a, 0xa082000b, 0xa4870010, 0xac800024,
+       0x8f420144, 0x3c031000, 0xac820028, 0x03e00008, 0xaf4301b8, 0x00071c02,
+       0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020001, 0xa4830008,
+       0x24030002, 0xa082000a, 0x3c021000, 0xac860000, 0xac800004, 0xa083000b,
+       0xa4870010, 0xac800024, 0xac800028, 0x03e00008, 0xaf4201b8, 0x3c058000,
+       0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020002, 0xac860000, 0xac800004,
+       0xa4830008, 0xa080000a, 0x0a000748, 0xa082000b, 0x0000000d, 0x03e00008,
+       0x00000000, 0x03e00008, 0x00000000, 0x8f420100, 0x3042003e, 0x14400011,
+       0x24020001, 0xaf400048, 0x8f420100, 0x304207c0, 0x10400005, 0x00000000,
+       0xaf40004c, 0xaf400050, 0x03e00008, 0x24020001, 0xaf400054, 0xaf400040,
+       0x8f420100, 0x30423800, 0x54400001, 0xaf400044, 0x24020001, 0x03e00008,
+       0x00000000, 0x3c029000, 0x34420001, 0x00822025, 0xaf440020, 0x3c038000,
+       0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x03e00008, 0x00000000,
+       0x3c028000, 0x34420001, 0x00822025, 0x03e00008, 0xaf440020, 0x8f430128,
+       0x27420180, 0xac430000, 0x8f650040, 0x240340c1, 0xa4430008, 0x24030002,
+       0xa044000a, 0x24040008, 0xa043000b, 0x3c031000, 0xa4440010, 0xa0400012,
+       0xa0400013, 0xac400014, 0xac400024, 0xac400028, 0xac40002c, 0xac450018,
+       0x03e00008, 0xaf4301b8, 0x24020001, 0xacc40000, 0x03e00008, 0xa4e50000,
+       0x03e00008, 0x24020001, 0x24020001, 0xaf400044, 0x03e00008, 0xaf400050,
+       0x00803021, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd,
+       0x00000000, 0x8f420128, 0xaca20000, 0x8cc30018, 0x240240c1, 0xa4a20008,
+       0xaca30018, 0x90c4000a, 0x24020002, 0xa0a2000b, 0xa0a4000a, 0x94c20010,
+       0xa4a20010, 0x90c30012, 0xa0a30012, 0x90c20013, 0xa0a20013, 0x8cc30014,
+       0xaca30014, 0x8cc20024, 0xaca20024, 0x8cc30028, 0xaca30028, 0x8cc2002c,
+       0x3c031000, 0xaca2002c, 0x24020001, 0xaf4301b8, 0xaf400044, 0x03e00008,
+       0xaf400050, 0x27bdffe8, 0xafbf0010, 0x0e000326, 0x00000000, 0x00002021,
+       0x0e00004c, 0xaf400180, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x8f460148,
+       0x27450180, 0x3c038000, 0x00061402, 0x304700ff, 0x8f4201b8, 0x00431024,
+       0x1440fffd, 0x00000000, 0x8f440140, 0x00061202, 0x304200ff, 0x00061c02,
+       0xaca20004, 0x24020002, 0xa4a30008, 0x30c300ff, 0xa0a2000b, 0xaca30024,
+       0x10e0000a, 0xaca40000, 0x28e20004, 0x14400005, 0x24020001, 0x24020005,
+       0x54e20005, 0xa0a0000a, 0x24020001, 0x0a000816, 0xa0a2000a, 0xa0a0000a,
+       0x3c021000, 0x03e00008, 0xaf4201b8, 0x03e00008, 0x00001021, 0x10c00007,
+       0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000, 0x14c0fffb,
+       0x24840004, 0x03e00008, 0x00000000, 0x0a00082a, 0x00a01021, 0xac860000,
+       0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, 0x03e00008, 0x00000000,
+       0x00000000 }; 
+
+static u32 bnx2_RXP_b06FwData[(0x0/4) + 1] = { 0x00000000 };
+static u32 bnx2_RXP_b06FwRodata[(0x0/4) + 1] = { 0x00000000 };
+static u32 bnx2_RXP_b06FwBss[(0x239c/4) + 1] = { 0x00000000 };
+static u32 bnx2_RXP_b06FwSbss[(0x14/4) + 1] = { 0x00000000 };
+
+static u32 bnx2_rv2p_proc1[] = {
+       0x00000008, 0xac000001, 0x0000000c, 0x2f800001, 0x00000010, 0x213f0004,
+       0x00000010, 0x20bf002c, 0x00000010, 0x203f0143, 0x00000018, 0x8000fffd,
+       0x00000010, 0xb1b8b017, 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000,
+       0x00000000, 0x2c380000, 0x00000008, 0x2c800000, 0x00000008, 0x2d000000,
+       0x00000010, 0x91d40000, 0x00000008, 0x2d800108, 0x00000008, 0x02000002,
+       0x00000010, 0x91de0000, 0x0000000f, 0x42e0001c, 0x00000010, 0x91840a08,
+       0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000008, 0x2d800150,
+       0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x00000010, 0x2c620002,
+       0x00000018, 0x80000012, 0x0000000b, 0x2fdf0002, 0x0000000c, 0x1f800002,
+       0x00000000, 0x2c070000, 0x00000018, 0x8000ffe6, 0x00000008, 0x02000002,
+       0x0000000f, 0x42e0001c, 0x00000010, 0x91840a08, 0x00000008, 0x2c8000b0,
+       0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800108,
+       0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x00000018, 0x80000004,
+       0x0000000c, 0x1f800002, 0x00000000, 0x00000000, 0x00000018, 0x8000ffd9,
+       0x0000000c, 0x29800002, 0x0000000c, 0x1f800002, 0x00000000, 0x2adf0000,
+       0x00000008, 0x2a000005, 0x00000018, 0x8000ffd4, 0x00000008, 0x02240030,
+       0x00000018, 0x00040000, 0x00000018, 0x80000015, 0x00000018, 0x80000017,
+       0x00000018, 0x8000001b, 0x00000018, 0x8000004c, 0x00000018, 0x8000008c,
+       0x00000018, 0x8000000f, 0x00000018, 0x8000000e, 0x00000018, 0x8000000d,
+       0x00000018, 0x8000000c, 0x00000018, 0x800000c2, 0x00000018, 0x8000000a,
+       0x00000018, 0x80000009, 0x00000018, 0x80000008, 0x00000018, 0x800000fd,
+       0x00000018, 0x80000006, 0x00000018, 0x80000005, 0x00000018, 0x800000ff,
+       0x00000018, 0x80000104, 0x00000018, 0x80000002, 0x00000018, 0x80000098,
+       0x00000018, 0x80000000, 0x0000000c, 0x1f800001, 0x00000000, 0x00000000,
+       0x00000018, 0x8000ffba, 0x00000010, 0x91d40000, 0x0000000c, 0x29800001,
+       0x0000000c, 0x1f800001, 0x00000008, 0x2a000002, 0x00000018, 0x8000ffb5,
+       0x00000010, 0xb1a0b012, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c200000,
+       0x00000008, 0x2c800000, 0x00000008, 0x2d000000, 0x00000010, 0x91d40000,
+       0x00000008, 0x2d80011c, 0x00000000, 0x00000000, 0x00000010, 0x91de0000,
+       0x0000000f, 0x47600008, 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000,
+       0x00000000, 0x0f580000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000,
+       0x00000000, 0x0b660000, 0x00000000, 0x0d610000, 0x00000018, 0x80000013,
+       0x0000000f, 0x47600008, 0x0000000b, 0x2fdf0002, 0x00000008, 0x2c800000,
+       0x00000008, 0x2d000000, 0x00000010, 0x91d40000, 0x00000008, 0x2d80011c,
+       0x0000000f, 0x060e0001, 0x00000010, 0x001f0000, 0x00000000, 0x0f580000,
+       0x00000010, 0x91de0000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000,
+       0x00000000, 0x0b660000, 0x00000000, 0x0d610000, 0x00000000, 0x02620000,
+       0x0000000b, 0x2fdf0002, 0x00000000, 0x309a0000, 0x00000000, 0x31040000,
+       0x00000000, 0x0c961800, 0x00000009, 0x0c99ffff, 0x00000004, 0xcc993400,
+       0x00000010, 0xb1963202, 0x00000008, 0x0f800000, 0x0000000c, 0x29800001,
+       0x00000010, 0x00220002, 0x0000000c, 0x29520001, 0x0000000c, 0x29520000,
+       0x00000008, 0x22000001, 0x0000000c, 0x1f800001, 0x00000000, 0x2adf0000,
+       0x00000008, 0x2a000003, 0x00000018, 0x8000ff83, 0x00000010, 0xb1a0b01d,
+       0x0000000b, 0x2fdf0002, 0x00000000, 0x2c200000, 0x00000008, 0x2c8000b0,
+       0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800150,
+       0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800000,
+       0x00000008, 0x2d000000, 0x00000008, 0x2d800108, 0x00000000, 0x00000000,
+       0x00000010, 0x91de0000, 0x0000000f, 0x47600008, 0x00000000, 0x060e0000,
+       0x00000010, 0x001f0000, 0x00000000, 0x0f580000, 0x00000010, 0x91de0000,
+       0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, 0x00000000, 0x0b670000,
+       0x00000000, 0x0d620000, 0x00000000, 0x0ce71800, 0x00000009, 0x0c99ffff,
+       0x00000004, 0xcc993400, 0x00000010, 0xb1963220, 0x00000008, 0x0f800000,
+       0x00000018, 0x8000001e, 0x0000000f, 0x47600008, 0x0000000b, 0x2fdf0002,
+       0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000010, 0x91d40000,
+       0x00000008, 0x2d80012c, 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000,
+       0x00000000, 0x0f580000, 0x00000010, 0x91de0000, 0x00000000, 0x0a640000,
+       0x00000000, 0x0ae50000, 0x00000000, 0x0b670000, 0x00000000, 0x0d620000,
+       0x00000000, 0x02630000, 0x0000000f, 0x47620010, 0x00000000, 0x0ce71800,
+       0x0000000b, 0x2fdf0002, 0x00000000, 0x311a0000, 0x00000000, 0x31840000,
+       0x0000000b, 0xc20000ff, 0x00000002, 0x42040000, 0x00000001, 0x31620800,
+       0x0000000f, 0x020e0010, 0x00000002, 0x31620800, 0x00000009, 0x0c99ffff,
+       0x00000004, 0xcc993400, 0x00000010, 0xb1963202, 0x00000008, 0x0f800000,
+       0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x0000000c, 0x61420006,
+       0x00000008, 0x22000008, 0x00000000, 0x2adf0000, 0x00000008, 0x2a000004,
+       0x00000018, 0x8000ff42, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008,
+       0x00000010, 0x91a0b008, 0x00000010, 0x91d40000, 0x0000000c, 0x31620018,
+       0x00000008, 0x2d800001, 0x00000000, 0x00000000, 0x00000010, 0x91de0000,
+       0x00000008, 0xac000001, 0x00000018, 0x8000000e, 0x00000000, 0x0380b000,
+       0x0000000b, 0x2fdf0002, 0x00000000, 0x2c004000, 0x00000010, 0x91d40000,
+       0x00000008, 0x2d800101, 0x00000000, 0x00000000, 0x00000010, 0x91de0000,
+       0x0000000c, 0x31620018, 0x00000008, 0x2d800001, 0x00000000, 0x00000000,
+       0x00000010, 0x91de0000, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c000e00,
+       0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000008, 0x2a000007,
+       0x00000018, 0x8000ff27, 0x00000010, 0xb1a0b016, 0x0000000b, 0x2fdf0002,
+       0x00000000, 0x03d80000, 0x00000000, 0x2c200000, 0x00000008, 0x2c8000b0,
+       0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800150,
+       0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800000,
+       0x00000008, 0x2d000000, 0x00000008, 0x2d800108, 0x00000008, 0x07000001,
+       0x00000010, 0xb5de1c00, 0x00000010, 0x2c620002, 0x00000018, 0x8000000a,
+       0x0000000b, 0x2fdf0002, 0x00000000, 0x2c070000, 0x0000000c, 0x1f800001,
+       0x00000010, 0x91de0000, 0x00000018, 0x8000ff11, 0x00000008, 0x2c8000b0,
+       0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800108,
+       0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000010, 0x91de0000,
+       0x00000000, 0x2adf0000, 0x00000008, 0x2a00000a, 0x00000018, 0x8000ff07,
+       0x00000000, 0x82265600, 0x0000000f, 0x47220008, 0x00000009, 0x070e000f,
+       0x00000008, 0x070e0008, 0x00000008, 0x02800001, 0x00000007, 0x02851c00,
+       0x00000008, 0x82850001, 0x00000000, 0x02840a00, 0x00000007, 0x42851c00,
+       0x00000003, 0xc3aa5200, 0x00000000, 0x03b10e00, 0x00000010, 0x001f0000,
+       0x0000000f, 0x0f280007, 0x00000007, 0x4b071c00, 0x00000000, 0x00000000,
+       0x0000000f, 0x0a960003, 0x00000000, 0x0a955c00, 0x00000000, 0x4a005a00,
+       0x00000000, 0x0c960a00, 0x00000009, 0x0c99ffff, 0x00000008, 0x0d00ffff,
+       0x00000010, 0xb1963202, 0x00000008, 0x0f800005, 0x00000010, 0x00220020,
+       0x00000000, 0x02a70000, 0x00000010, 0xb1850002, 0x00000008, 0x82850200,
+       0x00000000, 0x02000000, 0x00000000, 0x03a60000, 0x00000018, 0x8000004e,
+       0x00000000, 0x072b0000, 0x00000001, 0x878c1c00, 0x00000000, 0x870e1e00,
+       0x00000000, 0x860c1e00, 0x00000000, 0x03061e00, 0x00000010, 0xb18e0003,
+       0x00000018, 0x80000047, 0x00000018, 0x8000fffa, 0x00000010, 0x918c0003,
+       0x00000010, 0xb1870002, 0x00000018, 0x80000043, 0x00000010, 0x91d40000,
+       0x0000000c, 0x29800001, 0x00000000, 0x2a860000, 0x00000000, 0x230c0000,
+       0x00000000, 0x2b070000, 0x00000010, 0xb187000e, 0x00000008, 0x2a000008,
+       0x00000018, 0x8000003b, 0x00000010, 0x91d40000, 0x00000000, 0x28d18c00,
+       0x00000000, 0x2a860000, 0x00000000, 0x230c0000, 0x00000000, 0x2b070000,
+       0x00000018, 0x8000fff8, 0x00000010, 0x91d40000, 0x0000000c, 0x29800001,
+       0x00000000, 0x2aab0000, 0x00000000, 0xa3265600, 0x00000000, 0x2b000000,
+       0x0000000c, 0x1f800001, 0x00000008, 0x2a000008, 0x00000018, 0x8000fec8,
+       0x00000010, 0x91d40000, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001,
+       0x00000008, 0x2a000009, 0x00000018, 0x8000fec3, 0x00000010, 0x91d40000,
+       0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000000, 0x29420000,
+       0x00000008, 0x2a000002, 0x00000018, 0x8000febd, 0x00000018, 0x8000febc,
+       0x00000010, 0xb1bcb016, 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000,
+       0x00000000, 0x2c3c0000, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008,
+       0x00000010, 0x91d40000, 0x00000008, 0x2d800150, 0x00000000, 0x00000000,
+       0x00000010, 0x205f0000, 0x00000008, 0x2c800000, 0x00000008, 0x2d000000,
+       0x00000008, 0x2d800108, 0x00000008, 0x07000001, 0x00000010, 0xb5de1c00,
+       0x00000010, 0x2c620002, 0x00000018, 0x8000000a, 0x0000000b, 0x2fdf0002,
+       0x00000000, 0x2c070000, 0x0000000c, 0x1f800000, 0x00000010, 0x91de0000,
+       0x00000018, 0x8000fea6, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008,
+       0x00000010, 0x91d40000, 0x00000008, 0x2d800108, 0x0000000c, 0x29800000,
+       0x0000000c, 0x1f800000, 0x00000010, 0x91de0000, 0x00000000, 0x2adf0000,
+       0x00000008, 0x2a000006, 0x00000018, 0x8000fe9c, 0x00000008, 0x03050004,
+       0x00000006, 0x83040c00, 0x00000008, 0x02850200, 0x00000000, 0x86050c00,
+       0x00000001, 0x860c0e00, 0x00000008, 0x02040004, 0x00000000, 0x02041800,
+       0x00000000, 0x83871800, 0x00000018, 0x00020000 };
+
+static u32 bnx2_rv2p_proc2[] = {
+       0x00000000, 0x2a000000, 0x00000010, 0xb1d40000, 0x00000008, 0x02540003,
+       0x00000018, 0x00040000, 0x00000018, 0x8000000a, 0x00000018, 0x8000000a,
+       0x00000018, 0x8000000e, 0x00000018, 0x80000056, 0x00000018, 0x800001b9,
+       0x00000018, 0x800001e1, 0x00000018, 0x8000019b, 0x00000018, 0x800001f9,
+       0x00000018, 0x8000019f, 0x00000018, 0x800001a6, 0x00000018, 0x80000000,
+       0x0000000c, 0x29800001, 0x00000000, 0x2a000000, 0x0000000c, 0x29800000,
+       0x00000010, 0x20530000, 0x00000018, 0x8000ffee, 0x0000000c, 0x29800001,
+       0x00000010, 0x91de0000, 0x00000010, 0x001f0000, 0x00000000, 0x2f80aa00,
+       0x00000000, 0x2a000000, 0x00000000, 0x0d610000, 0x00000000, 0x03620000,
+       0x00000000, 0x2c400000, 0x00000000, 0x02638c00, 0x00000000, 0x26460000,
+       0x00000010, 0x00420002, 0x00000008, 0x02040012, 0x00000010, 0xb9060836,
+       0x00000000, 0x0f580000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000,
+       0x00000000, 0x0b660000, 0x00000000, 0x0c000000, 0x00000000, 0x0b800000,
+       0x00000010, 0x00420009, 0x00000008, 0x0cc60012, 0x00000008, 0x0f800003,
+       0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000008, 0x27110012,
+       0x00000000, 0x66900000, 0x00000008, 0xa31b0012, 0x00000018, 0x80000008,
+       0x00000000, 0x0cc60000, 0x00000008, 0x0f800003, 0x00000000, 0x00000000,
+       0x00000010, 0x009f0000, 0x00000000, 0x27110000, 0x00000000, 0x66900000,
+       0x00000000, 0x231b0000, 0x00000010, 0xb197320e, 0x00000000, 0x25960000,
+       0x00000000, 0x021b0000, 0x00000010, 0x001f0000, 0x00000008, 0x0f800003,
+       0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000000, 0x22c50800,
+       0x00000010, 0x009f0000, 0x00000000, 0x27002200, 0x00000000, 0x26802000,
+       0x00000000, 0x231b0000, 0x0000000c, 0x69520001, 0x00000018, 0x8000fff3,
+       0x00000010, 0x01130002, 0x00000010, 0xb1980003, 0x00000010, 0x001f0000,
+       0x00000008, 0x0f800004, 0x00000008, 0x22000003, 0x00000008, 0x2c80000c,
+       0x00000008, 0x2d00000c, 0x00000010, 0x009f0000, 0x00000000, 0x25960000,
+       0x0000000c, 0x29800000, 0x00000000, 0x32140000, 0x00000000, 0x32950000,
+       0x00000000, 0x33160000, 0x00000000, 0x31e32e00, 0x00000008, 0x2d800010,
+       0x00000010, 0x20530000, 0x00000018, 0x8000ffac, 0x00000000, 0x23000000,
+       0x00000000, 0x25e60000, 0x00000008, 0x2200000b, 0x0000000c, 0x69520000,
+       0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000018, 0x8000ffa5,
+       0x0000000c, 0x29800001, 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000,
+       0x00000010, 0x001f0000, 0x00000000, 0x02700000, 0x00000000, 0x0d620000,
+       0x00000000, 0xbb630800, 0x00000000, 0x2a000000, 0x00000009, 0x076000ff,
+       0x0000000f, 0x2c0e0007, 0x00000008, 0x2c800000, 0x00000008, 0x2d000064,
+       0x00000008, 0x2d80011c, 0x00000009, 0x06420002, 0x0000000c, 0x61420001,
+       0x00000000, 0x0f400000, 0x00000000, 0x02d08c00, 0x00000000, 0x23000000,
+       0x00000004, 0x826da000, 0x00000000, 0x8304a000, 0x00000000, 0x22c50c00,
+       0x00000000, 0x03760000, 0x00000004, 0x83860a00, 0x00000000, 0x83870c00,
+       0x00000010, 0x91de0000, 0x00000000, 0x037c0000, 0x00000000, 0x837b0c00,
+       0x00000001, 0x83060e00, 0x00000000, 0x83870c00, 0x00000000, 0x82850e00,
+       0x00000010, 0xb1860016, 0x0000000f, 0x47610018, 0x00000000, 0x068e0000,
+       0x0000000f, 0x47670010, 0x0000000f, 0x47e20010, 0x00000000, 0x870e1e00,
+       0x00000010, 0xb70e1a10, 0x00000010, 0x0ce7000e, 0x00000008, 0x22000009,
+       0x00000000, 0x286d0000, 0x0000000f, 0x65680010, 0x00000003, 0xf66c9400,
+       0x00000010, 0xb972a003, 0x0000000c, 0x73e70019, 0x0000000c, 0x21420004,
+       0x00000018, 0x8000023f, 0x00000000, 0x37ed0000, 0x0000000c, 0x73e7001a,
+       0x00000010, 0x20530000, 0x00000008, 0x22000008, 0x0000000c, 0x61420004,
+       0x00000000, 0x02f60000, 0x00000004, 0x82840a00, 0x00000010, 0xb1840a2b,
+       0x00000010, 0x2d67000a, 0x00000010, 0xb96d0804, 0x00000004, 0xb6ed0a00,
+       0x00000000, 0x37ed0000, 0x00000018, 0x80000029, 0x0000000c, 0x61420000,
+       0x00000000, 0x37040000, 0x00000000, 0x37850000, 0x0000000c, 0x33e7001a,
+       0x00000018, 0x80000024, 0x00000010, 0xb96d0809, 0x00000004, 0xb6ed0a00,
+       0x00000000, 0x036d0000, 0x00000004, 0xb76e0c00, 0x00000010, 0x91ee0c1f,
+       0x0000000c, 0x73e7001a, 0x00000004, 0xb6ef0c00, 0x00000000, 0x37ed0000,
+       0x00000018, 0x8000001b, 0x0000000c, 0x61420000, 0x00000010, 0xb7ee0a05,
+       0x00000010, 0xb96f0815, 0x00000003, 0xb76e0800, 0x00000004, 0xb7ef0a00,
+       0x00000018, 0x80000015, 0x00000010, 0x0ce7000c, 0x00000008, 0x22000009,
+       0x00000000, 0x286d0000, 0x0000000f, 0x65680010, 0x00000003, 0xf66c9400,
+       0x00000010, 0xb972a003, 0x0000000c, 0x73e70019, 0x0000000c, 0x21420004,
+       0x00000018, 0x80000215, 0x00000010, 0x20530000, 0x00000008, 0x22000008,
+       0x0000000c, 0x61420004, 0x00000000, 0x37040000, 0x00000000, 0x37850000,
+       0x00000000, 0x036d0000, 0x00000003, 0xb8f10c00, 0x00000018, 0x80000004,
+       0x00000000, 0x02840000, 0x00000002, 0x21421800, 0x0000000c, 0x61420000,
+       0x00000000, 0x286d0000, 0x0000000f, 0x65ed0010, 0x00000009, 0x266dffff,
+       0x00000000, 0x23000000, 0x00000010, 0xb1840a3d, 0x00000010, 0x01420002,
+       0x00000004, 0xb8f10a00, 0x00000003, 0x83760a00, 0x00000010, 0xb8040c39,
+       0x00000010, 0xb7e6080a, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000,
+       0x00000009, 0x0c68ffff, 0x00000009, 0x0b67ffff, 0x00000000, 0x0be60000,
+       0x00000000, 0x0c840000, 0x00000010, 0xb197320c, 0x00000008, 0x0f800002,
+       0x00000018, 0x8000000a, 0x00000000, 0x0a6a0000, 0x00000000, 0x0aeb0000,
+       0x00000000, 0x0c000000, 0x00000009, 0x0b6cffff, 0x00000000, 0x0be90000,
+       0x00000000, 0x0c840000, 0x00000010, 0xb1973203, 0x00000008, 0x0f800002,
+       0x00000018, 0x80000001, 0x00000010, 0x001f0000, 0x00000000, 0x0c860000,
+       0x00000000, 0x06980000, 0x00000008, 0x0f800003, 0x00000000, 0x00000000,
+       0x00000010, 0x009f0000, 0x00000010, 0xb1973210, 0x00000000, 0x231b0000,
+       0x00000000, 0x02043600, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010,
+       0x00000009, 0x2607ffff, 0x00000000, 0x27111a00, 0x00000000, 0x66900000,
+       0x0000000c, 0x29000000, 0x00000018, 0x800001de, 0x00000000, 0x06980000,
+       0x00000010, 0x20530000, 0x00000000, 0x22c58c00, 0x00000010, 0x001f0000,
+       0x00000008, 0x0f800003, 0x00000018, 0x8000fff0, 0x00000000, 0x02043600,
+       0x00000000, 0x231b0000, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010,
+       0x00000009, 0x2607ffff, 0x00000000, 0x27111a00, 0x00000000, 0x66900000,
+       0x0000000c, 0x29000000, 0x00000010, 0x91840a02, 0x00000002, 0x21421800,
+       0x00000000, 0x32140000, 0x00000000, 0x32950000, 0x00000005, 0x73e72c00,
+       0x00000005, 0x74683000, 0x00000000, 0x33170000, 0x00000018, 0x80000138,
+       0x00000010, 0x91c60004, 0x00000008, 0x07000004, 0x00000010, 0xb1c41c02,
+       0x00000010, 0x91840a04, 0x00000018, 0x800001c3, 0x00000010, 0x20530000,
+       0x00000000, 0x22c58c00, 0x00000010, 0xb1840a8e, 0x0000000c, 0x21420006,
+       0x00000010, 0x0ce7001a, 0x0000000f, 0x43680010, 0x00000000, 0x03f30c00,
+       0x00000010, 0x91870850, 0x0000000f, 0x46ec0010, 0x00000010, 0xb68d0c4e,
+       0x00000000, 0x838d0c00, 0x00000000, 0xa3050800, 0x00000001, 0xa3460e00,
+       0x00000000, 0x02048c00, 0x00000010, 0x91840a02, 0x00000002, 0x21421800,
+       0x00000010, 0x001f0000, 0x00000008, 0x22000008, 0x00000003, 0x8384a000,
+       0x0000000f, 0x65870010, 0x00000009, 0x2607ffff, 0x00000000, 0x27750c00,
+       0x00000000, 0x66f40000, 0x0000000c, 0x29000000, 0x00000018, 0x800001aa,
+       0x00000000, 0x03068c00, 0x00000003, 0xf4680c00, 0x00000010, 0x20530000,
+       0x00000000, 0x22c58c00, 0x00000018, 0x8000ffe5, 0x00000000, 0x39760000,
+       0x00000000, 0x39840000, 0x0000000c, 0x33e70019, 0x00000010, 0x001f0000,
+       0x00000000, 0x031e0000, 0x00000000, 0x0760fe00, 0x0000000f, 0x0f0e0007,
+       0x00000000, 0x83850800, 0x00000000, 0x0a7d0000, 0x00000000, 0x0afe0000,
+       0x00000000, 0x0b7f0000, 0x00000000, 0x0d7a0000, 0x00000000, 0x0c000000,
+       0x00000000, 0x0bfc0000, 0x00000000, 0x0c970e00, 0x00000008, 0x0f800003,
+       0x0000000f, 0x47670010, 0x00000008, 0x070e0001, 0x0000000b, 0xc38000ff,
+       0x00000002, 0x43870000, 0x00000001, 0x33e70e00, 0x0000000f, 0x038e0010,
+       0x00000002, 0x33e70e00, 0x00000000, 0x28f30000, 0x00000010, 0x009f0000,
+       0x00000000, 0x02043600, 0x00000010, 0x91840a02, 0x00000002, 0x21421800,
+       0x00000008, 0x22000006, 0x00000000, 0x231b0000, 0x00000000, 0x23ff0000,
+       0x00000000, 0x241b0000, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010,
+       0x00000009, 0x2607ffff, 0x00000000, 0x27110000, 0x00000000, 0x26900000,
+       0x0000000c, 0x29000000, 0x00000018, 0x8000017e, 0x00000003, 0xf4683600,
+       0x00000000, 0x3a100000, 0x00000000, 0x3a910000, 0x00000003, 0xf66c2400,
+       0x00000010, 0x001f0000, 0x00000010, 0xb1923604, 0x00000008, 0x0f800004,
+       0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000000, 0x3e170000,
+       0x00000000, 0x3e940000, 0x00000000, 0x3f150000, 0x00000000, 0x3f960000,
+       0x00000010, 0x001f0000, 0x00000000, 0x0f060000, 0x00000010, 0x20530000,
+       0x00000000, 0x22c53600, 0x00000018, 0x8000ffac, 0x00000010, 0x001f0000,
+       0x00000000, 0x031e0000, 0x00000000, 0x83850800, 0x00000009, 0x076000ff,
+       0x0000000f, 0x0f0e0007, 0x00000000, 0x0c000000, 0x00000000, 0x0a7d0000,
+       0x00000000, 0x0afe0000, 0x00000000, 0x0b7f0000, 0x00000000, 0x0d7a0000,
+       0x00000000, 0x0bfc0000, 0x00000000, 0x0c970e00, 0x00000008, 0x0f800003,
+       0x0000000f, 0x47670010, 0x00000008, 0x070e0001, 0x0000000b, 0xc38000ff,
+       0x00000002, 0x43870000, 0x00000001, 0x33e70e00, 0x0000000f, 0x038e0010,
+       0x00000002, 0x33e70e00, 0x00000000, 0x39840000, 0x00000003, 0xb9720800,
+       0x00000000, 0x28f30000, 0x0000000f, 0x65680010, 0x00000010, 0x009f0000,
+       0x00000000, 0x02043600, 0x00000010, 0x91840a02, 0x00000002, 0x21421800,
+       0x00000008, 0x22000007, 0x00000000, 0x231b0000, 0x00000000, 0x23ff0000,
+       0x00000000, 0x241b0000, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010,
+       0x00000009, 0x2607ffff, 0x00000000, 0x27110000, 0x00000000, 0x26900000,
+       0x0000000c, 0x29000000, 0x00000018, 0x80000145, 0x00000003, 0xf4683600,
+       0x00000000, 0x3a100000, 0x00000000, 0x3a910000, 0x00000003, 0xf66c2400,
+       0x00000010, 0x001f0000, 0x00000010, 0xb1923604, 0x00000008, 0x0f800004,
+       0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000000, 0x3e170000,
+       0x00000000, 0x3e940000, 0x00000000, 0x3f150000, 0x00000000, 0x3f960000,
+       0x00000010, 0x001f0000, 0x00000000, 0x0f060000, 0x00000010, 0x20530000,
+       0x00000000, 0x22c53600, 0x00000018, 0x8000ff73, 0x00000010, 0x0ce70005,
+       0x00000008, 0x2c80000c, 0x00000008, 0x2d000070, 0x00000008, 0x2d800010,
+       0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000018, 0x8000011d,
+       0x00000000, 0x2c1e0000, 0x00000008, 0x2c8000b8, 0x00000008, 0x2d000010,
+       0x00000008, 0x2d800048, 0x00000000, 0x00000000, 0x00000010, 0x91de0000,
+       0x00000018, 0x8000fe5d, 0x0000000c, 0x29800001, 0x00000000, 0x2a000000,
+       0x00000010, 0x001f0000, 0x00000000, 0x0f008000, 0x00000008, 0x0f800007,
+       0x00000018, 0x80000006, 0x0000000c, 0x29800001, 0x00000000, 0x2a000000,
+       0x00000010, 0x001f0000, 0x0000000f, 0x0f470007, 0x00000008, 0x0f800008,
+       0x00000018, 0x80000119, 0x00000010, 0x20530000, 0x00000018, 0x8000fe4f,
+       0x0000000c, 0x29800001, 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000,
+       0x00000000, 0x2a000000, 0x00000009, 0x0261ffff, 0x0000000d, 0x70e10001,
+       0x00000018, 0x80000101, 0x00000000, 0x2c400000, 0x00000008, 0x2c8000c4,
+       0x00000008, 0x2d00001c, 0x00000008, 0x2d800001, 0x00000005, 0x70e10800,
+       0x00000010, 0x91de0000, 0x00000018, 0x8000fe41, 0x0000000c, 0x29800001,
+       0x00000010, 0x91de0000, 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000,
+       0x00000000, 0x02700000, 0x00000000, 0x0d620000, 0x00000000, 0xbb630800,
+       0x00000000, 0x2a000000, 0x00000000, 0x0f400000, 0x00000000, 0x2c400000,
+       0x0000000c, 0x73e7001b, 0x00000010, 0x0ce7000e, 0x00000000, 0x286d0000,
+       0x0000000f, 0x65ed0010, 0x00000009, 0x266dffff, 0x00000018, 0x80000069,
+       0x00000008, 0x02000004, 0x00000010, 0x91c40803, 0x00000018, 0x800000f6,
+       0x00000010, 0x20530000, 0x00000018, 0x800000e5, 0x00000008, 0x2c8000b8,
+       0x00000008, 0x2d000010, 0x00000008, 0x2d800048, 0x00000018, 0x80000005,
+       0x00000008, 0x2c8000c4, 0x00000008, 0x2d00001c, 0x00000008, 0x2d800001,
+       0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800048,
+       0x00000008, 0x2d000068, 0x00000008, 0x2d800104, 0x00000000, 0x00000000,
+       0x00000010, 0x91de0000, 0x00000000, 0x27f60000, 0x00000010, 0xb87a9e04,
+       0x00000008, 0x2200000d, 0x00000018, 0x800000e2, 0x00000010, 0x20530000,
+       0x00000018, 0x8000fe18, 0x0000000c, 0x29800001, 0x00000010, 0x91de0000,
+       0x00000000, 0x2fd50000, 0x00000010, 0x001f0000, 0x00000000, 0x02700000,
+       0x00000000, 0x0d620000, 0x00000000, 0xbb630800, 0x00000000, 0x2a000000,
+       0x00000010, 0x0e670011, 0x00000000, 0x286d0000, 0x0000000f, 0x65ed0010,
+       0x00000009, 0x266dffff, 0x00000004, 0xb8f1a000, 0x00000000, 0x0f400000,
+       0x0000000c, 0x73e7001c, 0x00000018, 0x80000040, 0x00000008, 0x02000004,
+       0x00000010, 0x91c40802, 0x00000018, 0x800000cd, 0x00000000, 0x2c1e0000,
+       0x00000008, 0x2c8000b8, 0x00000008, 0x2d000010, 0x00000008, 0x2d800048,
+       0x00000010, 0x20530000, 0x00000010, 0x91de0000, 0x00000018, 0x8000fdfe,
+       0x0000000c, 0x29800001, 0x00000000, 0x03550000, 0x00000000, 0x06460000,
+       0x00000000, 0x03d60000, 0x00000000, 0x2a000000, 0x0000000f, 0x0f480007,
+       0x00000010, 0xb18c0027, 0x0000000f, 0x47420008, 0x00000009, 0x070e000f,
+       0x00000008, 0x070e0008, 0x00000010, 0x001f0000, 0x00000008, 0x09000001,
+       0x00000007, 0x09121c00, 0x00000003, 0xcbca9200, 0x00000000, 0x0b97a200,
+       0x00000007, 0x4b171c00, 0x0000000f, 0x0a960003, 0x00000000, 0x0a959c00,
+       0x00000000, 0x4a009a00, 0x00000008, 0x82120001, 0x00000001, 0x0c170800,
+       0x00000000, 0x02180000, 0x00000000, 0x0c971800, 0x00000008, 0x0d00ffff,
+       0x00000008, 0x0f800006, 0x0000000c, 0x29000000, 0x00000008, 0x22000001,
+       0x00000000, 0x22c50c00, 0x00000010, 0x009f0000, 0x00000010, 0xb197320b,
+       0x00000000, 0x231b0000, 0x00000000, 0x27110800, 0x00000000, 0x66900000,
+       0x00000018, 0x800000a4, 0x00000000, 0x02180000, 0x00000010, 0x20530000,
+       0x00000000, 0x22c53600, 0x00000010, 0x001f0000, 0x00000008, 0x0f800006,
+       0x00000018, 0x8000fff5, 0x00000010, 0x91870002, 0x00000008, 0x2200000a,
+       0x00000000, 0x231b0000, 0x00000000, 0x27110800, 0x00000000, 0x66900000,
+       0x00000018, 0x80000098, 0x00000008, 0x0200000a, 0x00000010, 0x91c40804,
+       0x00000010, 0x02c20003, 0x00000010, 0x001f0000, 0x00000008, 0x0f800008,
+       0x00000010, 0x20530000, 0x00000018, 0x8000fdc9, 0x00000000, 0x06820000,
+       0x00000010, 0x001f0000, 0x00000010, 0x0ce70028, 0x00000000, 0x03720000,
+       0x00000000, 0xa8760c00, 0x00000000, 0x0cf60000, 0x00000010, 0xb8723224,
+       0x00000000, 0x03440000, 0x00000008, 0x22000010, 0x00000000, 0x03ca0000,
+       0x0000000f, 0x65680010, 0x00000000, 0x0bcf0000, 0x00000000, 0x27f20000,
+       0x00000010, 0xb7ef3203, 0x0000000c, 0x21420004, 0x0000000c, 0x73e70019,
+       0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x00000018, 0x8000007e,
+       0x00000004, 0xb9723200, 0x00000010, 0x20530000, 0x00000000, 0x22060000,
+       0x0000000c, 0x61420004, 0x00000000, 0x25070000, 0x00000000, 0x27970000,
+       0x00000000, 0x290e0000, 0x00000010, 0x0ce70010, 0x00000010, 0xb873320f,
+       0x0000000f, 0x436c0010, 0x00000000, 0x03f30c00, 0x00000000, 0x03f30000,
+       0x00000000, 0x83990e00, 0x00000001, 0x83860e00, 0x00000000, 0x83060e00,
+       0x00000003, 0xf66c0c00, 0x00000000, 0x39f30e00, 0x00000000, 0x3af50e00,
+       0x00000000, 0x7a740000, 0x0000000f, 0x43680010, 0x00000001, 0x83860e00,
+       0x00000000, 0x83060e00, 0x00000003, 0xf4680c00, 0x00000000, 0x286d0000,
+       0x00000000, 0x03690000, 0x00000010, 0xb1f60c54, 0x00000000, 0x0a6a0000,
+       0x00000000, 0x0aeb0000, 0x00000009, 0x0b6cffff, 0x00000000, 0x0c000000,
+       0x00000000, 0x0be90000, 0x00000003, 0x8cf6a000, 0x0000000c, 0x09800002,
+       0x00000010, 0x009f0000, 0x00000010, 0xb8173209, 0x00000000, 0x35140000,
+       0x00000000, 0x35950000, 0x00000005, 0x766c2c00, 0x00000000, 0x34970000,
+       0x00000004, 0xb8f12e00, 0x00000010, 0x001f0000, 0x00000008, 0x0f800004,
+       0x00000018, 0x8000fff7, 0x00000000, 0x03e90000, 0x00000010, 0xb8f6a01a,
+       0x00000010, 0x20130019, 0x00000010, 0xb1f10e18, 0x00000000, 0x83973200,
+       0x00000000, 0x38700e00, 0x00000000, 0xbb760e00, 0x00000000, 0x37d00000,
+       0x0000000c, 0x73e7001a, 0x00000003, 0xb8f1a000, 0x00000000, 0x32140000,
+       0x00000000, 0x32950000, 0x00000005, 0x73e72c00, 0x00000000, 0x33190000,
+       0x00000005, 0x74680000, 0x00000010, 0x0ce7000d, 0x00000008, 0x22000009,
+       0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x0000000c, 0x73e70019,
+       0x0000000f, 0x65680010, 0x0000000c, 0x21420004, 0x00000018, 0x8000003c,
+       0x00000010, 0x20530000, 0x0000000c, 0x61420004, 0x00000000, 0x290e0000,
+       0x00000018, 0x80000002, 0x00000010, 0x91973206, 0x00000000, 0x35140000,
+       0x00000000, 0x35950000, 0x00000005, 0x766c2c00, 0x00000000, 0x34990000,
+       0x00000004, 0xb8f13200, 0x00000000, 0x83690c00, 0x00000010, 0xb1860013,
+       0x00000000, 0x28e90000, 0x00000008, 0x22000004, 0x00000000, 0x23ec0000,
+       0x00000000, 0x03690000, 0x00000010, 0xb8660c07, 0x00000009, 0x036cffff,
+       0x00000000, 0x326a0000, 0x00000000, 0x32eb0000, 0x00000005, 0x73e70c00,
+       0x00000000, 0x33690000, 0x00000005, 0x74680000, 0x0000000c, 0x73e7001c,
+       0x00000000, 0x03690000, 0x00000010, 0xb1f60c12, 0x00000010, 0xb1d00c11,
+       0x0000000c, 0x21420005, 0x0000000c, 0x33e7001c, 0x00000018, 0x8000000e,
+       0x00000010, 0x2e67000d, 0x00000000, 0x03690000, 0x00000010, 0xb1f60c0b,
+       0x00000010, 0xb1d00c0a, 0x00000000, 0x03440000, 0x00000008, 0x2200000c,
+       0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x00000018, 0x80000015,
+       0x0000000c, 0x33e7001c, 0x00000010, 0x20530000, 0x00000000, 0x22060000,
+       0x00000000, 0x290e0000, 0x00000018, 0x000d0000, 0x00000000, 0x06820000,
+       0x00000010, 0x2de7000d, 0x00000010, 0x0ce7000c, 0x00000000, 0x27f20000,
+       0x00000010, 0xb96d9e0a, 0x00000000, 0xa86d9e00, 0x00000009, 0x0361ffff,
+       0x00000010, 0xb7500c07, 0x00000008, 0x2200000f, 0x0000000f, 0x65680010,
+       0x00000000, 0x29000000, 0x00000018, 0x80000004, 0x0000000c, 0x33e7001b,
+       0x00000010, 0x20530000, 0x00000018, 0x000d0000, 0x00000000, 0x2b820000,
+       0x00000010, 0x20d2002f, 0x00000010, 0x0052002e, 0x00000009, 0x054e0007,
+       0x00000010, 0xb18a002c, 0x00000000, 0x050a8c00, 0x00000008, 0x850a0008,
+       0x00000010, 0x918a0029, 0x00000003, 0xc5008800, 0x00000008, 0xa3460001,
+       0x00000010, 0xb1c60007, 0x00000008, 0x22000001, 0x0000000c, 0x29800000,
+       0x00000010, 0x20530000, 0x00000000, 0x274e8c00, 0x00000000, 0x66cd0000,
+       0x00000000, 0x22c58c00, 0x00000008, 0x22000014, 0x00000003, 0x22c58e00,
+       0x00000003, 0x23c58e00, 0x00000003, 0x22c58e00, 0x00000003, 0x26cd9e00,
+       0x00000003, 0x27cd9e00, 0x00000003, 0x26cd9e00, 0x00000003, 0x274ea000,
+       0x00000003, 0x284ea000, 0x00000003, 0x274ea000, 0x0000000c, 0x69520000,
+       0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000003, 0x22c58e00,
+       0x00000003, 0x23c58e00, 0x00000003, 0x22c58e00, 0x00000003, 0x26cd9e00,
+       0x00000003, 0x27cd9e00, 0x00000003, 0x26cd9e00, 0x00000003, 0x274ea000,
+       0x00000003, 0x284ea000, 0x00000003, 0x274ea000, 0x00000000, 0xa2c58c00,
+       0x00000000, 0xa74e8c00, 0x00000000, 0xe6cd0000, 0x0000000f, 0x620a0010,
+       0x00000008, 0x23460001, 0x0000000c, 0x29800000, 0x00000010, 0x20530000,
+       0x0000000c, 0x29520000, 0x00000018, 0x80000002, 0x0000000c, 0x29800000,
+       0x00000018, 0x00570000 };
+
+static int bnx2_TPAT_b06FwReleaseMajor = 0x0;
+static int bnx2_TPAT_b06FwReleaseMinor = 0x0;
+static int bnx2_TPAT_b06FwReleaseFix = 0x0;
+static u32 bnx2_TPAT_b06FwStartAddr = 0x08000858;
+static u32 bnx2_TPAT_b06FwTextAddr = 0x08000800;
+static int bnx2_TPAT_b06FwTextLen = 0x1314;
+static u32 bnx2_TPAT_b06FwDataAddr = 0x08001b40;
+static int bnx2_TPAT_b06FwDataLen = 0x0;
+static u32 bnx2_TPAT_b06FwRodataAddr = 0x00000000;
+static int bnx2_TPAT_b06FwRodataLen = 0x0;
+static u32 bnx2_TPAT_b06FwBssAddr = 0x08001b90;
+static int bnx2_TPAT_b06FwBssLen = 0x80;
+static u32 bnx2_TPAT_b06FwSbssAddr = 0x08001b40;
+static int bnx2_TPAT_b06FwSbssLen = 0x48;
+
+static u32 bnx2_TPAT_b06FwText[(0x1314/4) + 1] = {
+       0x0a000216, 0x00000000, 0x00000000, 0x0000000d, 0x74706174, 0x20302e36,
+       0x2e390000, 0x00060901, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10000003,
+       0x00000000, 0x0000000d, 0x0000000d, 0x3c020800, 0x24421b40, 0x3c030800,
+       0x24631c10, 0xac400000, 0x0043202b, 0x1480fffd, 0x24420004, 0x3c1d0800,
+       0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100858, 0x3c1c0800, 0x279c1b40,
+       0x0e00051f, 0x00000000, 0x0000000d, 0x8f820024, 0x27bdffe8, 0xafbf0014,
+       0x10400004, 0xafb00010, 0x0000000d, 0x00000000, 0x2400015f, 0x8f82001c,
+       0x8c450008, 0x24030800, 0xaf430178, 0x97430104, 0x3c020008, 0xaf420140,
+       0x8f820034, 0x30420001, 0x10400006, 0x3070ffff, 0x24020002, 0x2603fffe,
+       0xa7420146, 0x0a000246, 0xa7430148, 0xa7400146, 0x8f850034, 0x30a20020,
+       0x0002102b, 0x00021023, 0x30460009, 0x30a30c00, 0x24020400, 0x14620002,
+       0x34c40001, 0x34c40005, 0xa744014a, 0x3c020800, 0x8c440820, 0x3c030048,
+       0x24020002, 0x00832025, 0x30a30006, 0x1062000d, 0x2c620003, 0x50400005,
+       0x24020004, 0x10600012, 0x3c020001, 0x0a000271, 0x00000000, 0x10620007,
+       0x24020006, 0x1462000f, 0x3c020111, 0x0a000269, 0x00821025, 0x0a000268,
+       0x3c020101, 0x3c020011, 0x00821025, 0x24030001, 0xaf421000, 0xaf830030,
+       0x0a000271, 0x00000000, 0x00821025, 0xaf421000, 0xaf800030, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x8f830030, 0x1060003f, 0x3c048000,
+       0x8f421000, 0x00441024, 0x1040fffd, 0x00000000, 0x10600039, 0x00000000,
+       0x8f421000, 0x3c030020, 0x00431024, 0x10400034, 0x00000000, 0x97421014,
+       0x14400031, 0x00000000, 0x97421008, 0x8f84001c, 0x24420006, 0x00024082,
+       0x00081880, 0x00643821, 0x8ce50000, 0x30430003, 0x30420001, 0x10400004,
+       0x00000000, 0x0000000d, 0x0a0002b0, 0x00081080, 0x5460000f, 0x30a5ffff,
+       0x3c06ffff, 0x00a62824, 0x0005182b, 0x00a61026, 0x0002102b, 0x00621824,
+       0x10600004, 0x00000000, 0x0000000d, 0x00000000, 0x240001fc, 0x8ce20000,
+       0x0a0002af, 0x00462825, 0x0005182b, 0x38a2ffff, 0x0002102b, 0x00621824,
+       0x10600004, 0x00000000, 0x0000000d, 0x00000000, 0x24000206, 0x8ce20000,
+       0x3445ffff, 0x00081080, 0x00441021, 0x3c030800, 0xac450000, 0x8c620840,
+       0x24420001, 0xac620840, 0x8f820008, 0x10400003, 0x00000000, 0x0e000660,
+       0x00000000, 0x8f840028, 0x02002821, 0x24820008, 0x30421fff, 0x24434000,
+       0x0343d821, 0x30a30007, 0xaf840018, 0xaf820028, 0xaf420084, 0x10600002,
+       0x24a20007, 0x3045fff8, 0x8f820044, 0x8f840004, 0x00451821, 0xaf82002c,
+       0x0064102b, 0xaf830044, 0x14400002, 0x00641023, 0xaf820044, 0x8f840044,
+       0x34028000, 0x8fbf0014, 0x8fb00010, 0x00821021, 0x03421821, 0x3c021000,
+       0xaf83001c, 0xaf440080, 0xaf420178, 0x03e00008, 0x27bd0018, 0x8f820024,
+       0x27bdffe8, 0xafbf0014, 0x10400004, 0xafb00010, 0x0000000d, 0x00000000,
+       0x24000249, 0x8f85001c, 0x24020001, 0xaf820024, 0x8ca70008, 0xa3800023,
+       0x8f620004, 0x3c100800, 0x26041b90, 0x00021402, 0xa3820010, 0x304600ff,
+       0x24c60005, 0x0e00064a, 0x00063082, 0x8f640004, 0x8f430108, 0x3c021000,
+       0x00621824, 0xa7840020, 0x10600008, 0x00000000, 0x97420104, 0x93830023,
+       0x2442ffec, 0x34630002, 0xa3830023, 0x0a000304, 0x3045ffff, 0x97420104,
+       0x2442fff0, 0x3045ffff, 0x8f620004, 0x3042ffff, 0x2c420013, 0x14400004,
+       0x00000000, 0x93820023, 0x34420001, 0xa3820023, 0x93830023, 0x24020001,
+       0x10620009, 0x28620002, 0x14400014, 0x24020002, 0x10620012, 0x24020003,
+       0x1062000a, 0x00000000, 0x0a000325, 0x00000000, 0x8f82001c, 0x8c43000c,
+       0x3c04ffff, 0x00641824, 0x00651825, 0x0a000325, 0xac43000c, 0x8f82001c,
+       0x8c430010, 0x3c04ffff, 0x00641824, 0x00651825, 0xac430010, 0x8f620004,
+       0x3042ffff, 0x24420002, 0x00021083, 0xa3820038, 0x304500ff, 0x8f82001c,
+       0x3c04ffff, 0x00052880, 0x00a22821, 0x8ca70000, 0x97820020, 0x97430104,
+       0x00e42024, 0x24420002, 0x00621823, 0x00833825, 0xaca70000, 0x93840038,
+       0x26061b90, 0x00041080, 0x00461021, 0x90430000, 0x3063000f, 0x00832021,
+       0xa3840022, 0x308200ff, 0x3c04fff6, 0x24420003, 0x00021080, 0x00461021,
+       0x8c450000, 0x93830022, 0x8f82001c, 0x3484ffff, 0x00a43824, 0x00031880,
+       0x00621821, 0xaf850000, 0xac67000c, 0x93820022, 0x93830022, 0x8f84001c,
+       0x24420003, 0x00021080, 0x00461021, 0x24630004, 0x00031880, 0xac470000,
+       0x93820022, 0x00661821, 0x94670002, 0x00021080, 0x00441021, 0xac670000,
+       0x24030010, 0xac470010, 0xa7430140, 0x24030002, 0xa7400142, 0xa7400144,
+       0xa7430146, 0x97420104, 0x8f840034, 0x24030001, 0x2442fffe, 0x30840006,
+       0xa7420148, 0x24020002, 0xa743014a, 0x1082000d, 0x2c820003, 0x10400005,
+       0x24020004, 0x10800011, 0x3c020009, 0x0a000383, 0x00000000, 0x10820007,
+       0x24020006, 0x1482000d, 0x3c020119, 0x0a00037d, 0x24030001, 0x0a00037c,
+       0x3c020109, 0x3c020019, 0x24030001, 0xaf421000, 0xaf830030, 0x0a000383,
+       0x00000000, 0xaf421000, 0xaf800030, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x93820010, 0x24030008, 0x8f840030, 0x24420002, 0x30420007,
+       0x00621823, 0x30630007, 0xaf83000c, 0x10800005, 0x3c038000, 0x8f421000,
+       0x00431024, 0x1040fffd, 0x00000000, 0x8f820028, 0xaf820018, 0x24420010,
+       0x30421fff, 0xaf820028, 0xaf420084, 0x97430104, 0x24424000, 0x0342d821,
+       0x3063ffff, 0x30620007, 0x10400002, 0x24620007, 0x3043fff8, 0x8f820044,
+       0x8f840004, 0x00431821, 0xaf82002c, 0x0064102b, 0xaf830044, 0x14400002,
+       0x00641023, 0xaf820044, 0x8f840044, 0x34028000, 0x8fbf0014, 0x8fb00010,
+       0x00821021, 0x03421821, 0x3c021000, 0xaf83001c, 0xaf440080, 0xaf420178,
+       0x03e00008, 0x27bd0018, 0x8f820024, 0x27bdffe8, 0xafbf0014, 0x14400004,
+       0xafb00010, 0x0000000d, 0x00000000, 0x240002db, 0x8f620004, 0x04410009,
+       0x3c050800, 0x93820022, 0x8f830000, 0x24a41b90, 0xaf800024, 0x24420003,
+       0x00021080, 0x00441021, 0xac430000, 0x93820038, 0x24a51b90, 0x93860010,
+       0x3c040001, 0x27700008, 0x24420001, 0x00021080, 0x00451021, 0x8c430000,
+       0x24c60005, 0x00063082, 0x00641821, 0x02002021, 0x0e00064a, 0xac430000,
+       0x93840022, 0x3c057fff, 0x8f620004, 0x00042080, 0x00902021, 0x8c830004,
+       0x34a5ffff, 0x00451024, 0x00621821, 0xac830004, 0x93850038, 0x3c07ffff,
+       0x93840010, 0x00052880, 0x00b02821, 0x8ca30000, 0x97420104, 0x97860020,
+       0x00671824, 0x00441021, 0x00461023, 0x3042ffff, 0x00621825, 0xaca30000,
+       0x93830023, 0x24020001, 0x10620009, 0x28620002, 0x1440001a, 0x24020002,
+       0x10620018, 0x24020003, 0x1062000d, 0x00000000, 0x0a000411, 0x00000000,
+       0x93820010, 0x97430104, 0x8e04000c, 0x00621821, 0x2463fff2, 0x3063ffff,
+       0x00872024, 0x00832025, 0x0a000411, 0xae04000c, 0x93820010, 0x97430104,
+       0x8e040010, 0x00621821, 0x2463ffee, 0x3063ffff, 0x00872024, 0x00832025,
+       0xae040010, 0x9783000e, 0x8f840034, 0x2402000a, 0xa7420140, 0xa7430142,
+       0x93820010, 0xa7420144, 0xa7400146, 0x97430104, 0x30840006, 0x24020001,
+       0xa7430148, 0xa742014a, 0x24020002, 0x1082000d, 0x2c820003, 0x10400005,
+       0x24020004, 0x10800011, 0x3c020041, 0x0a000437, 0x00000000, 0x10820007,
+       0x24020006, 0x1482000d, 0x3c020151, 0x0a000431, 0x24030001, 0x0a000430,
+       0x3c020141, 0x3c020051, 0x24030001, 0xaf421000, 0xaf830030, 0x0a000437,
+       0x00000000, 0xaf421000, 0xaf800030, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x8f820030, 0x93840010, 0x8f850028, 0x10400005, 0x3c038000,
+       0x8f421000, 0x00431024, 0x1040fffd, 0x00000000, 0x2483000a, 0x30620007,
+       0x10400002, 0x24620007, 0x304303f8, 0x00a31021, 0x30421fff, 0xaf850018,
+       0xaf820028, 0xaf420084, 0x97430104, 0x24424000, 0x0342d821, 0x3063ffff,
+       0x30620007, 0x10400002, 0x24620007, 0x3043fff8, 0x8f820044, 0x8f840004,
+       0x00431821, 0xaf82002c, 0x0064102b, 0xaf830044, 0x14400002, 0x00641023,
+       0xaf820044, 0x8f840044, 0x34028000, 0x8fbf0014, 0x8fb00010, 0x00821021,
+       0x03421821, 0x3c021000, 0xaf83001c, 0xaf440080, 0xaf420178, 0x03e00008,
+       0x27bd0018, 0x3c026000, 0x8c444448, 0x3c030800, 0xac64082c, 0x8f620000,
+       0x97430104, 0x3c048000, 0x3046ffff, 0x3067ffff, 0x8f420178, 0x00441024,
+       0x1440fffd, 0x2402000a, 0x30c30007, 0xa7420140, 0x24020008, 0x00431023,
+       0x30420007, 0x24c3fffe, 0xa7420142, 0xa7430144, 0xa7400146, 0xa7470148,
+       0x8f420108, 0x3c036000, 0x8f850034, 0x30420020, 0x0002102b, 0x00021023,
+       0x30420009, 0x34420001, 0xa742014a, 0x8c644448, 0x3c020800, 0x30a50006,
+       0xac440830, 0x24020002, 0x10a2000d, 0x2ca20003, 0x10400005, 0x24020004,
+       0x10a00011, 0x3c020041, 0x0a0004a8, 0x00000000, 0x10a20007, 0x24020006,
+       0x14a2000d, 0x3c020151, 0x0a0004a2, 0x24030001, 0x0a0004a1, 0x3c020141,
+       0x3c020051, 0x24030001, 0xaf421000, 0xaf830030, 0x0a0004a8, 0x00000000,
+       0xaf421000, 0xaf800030, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x8f820030, 0x24c30008, 0x10400006, 0x30e6ffff, 0x3c048000, 0x8f421000,
+       0x00441024, 0x1040fffd, 0x00000000, 0x3c026000, 0x8c444448, 0x3065ffff,
+       0x3c020800, 0x30a30007, 0x10600003, 0xac440834, 0x24a20007, 0x3045fff8,
+       0x8f840028, 0x00851021, 0x30421fff, 0x24434000, 0x0343d821, 0x30c30007,
+       0xaf840018, 0xaf820028, 0xaf420084, 0x10600002, 0x24c20007, 0x3046fff8,
+       0x8f820044, 0x8f840004, 0x00461821, 0xaf82002c, 0x0064102b, 0xaf830044,
+       0x14400002, 0x00641023, 0xaf820044, 0x8f840044, 0x34028000, 0x3c030800,
+       0x8c650844, 0x00821021, 0x03421821, 0xaf83001c, 0xaf440080, 0x10a00006,
+       0x2402000e, 0x93830043, 0x14620004, 0x3c021000, 0x2402043f, 0xa7420148,
+       0x3c021000, 0x3c036000, 0xaf420178, 0x8c644448, 0x3c020800, 0x03e00008,
+       0xac440838, 0x8f820034, 0x30424000, 0x10400005, 0x24020800, 0x0000000d,
+       0x00000000, 0x24000405, 0x24020800, 0xaf420178, 0x97440104, 0x3c030008,
+       0xaf430140, 0x8f820034, 0x30420001, 0x10400006, 0x3085ffff, 0x24020002,
+       0x24a3fffe, 0xa7420146, 0x0a0004ff, 0xa7430148, 0xa7400146, 0x8f840028,
+       0x2402000d, 0xa742014a, 0x24830008, 0x30631fff, 0x24624000, 0x0342d821,
+       0x30a20007, 0xaf840018, 0xaf830028, 0xaf430084, 0x10400002, 0x24a20007,
+       0x3045fff8, 0x8f820044, 0x8f840004, 0x00451821, 0xaf82002c, 0x0064102b,
+       0xaf830044, 0x14400002, 0x00641023, 0xaf820044, 0x8f840044, 0x34028000,
+       0x00821021, 0x03421821, 0x3c021000, 0xaf83001c, 0xaf440080, 0x03e00008,
+       0xaf420178, 0x27bdffe8, 0x3c046008, 0xafbf0014, 0xafb00010, 0x8c825000,
+       0x3c1a8000, 0x2403ff7f, 0x375b4000, 0x00431024, 0x3442380c, 0xac825000,
+       0x8f430008, 0x3c100800, 0x37428000, 0x34630001, 0xaf430008, 0xaf82001c,
+       0x3c02601c, 0xaf800028, 0xaf400080, 0xaf400084, 0x8c450008, 0x3c036000,
+       0x8c620808, 0x3c040800, 0x3c030080, 0xac830820, 0x3042fff0, 0x38420010,
+       0x2c420001, 0xaf850004, 0xaf820008, 0x0e00062f, 0x00000000, 0x8f420000,
+       0x30420001, 0x1040fffb, 0x00000000, 0x8f440108, 0x30822000, 0xaf840034,
+       0x10400004, 0x8e02083c, 0x24420001, 0x0a00059d, 0xae02083c, 0x30820200,
+       0x10400027, 0x00000000, 0x97420104, 0x1040001c, 0x30824000, 0x14400005,
+       0x00000000, 0x0e00022d, 0x00000000, 0x0a000592, 0x00000000, 0x8f620008,
+       0x8f630000, 0x24020030, 0x00031e02, 0x306300f0, 0x10620007, 0x28620031,
+       0x14400031, 0x24020040, 0x10620007, 0x00000000, 0x0a000592, 0x00000000,
+       0x0e0002dd, 0x00000000, 0x0a000592, 0x00000000, 0x0e0003b8, 0x00000000,
+       0x0a000592, 0x00000000, 0x30820040, 0x1440002d, 0x00000000, 0x0000000d,
+       0x00000000, 0x240004a6, 0x0a00059d, 0x00000000, 0x8f430100, 0x24020d00,
+       0x1462000f, 0x30820006, 0x97420104, 0x10400005, 0x30820040, 0x0e0004e9,
+       0x00000000, 0x0a000592, 0x00000000, 0x1440001b, 0x00000000, 0x0000000d,
+       0x00000000, 0x240004b8, 0x0a00059d, 0x00000000, 0x1040000e, 0x30821000,
+       0x10400005, 0x00000000, 0x0e00065d, 0x00000000, 0x0a000592, 0x00000000,
+       0x0e00046b, 0x00000000, 0x8f820040, 0x24420001, 0xaf820040, 0x0a00059d,
+       0x00000000, 0x30820040, 0x14400004, 0x00000000, 0x0000000d, 0x00000000,
+       0x240004cf, 0x8f420138, 0x3c034000, 0x00431025, 0xaf420138, 0x0a00053f,
+       0x00000000, 0x3c046008, 0x8c835000, 0x3c1a8000, 0x2402ff7f, 0x375b4000,
+       0x00621824, 0x3463380c, 0xac835000, 0x8f420008, 0x3c056000, 0x3c03601c,
+       0x34420001, 0xaf420008, 0x37428000, 0xaf800028, 0xaf82001c, 0xaf400080,
+       0xaf400084, 0x8c660008, 0x8ca20808, 0x3c040800, 0x3c030080, 0xac830820,
+       0x3042fff0, 0x38420010, 0x2c420001, 0xaf860004, 0xaf820008, 0x03e00008,
+       0x00000000, 0x3084ffff, 0x30820007, 0x10400002, 0x24820007, 0x3044fff8,
+       0x8f820028, 0x00441821, 0x30631fff, 0x24644000, 0x0344d821, 0xaf820018,
+       0xaf830028, 0x03e00008, 0xaf430084, 0x3084ffff, 0x30820007, 0x10400002,
+       0x24820007, 0x3044fff8, 0x8f820044, 0x8f830004, 0x00442021, 0xaf82002c,
+       0x0083102b, 0xaf840044, 0x14400002, 0x00831023, 0xaf820044, 0x8f820044,
+       0x34038000, 0x00431821, 0x03432021, 0xaf84001c, 0x03e00008, 0xaf420080,
+       0x8f830034, 0x24020002, 0x30630006, 0x1062000d, 0x2c620003, 0x50400005,
+       0x24020004, 0x10600012, 0x3c020001, 0x0a000601, 0x00000000, 0x10620007,
+       0x24020006, 0x1462000f, 0x3c020111, 0x0a0005f9, 0x00821025, 0x0a0005f8,
+       0x3c020101, 0x3c020011, 0x00821025, 0x24030001, 0xaf421000, 0xaf830030,
+       0x0a000601, 0x00000000, 0x00821025, 0xaf421000, 0xaf800030, 0x00000000,
+       0x00000000, 0x00000000, 0x03e00008, 0x00000000, 0x8f820030, 0x10400005,
+       0x3c038000, 0x8f421000, 0x00431024, 0x1040fffd, 0x00000000, 0x03e00008,
+       0x00000000, 0x8f820034, 0x27bdffe8, 0x30424000, 0x14400005, 0xafbf0010,
+       0x0e00022d, 0x00000000, 0x0a00062d, 0x8fbf0010, 0x8f620008, 0x8f630000,
+       0x24020030, 0x00031e02, 0x306300f0, 0x10620008, 0x28620031, 0x1440000d,
+       0x8fbf0010, 0x24020040, 0x10620007, 0x00000000, 0x0a00062d, 0x00000000,
+       0x0e0002dd, 0x00000000, 0x0a00062d, 0x8fbf0010, 0x0e0003b8, 0x00000000,
+       0x8fbf0010, 0x03e00008, 0x27bd0018, 0x8f84003c, 0x1080000f, 0x3c026000,
+       0x8c430c3c, 0x30630fff, 0xaf830014, 0x14600011, 0x3082000f, 0x10400005,
+       0x308200f0, 0x10400003, 0x30820f00, 0x14400006, 0x00000000, 0x0000000d,
+       0x00000000, 0x2400050e, 0x03e00008, 0x00000000, 0x0000000d, 0x00000000,
+       0x24000513, 0x03e00008, 0x00000000, 0xaf83003c, 0x03e00008, 0x00000000,
+       0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000,
+       0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a000659, 0x00a01021,
+       0xac860000, 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, 0x03e00008,
+       0x00000000, 0x0000000d, 0x03e00008, 0x00000000, 0x3c040800, 0x8c82084c,
+       0x54400007, 0xac80084c, 0x8f820034, 0x24030400, 0x30420c00, 0x1443005b,
+       0x00000000, 0xac80084c, 0x0000000d, 0x00000000, 0x2400003c, 0x3c026000,
+       0x8c444448, 0x3c030800, 0xac640850, 0x24000043, 0x97420104, 0x3045ffff,
+       0x000530c2, 0x24a2007f, 0x000239c2, 0x2400004e, 0x3c046020, 0x24030020,
+       0xac830000, 0x8c820000, 0x30420020, 0x10400005, 0x3c036020, 0x8c620000,
+       0x30420020, 0x1440fffd, 0x00000000, 0x3c026020, 0x8c430010, 0x24040001,
+       0x0087102b, 0x30ea007f, 0x24abfffe, 0x10400010, 0x00034240, 0x3c056020,
+       0x24090020, 0xaca90000, 0x8ca20000, 0x30420020, 0x10400006, 0x24840001,
+       0x3c036020, 0x8c620000, 0x30420020, 0x1440fffd, 0x00000000, 0x0087102b,
+       0x1440fff4, 0x00000000, 0x8f85001c, 0x3c026020, 0x8c430010, 0x3c046020,
+       0x34848000, 0x006a1825, 0x01034025, 0x2400006b, 0x10c0000b, 0x00000000,
+       0x8ca30000, 0x24a50004, 0x8ca20000, 0x24a50004, 0x24c6ffff, 0xac820000,
+       0x24840004, 0xac830000, 0x14c0fff7, 0x24840004, 0x24000077, 0x3c020007,
+       0x34427700, 0x3c036000, 0xac6223c8, 0xac6b23cc, 0xac6823e4, 0x24000086,
+       0x3c046000, 0x3c038000, 0x8c8223f8, 0x00431024, 0x1440fffd, 0x3c021000,
+       0x3c056000, 0x24030019, 0xaca223f8, 0xa743014a, 0x8ca44448, 0x3c020800,
+       0xac440854, 0x03e00008, 0x00000000, 0x00000000 };
+
+static u32 bnx2_TPAT_b06FwData[(0x0/4) + 1] = { 0x00000000 };
+static u32 bnx2_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x00000000 };
+static u32 bnx2_TPAT_b06FwBss[(0x80/4) + 1] = { 0x00000000 };
+static u32 bnx2_TPAT_b06FwSbss[(0x48/4) + 1] = { 0x00000000 };
+
+static int bnx2_TXP_b06FwReleaseMajor = 0x0;
+static int bnx2_TXP_b06FwReleaseMinor = 0x0;
+static int bnx2_TXP_b06FwReleaseFix = 0x0;
+static u32 bnx2_TXP_b06FwStartAddr = 0x08002090;
+static u32 bnx2_TXP_b06FwTextAddr = 0x08000000;
+static int bnx2_TXP_b06FwTextLen = 0x3ffc;
+static u32 bnx2_TXP_b06FwDataAddr = 0x08004020;
+static int bnx2_TXP_b06FwDataLen = 0x0;
+static u32 bnx2_TXP_b06FwRodataAddr = 0x00000000;
+static int bnx2_TXP_b06FwRodataLen = 0x0;
+static u32 bnx2_TXP_b06FwBssAddr = 0x08004060;
+static int bnx2_TXP_b06FwBssLen = 0x194;
+static u32 bnx2_TXP_b06FwSbssAddr = 0x08004020;
+static int bnx2_TXP_b06FwSbssLen = 0x34;
+static u32 bnx2_TXP_b06FwText[(0x3ffc/4) + 1] = {
+       0x0a000824, 0x00000000, 0x00000000, 0x0000000d, 0x74787020, 0x302e362e,
+       0x39000000, 0x00060900, 0x0000000a, 0x000003e8, 0x0000ea60, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+       0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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