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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: ths@linux-mips.org
Date: Fri, 03 Jun 2005 03:21:13 +0100
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ths@ftp.linux-mips.org  05/06/03 03:21:07

Modified files:
        arch/mips/mm   : Tag: linux_2_4 tlbex-r4k.S 
        arch/mips64/mm : Tag: linux_2_4 tlbex-r4k.S 
        include/asm-mips: Tag: linux_2_4 hazards.h 
        include/asm-mips64: Tag: linux_2_4 hazards.h 

Log message:
        Fix R4[04]00 hazards breakage.

diff -urN linux/arch/mips/mm/tlbex-r4k.S linux/arch/mips/mm/tlbex-r4k.S
--- linux/arch/mips/mm/Attic/tlbex-r4k.S        2004/11/25 22:18:38     1.2.2.19
+++ linux/arch/mips/mm/Attic/tlbex-r4k.S        2005/06/03 02:21:06     1.2.2.20
@@ -186,6 +186,7 @@
        P_MTC0  k1, CP0_ENTRYLO1                # load it
        mtc0_tlbw_hazard
        tlbwr                                   # write random tlb entry
+       nop
        tlbw_eret_hazard
        eret
        END(except_vec0_r4000)
diff -urN linux/arch/mips64/mm/tlbex-r4k.S linux/arch/mips64/mm/tlbex-r4k.S
--- linux/arch/mips64/mm/Attic/tlbex-r4k.S      2004/11/25 22:18:38     1.1.2.19
+++ linux/arch/mips64/mm/Attic/tlbex-r4k.S      2005/06/03 02:21:07     1.1.2.20
@@ -163,6 +163,7 @@
        PTE_RELOAD k0 k1
        mtc0_tlbw_hazard
        tlbwr
+       nop
 1:     tlbw_eret_hazard
        eret
 END(handle_vec1_r4k)
diff -urN linux/include/asm-mips/hazards.h linux/include/asm-mips/hazards.h
--- linux/include/asm-mips/hazards.h    2004/11/25 22:18:38     1.1.2.2
+++ linux/include/asm-mips/hazards.h    2005/06/03 02:21:07     1.1.2.3
@@ -68,11 +68,25 @@
 #define irq_disable_hazard                                             \
        ehb             # irq_disable_hazard
 
-#else
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
+
+/*
+ * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
+ */
 
 #define irq_enable_hazard
+
 #define irq_disable_hazard
 
+#else
+
+/*
+ * Classic MIPS needs 1 - 3 nops or ssnops
+ */
+#define irq_enable_hazard
+#define irq_disable_hazard                                             \
+       _ssnop; _ssnop; _ssnop
+
 #endif
 
 #else /* __ASSEMBLY__ */
diff -urN linux/include/asm-mips64/hazards.h linux/include/asm-mips64/hazards.h
--- linux/include/asm-mips64/Attic/hazards.h    2004/11/25 22:18:38     1.1.2.2
+++ linux/include/asm-mips64/Attic/hazards.h    2005/06/03 02:21:07     1.1.2.3
@@ -68,11 +68,25 @@
 #define irq_disable_hazard                                             \
        ehb             # irq_disable_hazard
 
-#else
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
+
+/*
+ * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
+ */
 
 #define irq_enable_hazard
+
 #define irq_disable_hazard
 
+#else
+
+/*
+ * Classic MIPS needs 1 - 3 nops or ssnops
+ */
+#define irq_enable_hazard
+#define irq_disable_hazard                                             \
+       _ssnop; _ssnop; _ssnop
+
 #endif
 
 #else /* __ASSEMBLY__ */

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