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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: ralf@linux-mips.org
Date: Wed, 25 May 2005 18:14:30 +0100
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 05/05/25 18:14:25

Modified files:
        .              : Tag: linux_2_4 Makefile 
        arch/i386/kernel: Tag: linux_2_4 pci-irq.c 
        arch/ia64/lib  : Tag: linux_2_4 swiotlb.c 
        arch/x86_64/kernel: Tag: linux_2_4 pci-gart.c pci-pc.c 
        drivers/block  : Tag: linux_2_4 cciss.c floppy.c loop.c 
        drivers/char   : Tag: linux_2_4 moxa.c random.c 
        drivers/net    : Tag: linux_2_4 tg3.c tg3.h 
        drivers/usb/serial: Tag: linux_2_4 io_edgeport.c 
        drivers/video  : Tag: linux_2_4 fbmem.c 
        fs/jfs         : Tag: linux_2_4 super.c 
        fs/xfs/linux-2.4: Tag: linux_2_4 xfs_buf.c 
        include/asm-x86_64: Tag: linux_2_4 hw_irq.h 
        include/linux  : Tag: linux_2_4 pci_ids.h 
        net/core       : Tag: linux_2_4 rtnetlink.c 
        net/ipv4       : Tag: linux_2_4 tcp_input.c 

Log message:
        Merge with Linux 2.4.31-rc1.

diff -urN linux/Makefile linux/Makefile
--- linux/Makefile      2005/05/23 12:12:30     1.119.2.37
+++ linux/Makefile      2005/05/25 17:14:22     1.119.2.38
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 4
 SUBLEVEL = 31
-EXTRAVERSION = -pre2
+EXTRAVERSION = -rc1
 
 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 
diff -urN linux/arch/i386/kernel/pci-irq.c linux/arch/i386/kernel/pci-irq.c
--- linux/arch/i386/kernel/Attic/pci-irq.c      2005/03/18 12:13:20     
1.18.2.13
+++ linux/arch/i386/kernel/Attic/pci-irq.c      2005/05/25 17:14:22     
1.18.2.14
@@ -215,6 +215,24 @@
 }
 
 /*
+ * The VIA pirq rules are nibble-based, like ALI,
+ * but without the ugly irq number munging.
+ * However, for 82C586, nibble map is different .
+ */
+static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int 
pirq)
+{
+       static unsigned int pirqmap[4] = { 3, 2, 5, 1 };
+       return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
+}
+
+static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int 
pirq, int irq)
+{
+       static unsigned int pirqmap[4] = { 3, 2, 5, 1 };
+       write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
+       return 1;
+}
+
+/*
  * ITE 8330G pirq rules are nibble-based
  * FIXME: pirqmap may be { 1, 0, 3, 2 },
  *       2+3 are both mapped to irq 9 on my system
@@ -649,6 +667,10 @@
        switch(device)
        {
                case PCI_DEVICE_ID_VIA_82C586_0:
+                       r->name = "VIA";
+                       r->get = pirq_via586_get;
+                       r->set = pirq_via586_set;
+                       return 1;
                case PCI_DEVICE_ID_VIA_82C596:
                case PCI_DEVICE_ID_VIA_82C686:
                case PCI_DEVICE_ID_VIA_8231:
diff -urN linux/arch/ia64/lib/swiotlb.c linux/arch/ia64/lib/swiotlb.c
--- linux/arch/ia64/lib/swiotlb.c       2003/08/13 17:19:08     1.4.2.4
+++ linux/arch/ia64/lib/swiotlb.c       2005/05/25 17:14:23     1.4.2.5
@@ -50,13 +50,13 @@
  * Used to do a quick range check in swiotlb_unmap_single and 
swiotlb_sync_single, to see
  * if the memory was in fact allocated by this API.
  */
-static char *io_tlb_start, *io_tlb_end;
+char *io_tlb_start, *io_tlb_end;
 
 /*
  * The number of IO TLB blocks (in groups of 64) betweeen io_tlb_start and 
io_tlb_end.
  * This is command line adjustable via setup_io_tlb_npages.
  */
-static unsigned long io_tlb_nslabs = 1024;
+static unsigned long io_tlb_nslabs = 32768;
 
 /*
  * This is a free list describing the number of free entries available from 
each index
diff -urN linux/arch/x86_64/kernel/pci-gart.c 
linux/arch/x86_64/kernel/pci-gart.c
--- linux/arch/x86_64/kernel/pci-gart.c 2004/08/14 18:38:48     1.1.2.10
+++ linux/arch/x86_64/kernel/pci-gart.c 2005/05/25 17:14:23     1.1.2.11
@@ -155,7 +155,7 @@
        int i;
        unsigned long iommu_page;
 
-       if (hwdev == NULL || hwdev->dma_mask < 0xffffffff || no_iommu)
+       if (hwdev == NULL || hwdev->dma_mask < 0xffffffff || (no_iommu && 
!swiotlb))
                gfp |= GFP_DMA;
 
        /* 
@@ -174,6 +174,22 @@
                if (force_mmu && !(gfp & GFP_DMA)) 
                        mmu = 1;
                if (no_iommu) { 
+#ifdef CONFIG_SWIOTLB
+                       if (swiotlb && high && hwdev) {
+                               unsigned long dma_mask = 0;
+                               if (hwdev->dma_mask == ~0UL) {
+                                       hwdev->dma_mask = 0xffffffff;
+                                       dma_mask = ~0UL;
+                               }
+                               *dma_handle = swiotlb_map_single(hwdev, memory, 
size,
+                                                                
PCI_DMA_FROMDEVICE);
+                               if (dma_mask)
+                                       hwdev->dma_mask = dma_mask;
+                               memset(phys_to_virt(*dma_handle), 0, size); 
+                               free_pages((unsigned long)memory, 
get_order(size));
+                               return phys_to_virt(*dma_handle);
+                       }
+#endif
                        if (high) goto error;
                        mmu = 0; 
                }       
@@ -218,8 +234,16 @@
                         void *vaddr, dma_addr_t bus)
 {
        unsigned long iommu_page;
-
+       extern  char *io_tlb_start, *io_tlb_end;
+ 
        size = round_up(size, PAGE_SIZE); 
+#ifdef CONFIG_SWIOTLB
+       if (swiotlb && vaddr >= (void *)io_tlb_start &&
+           vaddr < (void *)io_tlb_end) {
+               swiotlb_unmap_single (hwdev, bus, size, PCI_DMA_TODEVICE);
+               return;
+       }
+#endif
        if (bus >= iommu_bus_base && bus < iommu_bus_base + iommu_size) { 
                unsigned pages = size >> PAGE_SHIFT;
                iommu_page = (bus - iommu_bus_base) >> PAGE_SHIFT;
diff -urN linux/arch/x86_64/kernel/pci-pc.c linux/arch/x86_64/kernel/pci-pc.c
--- linux/arch/x86_64/kernel/Attic/pci-pc.c     2004/08/14 18:38:48     1.2.2.8
+++ linux/arch/x86_64/kernel/Attic/pci-pc.c     2005/05/25 17:14:23     1.2.2.9
@@ -115,44 +115,59 @@
 
 static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 
*value)
 {
-       outl(CONFIG_CMD(dev,where), 0xCF8);
-       *value = inb(0xCFC + (where&3));
-       return PCIBIOS_SUCCESSFUL;
+       int result;
+       u32 data;
+
+       if (!value)
+               return -EINVAL;
+
+       result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
+                               PCI_FUNC(dev->devfn), where, 1, &data);
+
+       *value = (u8)data;
+
+       return result;
 }
 
 static int pci_conf1_read_config_word(struct pci_dev *dev, int where, u16 
*value)
 {
-       outl(CONFIG_CMD(dev,where), 0xCF8);    
-       *value = inw(0xCFC + (where&2));
-       return PCIBIOS_SUCCESSFUL;    
+       int result;
+       u32 data;
+
+       if (!value)
+               return -EINVAL;
+
+       result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
+                               PCI_FUNC(dev->devfn), where, 2, &data);
+
+       *value = (u16)data;
+
+       return result;
 }
 
 static int pci_conf1_read_config_dword(struct pci_dev *dev, int where, u32 
*value)
 {
-       outl(CONFIG_CMD(dev,where), 0xCF8);
-       *value = inl(0xCFC);
-       return PCIBIOS_SUCCESSFUL;    
+       return pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
+                             PCI_FUNC(dev->devfn), where, 4, value);
+
 }
 
 static int pci_conf1_write_config_byte(struct pci_dev *dev, int where, u8 
value)
 {
-       outl(CONFIG_CMD(dev,where), 0xCF8);    
-       outb(value, 0xCFC + (where&3));
-       return PCIBIOS_SUCCESSFUL;
+       return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
+                              PCI_FUNC(dev->devfn), where, 1, value);
 }
 
 static int pci_conf1_write_config_word(struct pci_dev *dev, int where, u16 
value)
 {
-       outl(CONFIG_CMD(dev,where), 0xCF8);
-       outw(value, 0xCFC + (where&2));
-       return PCIBIOS_SUCCESSFUL;
+       return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
+                              PCI_FUNC(dev->devfn), where, 2, value);
 }
 
 static int pci_conf1_write_config_dword(struct pci_dev *dev, int where, u32 
value)
 {
-       outl(CONFIG_CMD(dev,where), 0xCF8);
-       outl(value, 0xCFC);
-       return PCIBIOS_SUCCESSFUL;
+       return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
+                              PCI_FUNC(dev->devfn), where, 4, value);
 }
 
 #undef CONFIG_CMD
@@ -248,50 +263,58 @@
 
 static int pci_conf2_read_config_byte(struct pci_dev *dev, int where, u8 
*value)
 {
-       SET(dev);
-       *value = inb(IOADDR(dev->devfn,where));
-       outb (0, 0xCF8);
-       return PCIBIOS_SUCCESSFUL;
+       int result;
+       u32 data;
+
+       if (!value)
+               return -EINVAL;
+
+       result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
+                               PCI_FUNC(dev->devfn), where, 1, &data);
+
+       *value = (u8)data;
+       
+       return result;
 }
 
 static int pci_conf2_read_config_word(struct pci_dev *dev, int where, u16 
*value)
 {
-       SET(dev);
-       *value = inw(IOADDR(dev->devfn,where));
-       outb (0, 0xCF8);
-       return PCIBIOS_SUCCESSFUL;
+       int result;
+       u32 data;
+
+       if (!value)
+               return -EINVAL;
+
+       result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
+                               PCI_FUNC(dev->devfn), where, 2, &data);
+
+       *value = (u16)data;
+       
+       return result;
 }
 
 static int pci_conf2_read_config_dword(struct pci_dev *dev, int where, u32 
*value)
 {
-       SET(dev);
-       *value = inl (IOADDR(dev->devfn,where));    
-       outb (0, 0xCF8);    
-       return PCIBIOS_SUCCESSFUL;
+       return pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
+                             PCI_FUNC(dev->devfn), where, 4, value);
 }
 
 static int pci_conf2_write_config_byte(struct pci_dev *dev, int where, u8 
value)
 {
-       SET(dev);
-       outb (value, IOADDR(dev->devfn,where));
-       outb (0, 0xCF8);    
-       return PCIBIOS_SUCCESSFUL;
+       return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
+                              PCI_FUNC(dev->devfn), where, 1, value);
 }
 
 static int pci_conf2_write_config_word(struct pci_dev *dev, int where, u16 
value)
 {
-       SET(dev);
-       outw (value, IOADDR(dev->devfn,where));
-       outb (0, 0xCF8);    
-       return PCIBIOS_SUCCESSFUL;
+       return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
+                              PCI_FUNC(dev->devfn), where, 2, value);
 }
 
 static int pci_conf2_write_config_dword(struct pci_dev *dev, int where, u32 
value)
 {
-       SET(dev);
-       outl (value, IOADDR(dev->devfn,where));    
-       outb (0, 0xCF8);    
-       return PCIBIOS_SUCCESSFUL;
+       return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
+                              PCI_FUNC(dev->devfn), where, 4, value);
 }
 
 #undef SET
diff -urN linux/drivers/block/cciss.c linux/drivers/block/cciss.c
--- linux/drivers/block/cciss.c 2004/11/19 00:28:36     1.12.2.12
+++ linux/drivers/block/cciss.c 2005/05/25 17:14:23     1.12.2.13
@@ -975,10 +975,10 @@
                        {
                                kfree(buff);
                                return -EFAULT;
-                       } else {
-                               memset(buff, 0, iocommand.buf_size);
                        }
                }
+               else 
+                       memset(buff, 0, iocommand.buf_size);
                if ((c = cmd_alloc(h , 0)) == NULL) {
                        kfree(buff);
                        return -ENOMEM;
@@ -1099,12 +1099,12 @@
                                   /* Copy the data into the buffer created */
                                   if (copy_from_user(buff[sg_used], data_ptr, 
                                                buff_size[sg_used])) {
-                                       status = -ENOMEM;
+                                       status = -EFAULT;
                                        goto cleanup1;                  
-                                  } else {
-                                       memset(buff[sg_used], 0, 
buff_size[sg_used]);
                                   }
                                   }
+                               else
+                                       memset(buff[sg_used], 0, 
buff_size[sg_used]);
                                size_left_alloc -= buff_size[sg_used];
                                data_ptr += buff_size[sg_used];
                                sg_used++;
diff -urN linux/drivers/block/floppy.c linux/drivers/block/floppy.c
--- linux/drivers/block/floppy.c        2004/12/27 04:13:41     1.42.2.5
+++ linux/drivers/block/floppy.c        2005/05/25 17:14:23     1.42.2.6
@@ -2548,7 +2548,7 @@
                               current_count_sectors);
                        if (CT(COMMAND) == FD_READ)
                                printk("read\n");
-                       if (CT(COMMAND) == FD_READ)
+                       if (CT(COMMAND) == FD_WRITE)
                                printk("write\n");
                        break;
                }
@@ -2889,7 +2889,7 @@
                               current_count_sectors);
                        if (CT(COMMAND) == FD_READ)
                                printk("read\n");
-                       if (CT(COMMAND) == FD_READ)
+                       if (CT(COMMAND) == FD_WRITE)
                                printk("write\n");
                        return 0;
                }
diff -urN linux/drivers/block/loop.c linux/drivers/block/loop.c
--- linux/drivers/block/loop.c  2003/08/24 15:59:53     1.38.2.6
+++ linux/drivers/block/loop.c  2005/05/25 17:14:23     1.38.2.7
@@ -974,7 +974,7 @@
 
 int loop_register_transfer(struct loop_func_table *funcs)
 {
-       if ((unsigned)funcs->number > MAX_LO_CRYPT || xfer_funcs[funcs->number])
+       if ((unsigned)funcs->number >= MAX_LO_CRYPT || 
xfer_funcs[funcs->number])
                return -EINVAL;
        xfer_funcs[funcs->number] = funcs;
        return 0; 
diff -urN linux/drivers/char/moxa.c linux/drivers/char/moxa.c
--- linux/drivers/char/moxa.c   2005/05/23 12:12:30     1.9.2.3
+++ linux/drivers/char/moxa.c   2005/05/25 17:14:23     1.9.2.4
@@ -294,6 +294,7 @@
 static int moxa_get_serial_info(struct moxa_str *, struct serial_struct *);
 static int moxa_set_serial_info(struct moxa_str *, struct serial_struct *);
 static void MoxaSetFifo(int port, int enable);
+static unsigned long moxaIntPend[MAX_BOARDS];
 
 #ifdef MODULE
 int init_module(void)
@@ -1579,7 +1580,6 @@
 
 static unsigned char moxaBuff[10240];
 static unsigned long moxaIntNdx[MAX_BOARDS];
-static unsigned long moxaIntPend[MAX_BOARDS];
 static unsigned long moxaIntTable[MAX_BOARDS];
 static char moxaChkPort[MAX_PORTS];
 static char moxaLineCtrl[MAX_PORTS];
diff -urN linux/drivers/char/random.c linux/drivers/char/random.c
--- linux/drivers/char/random.c 2005/01/13 10:59:03     1.26.2.6
+++ linux/drivers/char/random.c 2005/05/25 17:14:23     1.26.2.7
@@ -1771,7 +1771,7 @@
 static int proc_do_poolsize(ctl_table *table, int write, struct file *filp,
                            void *buffer, size_t *lenp)
 {
-       unsigned int    ret;
+       int     ret;
 
        sysctl_poolsize = random_state->poolinfo.POOLBYTES;
 
@@ -1787,7 +1787,7 @@
                             void *oldval, size_t *oldlenp,
                             void *newval, size_t newlen, void **context)
 {
-       int     len;
+       unsigned int    len;
        
        sysctl_poolsize = random_state->poolinfo.POOLBYTES;
 
diff -urN linux/drivers/net/tg3.c linux/drivers/net/tg3.c
--- linux/drivers/net/tg3.c     2005/04/05 19:09:56     1.1.2.20
+++ linux/drivers/net/tg3.c     2005/05/25 17:14:23     1.1.2.21
@@ -56,12 +56,18 @@
 #define TG3_TSO_SUPPORT        0
 #endif
 
+#ifdef CONFIG_PCI_MSI
+#define TG3_MSI_SUPPORT 1
+#else
+#define TG3_MSI_SUPPORT 0
+#endif
+
 #include "tg3.h"
 
 #define DRV_MODULE_NAME                "tg3"
 #define PFX DRV_MODULE_NAME    ": "
-#define DRV_MODULE_VERSION     "3.25"
-#define DRV_MODULE_RELDATE     "March 24, 2005"
+#define DRV_MODULE_VERSION     "3.26"
+#define DRV_MODULE_RELDATE     "April 24, 2005"
 
 #define TG3_DEF_MAC_MODE       0
 #define TG3_DEF_RX_MODE                0
@@ -84,8 +90,7 @@
 /* hardware minimum and maximum for a single frame's data payload */
 #define TG3_MIN_MTU                    60
 #define TG3_MAX_MTU(tp)        \
-       ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && \
-         GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) ? 9000 : 1500)
+       (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
 
 /* These numbers seem to be hard coded in the NIC firmware somehow.
  * You can't change the ring sizes, but you can change where you place
@@ -203,6 +208,10 @@
          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
+         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
+         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
@@ -417,12 +426,55 @@
 {
        tw32(TG3PCI_MISC_HOST_CTRL,
             (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
-       tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000);
+       tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
+                    (tp->last_tag << 24));
        tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
 
        tg3_cond_int(tp);
 }
 
+static inline unsigned int tg3_has_work(struct tg3 *tp)
+{
+       struct tg3_hw_status *sblk = tp->hw_status;
+       unsigned int work_exists = 0;
+
+       /* check for phy events */
+       if (!(tp->tg3_flags &
+             (TG3_FLAG_USE_LINKCHG_REG |
+              TG3_FLAG_POLL_SERDES))) {
+               if (sblk->status & SD_STATUS_LINK_CHG)
+                       work_exists = 1;
+       }
+       /* check for RX/TX work to do */
+       if (sblk->idx[0].tx_consumer != tp->tx_cons ||
+           sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
+               work_exists = 1;
+
+       return work_exists;
+}
+
+/* tg3_restart_ints
+ *  similar to tg3_enable_ints, but it accurately determines whether there
+ *  is new work pending and can return without flushing the PIO write
+ *  which reenables interrupts 
+ */
+static void tg3_restart_ints(struct tg3 *tp)
+{
+       tw32(TG3PCI_MISC_HOST_CTRL,
+               (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
+       tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
+                    tp->last_tag << 24);
+
+       /* When doing tagged status, this work check is unnecessary.
+        * The last_tag we write above tells the chip which piece of
+        * work we've completed.
+        */
+       if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
+           tg3_has_work(tp))
+               tw32(HOSTCC_MODE, tp->coalesce_mode |
+                    (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
+}
+
 static inline void tg3_netif_stop(struct tg3 *tp)
 {
        netif_poll_disable(tp->dev);
@@ -844,8 +896,7 @@
        if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
                /* Cannot do read-modify-write on 5401 */
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
-       } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
-                  GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+       } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
                u32 phy_reg;
 
                /* Set bit 14 with read-modify-write to preserve other bits */
@@ -857,8 +908,7 @@
        /* Set phy register 0x10 bit 0 to high fifo elasticity to support
         * jumbo frames transmission.
         */
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
-           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
                u32 phy_reg;
 
                if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
@@ -990,8 +1040,13 @@
                pci_write_config_word(tp->pdev,
                                      pm + PCI_PM_CTRL,
                                      power_control);
-               tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
-               udelay(100);
+               udelay(100);    /* Delay after power state change */
+
+               /* Switch out of Vaux if it is not a LOM */
+               if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
+                       tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
+                       udelay(100);
+               }
 
                return 0;
 
@@ -1052,7 +1107,7 @@
                        mac_mode = MAC_MODE_PORT_MODE_TBI;
                }
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750)
+               if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
                        tw32(MAC_LED_CTRL, tp->led_ctrl);
 
                if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
@@ -1079,7 +1134,7 @@
                     CLOCK_CTRL_ALTCLK |
                     CLOCK_CTRL_PWRDOWN_PLL133);
                udelay(40);
-       } else if (!((GET_ASIC_REV(tp->pci_chip_rev_id) == 5750) &&
+       } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
                u32 newbits1, newbits2;
 
@@ -1136,6 +1191,7 @@
 
        /* Finally, set the new power state. */
        pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
+       udelay(100);    /* Delay after power state change */
 
        tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
 
@@ -2456,7 +2512,7 @@
        if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
                if (netif_carrier_ok(tp->dev)) {
                        tw32(HOSTCC_STAT_COAL_TICKS,
-                            DEFAULT_STAT_COAL_TICKS);
+                            tp->coal.stats_block_coalesce_usecs);
                } else {
                        tw32(HOSTCC_STAT_COAL_TICKS, 0);
                }
@@ -2665,8 +2721,8 @@
 static int tg3_rx(struct tg3 *tp, int budget)
 {
        u32 work_mask;
-       u32 rx_rcb_ptr = tp->rx_rcb_ptr;
-       u16 hw_idx, sw_idx;
+       u32 sw_idx = tp->rx_rcb_ptr;
+       u16 hw_idx;
        int received;
 
        hw_idx = tp->hw_status->idx[0].rx_producer;
@@ -2675,7 +2731,6 @@
         * the opaque cookie.
         */
        rmb();
-       sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
        work_mask = 0;
        received = 0;
        while (sw_idx != hw_idx && budget > 0) {
@@ -2779,14 +2834,19 @@
 next_pkt:
                (*post_ptr)++;
 next_pkt_nopost:
-               rx_rcb_ptr++;
-               sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
+               sw_idx++;
+               sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
+
+               /* Refresh hw_idx to see if there is new work */
+               if (sw_idx == hw_idx) {
+                       hw_idx = tp->hw_status->idx[0].rx_producer;
+                       rmb();
+               }
        }
 
        /* ACK the status ring. */
-       tp->rx_rcb_ptr = rx_rcb_ptr;
-       tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW,
-                    (rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp)));
+       tp->rx_rcb_ptr = sw_idx;
+       tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
 
        /* Refill RX ring(s). */
        if (work_mask & RXD_OPAQUE_RING_STD) {
@@ -2836,7 +2896,6 @@
         * All RX "locking" is done by ensuring outside
         * code synchronizes with dev->poll()
         */
-       done = 1;
        if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
                int orig_budget = *budget;
                int work_done;
@@ -2848,41 +2907,61 @@
 
                *budget -= work_done;
                netdev->quota -= work_done;
-
-               if (work_done >= orig_budget)
-                       done = 0;
        }
 
+       if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
+               tp->last_tag = sblk->status_tag;
+       rmb();
+
        /* if no more work, tell net stack and NIC we're done */
+       done = !tg3_has_work(tp);
        if (done) {
                spin_lock_irqsave(&tp->lock, flags);
                __netif_rx_complete(netdev);
-               tg3_enable_ints(tp);
+               tg3_restart_ints(tp);
                spin_unlock_irqrestore(&tp->lock, flags);
        }
 
        return (done ? 0 : 1);
 }
 
-static inline unsigned int tg3_has_work(struct net_device *dev, struct tg3 *tp)
+#if TG3_MSI_SUPPORT != 0
+/* MSI ISR - No need to check for interrupt sharing and no need to
+ * flush status block and interrupt mailbox. PCI ordering rules
+ * guarantee that MSI will arrive after the status block.
+ */
+static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
 {
+       struct net_device *dev = dev_id;
+       struct tg3 *tp = netdev_priv(dev);
        struct tg3_hw_status *sblk = tp->hw_status;
-       unsigned int work_exists = 0;
+       unsigned long flags;
 
-       /* check for phy events */
-       if (!(tp->tg3_flags &
-             (TG3_FLAG_USE_LINKCHG_REG |
-              TG3_FLAG_POLL_SERDES))) {
-               if (sblk->status & SD_STATUS_LINK_CHG)
-                       work_exists = 1;
+       spin_lock_irqsave(&tp->lock, flags);
+
+       /*
+        * Writing any value to intr-mbox-0 clears PCI INTA# and
+        * chip-internal interrupt pending events.
+        * Writing non-zero to intr-mbox-0 additional tells the
+        * NIC to stop sending us irqs, engaging "in-intr-handler"
+        * event coalescing.
+        */
+       tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
+       tp->last_tag = sblk->status_tag;
+       sblk->status &= ~SD_STATUS_UPDATED;
+       if (likely(tg3_has_work(tp)))
+               netif_rx_schedule(dev);         /* schedule NAPI poll */
+       else {
+               /* No work, re-enable interrupts.  */
+               tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
+                            tp->last_tag << 24);
        }
-       /* check for RX/TX work to do */
-       if (sblk->idx[0].tx_consumer != tp->tx_cons ||
-           sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
-               work_exists = 1;
 
-       return work_exists;
+       spin_unlock_irqrestore(&tp->lock, flags);
+
+       return IRQ_RETVAL(1);
 }
+#endif
 
 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
@@ -2902,29 +2981,70 @@
        if ((sblk->status & SD_STATUS_UPDATED) ||
            !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
                /*
-                * writing any value to intr-mbox-0 clears PCI INTA# and
+                * Writing any value to intr-mbox-0 clears PCI INTA# and
                 * chip-internal interrupt pending events.
-                * writing non-zero to intr-mbox-0 additional tells the
+                * Writing non-zero to intr-mbox-0 additional tells the
                 * NIC to stop sending us irqs, engaging "in-intr-handler"
                 * event coalescing.
                 */
                tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
                             0x00000001);
+               sblk->status &= ~SD_STATUS_UPDATED;
+               if (likely(tg3_has_work(tp)))
+                       netif_rx_schedule(dev);         /* schedule NAPI poll */
+               else {
+                       /* No work, shared interrupt perhaps?  re-enable
+                        * interrupts, and flush that PCI write
+                        */
+                       tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
+                               0x00000000);
+                       tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
+               }
+       } else {        /* shared interrupt */
+               handled = 0;
+       }
+
+       spin_unlock_irqrestore(&tp->lock, flags);
+
+       return IRQ_RETVAL(handled);
+}
+
+static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs 
*regs)
+{
+       struct net_device *dev = dev_id;
+       struct tg3 *tp = netdev_priv(dev);
+       struct tg3_hw_status *sblk = tp->hw_status;
+       unsigned long flags;
+       unsigned int handled = 1;
+
+       spin_lock_irqsave(&tp->lock, flags);
+
+       /* In INTx mode, it is possible for the interrupt to arrive at
+        * the CPU before the status block posted prior to the interrupt.
+        * Reading the PCI State register will confirm whether the
+        * interrupt is ours and will flush the status block.
+        */
+       if ((sblk->status & SD_STATUS_UPDATED) ||
+           !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
                /*
-                * Flush PCI write.  This also guarantees that our
-                * status block has been flushed to host memory.
+                * writing any value to intr-mbox-0 clears PCI INTA# and
+                * chip-internal interrupt pending events.
+                * writing non-zero to intr-mbox-0 additional tells the
+                * NIC to stop sending us irqs, engaging "in-intr-handler"
+                * event coalescing.
                 */
-               tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
+               tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
+                            0x00000001);
+               tp->last_tag = sblk->status_tag;
                sblk->status &= ~SD_STATUS_UPDATED;
-
-               if (likely(tg3_has_work(dev, tp)))
+               if (likely(tg3_has_work(tp)))
                        netif_rx_schedule(dev);         /* schedule NAPI poll */
                else {
                        /* no work, shared interrupt perhaps?  re-enable
                         * interrupts, and flush that PCI write
                         */
                        tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
-                               0x00000000);
+                                    tp->last_tag << 24);
                        tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
                }
        } else {        /* shared interrupt */
@@ -2936,13 +3056,33 @@
        return IRQ_RETVAL(handled);
 }
 
+#if TG3_MSI_SUPPORT != 0
+/* ISR for interrupt test */
+static irqreturn_t tg3_test_isr(int irq, void *dev_id,
+               struct pt_regs *regs)
+{
+       struct net_device *dev = dev_id;
+       struct tg3 *tp = netdev_priv(dev);
+       struct tg3_hw_status *sblk = tp->hw_status;
+
+       if (sblk->status & SD_STATUS_UPDATED) {
+               tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
+                            0x00000001);
+               return IRQ_RETVAL(1);
+       }
+       return IRQ_RETVAL(0);
+}
+#endif
+
 static int tg3_init_hw(struct tg3 *);
-static int tg3_halt(struct tg3 *);
+static int tg3_halt(struct tg3 *, int);
 
 #ifdef CONFIG_NET_POLL_CONTROLLER
 static void tg3_poll_controller(struct net_device *dev)
 {
-       tg3_interrupt(dev->irq, dev, NULL);
+       struct tg3 *tp = netdev_priv(dev);
+
+       tg3_interrupt(tp->pdev->irq, dev, NULL);
 }
 #endif
 
@@ -2959,7 +3099,7 @@
        restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
        tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
 
-       tg3_halt(tp);
+       tg3_halt(tp, 0);
        tg3_init_hw(tp);
 
        tg3_netif_start(tp);
@@ -3294,7 +3434,7 @@
        spin_lock_irq(&tp->lock);
        spin_lock(&tp->tx_lock);
 
-       tg3_halt(tp);
+       tg3_halt(tp, 1);
 
        tg3_set_mtu(dev, tp, new_mtu);
 
@@ -3561,7 +3701,7 @@
 /* To stop a block, clear the enable bit and poll till it
  * clears.  tp->lock is held.
  */
-static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit)
+static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, 
int silent)
 {
        unsigned int i;
        u32 val;
@@ -3594,7 +3734,7 @@
                        break;
        }
 
-       if (i == MAX_WAIT_CNT) {
+       if (i == MAX_WAIT_CNT && !silent) {
                printk(KERN_ERR PFX "tg3_stop_block timed out, "
                       "ofs=%lx enable_bit=%x\n",
                       ofs, enable_bit);
@@ -3605,7 +3745,7 @@
 }
 
 /* tp->lock is held. */
-static int tg3_abort_hw(struct tg3 *tp)
+static int tg3_abort_hw(struct tg3 *tp, int silent)
 {
        int i, err;
 
@@ -3615,22 +3755,20 @@
        tw32_f(MAC_RX_MODE, tp->rx_mode);
        udelay(10);
 
-       err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE);
-       err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE);
-       err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE);
-       err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE);
-       err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE);
-       err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE);
-
-       err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE);
-       err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE);
-       err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
-       err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE);
-       err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
-       err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE);
-       err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE);
-       if (err)
-               goto out;
+       err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
+
+       err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
 
        tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
        tw32_f(MAC_MODE, tp->mac_mode);
@@ -3648,27 +3786,24 @@
                printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
                       "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
                       tp->dev->name, tr32(MAC_TX_MODE));
-               return -ENODEV;
+               err |= -ENODEV;
        }
 
-       err  = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
-       err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE);
-       err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
+       err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
 
        tw32(FTQ_RESET, 0xffffffff);
        tw32(FTQ_RESET, 0x00000000);
 
-       err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
-       err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
-       if (err)
-               goto out;
+       err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
 
        if (tp->hw_status)
                memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
        if (tp->hw_stats)
                memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
 
-out:
        return err;
 }
 
@@ -3698,6 +3833,28 @@
 }
 
 /* tp->lock is held. */
+static void tg3_enable_nvram_access(struct tg3 *tp)
+{
+       if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
+           !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
+               u32 nvaccess = tr32(NVRAM_ACCESS);
+
+               tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
+       }
+}
+
+/* tp->lock is held. */
+static void tg3_disable_nvram_access(struct tg3 *tp)
+{
+       if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
+           !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
+               u32 nvaccess = tr32(NVRAM_ACCESS);
+
+               tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
+       }
+}
+
+/* tp->lock is held. */
 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
 {
        if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
@@ -3938,7 +4095,7 @@
                tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
                if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
                        tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
-                       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+                       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
                                tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
                }
        }
@@ -3968,7 +4125,7 @@
 }
 
 /* tp->lock is held. */
-static int tg3_halt(struct tg3 *tp)
+static int tg3_halt(struct tg3 *tp, int silent)
 {
        int err;
 
@@ -3976,7 +4133,7 @@
 
        tg3_write_sig_pre_reset(tp, RESET_KIND_SHUTDOWN);
 
-       tg3_abort_hw(tp);
+       tg3_abort_hw(tp, silent);
        err = tg3_chip_reset(tp);
 
        tg3_write_sig_legacy(tp, RESET_KIND_SHUTDOWN);
@@ -4931,6 +5088,27 @@
 }
 
 static void __tg3_set_rx_mode(struct net_device *);
+static void tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
+{
+       tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
+       tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
+       tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
+       tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
+       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+               tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
+               tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
+       }
+       tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
+       tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
+       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+               u32 val = ec->stats_block_coalesce_usecs;
+
+               if (!netif_carrier_ok(tp->dev))
+                       val = 0;
+
+               tw32(HOSTCC_STAT_COAL_TICKS, val);
+       }
+}
 
 /* tp->lock is held. */
 static int tg3_reset_hw(struct tg3 *tp)
@@ -4945,9 +5123,7 @@
        tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
 
        if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
-               err = tg3_abort_hw(tp);
-               if (err)
-                       return err;
+               tg3_abort_hw(tp, 1);
        }
 
        err = tg3_chip_reset(tp);
@@ -5012,7 +5188,7 @@
        tw32(GRC_MISC_CFG, val);
 
        /* Initialize MBUF/DESC pool. */
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
                /* Do nothing.  */
        } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
                tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
@@ -5209,6 +5385,8 @@
                      RDMAC_MODE_LNGREAD_ENAB);
        if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
                rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
+
+       /* If statement applies to 5705 and 5750 PCI devices only */
        if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
            (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
@@ -5222,6 +5400,9 @@
                }
        }
 
+       if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
+               rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
+
 #if TG3_TSO_SUPPORT != 0
        if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
                rdmac_mode |= (1 << 27);
@@ -5250,16 +5431,7 @@
                udelay(10);
        }
 
-       tw32(HOSTCC_RXCOL_TICKS, 0);
-       tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
-       tw32(HOSTCC_RXMAX_FRAMES, 1);
-       tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
-               tw32(HOSTCC_RXCOAL_TICK_INT, 0);
-               tw32(HOSTCC_TXCOAL_TICK_INT, 0);
-       }
-       tw32(HOSTCC_RXCOAL_MAXF_INT, 1);
-       tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
+       tg3_set_coalesce(tp, &tp->coal);
 
        /* set status block DMA address */
        tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
@@ -5272,8 +5444,6 @@
                 * the tg3_periodic_fetch_stats call there, and
                 * tg3_get_stats to see how this works for 5705/5750 chips.
                 */
-               tw32(HOSTCC_STAT_COAL_TICKS,
-                    DEFAULT_STAT_COAL_TICKS);
                tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
                     ((u64) tp->stats_mapping >> 32));
                tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
@@ -5303,15 +5473,34 @@
        tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | 
MAC_MODE_TXSTAT_CLEAR);
        udelay(40);
 
-       tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
+       /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
+        * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
+        * register to preserve the GPIO settings for LOMs. The GPIOs,
+        * whether used as inputs or outputs, are set by boot code after
+        * reset.
+        */
+       if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
+               u32 gpio_mask;
+
+               gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
+                           GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
+
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+                       gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
+                                    GRC_LCLCTRL_GPIO_OUTPUT3;
+
+               tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
+
+               /* GPIO1 must be driven high for eeprom write protect */
                tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
                                       GRC_LCLCTRL_GPIO_OUTPUT1);
+       }
        tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
        udelay(100);
 
        tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
-       tr32(MAILBOX_INTERRUPT_0);
+       tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
+       tp->last_tag = 0;
 
        if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
                tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
@@ -5324,6 +5513,7 @@
               WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
               WDMAC_MODE_LNGREAD_ENAB);
 
+       /* If statement applies to 5705 and 5750 PCI devices only */
        if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
@@ -5588,31 +5778,33 @@
        spin_lock_irqsave(&tp->lock, flags);
        spin_lock(&tp->tx_lock);
 
-       /* All of this garbage is because when using non-tagged
-        * IRQ status the mailbox/status_block protocol the chip
-        * uses with the cpu is race prone.
-        */
-       if (tp->hw_status->status & SD_STATUS_UPDATED) {
-               tw32(GRC_LOCAL_CTRL,
-                    tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
-       } else {
-               tw32(HOSTCC_MODE, tp->coalesce_mode |
-                    (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
-       }
+       if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
+               /* All of this garbage is because when using non-tagged
+                * IRQ status the mailbox/status_block protocol the chip
+                * uses with the cpu is race prone.
+                */
+               if (tp->hw_status->status & SD_STATUS_UPDATED) {
+                       tw32(GRC_LOCAL_CTRL,
+                            tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
+               } else {
+                       tw32(HOSTCC_MODE, tp->coalesce_mode |
+                            (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
+               }
 
-       if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
-               tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
-               spin_unlock(&tp->tx_lock);
-               spin_unlock_irqrestore(&tp->lock, flags);
-               schedule_task(&tp->reset_task);
-               return;
+               if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
+                       tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
+                       spin_unlock(&tp->tx_lock);
+                       spin_unlock_irqrestore(&tp->lock, flags);
+                       schedule_task(&tp->reset_task);
+                       return;
+               }
        }
 
-       if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
-               tg3_periodic_fetch_stats(tp);
-
        /* This part only runs once per second. */
        if (!--tp->timer_counter) {
+               if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
+                       tg3_periodic_fetch_stats(tp);
+
                if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
                        u32 mac_stat;
                        int phy_event;
@@ -5677,6 +5869,129 @@
        add_timer(&tp->timer);
 }
 
+#if TG3_MSI_SUPPORT != 0
+static int tg3_test_interrupt(struct tg3 *tp)
+{
+       struct net_device *dev = tp->dev;
+       int err, i;
+       u32 int_mbox = 0;
+
+       tg3_disable_ints(tp);
+
+       free_irq(tp->pdev->irq, dev);
+
+       err = request_irq(tp->pdev->irq, tg3_test_isr,
+                         SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
+       if (err)
+               return err;
+
+       tg3_enable_ints(tp);
+
+       tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
+              HOSTCC_MODE_NOW);
+
+       for (i = 0; i < 5; i++) {
+               int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
+               if (int_mbox != 0)
+                       break;
+               msleep(10);
+       }
+
+       tg3_disable_ints(tp);
+
+       free_irq(tp->pdev->irq, dev);
+       
+       if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
+               err = request_irq(tp->pdev->irq, tg3_msi,
+                                 SA_SAMPLE_RANDOM, dev->name, dev);
+       else {
+               irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
+               if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
+                       fn = tg3_interrupt_tagged;
+               err = request_irq(tp->pdev->irq, fn,
+                                 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
+       }
+
+       if (err)
+               return err;
+
+       if (int_mbox != 0)
+               return 0;
+
+       return -EIO;
+}
+
+/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
+ * successfully restored
+ */
+static int tg3_test_msi(struct tg3 *tp)
+{
+       struct net_device *dev = tp->dev;
+       int err;
+       u16 pci_cmd;
+
+       if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
+               return 0;
+
+       /* Turn off SERR reporting in case MSI terminates with Master
+        * Abort.
+        */
+       pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
+       pci_write_config_word(tp->pdev, PCI_COMMAND,
+                             pci_cmd & ~PCI_COMMAND_SERR);
+
+       err = tg3_test_interrupt(tp);
+
+       pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
+
+       if (!err)
+               return 0;
+
+       /* other failures */
+       if (err != -EIO)
+               return err;
+
+       /* MSI test failed, go back to INTx mode */
+       printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
+              "switching to INTx mode. Please report this failure to "
+              "the PCI maintainer and include system chipset information.\n",
+                      tp->dev->name);
+
+       free_irq(tp->pdev->irq, dev);
+       pci_disable_msi(tp->pdev);
+
+       tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
+
+       {
+               irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
+               if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
+                       fn = tg3_interrupt_tagged;
+
+               err = request_irq(tp->pdev->irq, fn,
+                                 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
+       }
+       if (err)
+               return err;
+
+       /* Need to reset the chip because the MSI cycle may have terminated
+        * with Master Abort.
+        */
+       spin_lock_irq(&tp->lock);
+       spin_lock(&tp->tx_lock);
+
+       tg3_halt(tp, 1);
+       err = tg3_init_hw(tp);
+
+       spin_unlock(&tp->tx_lock);
+       spin_unlock_irq(&tp->lock);
+
+       if (err)
+               free_irq(tp->pdev->irq, dev);
+
+       return err;
+}
+#endif
+
 static int tg3_open(struct net_device *dev)
 {
        struct tg3 *tp = netdev_priv(dev);
@@ -5698,10 +6013,45 @@
        if (err)
                return err;
 
-       err = request_irq(dev->irq, tg3_interrupt,
-                         SA_SHIRQ, dev->name, dev);
+#if TG3_MSI_SUPPORT != 0
+       if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
+           (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
+           (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
+               /* All MSI supporting chips should support tagged
+                * status.  Assert that this is the case.
+                */
+               if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
+                       printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
+                              "Not using MSI.\n", tp->dev->name);
+               } else if (pci_enable_msi(tp->pdev) == 0) {
+                       u32 msi_mode;
+
+                       msi_mode = tr32(MSGINT_MODE);
+                       tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
+                       tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
+               }
+       }
+       if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
+               err = request_irq(tp->pdev->irq, tg3_msi,
+                                 SA_SAMPLE_RANDOM, dev->name, dev);
+       else
+#endif
+       {
+               irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
+               if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
+                       fn = tg3_interrupt_tagged;
+
+               err = request_irq(tp->pdev->irq, fn,
+                                 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
+       }
 
        if (err) {
+#if TG3_MSI_SUPPORT != 0
+               if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+                       pci_disable_msi(tp->pdev);
+                       tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
+               }
+#endif
                tg3_free_consistent(tp);
                return err;
        }
@@ -5711,34 +6061,70 @@
 
        err = tg3_init_hw(tp);
        if (err) {
-               tg3_halt(tp);
+               tg3_halt(tp, 1);
                tg3_free_rings(tp);
        } else {
-               tp->timer_offset = HZ / 10;
-               tp->timer_counter = tp->timer_multiplier = 10;
-               tp->asf_counter = tp->asf_multiplier = (10 * 120);
+               if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
+                       tp->timer_offset = HZ;
+               else
+                       tp->timer_offset = HZ / 10;
+
+               BUG_ON(tp->timer_offset > HZ);
+               tp->timer_counter = tp->timer_multiplier =
+                       (HZ / tp->timer_offset);
+               tp->asf_counter = tp->asf_multiplier =
+                       ((HZ / tp->timer_offset) * 120);
 
                init_timer(&tp->timer);
                tp->timer.expires = jiffies + tp->timer_offset;
                tp->timer.data = (unsigned long) tp;
                tp->timer.function = tg3_timer;
-               add_timer(&tp->timer);
-
-               tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
        }
 
        spin_unlock(&tp->tx_lock);
        spin_unlock_irq(&tp->lock);
 
        if (err) {
-               free_irq(dev->irq, dev);
+               free_irq(tp->pdev->irq, dev);
+#if TG3_MSI_SUPPORT != 0
+               if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+                       pci_disable_msi(tp->pdev);
+                       tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
+               }
+#endif
                tg3_free_consistent(tp);
                return err;
        }
 
+#if TG3_MSI_SUPPORT != 0
+       if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+               err = tg3_test_msi(tp);
+
+               if (err) {
+                       spin_lock_irq(&tp->lock);
+                       spin_lock(&tp->tx_lock);
+
+                       if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+                               pci_disable_msi(tp->pdev);
+                               tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
+                       }
+                       tg3_halt(tp, 1);
+                       tg3_free_rings(tp);
+                       tg3_free_consistent(tp);
+
+                       spin_unlock(&tp->tx_lock);
+                       spin_unlock_irq(&tp->lock);
+
+                       return err;
+               }
+       }
+#endif
+
        spin_lock_irq(&tp->lock);
        spin_lock(&tp->tx_lock);
 
+       add_timer(&tp->timer);
+       tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
        tg3_enable_ints(tp);
 
        spin_unlock(&tp->tx_lock);
@@ -5996,7 +6382,7 @@
 
        tg3_disable_ints(tp);
 
-       tg3_halt(tp);
+       tg3_halt(tp, 1);
        tg3_free_rings(tp);
        tp->tg3_flags &=
                ~(TG3_FLAG_INIT_COMPLETE |
@@ -6006,8 +6392,13 @@
        spin_unlock(&tp->tx_lock);
        spin_unlock_irq(&tp->lock);
 
-       free_irq(dev->irq, dev);
-
+       free_irq(tp->pdev->irq, dev);
+#if TG3_MSI_SUPPORT != 0
+       if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+               pci_disable_msi(tp->pdev);
+               tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
+       }
+#endif
        memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
               sizeof(tp->net_stats_prev));
        memcpy(&tp->estats_prev, tg3_get_estats(tp),
@@ -6309,7 +6700,9 @@
        struct tg3 *tp = netdev_priv(dev);
 
        spin_lock_irq(&tp->lock);
+       spin_lock(&tp->tx_lock);
        __tg3_set_rx_mode(dev);
+       spin_unlock(&tp->tx_lock);
        spin_unlock_irq(&tp->lock);
 }
 
@@ -6478,10 +6871,12 @@
                start = cpu_to_le32(start);
                len += b_offset;
                offset &= ~3;
+               if (len < 4)
+                       len = 4;
        }
 
        odd_len = 0;
-       if ((len & 3) && ((len > 4) || (b_offset == 0))) {
+       if (len & 3) {
                /* adjustments to end on required 4 byte boundary */
                odd_len = 1;
                len = (len + 3) & ~3;
@@ -6708,7 +7103,7 @@
        tp->tx_pending = ering->tx_pending;
 
        if (netif_running(dev)) {
-               tg3_halt(tp);
+               tg3_halt(tp, 1);
                tg3_init_hw(tp);
                tg3_netif_start(tp);
        }
@@ -6751,7 +7146,7 @@
                tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
 
        if (netif_running(dev)) {
-               tg3_halt(tp);
+               tg3_halt(tp, 1);
                tg3_init_hw(tp);
                tg3_netif_start(tp);
        }
@@ -6905,6 +7300,14 @@
 }
 #endif
 
+static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce 
*ec)
+{
+       struct tg3 *tp = netdev_priv(dev);
+
+       memcpy(ec, &tp->coal, sizeof(*ec));
+       return 0;
+}
+
 static struct ethtool_ops tg3_ethtool_ops = {
        .get_settings           = tg3_get_settings,
        .set_settings           = tg3_set_settings,
@@ -6937,6 +7340,7 @@
        .get_strings            = tg3_get_strings,
        .get_stats_count        = tg3_get_stats_count,
        .get_ethtool_stats      = tg3_get_ethtool_stats,
+       .get_coalesce           = tg3_get_coalesce,
 };
 
 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
@@ -7036,6 +7440,67 @@
        }
 }
 
+static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
+{
+       u32 nvcfg1;
+
+       nvcfg1 = tr32(NVRAM_CFG1);
+
+       /* NVRAM protection for TPM */
+       if (nvcfg1 & (1 << 27))
+               tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
+
+       switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
+               case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
+               case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
+                       tp->nvram_jedecnum = JEDEC_ATMEL;
+                       tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                       break;
+               case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
+                       tp->nvram_jedecnum = JEDEC_ATMEL;
+                       tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                       tp->tg3_flags2 |= TG3_FLG2_FLASH;
+                       break;
+               case FLASH_5752VENDOR_ST_M45PE10:
+               case FLASH_5752VENDOR_ST_M45PE20:
+               case FLASH_5752VENDOR_ST_M45PE40:
+                       tp->nvram_jedecnum = JEDEC_ST;
+                       tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                       tp->tg3_flags2 |= TG3_FLG2_FLASH;
+                       break;
+       }
+
+       if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
+               switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
+                       case FLASH_5752PAGE_SIZE_256:
+                               tp->nvram_pagesize = 256;
+                               break;
+                       case FLASH_5752PAGE_SIZE_512:
+                               tp->nvram_pagesize = 512;
+                               break;
+                       case FLASH_5752PAGE_SIZE_1K:
+                               tp->nvram_pagesize = 1024;
+                               break;
+                       case FLASH_5752PAGE_SIZE_2K:
+                               tp->nvram_pagesize = 2048;
+                               break;
+                       case FLASH_5752PAGE_SIZE_4K:
+                               tp->nvram_pagesize = 4096;
+                               break;
+                       case FLASH_5752PAGE_SIZE_264:
+                               tp->nvram_pagesize = 264;
+                               break;
+               }
+       }
+       else {
+               /* For eeprom, set pagesize to maximum eeprom size */
+               tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
+
+               nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
+               tw32(NVRAM_CFG1, nvcfg1);
+       }
+}
+
 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
 static void __devinit tg3_nvram_init(struct tg3 *tp)
 {
@@ -7062,20 +7527,16 @@
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
                tp->tg3_flags |= TG3_FLAG_NVRAM;
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
-                       u32 nvaccess = tr32(NVRAM_ACCESS);
+               tg3_enable_nvram_access(tp);
 
-                       tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
-               }
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+                       tg3_get_5752_nvram_info(tp);
+               else
+                       tg3_get_nvram_info(tp);
 
-               tg3_get_nvram_info(tp);
                tg3_get_nvram_size(tp);
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
-                       u32 nvaccess = tr32(NVRAM_ACCESS);
-
-                       tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
-               }
+               tg3_disable_nvram_access(tp);
 
        } else {
                tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
@@ -7164,11 +7625,7 @@
 
        tg3_nvram_lock(tp);
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
-               u32 nvaccess = tr32(NVRAM_ACCESS);
-
-               tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
-       }
+       tg3_enable_nvram_access(tp);
 
        tw32(NVRAM_ADDR, offset);
        ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
@@ -7179,11 +7636,7 @@
 
        tg3_nvram_unlock(tp);
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
-               u32 nvaccess = tr32(NVRAM_ACCESS);
-
-               tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
-       }
+       tg3_disable_nvram_access(tp);
 
        return ret;
 }
@@ -7246,7 +7699,7 @@
 
        while (len) {
                int j;
-               u32 phy_addr, page_off, size, nvaccess;
+               u32 phy_addr, page_off, size;
 
                phy_addr = offset & ~pagemask;
        
@@ -7269,8 +7722,7 @@
 
                offset = offset + (pagesize - page_off);
 
-               nvaccess = tr32(NVRAM_ACCESS);
-               tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
+               tg3_enable_nvram_access(tp);
 
                /*
                 * Before we can erase the flash page, we need
@@ -7394,8 +7846,8 @@
        }
 
        if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
-               tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-                      GRC_LCLCTRL_GPIO_OE1);
+               tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
+                      ~GRC_LCLCTRL_GPIO_OUTPUT1);
                udelay(40);
        }
 
@@ -7407,13 +7859,10 @@
 
                tg3_nvram_lock(tp);
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
-                       u32 nvaccess = tr32(NVRAM_ACCESS);
-
-                       tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
-
+               tg3_enable_nvram_access(tp);
+               if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
+                   !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
                        tw32(NVRAM_WRITE1, 0x406);
-               }
 
                grc_mode = tr32(GRC_MODE);
                tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
@@ -7432,17 +7881,12 @@
                grc_mode = tr32(GRC_MODE);
                tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
-                       u32 nvaccess = tr32(NVRAM_ACCESS);
-
-                       tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
-               }
+               tg3_disable_nvram_access(tp);
                tg3_nvram_unlock(tp);
        }
 
        if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
-               tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-                      GRC_LCLCTRL_GPIO_OE1 | GRC_LCLCTRL_GPIO_OUTPUT1);
+               tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
                udelay(40);
        }
 
@@ -7506,21 +7950,27 @@
        return NULL;
 }
 
-static int __devinit tg3_phy_probe(struct tg3 *tp)
+/* Since this function may be called in D3-hot power state during
+ * tg3_init_one(), only config cycles are allowed.
+ */
+static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
 {
-       u32 eeprom_phy_id, hw_phy_id_1, hw_phy_id_2;
-       u32 hw_phy_id, hw_phy_id_masked;
        u32 val;
-       int eeprom_signature_found, eeprom_phy_serdes, err;
+
+       /* Make sure register accesses (indirect or otherwise)
+        * will function correctly.
+        */
+       pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
+                              tp->misc_host_ctrl);
 
        tp->phy_id = PHY_ID_INVALID;
-       eeprom_phy_id = PHY_ID_INVALID;
-       eeprom_phy_serdes = 0;
-       eeprom_signature_found = 0;
+       tp->led_ctrl = LED_CTRL_MODE_PHY_1;
+
        tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
        if (val == NIC_SRAM_DATA_SIG_MAGIC) {
                u32 nic_cfg, led_cfg;
-               u32 nic_phy_id, ver, cfg2 = 0;
+               u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
+               int eeprom_phy_serdes = 0;
 
                tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
                tp->nic_sram_data_cfg = nic_cfg;
@@ -7533,8 +7983,6 @@
                    (ver > 0) && (ver < 0x100))
                        tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
 
-               eeprom_signature_found = 1;
-
                if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
                    NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
                        eeprom_phy_serdes = 1;
@@ -7550,10 +7998,14 @@
                } else
                        eeprom_phy_id = 0;
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+               tp->phy_id = eeprom_phy_id;
+               if (eeprom_phy_serdes)
+                       tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
+
+               if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
                        led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
                                    SHASTA_EXT_LED_MODE_MASK);
-               } else
+               else
                        led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
 
                switch (led_cfg) {
@@ -7603,7 +8055,7 @@
 
                if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
                        tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
-                       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+                       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
                                tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
                }
                if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
@@ -7617,6 +8069,13 @@
                if (cfg2 & (1 << 18))
                        tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
        }
+}
+
+static int __devinit tg3_phy_probe(struct tg3 *tp)
+{
+       u32 hw_phy_id_1, hw_phy_id_2;
+       u32 hw_phy_id, hw_phy_id_masked;
+       int err;
 
        /* Reading the PHY ID register can conflict with ASF
         * firwmare access to the PHY hardware.
@@ -7645,10 +8104,10 @@
                if (hw_phy_id_masked == PHY_ID_BCM8002)
                        tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
        } else {
-               if (eeprom_signature_found) {
-                       tp->phy_id = eeprom_phy_id;
-                       if (eeprom_phy_serdes)
-                               tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
+               if (tp->phy_id != PHY_ID_INVALID) {
+                       /* Do nothing, phy ID already set up in
+                        * tg3_get_eeprom_hw_cfg().
+                        */
                } else {
                        struct subsys_tbl_ent *p;
 
@@ -7719,9 +8178,6 @@
                err = tg3_init_5401phy_dsp(tp);
        }
 
-       if (!eeprom_signature_found)
-               tp->led_ctrl = LED_CTRL_MODE_PHY_1;
-
        if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
                tp->link_config.advertising =
                        (ADVERTISED_1000baseT_Half |
@@ -7882,6 +8338,12 @@
        tp->pci_chip_rev_id = (misc_ctrl_reg >>
                               MISC_HOST_CTRL_CHIPREV_SHIFT);
 
+       /* Wrong chip ID in 5752 A0. This code can be removed later
+        * as A0 is not in production.
+        */
+       if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
+               tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
+
        /* Initialize misc host control in PCI block. */
        tp->misc_host_ctrl |= (misc_ctrl_reg &
                               MISC_HOST_CTRL_CHIPREV);
@@ -7896,11 +8358,15 @@
        tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
        tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
 
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+               tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
+
        if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
-           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
+           (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
                tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
                tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
 
        if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
@@ -7978,6 +8444,31 @@
                pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, 
pci_state_reg);
        }
 
+       /* Get eeprom hw config before calling tg3_set_power_state().
+        * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
+        * determined before calling tg3_set_power_state() so that
+        * we know whether or not to switch out of Vaux power.
+        * When the flag is set, it means that GPIO1 is used for eeprom
+        * write protect and also implies that it is a LOM where GPIOs
+        * are not used to switch power.
+        */ 
+       tg3_get_eeprom_hw_cfg(tp);
+
+       /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
+        * GPIO1 driven high will bring 5700's external PHY out of reset.
+        * It is also used as eeprom write protect on LOMs.
+        */
+       tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
+       if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
+           (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
+               tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
+                                      GRC_LCLCTRL_GPIO_OUTPUT1);
+       /* Unused GPIO3 must be driven as output on 5752 because there
+        * are no pull-up resistors on unused GPIO pins.
+        */
+       else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+               tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
+
        /* Force the chip into D0. */
        err = tg3_set_power_state(tp, 0);
        if (err) {
@@ -8030,19 +8521,10 @@
        if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
                tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+       if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
                tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
 
-       /* Only 5701 and later support tagged irq status mode.
-        * Also, 5788 chips cannot use tagged irq status.
-        *
-        * However, since we are using NAPI avoid tagged irq status
-        * because the interrupt condition is more difficult to
-        * fully clear in that mode.
-        */
        tp->coalesce_mode = 0;
-
        if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
            GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
                tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
@@ -8106,6 +8588,18 @@
             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
                tp->tg3_flags2 |= TG3_FLG2_IS_5788;
 
+       if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
+           (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
+               tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
+       if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
+               tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
+                                     HOSTCC_MODE_CLRTICK_TXBD);
+
+               tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
+               pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
+                                      tp->misc_host_ctrl);
+       }
+
        /* these are limited to 10/100 only */
        if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
             (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
@@ -8283,6 +8777,146 @@
        return 0;
 }
 
+#define BOUNDARY_SINGLE_CACHELINE      1
+#define BOUNDARY_MULTI_CACHELINE       2
+
+static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
+{
+       int cacheline_size;
+       u8 byte;
+       int goal;
+
+       pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
+       if (byte == 0)
+               cacheline_size = 1024;
+       else
+               cacheline_size = (int) byte * 4;
+
+       /* On 5703 and later chips, the boundary bits have no
+        * effect.
+        */
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
+           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
+           !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
+               goto out;
+
+#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
+       goal = BOUNDARY_MULTI_CACHELINE;
+#else
+#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
+       goal = BOUNDARY_SINGLE_CACHELINE;
+#else
+       goal = 0;
+#endif
+#endif
+
+       if (!goal)
+               goto out;
+
+       /* PCI controllers on most RISC systems tend to disconnect
+        * when a device tries to burst across a cache-line boundary.
+        * Therefore, letting tg3 do so just wastes PCI bandwidth.
+        *
+        * Unfortunately, for PCI-E there are only limited
+        * write-side controls for this, and thus for reads
+        * we will still get the disconnects.  We'll also waste
+        * these PCI cycles for both read and write for chips
+        * other than 5700 and 5701 which do not implement the
+        * boundary bits.
+        */
+       if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
+           !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
+               switch (cacheline_size) {
+               case 16:
+               case 32:
+               case 64:
+               case 128:
+                       if (goal == BOUNDARY_SINGLE_CACHELINE) {
+                               val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
+                                       DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
+                       } else {
+                               val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
+                                       DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
+                       }
+                       break;
+
+               case 256:
+                       val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
+                               DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
+                       break;
+
+               default:
+                       val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
+                               DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
+                       break;
+               };
+       } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
+               switch (cacheline_size) {
+               case 16:
+               case 32:
+               case 64:
+                       if (goal == BOUNDARY_SINGLE_CACHELINE) {
+                               val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
+                               val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
+                               break;
+                       }
+                       /* fallthrough */
+               case 128:
+               default:
+                       val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
+                       val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
+                       break;
+               };
+       } else {
+               switch (cacheline_size) {
+               case 16:
+                       if (goal == BOUNDARY_SINGLE_CACHELINE) {
+                               val |= (DMA_RWCTRL_READ_BNDRY_16 |
+                                       DMA_RWCTRL_WRITE_BNDRY_16);
+                               break;
+                       }
+                       /* fallthrough */
+               case 32:
+                       if (goal == BOUNDARY_SINGLE_CACHELINE) {
+                               val |= (DMA_RWCTRL_READ_BNDRY_32 |
+                                       DMA_RWCTRL_WRITE_BNDRY_32);
+                               break;
+                       }
+                       /* fallthrough */
+               case 64:
+                       if (goal == BOUNDARY_SINGLE_CACHELINE) {
+                               val |= (DMA_RWCTRL_READ_BNDRY_64 |
+                                       DMA_RWCTRL_WRITE_BNDRY_64);
+                               break;
+                       }
+                       /* fallthrough */
+               case 128:
+                       if (goal == BOUNDARY_SINGLE_CACHELINE) {
+                               val |= (DMA_RWCTRL_READ_BNDRY_128 |
+                                       DMA_RWCTRL_WRITE_BNDRY_128);
+                               break;
+                       }
+                       /* fallthrough */
+               case 256:
+                       val |= (DMA_RWCTRL_READ_BNDRY_256 |
+                               DMA_RWCTRL_WRITE_BNDRY_256);
+                       break;
+               case 512:
+                       val |= (DMA_RWCTRL_READ_BNDRY_512 |
+                               DMA_RWCTRL_WRITE_BNDRY_512);
+                       break;
+               case 1024:
+               default:
+                       val |= (DMA_RWCTRL_READ_BNDRY_1024 |
+                               DMA_RWCTRL_WRITE_BNDRY_1024);
+                       break;
+               };
+       }
+
+out:
+       return val;
+}
+
 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t 
buf_dma, int size, int to_device)
 {
        struct tg3_internal_buffer_desc test_desc;
@@ -8370,7 +9004,7 @@
 static int __devinit tg3_test_dma(struct tg3 *tp)
 {
        dma_addr_t buf_dma;
-       u32 *buf;
+       u32 *buf, saved_dma_rwctrl;
        int ret;
 
        buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
@@ -8382,46 +9016,7 @@
        tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
                          (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
 
-#ifndef CONFIG_X86
-       {
-               u8 byte;
-               int cacheline_size;
-               pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
-
-               if (byte == 0)
-                       cacheline_size = 1024;
-               else
-                       cacheline_size = (int) byte * 4;
-
-               switch (cacheline_size) {
-               case 16:
-               case 32:
-               case 64:
-               case 128:
-                       if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
-                           !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
-                               tp->dma_rwctrl |=
-                                       DMA_RWCTRL_WRITE_BNDRY_384_PCIX;
-                               break;
-                       } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
-                               tp->dma_rwctrl &=
-                                       ~(DMA_RWCTRL_PCI_WRITE_CMD);
-                               tp->dma_rwctrl |=
-                                       DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
-                               break;
-                       }
-                       /* fallthrough */
-               case 256:
-                       if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
-                           !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
-                               tp->dma_rwctrl |=
-                                       DMA_RWCTRL_WRITE_BNDRY_256;
-                       else if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
-                               tp->dma_rwctrl |=
-                                       DMA_RWCTRL_WRITE_BNDRY_256_PCIX;
-               };
-       }
-#endif
+       tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
 
        if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
                /* DMA read watermark not used on PCIE */
@@ -8440,7 +9035,7 @@
                        if (ccval == 0x6 || ccval == 0x7)
                                tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
 
-                       /* Set bit 23 to renable PCIX hw bug fix */
+                       /* Set bit 23 to enable PCIX hw bug fix */
                        tp->dma_rwctrl |= 0x009f0000;
                } else {
                        tp->dma_rwctrl |= 0x001b000f;
@@ -8481,6 +9076,13 @@
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
                goto out;
 
+       /* It is best to perform DMA test with maximum write burst size
+        * to expose the 5700/5701 write DMA bug.
+        */
+       saved_dma_rwctrl = tp->dma_rwctrl;
+       tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
+       tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
+
        while (1) {
                u32 *p = buf, i;
 
@@ -8519,8 +9121,9 @@
                        if (p[i] == i)
                                continue;
 
-                       if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) ==
-                           DMA_RWCTRL_WRITE_BNDRY_DISAB) {
+                       if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
+                           DMA_RWCTRL_WRITE_BNDRY_16) {
+                               tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
                                tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
                                tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
                                break;
@@ -8537,6 +9140,14 @@
                        break;
                }
        }
+       if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
+           DMA_RWCTRL_WRITE_BNDRY_16) {
+               /* DMA test passed without adjusting DMA boundary,
+                * just restore the calculated DMA boundary
+                */
+               tp->dma_rwctrl = saved_dma_rwctrl;
+               tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
+       }
 
 out:
        pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
@@ -8594,6 +9205,7 @@
        case PHY_ID_BCM5704:    return "5704";
        case PHY_ID_BCM5705:    return "5705";
        case PHY_ID_BCM5750:    return "5750";
+       case PHY_ID_BCM5752:    return "5752";
        case PHY_ID_BCM8002:    return "8002/serdes";
        case 0:                 return "serdes";
        default:                return "unknown";
@@ -8622,6 +9234,31 @@
        return peer;
 }
 
+static void __devinit tg3_init_coal(struct tg3 *tp)
+{
+       struct ethtool_coalesce *ec = &tp->coal;
+
+       memset(ec, 0, sizeof(*ec));
+       ec->cmd = ETHTOOL_GCOALESCE;
+       ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
+       ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
+       ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
+       ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
+       ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
+       ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
+       ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
+       ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
+       ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
+
+       if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
+                                HOSTCC_MODE_CLRTICK_TXBD)) {
+               ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
+               ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
+               ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
+               ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
+       }
+}
+
 static int __devinit tg3_init_one(struct pci_dev *pdev,
                                  const struct pci_device_id *ent)
 {
@@ -8836,7 +9473,7 @@
            (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
                pci_save_state(tp->pdev, tp->pci_cfg_state);
                tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
-               tg3_halt(tp);
+               tg3_halt(tp, 1);
        }
 
        err = tg3_test_dma(tp);
@@ -8860,6 +9497,8 @@
        /* flow control autonegotiation is default behavior */
        tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
 
+       tg3_init_coal(tp);
+
        err = register_netdev(dev);
        if (err) {
                printk(KERN_ERR PFX "Cannot register net device, "
@@ -8902,6 +9541,8 @@
               (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
               (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
               (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
+       printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
+              dev->name, tp->dma_rwctrl);
 
        return 0;
 
@@ -8959,7 +9600,7 @@
 
        spin_lock_irq(&tp->lock);
        spin_lock(&tp->tx_lock);
-       tg3_halt(tp);
+       tg3_halt(tp, 1);
        spin_unlock(&tp->tx_lock);
        spin_unlock_irq(&tp->lock);
 
diff -urN linux/drivers/net/tg3.h linux/drivers/net/tg3.h
--- linux/drivers/net/tg3.h     2005/04/05 19:09:56     1.1.2.12
+++ linux/drivers/net/tg3.h     2005/05/25 17:14:24     1.1.2.13
@@ -125,6 +125,9 @@
 #define  CHIPREV_ID_5750_A0             0x4000
 #define  CHIPREV_ID_5750_A1             0x4001
 #define  CHIPREV_ID_5750_A3             0x4003
+#define  CHIPREV_ID_5752_A0_HW          0x5000
+#define  CHIPREV_ID_5752_A0             0x6000
+#define  CHIPREV_ID_5752_A1             0x6001
 #define  GET_ASIC_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                         0x07
 #define   ASIC_REV_5701                         0x00
@@ -132,6 +135,7 @@
 #define   ASIC_REV_5704                         0x02
 #define   ASIC_REV_5705                         0x03
 #define   ASIC_REV_5750                         0x04
+#define   ASIC_REV_5752                         0x06
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
@@ -872,10 +876,12 @@
 #define  HOSTCC_STATUS_ERROR_ATTN       0x00000004
 #define HOSTCC_RXCOL_TICKS             0x00003c08
 #define  LOW_RXCOL_TICKS                0x00000032
+#define  LOW_RXCOL_TICKS_CLRTCKS        0x00000014
 #define  DEFAULT_RXCOL_TICKS            0x00000048
 #define  HIGH_RXCOL_TICKS               0x00000096
 #define HOSTCC_TXCOL_TICKS             0x00003c0c
 #define  LOW_TXCOL_TICKS                0x00000096
+#define  LOW_TXCOL_TICKS_CLRTCKS        0x00000048
 #define  DEFAULT_TXCOL_TICKS            0x0000012c
 #define  HIGH_TXCOL_TICKS               0x00000145
 #define HOSTCC_RXMAX_FRAMES            0x00003c10
@@ -888,8 +894,10 @@
 #define  HIGH_TXMAX_FRAMES              0x00000052
 #define HOSTCC_RXCOAL_TICK_INT         0x00003c18
 #define  DEFAULT_RXCOAL_TICK_INT        0x00000019
+#define  DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
 #define HOSTCC_TXCOAL_TICK_INT         0x00003c1c
 #define  DEFAULT_TXCOAL_TICK_INT        0x00000019
+#define  DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
 #define HOSTCC_RXCOAL_MAXF_INT         0x00003c20
 #define  DEFAULT_RXCOAL_MAXF_INT        0x00000005
 #define HOSTCC_TXCOAL_MAXF_INT         0x00003c24
@@ -1307,6 +1315,9 @@
 #define  GRC_LCLCTRL_CLEARINT          0x00000002
 #define  GRC_LCLCTRL_SETINT            0x00000004
 #define  GRC_LCLCTRL_INT_ON_ATTN       0x00000008
+#define  GRC_LCLCTRL_GPIO_INPUT3       0x00000020
+#define  GRC_LCLCTRL_GPIO_OE3          0x00000040
+#define  GRC_LCLCTRL_GPIO_OUTPUT3      0x00000080
 #define  GRC_LCLCTRL_GPIO_INPUT0       0x00000100
 #define  GRC_LCLCTRL_GPIO_INPUT1       0x00000200
 #define  GRC_LCLCTRL_GPIO_INPUT2       0x00000400
@@ -1392,6 +1403,20 @@
 #define  FLASH_VENDOR_SAIFUN            0x01000003
 #define  FLASH_VENDOR_SST_SMALL                 0x00000001
 #define  FLASH_VENDOR_SST_LARGE                 0x02000001
+#define  NVRAM_CFG1_5752VENDOR_MASK     0x03c00003
+#define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ    0x00000000
+#define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ   0x02000000
+#define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED  0x02000003
+#define  FLASH_5752VENDOR_ST_M45PE10    0x02400000
+#define  FLASH_5752VENDOR_ST_M45PE20    0x02400002
+#define  FLASH_5752VENDOR_ST_M45PE40    0x02400001
+#define  NVRAM_CFG1_5752PAGE_SIZE_MASK  0x70000000
+#define  FLASH_5752PAGE_SIZE_256        0x00000000
+#define  FLASH_5752PAGE_SIZE_512        0x10000000
+#define  FLASH_5752PAGE_SIZE_1K                 0x20000000
+#define  FLASH_5752PAGE_SIZE_2K                 0x30000000
+#define  FLASH_5752PAGE_SIZE_4K                 0x40000000
+#define  FLASH_5752PAGE_SIZE_264        0x50000000
 #define NVRAM_CFG2                     0x00007018
 #define NVRAM_CFG3                     0x0000701c
 #define NVRAM_SWARB                    0x00007020
@@ -2016,6 +2041,7 @@
 
        struct tg3_hw_status            *hw_status;
        dma_addr_t                      status_mapping;
+       u32                             last_tag;
 
        u32                             msg_enable;
 
@@ -2061,6 +2087,7 @@
 
        u32                             rx_offset;
        u32                             tg3_flags;
+#define TG3_FLAG_TAGGED_STATUS         0x00000001
 #define TG3_FLAG_TXD_MBOX_HWBUG                0x00000002
 #define TG3_FLAG_RX_CHECKSUMS          0x00000004
 #define TG3_FLAG_USE_LINKCHG_REG       0x00000008
@@ -2114,6 +2141,9 @@
 #define TG3_FLG2_HW_TSO                        0x00010000
 #define TG3_FLG2_SERDES_PREEMPHASIS    0x00020000
 #define TG3_FLG2_5705_PLUS             0x00040000
+#define TG3_FLG2_5750_PLUS             0x00080000
+#define TG3_FLG2_PROTECTED_NVRAM       0x00100000
+#define TG3_FLG2_USING_MSI             0x00200000
 
        u32                             split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ                3
@@ -2160,6 +2190,7 @@
 #define PHY_ID_BCM5704                 0x60008190
 #define PHY_ID_BCM5705                 0x600081a0
 #define PHY_ID_BCM5750                 0x60008180
+#define PHY_ID_BCM5752                 0x60008100
 #define PHY_ID_BCM8002                 0x60010140
 #define PHY_ID_INVALID                 0xffffffff
 #define PHY_ID_REV_MASK                        0x0000000f
@@ -2215,7 +2246,7 @@
 
 #define SST_25VF0X0_PAGE_SIZE          4098
 
-
+       struct ethtool_coalesce         coal;
 };
 
 #endif /* !(_T3_H) */
diff -urN linux/drivers/usb/serial/io_edgeport.c 
linux/drivers/usb/serial/io_edgeport.c
--- linux/drivers/usb/serial/io_edgeport.c      2004/12/27 04:13:50     1.9.2.11
+++ linux/drivers/usb/serial/io_edgeport.c      2005/05/25 17:14:24     1.9.2.12
@@ -2803,9 +2803,13 @@
 static void unicode_to_ascii (char *string, short *unicode, int unicode_size)
 {
        int i;
-       for (i = 0; i < unicode_size; ++i) {
+
+       if (unicode_size <= 0)
+               return;
+       
+       for (i = 0; i < unicode_size; ++i)
                string[i] = (char)(le16_to_cpu(unicode[i]));
-       }
+
        string[unicode_size] = 0x00;
 }
 
diff -urN linux/drivers/video/fbmem.c linux/drivers/video/fbmem.c
--- linux/drivers/video/fbmem.c 2005/02/11 21:16:44     1.50.2.15
+++ linux/drivers/video/fbmem.c 2005/05/25 17:14:24     1.50.2.16
@@ -630,10 +630,7 @@
 
        /* frame buffer memory */
        start = fix.smem_start;
-       if (info->mapped_vram)
-               len = PAGE_ALIGN((start & ~PAGE_MASK) + info->mapped_vram);
-       else
-               len = PAGE_ALIGN((start & ~PAGE_MASK) + fix.smem_len);
+       len = PAGE_ALIGN((start & ~PAGE_MASK) + fix.smem_len);
        if (off >= len) {
                /* memory mapped io */
                off -= len;
diff -urN linux/fs/jfs/super.c linux/fs/jfs/super.c
--- linux/fs/jfs/super.c        2005/03/18 12:13:30     1.6.2.10
+++ linux/fs/jfs/super.c        2005/05/25 17:14:24     1.6.2.11
@@ -407,7 +407,7 @@
                jfs_err("jfs_umount failed with return code %d", rc);
        }
 out_kfree:
-       if (sbi->nls_tab)
+       if (sbi->nls_tab && sbi->nls_tab != (void *) -1)
                unload_nls(sbi->nls_tab);
        kfree(sbi);
        return NULL;
diff -urN linux/fs/xfs/linux-2.4/xfs_buf.c linux/fs/xfs/linux-2.4/xfs_buf.c
--- linux/fs/xfs/linux-2.4/Attic/xfs_buf.c      2005/01/13 10:59:04     1.1.2.4
+++ linux/fs/xfs/linux-2.4/Attic/xfs_buf.c      2005/05/25 17:14:24     1.1.2.5
@@ -1073,7 +1073,7 @@
        return(locked ? 0 : -EBUSY);
 }
 
-#ifdef DEBUG
+#if defined(DEBUG) || defined(XFS_BLI_TRACE)
 /*
  *     pagebuf_lock_value
  *
diff -urN linux/include/asm-x86_64/hw_irq.h linux/include/asm-x86_64/hw_irq.h
--- linux/include/asm-x86_64/hw_irq.h   2005/05/05 13:43:41     1.2.2.4
+++ linux/include/asm-x86_64/hw_irq.h   2005/05/25 17:14:24     1.2.2.5
@@ -156,7 +156,7 @@
        atomic_inc((atomic_t *)&prof_buffer[eip]);
 }
 
-#ifdef CONFIG_X86_IO_APIC
+#ifdef CONFIG_SMP /*more of this file should probably be ifdefed SMP */
 static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {
        if (IO_APIC_IRQ(i))
                send_IPI_self(IO_APIC_VECTOR(i));
diff -urN linux/include/linux/pci_ids.h linux/include/linux/pci_ids.h
--- linux/include/linux/pci_ids.h       2005/03/18 12:13:31     1.50.2.27
+++ linux/include/linux/pci_ids.h       2005/05/25 17:14:24     1.50.2.28
@@ -1699,6 +1699,8 @@
 #define PCI_DEVICE_ID_AFAVLAB_P028     0x2180
 
 #define PCI_VENDOR_ID_BROADCOM         0x14e4
+#define PCI_DEVICE_ID_TIGON3_5752      0x1600
+#define PCI_DEVICE_ID_TIGON3_5752M     0x1601
 #define PCI_DEVICE_ID_TIGON3_5700      0x1644
 #define PCI_DEVICE_ID_TIGON3_5701      0x1645
 #define PCI_DEVICE_ID_TIGON3_5702      0x1646
diff -urN linux/net/core/rtnetlink.c linux/net/core/rtnetlink.c
--- linux/net/core/rtnetlink.c  2003/08/13 17:19:30     1.12.2.5
+++ linux/net/core/rtnetlink.c  2005/05/25 17:14:25     1.12.2.6
@@ -303,7 +303,7 @@
                return 0;
 
        family = ((struct rtgenmsg*)NLMSG_DATA(nlh))->rtgen_family;
-       if (family > NPROTO) {
+       if (family >= NPROTO) {
                *errp = -EAFNOSUPPORT;
                return -1;
        }
diff -urN linux/net/ipv4/tcp_input.c linux/net/ipv4/tcp_input.c
--- linux/net/ipv4/tcp_input.c  2005/04/05 19:09:59     1.45.2.15
+++ linux/net/ipv4/tcp_input.c  2005/05/25 17:14:25     1.45.2.16
@@ -4243,16 +4243,7 @@
                                        goto no_ack;
                        }
 
-                       if (eaten) {
-                               if (tcp_in_quickack_mode(tp)) {
-                                       tcp_send_ack(sk);
-                               } else {
-                                       tcp_send_delayed_ack(sk);
-                               }
-                       } else {
-                               __tcp_ack_snd_check(sk, 0);
-                       }
-
+                       __tcp_ack_snd_check(sk, 0);
 no_ack:
                        if (eaten)
                                __kfree_skb(skb);

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