CVS Update@linux-mips.org: linux

[ralf@linux-mips.org]

CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 05/05/25 14:32:49

Modified files:
        arch/mips/kernel: cpu-probe.c 

Log message:
        64-bit fixes for Alchemy code ;)

diff -urN linux/arch/mips/kernel/cpu-probe.c linux/arch/mips/kernel/cpu-probe.c
--- linux/arch/mips/kernel/cpu-probe.c  2005/05/06 14:31:13     1.46
+++ linux/arch/mips/kernel/cpu-probe.c  2005/05/25 13:32:49     1.47
@@ -53,14 +53,13 @@
 /* The Au1xxx wait is available only if using 32khz counter or
  * external timer source, but specifically not CP0 Counter. */
 int allow_au1k_wait; 
+
 static void au1k_wait(void)
 {
-       unsigned long addr = 0;
        /* using the wait instruction makes CP0 counter unusable */
-       __asm__("la %0,au1k_wait\n\t"
-               ".set mips3\n\t"
-               "cache 0x14,0(%0)\n\t"
-               "cache 0x14,32(%0)\n\t"
+       __asm__(".set mips3\n\t"
+               "cache 0x14, 0(%0)\n\t"
+               "cache 0x14, 32(%0)\n\t"
                "sync\n\t"
                "nop\n\t"
                "wait\n\t"
@@ -69,7 +68,7 @@
                "nop\n\t"
                "nop\n\t"
                ".set mips0\n\t"
-               : : "r" (addr));
+               : : "r" (au1k_wait));
 }
 
 static inline void check_wait(void)