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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: ralf@linux-mips.org
Date: Thu, 05 May 2005 17:46:05 +0100
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 05/05/05 17:45:59

Modified files:
        include/asm-mips: cpu-features.h cpu-info.h cpu.h mipsregs.h 
        arch/mips/kernel: cpu-probe.c proc.c 

Log message:
        Cleanup decoding of MIPSxx config registers.

diff -urN linux/include/asm-mips/cpu-features.h 
linux/include/asm-mips/cpu-features.h
--- linux/include/asm-mips/cpu-features.h       2004/12/16 03:51:05     1.10
+++ linux/include/asm-mips/cpu-features.h       2005/05/05 16:45:59     1.11
@@ -4,6 +4,7 @@
  * for more details.
  *
  * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004  Maciej W. Rozycki
  */
 #ifndef __ASM_CPU_FEATURES_H
 #define __ASM_CPU_FEATURES_H
@@ -39,9 +40,6 @@
 #ifndef cpu_has_watch
 #define cpu_has_watch          (cpu_data[0].options & MIPS_CPU_WATCH)
 #endif
-#ifndef cpu_has_mips16
-#define cpu_has_mips16         (cpu_data[0].options & MIPS_CPU_MIPS16)
-#endif
 #ifndef cpu_has_divec
 #define cpu_has_divec          (cpu_data[0].options & MIPS_CPU_DIVEC)
 #endif
@@ -66,6 +64,18 @@
 #ifndef cpu_has_llsc
 #define cpu_has_llsc           (cpu_data[0].options & MIPS_CPU_LLSC)
 #endif
+#ifndef cpu_has_mips16
+#define cpu_has_mips16         (cpu_data[0].ases & MIPS_ASE_MIPS16)
+#endif
+#ifndef cpu_has_mdmx
+#define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
+#endif
+#ifndef cpu_has_mips3d
+#define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
+#endif
+#ifndef cpu_has_smartmips
+#define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
+#endif
 #ifndef cpu_has_vtag_icache
 #define cpu_has_vtag_icache    (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
 #endif
diff -urN linux/include/asm-mips/cpu-info.h linux/include/asm-mips/cpu-info.h
--- linux/include/asm-mips/cpu-info.h   2004/12/07 02:08:34     1.3
+++ linux/include/asm-mips/cpu-info.h   2005/05/05 16:45:59     1.4
@@ -7,6 +7,7 @@
  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
  * Copyright (C) 1996 Paul M. Antoine
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2004  Maciej W. Rozycki
  */
 #ifndef __ASM_CPU_INFO_H
 #define __ASM_CPU_INFO_H
@@ -61,6 +62,7 @@
         * Capability and feature descriptor structure for MIPS CPU
         */
        unsigned long           options;
+       unsigned long           ases;
        unsigned int            processor_id;
        unsigned int            fpu_id;
        unsigned int            cputype;
diff -urN linux/include/asm-mips/cpu.h linux/include/asm-mips/cpu.h
--- linux/include/asm-mips/cpu.h        2005/03/01 06:33:17     1.54
+++ linux/include/asm-mips/cpu.h        2005/05/05 16:45:59     1.55
@@ -3,6 +3,7 @@
  *        various MIPS cpu types.
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 2004  Maciej W. Rozycki
  */
 #ifndef _ASM_CPU_H
 #define _ASM_CPU_H
@@ -213,7 +214,6 @@
 #define MIPS_CPU_32FPR         0x00000020 /* 32 dbl. prec. FP registers */
 #define MIPS_CPU_COUNTER       0x00000040 /* Cycle count/compare */
 #define MIPS_CPU_WATCH         0x00000080 /* watchpoint registers */
-#define MIPS_CPU_MIPS16                0x00000100 /* code compression */
 #define MIPS_CPU_DIVEC         0x00000200 /* dedicated interrupt vector */
 #define MIPS_CPU_VCE           0x00000400 /* virt. coherence conflict possible 
*/
 #define MIPS_CPU_CACHE_CDEX_P  0x00000800 /* Create_Dirty_Exclusive CACHE op */
@@ -225,4 +225,12 @@
 #define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */
 #define MIPS_CPU_PREFETCH      0x00040000 /* CPU has usable prefetch */
 
+/*
+ * CPU ASE encodings
+ */
+#define MIPS_ASE_MIPS16                0x00000001 /* code compression */
+#define MIPS_ASE_MDMX          0x00000002 /* MIPS digital media extension */
+#define MIPS_ASE_MIPS3D                0x00000004 /* MIPS-3D */
+#define MIPS_ASE_SMARTMIPS     0x00000008 /* SmartMIPS */
+
 #endif /* _ASM_CPU_H */
diff -urN linux/include/asm-mips/mipsregs.h linux/include/asm-mips/mipsregs.h
--- linux/include/asm-mips/mipsregs.h   2005/04/25 16:36:23     1.71
+++ linux/include/asm-mips/mipsregs.h   2005/05/05 16:45:59     1.72
@@ -8,7 +8,7 @@
  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- * Copyright (C) 2003  Maciej W. Rozycki
+ * Copyright (C) 2003, 2004  Maciej W. Rozycki
  */
 #ifndef _ASM_MIPSREGS_H
 #define _ASM_MIPSREGS_H
@@ -478,6 +478,51 @@
 #define MIPS_CONF_M            (_ULCAST_(1) << 31)
 
 /*
+ * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
+ */
+#define MIPS_CONF1_FP          (_ULCAST_(1) <<  0)
+#define MIPS_CONF1_EP          (_ULCAST_(1) <<  1)
+#define MIPS_CONF1_CA          (_ULCAST_(1) <<  2)
+#define MIPS_CONF1_WR          (_ULCAST_(1) <<  3)
+#define MIPS_CONF1_PC          (_ULCAST_(1) <<  4)
+#define MIPS_CONF1_MD          (_ULCAST_(1) <<  5)
+#define MIPS_CONF1_C2          (_ULCAST_(1) <<  6)
+#define MIPS_CONF1_DA          (_ULCAST_(7) <<  7)
+#define MIPS_CONF1_DL          (_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS          (_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA          (_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL          (_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS          (_ULCAST_(7) << 22)
+#define MIPS_CONF1_TLBS                (_ULCAST_(63)<< 25)
+
+#define MIPS_CONF2_SA          (_ULCAST_(15)<<  0)
+#define MIPS_CONF2_SL          (_ULCAST_(15)<<  4)
+#define MIPS_CONF2_SS          (_ULCAST_(15)<<  8)
+#define MIPS_CONF2_SU          (_ULCAST_(15)<< 12)
+#define MIPS_CONF2_TA          (_ULCAST_(15)<< 16)
+#define MIPS_CONF2_TL          (_ULCAST_(15)<< 20)
+#define MIPS_CONF2_TS          (_ULCAST_(15)<< 24)
+#define MIPS_CONF2_TU          (_ULCAST_(7) << 28)
+
+#define MIPS_CONF3_TL          (_ULCAST_(1) <<  0)
+#define MIPS_CONF3_SM          (_ULCAST_(1) <<  1)
+#define MIPS_CONF3_SP          (_ULCAST_(1) <<  4)
+#define MIPS_CONF3_VINT                (_ULCAST_(1) <<  5)
+#define MIPS_CONF3_VEIC                (_ULCAST_(1) <<  6)
+#define MIPS_CONF3_LPA         (_ULCAST_(1) <<  7)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
+ */
+#define MIPS_FPIR_S            (_ULCAST_(1) << 16)
+#define MIPS_FPIR_D            (_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS           (_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D           (_ULCAST_(1) << 19)
+#define MIPS_FPIR_W            (_ULCAST_(1) << 20)
+#define MIPS_FPIR_L            (_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64          (_ULCAST_(1) << 22)
+
+/*
  * R10000 performance counter definitions.
  *
  * FIXME: The R10000 performance counter opens a nice way to implement CPU
diff -urN linux/arch/mips/kernel/cpu-probe.c linux/arch/mips/kernel/cpu-probe.c
--- linux/arch/mips/kernel/cpu-probe.c  2005/04/13 13:37:32     1.44
+++ linux/arch/mips/kernel/cpu-probe.c  2005/05/05 16:45:59     1.45
@@ -2,9 +2,9 @@
  * Processor capabilities determination functions.
  *
  * Copyright (C) xxxx  the Anonymous
- * Copyright (C) 2003  Maciej W. Rozycki
+ * Copyright (C) 2003, 2004  Maciej W. Rozycki
  * Copyright (C) 1994 - 2003 Ralf Baechle
- * Copyright (C) 2001 MIPS Inc.
+ * Copyright (C) 2001, 2004  MIPS Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -421,69 +421,126 @@
        }
 }
 
-static inline void decode_config1(struct cpuinfo_mips *c)
+static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 {
-       unsigned long config0 = read_c0_config();
-       unsigned long config1;
+       unsigned int config0;
+       int isa;
 
-       if ((config0 & (1 << 31)) == 0)
-               return;                 /* actually wort a panic() */
+       config0 = read_c0_config();
+
+       if (((config0 & MIPS_CONF_MT) >> 7) == 1)
+               c->options |= MIPS_CPU_TLB;
+       isa = (config0 & MIPS_CONF_AT) >> 13;
+       switch (isa) {
+       case 0:
+               c->isa_level = MIPS_CPU_ISA_M32;
+               break;
+       case 2:
+               c->isa_level = MIPS_CPU_ISA_M64;
+               break;
+       default:
+               panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
+       }
+       
+       return config0 & MIPS_CONF_M;
+}
+
+static inline unsigned int decode_config1(struct cpuinfo_mips *c)
+{
+       unsigned int config1;
 
-       /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
-       c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
-               MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
-               MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
        config1 = read_c0_config1();
-       if (config1 & (1 << 3))
+
+       if (config1 & MIPS_CONF1_MD)
+               c->ases |= MIPS_ASE_MDMX;
+       if (config1 & MIPS_CONF1_WR)
                c->options |= MIPS_CPU_WATCH;
-       if (config1 & (1 << 2))
-               c->options |= MIPS_CPU_MIPS16;
-       if (config1 & (1 << 1))
+       if (config1 & MIPS_CONF1_CA)
+               c->ases |= MIPS_ASE_MIPS16;
+       if (config1 & MIPS_CONF1_EP)
                c->options |= MIPS_CPU_EJTAG;
-       if (config1 & 1) {
+       if (config1 & MIPS_CONF1_FP) {
                c->options |= MIPS_CPU_FPU;
                c->options |= MIPS_CPU_32FPR;
        }
+       if (cpu_has_tlb)
+               c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
+
+       return config1 & MIPS_CONF_M;
+}
+
+static inline unsigned int decode_config2(struct cpuinfo_mips *c)
+{
+       unsigned int config2;
+
+       config2 = read_c0_config2();
+
+       if (config2 & MIPS_CONF2_SL)
+               c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
+       
+       return config2 & MIPS_CONF_M;
+}
+
+static inline unsigned int decode_config3(struct cpuinfo_mips *c)
+{
+       unsigned int config3;
+
+       config3 = read_c0_config3();
+
+       if (config3 & MIPS_CONF3_SM)
+               c->ases |= MIPS_ASE_SMARTMIPS;
+       
+       return config3 & MIPS_CONF_M;
+}
+
+static inline void decode_configs(struct cpuinfo_mips *c)
+{
+       /* MIPS32 or MIPS64 compliant CPU.  */
+       c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
+                    MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
+
        c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 
-       c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
+       /* Read Config registers.  */
+       if (!decode_config0(c))
+               return;                 /* actually worth a panic() */
+       if (!decode_config1(c))
+               return;
+       if (!decode_config2(c))
+               return;
+       if (!decode_config3(c))
+               return;
 }
 
 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 {
-       decode_config1(c);
+       decode_configs(c);
+       if (cpu_has_tlb)
+               c->options |= MIPS_CPU_4KTLB;
        switch (c->processor_id & 0xff00) {
        case PRID_IMP_4KC:
                c->cputype = CPU_4KC;
-               c->isa_level = MIPS_CPU_ISA_M32;
                break;
        case PRID_IMP_4KEC:
                c->cputype = CPU_4KEC;
-               c->isa_level = MIPS_CPU_ISA_M32;
                break;
        case PRID_IMP_4KECR2:
                c->cputype = CPU_4KEC;
-               c->isa_level = MIPS_CPU_ISA_M32;
                break;
        case PRID_IMP_4KSC:
                c->cputype = CPU_4KSC;
-               c->isa_level = MIPS_CPU_ISA_M32;
                break;
        case PRID_IMP_5KC:
                c->cputype = CPU_5KC;
-               c->isa_level = MIPS_CPU_ISA_M64;
                break;
        case PRID_IMP_20KC:
                c->cputype = CPU_20KC;
-               c->isa_level = MIPS_CPU_ISA_M64;
                break;
        case PRID_IMP_24K:
                c->cputype = CPU_24K;
-               c->isa_level = MIPS_CPU_ISA_M32;
                break;
        case PRID_IMP_25KF:
                c->cputype = CPU_25KF;
-               c->isa_level = MIPS_CPU_ISA_M64;
                /* Probe for L2 cache */
                c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
                break;
@@ -492,7 +549,7 @@
 
 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 {
-       decode_config1(c);
+       decode_configs(c);
        switch (c->processor_id & 0xff00) {
        case PRID_IMP_AU1_REV1:
        case PRID_IMP_AU1_REV2:
@@ -516,25 +573,19 @@
                        panic("Unknown Au Core!");
                        break;
                }
-               c->isa_level = MIPS_CPU_ISA_M32;
                break;
        }
 }
 
 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 {
-       decode_config1(c);
+       decode_configs(c);
        switch (c->processor_id & 0xff00) {
        case PRID_IMP_SB1:
                c->cputype = CPU_SB1;
-               c->isa_level = MIPS_CPU_ISA_M64;
-               c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
-                            MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
-                            MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
-                            MIPS_CPU_WATCH | MIPS_CPU_LLSC;
-#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
                /* FPU in pass1 is known to have issues. */
-               c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
+               c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 #endif
                break;
        }
@@ -542,14 +593,12 @@
 
 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
 {
-       decode_config1(c);
+       decode_configs(c);
+       if (cpu_has_tlb)
+               c->options |= MIPS_CPU_4KTLB;
        switch (c->processor_id & 0xff00) {
        case PRID_IMP_SR71000:
                c->cputype = CPU_SR71000;
-               c->isa_level = MIPS_CPU_ISA_M64;
-               c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
-                            MIPS_CPU_4KTLB | MIPS_CPU_FPU |
-                            MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
                c->scache.ways = 8;
                c->tlbsize = 64;
                break;
@@ -578,15 +627,21 @@
        case PRID_COMP_SIBYTE:
                cpu_probe_sibyte(c);
                break;
-
        case PRID_COMP_SANDCRAFT:
                cpu_probe_sandcraft(c);
                break;
        default:
                c->cputype = CPU_UNKNOWN;
        }
-       if (c->options & MIPS_CPU_FPU)
+       if (c->options & MIPS_CPU_FPU) {
                c->fpu_id = cpu_get_fpu_id();
+
+               if (c->isa_level == MIPS_CPU_ISA_M32 ||
+                   c->isa_level == MIPS_CPU_ISA_M64) {
+                       if (c->fpu_id & MIPS_FPIR_3D)
+                               c->ases |= MIPS_ASE_MIPS3D;
+               }
+       }
 }
 
 __init void cpu_report(void)
diff -urN linux/arch/mips/kernel/proc.c linux/arch/mips/kernel/proc.c
--- linux/arch/mips/kernel/proc.c       2005/03/01 10:38:58     1.56
+++ linux/arch/mips/kernel/proc.c       2005/05/05 16:45:59     1.57
@@ -2,7 +2,8 @@
  *  linux/arch/mips/kernel/proc.c
  *
  *  Copyright (C) 1995, 1996, 2001  Ralf Baechle
- *  Copyright (C) 2001  MIPS Technologies, Inc.
+ *  Copyright (C) 2001, 2004  MIPS Technologies, Inc.
+ *  Copyright (C) 2004  Maciej W. Rozycki
  */
 #include <linux/config.h>
 #include <linux/delay.h>
@@ -118,6 +119,11 @@
                      cpu_has_divec ? "yes" : "no");
        seq_printf(m, "hardware watchpoint\t: %s\n",
                      cpu_has_watch ? "yes" : "no");
+       seq_printf(m, "ASEs implemented\t:%s%s%s%s\n",
+                     cpu_has_mips16 ? " mips16" : "",
+                     cpu_has_mdmx ? " mdmx" : "",
+                     cpu_has_mips3d ? " mips3d" : "",
+                     cpu_has_smartmips ? " smartmips" : "");
 
        sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
                cpu_has_vce ? "%u" : "not available");

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