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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: ralf@linux-mips.org
Date: Thu, 14 Apr 2005 19:23:34 +0100
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 05/04/14 19:23:28

Modified files:
        include/asm-mips: atomic.h 

Log message:
        Pull previous patch.  Gcc doesn't share your opinion, Thiemo ;-)

diff -urN linux/include/asm-mips/atomic.h linux/include/asm-mips/atomic.h
--- linux/include/asm-mips/atomic.h     2005/04/14 15:12:57     1.37
+++ linux/include/asm-mips/atomic.h     2005/04/14 18:23:28     1.38
@@ -67,7 +67,7 @@
                "       sc      %0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "1" (v->counter));
+               : "Ir" (i), "m" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -77,7 +77,7 @@
                "       sc      %0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "1" (v->counter));
+               : "Ir" (i), "m" (v->counter));
        } else {
                unsigned long flags;
 
@@ -105,7 +105,7 @@
                "       sc      %0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "1" (v->counter));
+               : "Ir" (i), "m" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -115,7 +115,7 @@
                "       sc      %0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "1" (v->counter));
+               : "Ir" (i), "m" (v->counter));
        } else {
                unsigned long flags;
 
@@ -143,7 +143,8 @@
                "       addu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "2" (v->counter));
+               : "Ir" (i), "m" (v->counter)
+               : "memory");
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -155,7 +156,8 @@
                "       addu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "2" (v->counter));
+               : "Ir" (i), "m" (v->counter)
+               : "memory");
        } else {
                unsigned long flags;
 
@@ -184,7 +186,8 @@
                "       subu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "2" (v->counter));
+               : "Ir" (i), "m" (v->counter)
+               : "memory");
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -196,7 +199,8 @@
                "       subu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "2" (v->counter));
+               : "Ir" (i), "m" (v->counter)
+               : "memory");
        } else {
                unsigned long flags;
 
@@ -233,7 +237,8 @@
                "       sync                                            \n"
                "1:                                                     \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "2" (v->counter));
+               : "Ir" (i), "m" (v->counter)
+               : "memory");
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -246,7 +251,8 @@
                "       sync                                            \n"
                "1:                                                     \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "2" (v->counter));
+               : "Ir" (i), "m" (v->counter)
+               : "memory");
        } else {
                unsigned long flags;
 
@@ -366,7 +372,7 @@
                "       scd     %0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "1" (v->counter));
+               : "Ir" (i), "m" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -376,7 +382,7 @@
                "       scd     %0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "1" (v->counter));
+               : "Ir" (i), "m" (v->counter));
        } else {
                unsigned long flags;
 
@@ -404,7 +410,7 @@
                "       scd     %0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "1" (v->counter));
+               : "Ir" (i), "m" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -414,7 +420,7 @@
                "       scd     %0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "1" (v->counter));
+               : "Ir" (i), "m" (v->counter));
        } else {
                unsigned long flags;
 
@@ -442,7 +448,8 @@
                "       addu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "2" (v->counter));
+               : "Ir" (i), "m" (v->counter)
+               : "memory");
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -454,7 +461,8 @@
                "       addu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "2" (v->counter));
+               : "Ir" (i), "m" (v->counter)
+               : "memory");
        } else {
                unsigned long flags;
 
@@ -483,7 +491,8 @@
                "       subu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "2" (v->counter));
+               : "Ir" (i), "m" (v->counter)
+               : "memory");
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -495,7 +504,8 @@
                "       subu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "2" (v->counter));
+               : "Ir" (i), "m" (v->counter)
+               : "memory");
        } else {
                unsigned long flags;
 
@@ -532,7 +542,8 @@
                "       sync                                            \n"
                "1:                                                     \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "2" (v->counter));
+               : "Ir" (i), "m" (v->counter)
+               : "memory");
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -545,7 +556,8 @@
                "       sync                                            \n"
                "1:                                                     \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "2" (v->counter));
+               : "Ir" (i), "m" (v->counter)
+               : "memory");
        } else {
                unsigned long flags;
 

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