CVS Update@linux-mips.org: linux

[ths@linux-mips.org]

CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ths@ftp.linux-mips.org  05/04/14 16:12:58

Modified files:
        include/asm-mips: atomic.h 

Log message:
        The same name for an asm arg does not guarantee it will occupy the same
        register, what we want here.

diff -urN linux/include/asm-mips/atomic.h linux/include/asm-mips/atomic.h
--- linux/include/asm-mips/atomic.h     2004/08/19 09:54:23     1.36
+++ linux/include/asm-mips/atomic.h     2005/04/14 15:12:57     1.37
@@ -67,7 +67,7 @@
                "       sc      %0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter));
+               : "Ir" (i), "1" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -77,7 +77,7 @@
                "       sc      %0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter));
+               : "Ir" (i), "1" (v->counter));
        } else {
                unsigned long flags;
 
@@ -105,7 +105,7 @@
                "       sc      %0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter));
+               : "Ir" (i), "1" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -115,7 +115,7 @@
                "       sc      %0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter));
+               : "Ir" (i), "1" (v->counter));
        } else {
                unsigned long flags;
 
@@ -143,8 +143,7 @@
                "       addu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter)
-               : "memory");
+               : "Ir" (i), "2" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -156,8 +155,7 @@
                "       addu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter)
-               : "memory");
+               : "Ir" (i), "2" (v->counter));
        } else {
                unsigned long flags;
 
@@ -186,8 +184,7 @@
                "       subu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter)
-               : "memory");
+               : "Ir" (i), "2" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -199,8 +196,7 @@
                "       subu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter)
-               : "memory");
+               : "Ir" (i), "2" (v->counter));
        } else {
                unsigned long flags;
 
@@ -237,8 +233,7 @@
                "       sync                                            \n"
                "1:                                                     \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter)
-               : "memory");
+               : "Ir" (i), "2" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -251,8 +246,7 @@
                "       sync                                            \n"
                "1:                                                     \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter)
-               : "memory");
+               : "Ir" (i), "2" (v->counter));
        } else {
                unsigned long flags;
 
@@ -372,7 +366,7 @@
                "       scd     %0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter));
+               : "Ir" (i), "1" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -382,7 +376,7 @@
                "       scd     %0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter));
+               : "Ir" (i), "1" (v->counter));
        } else {
                unsigned long flags;
 
@@ -410,7 +404,7 @@
                "       scd     %0, %1                                  \n"
                "       beqzl   %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter));
+               : "Ir" (i), "1" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -420,7 +414,7 @@
                "       scd     %0, %1                                  \n"
                "       beqz    %0, 1b                                  \n"
                : "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter));
+               : "Ir" (i), "1" (v->counter));
        } else {
                unsigned long flags;
 
@@ -448,8 +442,7 @@
                "       addu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter)
-               : "memory");
+               : "Ir" (i), "2" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -461,8 +454,7 @@
                "       addu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter)
-               : "memory");
+               : "Ir" (i), "2" (v->counter));
        } else {
                unsigned long flags;
 
@@ -491,8 +483,7 @@
                "       subu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter)
-               : "memory");
+               : "Ir" (i), "2" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -504,8 +495,7 @@
                "       subu    %0, %1, %3                              \n"
                "       sync                                            \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter)
-               : "memory");
+               : "Ir" (i), "2" (v->counter));
        } else {
                unsigned long flags;
 
@@ -542,8 +532,7 @@
                "       sync                                            \n"
                "1:                                                     \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter)
-               : "memory");
+               : "Ir" (i), "2" (v->counter));
        } else if (cpu_has_llsc) {
                unsigned long temp;
 
@@ -556,8 +545,7 @@
                "       sync                                            \n"
                "1:                                                     \n"
                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-               : "Ir" (i), "m" (v->counter)
-               : "memory");
+               : "Ir" (i), "2" (v->counter));
        } else {
                unsigned long flags;