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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: ppopov@linux-mips.org
Date: Tue, 01 Mar 2005 06:33:28 +0000
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ppopov@ftp.linux-mips.org       05/03/01 06:33:19

Modified files:
        arch/mips      : Kconfig Makefile 
        arch/mips/au1000/common: au1xxx_irqmap.c cputable.c dbdma.c 
                                 irq.c 
        arch/mips/kernel: cpu-probe.c proc.c 
        arch/mips/mm   : c-r4k.c tlbex.c 
        include/asm-mips: bootinfo.h cpu.h 
        include/asm-mips/mach-au1x00: au1000.h au1xxx_dbdma.h 
Added files:
        arch/mips/au1000/pb1200: Makefile board_setup.c init.c irqmap.c 
        include/asm-mips/mach-db1x00: db1200.h 
        include/asm-mips/mach-pb1x00: pb1200.h 

Log message:
        Base Au1200 2.6 support.

diff -urN linux/arch/mips/Kconfig linux/arch/mips/Kconfig
--- linux/arch/mips/Kconfig     2005/02/18 06:27:25     1.142
+++ linux/arch/mips/Kconfig     2005/03/01 06:33:16     1.143
@@ -58,6 +58,13 @@
        select MIPS_DISABLE_OBSOLETE_IDE
        select SYS_SUPPORTS_LITTLE_ENDIAN
 
+config MIPS_PB1200
+       bool "AMD Alchemy PB1200 board"
+       select SOC_AU1200
+       select DMA_NONCOHERENT
+       select MIPS_DISABLE_OBSOLETE_IDE
+       select SYS_SUPPORTS_LITTLE_ENDIAN
+
 config MIPS_DB1000
        bool "AMD Alchemy DB1000 board"
        select SOC_AU1000
@@ -87,6 +94,13 @@
        select MIPS_DISABLE_OBSOLETE_IDE
        select SYS_SUPPORTS_LITTLE_ENDIAN
 
+config MIPS_DB1200
+       bool "AMD Alchemy DB1200 board"
+       select SOC_AU1200
+       select DMA_NONCOHERENT
+       select MIPS_DISABLE_OBSOLETE_IDE
+       select SYS_SUPPORTS_LITTLE_ENDIAN
+
 config MIPS_MIRAGE
        bool "AMD Alchemy Mirage board"
        select DMA_NONCOHERENT
@@ -778,6 +792,10 @@
        bool
        select SOC_AU1X00
 
+config SOC_AU1200
+       bool
+       select SOC_AU1X00
+
 config SOC_AU1X00
        bool
        select SYS_SUPPORTS_32BIT_KERNEL
diff -urN linux/arch/mips/Makefile linux/arch/mips/Makefile
--- linux/arch/mips/Makefile    2005/02/21 16:18:36     1.190
+++ linux/arch/mips/Makefile    2005/03/01 06:33:16     1.191
@@ -267,6 +267,13 @@
 load-$(CONFIG_MIPS_PB1550)     += 0xffffffff80100000
 
 #
+# AMD Alchemy Pb1200 eval board
+#
+libs-$(CONFIG_MIPS_PB1200)     += arch/mips/au1000/pb1200/
+cflags-$(CONFIG_MIPS_PB1200)   += -Iinclude/asm-mips/mach-pb1x00
+load-$(CONFIG_MIPS_PB1200)     += 0xffffffff80100000
+
+#
 # AMD Alchemy Db1000 eval board
 #
 libs-$(CONFIG_MIPS_DB1000)     += arch/mips/au1000/db1x00/
@@ -295,6 +302,13 @@
 load-$(CONFIG_MIPS_DB1550)     += 0xffffffff80100000
 
 #
+# AMD Alchemy Db1200 eval board
+#
+libs-$(CONFIG_MIPS_DB1200)     += arch/mips/au1000/pb1200/
+cflags-$(CONFIG_MIPS_DB1200)   += -Iinclude/asm-mips/mach-db1x00
+load-$(CONFIG_MIPS_DB1200)     += 0xffffffff80100000
+
+#
 # AMD Alchemy Bosporus eval board
 #
 libs-$(CONFIG_MIPS_BOSPORUS)   += arch/mips/au1000/db1x00/
diff -urN linux/arch/mips/au1000/common/au1xxx_irqmap.c 
linux/arch/mips/au1000/common/au1xxx_irqmap.c
--- linux/arch/mips/au1000/common/au1xxx_irqmap.c       2005/01/15 01:31:04     
1.5
+++ linux/arch/mips/au1000/common/au1xxx_irqmap.c       2005/03/01 06:33:16     
1.6
@@ -173,14 +173,14 @@
        { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
        { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0},
        { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_TOY_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
-       { AU1550_RTC_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
+       { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0},
        { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
@@ -201,14 +201,14 @@
        { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
        { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0},
        { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1200_TOY_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
-       { AU1200_RTC_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
+       { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0},
        { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
diff -urN linux/arch/mips/au1000/common/cputable.c 
linux/arch/mips/au1000/common/cputable.c
--- linux/arch/mips/au1000/common/cputable.c    2005/01/15 01:31:04     1.4
+++ linux/arch/mips/au1000/common/cputable.c    2005/03/01 06:33:16     1.5
@@ -37,7 +37,8 @@
     { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 },
     { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 },
     { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 },
-    { 0xffffffff, 0x04030200, "Au1200 AA", 0, 1 },
+    { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 },
+    { 0xffffffff, 0x04030201, "Au1200 AC", 0, 1 },
     { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 },
 };
 
diff -urN linux/arch/mips/au1000/common/dbdma.c 
linux/arch/mips/au1000/common/dbdma.c
--- linux/arch/mips/au1000/common/dbdma.c       2005/01/15 01:31:04     1.11
+++ linux/arch/mips/au1000/common/dbdma.c       2005/03/01 06:33:16     1.12
@@ -29,6 +29,7 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
  */
+
 #include <linux/config.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
@@ -42,6 +43,8 @@
 #include <asm/mach-au1x00/au1xxx_dbdma.h>
 #include <asm/system.h>
 
+/* #include <linux/module.h> */
+
 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
 
 /*
@@ -55,43 +58,16 @@
  * functions.  The drivers allocate the data buffers and assign them
  * to the descriptors.
  */
-static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
+static spinlock_t au1xxx_dbdma_spin_lock = SPIN_LOCK_UNLOCKED;
 
 /* I couldn't find a macro that did this......
 */
 #define ALIGN_ADDR(x, a)       ((((u32)(x)) + (a-1)) & ~(a-1))
 
-static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t 
*)DDMA_GLOBAL_BASE;
-static int dbdma_initialized;
+static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
+static int dbdma_initialized=0;
 static void au1xxx_dbdma_init(void);
 
-typedef struct dbdma_device_table {
-       u32             dev_id;
-       u32             dev_flags;
-       u32             dev_tsize;
-       u32             dev_devwidth;
-       u32             dev_physaddr;           /* If FIFO */
-       u32             dev_intlevel;
-       u32             dev_intpolarity;
-} dbdev_tab_t;
-
-typedef struct dbdma_chan_config {
-       u32                     chan_flags;
-       u32                     chan_index;
-       dbdev_tab_t             *chan_src;
-       dbdev_tab_t             *chan_dest;
-       au1x_dma_chan_t         *chan_ptr;
-       au1x_ddma_desc_t        *chan_desc_base;
-       au1x_ddma_desc_t        *get_ptr, *put_ptr, *cur_ptr;
-       void                    *chan_callparam;
-       void (*chan_callback)(int, void *, struct pt_regs *);
-} chan_tab_t;
-
-#define        DEV_FLAGS_INUSE         (1 << 0)
-#define        DEV_FLAGS_ANYUSE        (1 << 1)
-#define DEV_FLAGS_OUT          (1 << 2)
-#define DEV_FLAGS_IN           (1 << 3)
-
 static dbdev_tab_t dbdev_tab[] = {
 #ifdef CONFIG_SOC_AU1550
        /* UARTS */
@@ -157,13 +133,13 @@
        { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
        { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
 
-       { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-       { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-       { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-       { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+       { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
+       { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
+       { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
+       { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
 
-       { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-       { DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+       { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
+       { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
 
        { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
        { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
@@ -173,9 +149,9 @@
        { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
        { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
 
-       { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-       { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-       { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+       { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
+       { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
+       { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
        { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
 
        { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
@@ -184,6 +160,24 @@
 
        { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
        { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+
+       /* Provide 16 user definable device types */
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
 };
 
 #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
@@ -203,6 +197,30 @@
        return NULL;
 }
 
+u32
+au1xxx_ddma_add_device(dbdev_tab_t *dev)
+{
+       u32 ret = 0;
+       dbdev_tab_t *p=NULL;
+       static u16 new_id=0x1000;
+
+       p = find_dbdev_id(0);
+       if ( NULL != p )
+       {
+               memcpy(p, dev, sizeof(dbdev_tab_t));
+               p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
+               ret = p->dev_id;
+               new_id++;
+#if 0
+               printk("add_device: id:%x flags:%x padd:%x\n", 
+                               p->dev_id, p->dev_flags, p->dev_physaddr );
+#endif
+       }
+
+       return ret;
+}
+EXPORT_SYMBOL(au1xxx_ddma_add_device);
+
 /* Allocate a channel and return a non-zero descriptor if successful.
 */
 u32
@@ -215,7 +233,7 @@
        int             i;
        dbdev_tab_t     *stp, *dtp;
        chan_tab_t      *ctp;
-       volatile au1x_dma_chan_t *cp;
+       au1x_dma_chan_t *cp;
 
        /* We do the intialization on the first channel allocation.
         * We have to wait because of the interrupt handler initialization
@@ -225,9 +243,6 @@
                au1xxx_dbdma_init();
        dbdma_initialized = 1;
 
-       if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS))
-               return 0;
-
        if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
        if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
 
@@ -269,9 +284,9 @@
                                /* If kmalloc fails, it is caught below same
                                 * as a channel not available.
                                 */
-                               ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
+                               ctp = (chan_tab_t *)
+                                       kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
                                chan_tab_ptr[i] = ctp;
-                               ctp->chan_index = chan = i;
                                break;
                        }
                }
@@ -279,10 +294,11 @@
 
                if (ctp != NULL) {
                        memset(ctp, 0, sizeof(chan_tab_t));
+                       ctp->chan_index = chan = i;
                        dcp = DDMA_CHANNEL_BASE;
                        dcp += (0x0100 * chan);
                        ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
-                       cp = (volatile au1x_dma_chan_t *)dcp;
+                       cp = (au1x_dma_chan_t *)dcp;
                        ctp->chan_src = stp;
                        ctp->chan_dest = dtp;
                        ctp->chan_callback = callback;
@@ -299,6 +315,9 @@
                                i |= DDMA_CFG_DED;
                        if (dtp->dev_intpolarity)
                                i |= DDMA_CFG_DP;
+                       if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
+                               (dtp->dev_flags & DEV_FLAGS_SYNC))
+                                       i |= DDMA_CFG_SYNC;
                        cp->ddma_cfg = i;
                        au_sync();
 
@@ -309,14 +328,14 @@
                        rv = (u32)(&chan_tab_ptr[chan]);
                }
                else {
-                       /* Release devices.
-                       */
+                       /* Release devices */
                        stp->dev_flags &= ~DEV_FLAGS_INUSE;
                        dtp->dev_flags &= ~DEV_FLAGS_INUSE;
                }
        }
        return rv;
 }
+EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
 
 /* Set the device width if source or destination is a FIFO.
  * Should be 8, 16, or 32 bits.
@@ -344,6 +363,7 @@
 
        return rv;
 }
+EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
 
 /* Allocate a descriptor ring, initializing as much as possible.
 */
@@ -370,7 +390,8 @@
         * and if we try that first we are likely to not waste larger
         * slabs of memory.
         */
-       desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), 
GFP_KERNEL);
+       desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), 
+                       GFP_KERNEL|GFP_DMA);
        if (desc_base == 0)
                return 0;
 
@@ -381,7 +402,7 @@
                kfree((const void *)desc_base);
                i = entries * sizeof(au1x_ddma_desc_t);
                i += (sizeof(au1x_ddma_desc_t) - 1);
-               if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0)
+               if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
                        return 0;
 
                desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
@@ -461,9 +482,14 @@
        /* If source input is fifo, set static address.
        */
        if (stp->dev_flags & DEV_FLAGS_IN) {
-               src0 = stp->dev_physaddr;
+               if ( stp->dev_flags & DEV_FLAGS_BURSTABLE ) 
+                       src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
+               else 
                src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
+
        }
+       if (stp->dev_physaddr) 
+               src0 = stp->dev_physaddr;
 
        /* Set up dest1.  For now, assume no stride and increment.
         * A channel attribute update can change this later.
@@ -487,10 +513,18 @@
        /* If destination output is fifo, set static address.
        */
        if (dtp->dev_flags & DEV_FLAGS_OUT) {
-               dest0 = dtp->dev_physaddr;
+               if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
+                       dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
+                               else
                dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
        }
+       if (dtp->dev_physaddr) 
+               dest0 = dtp->dev_physaddr;
 
+#if 0
+               printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x 
dest0:%x dest1:%x\n",
+                       dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, 
dest0, dest1 );
+#endif
        for (i=0; i<entries; i++) {
                dp->dscr_cmd0 = cmd0;
                dp->dscr_cmd1 = cmd1;
@@ -499,6 +533,7 @@
                dp->dscr_dest0 = dest0;
                dp->dscr_dest1 = dest1;
                dp->dscr_stat = 0;
+                               dp->sw_context = dp->sw_status = 0;
                dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
                dp++;
        }
@@ -511,13 +546,14 @@
 
        return (u32)(ctp->chan_desc_base);
 }
+EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
 
 /* Put a source buffer into the DMA ring.
  * This updates the source pointer and byte count.  Normally used
  * for memory to fifo transfers.
  */
 u32
-au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
+_au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
 {
        chan_tab_t              *ctp;
        au1x_ddma_desc_t        *dp;
@@ -544,24 +580,40 @@
        */
        dp->dscr_source0 = virt_to_phys(buf);
        dp->dscr_cmd1 = nbytes;
-       dp->dscr_cmd0 |= DSCR_CMD0_V;   /* Let it rip */
-       ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */
-
+       /* Check flags  */
+       if (flags & DDMA_FLAGS_IE) 
+               dp->dscr_cmd0 |= DSCR_CMD0_IE;
+       if (flags & DDMA_FLAGS_NOIE)
+               dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
        /* Get next descriptor pointer.
        */
        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
+       /*
+        * There is an errata on the Au1200/Au1550 parts that could result 
+        * in "stale" data being DMA'd. It has to do with the snoop logic on 
+        * the dache eviction buffer.  NONCOHERENT_IO is on by default for 
+        * these parts. If it is fixedin the future, these dma_cache_inv will 
+        * just be nothing more than empty macros. See io.h.
+        * */
+       dma_cache_wback_inv(buf,nbytes);
+        dp->dscr_cmd0 |= DSCR_CMD0_V;        /* Let it rip */
+       au_sync();
+       dma_cache_wback_inv(dp, sizeof(dp));
+        ctp->chan_ptr->ddma_dbell = 0;
+
        /* return something not zero.
        */
        return nbytes;
 }
+EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
 
 /* Put a destination buffer into the DMA ring.
  * This updates the destination pointer and byte count.  Normally used
  * to place an empty buffer into the ring for fifo to memory transfers.
  */
 u32
-au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
+_au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
 {
        chan_tab_t              *ctp;
        au1x_ddma_desc_t        *dp;
@@ -583,11 +635,33 @@
        if (dp->dscr_cmd0 & DSCR_CMD0_V)
                return 0;
 
-       /* Load up buffer address and byte count.
-       */
+       /* Load up buffer address and byte count */
+
+       /* Check flags  */
+       if (flags & DDMA_FLAGS_IE) 
+               dp->dscr_cmd0 |= DSCR_CMD0_IE;
+       if (flags & DDMA_FLAGS_NOIE)
+               dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
+
        dp->dscr_dest0 = virt_to_phys(buf);
        dp->dscr_cmd1 = nbytes;
+#if 0
+       printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", 
+                       dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0, 
+                       dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
+#endif
+       /*
+        * There is an errata on the Au1200/Au1550 parts that could result in 
+        * "stale" data being DMA'd. It has to do with the snoop logic on the 
+        * dache eviction buffer. NONCOHERENT_IO is on by default for these 
+        * parts. If it is fixedin the future, these dma_cache_inv will just 
+        * be nothing more than empty macros. See io.h. 
+        * */
+       dma_cache_inv(buf,nbytes);
        dp->dscr_cmd0 |= DSCR_CMD0_V;   /* Let it rip */
+       au_sync();
+       dma_cache_wback_inv(dp, sizeof(dp));
+        ctp->chan_ptr->ddma_dbell = 0;
 
        /* Get next descriptor pointer.
        */
@@ -597,6 +671,7 @@
        */
        return nbytes;
 }
+EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
 
 /* Get a destination buffer into the DMA ring.
  * Normally used to get a full buffer from the ring during fifo
@@ -646,7 +721,7 @@
 au1xxx_dbdma_stop(u32 chanid)
 {
        chan_tab_t      *ctp;
-       volatile au1x_dma_chan_t *cp;
+       au1x_dma_chan_t *cp;
        int halt_timeout = 0;
 
        ctp = *((chan_tab_t **)chanid);
@@ -666,6 +741,7 @@
        cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
        au_sync();
 }
+EXPORT_SYMBOL(au1xxx_dbdma_stop);
 
 /* Start using the current descriptor pointer.  If the dbdma encounters
  * a not valid descriptor, it will stop.  In this case, we can just
@@ -675,17 +751,17 @@
 au1xxx_dbdma_start(u32 chanid)
 {
        chan_tab_t      *ctp;
-       volatile au1x_dma_chan_t *cp;
+       au1x_dma_chan_t *cp;
 
        ctp = *((chan_tab_t **)chanid);
-
        cp = ctp->chan_ptr;
        cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
        cp->ddma_cfg |= DDMA_CFG_EN;    /* Enable channel */
        au_sync();
-       cp->ddma_dbell = 0xffffffff;    /* Make it go */
+       cp->ddma_dbell = 0;
        au_sync();
 }
+EXPORT_SYMBOL(au1xxx_dbdma_start);
 
 void
 au1xxx_dbdma_reset(u32 chanid)
@@ -704,15 +780,21 @@
 
        do {
                dp->dscr_cmd0 &= ~DSCR_CMD0_V;
+               /* reset our SW status -- this is used to determine 
+                * if a descriptor is in use by upper level SW. Since 
+                * posting can reset 'V' bit. 
+                */
+               dp->sw_status = 0;
                dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
        } while (dp != ctp->chan_desc_base);
 }
+EXPORT_SYMBOL(au1xxx_dbdma_reset);
 
 u32
 au1xxx_get_dma_residue(u32 chanid)
 {
        chan_tab_t      *ctp;
-       volatile au1x_dma_chan_t *cp;
+       au1x_dma_chan_t *cp;
        u32             rv;
 
        ctp = *((chan_tab_t **)chanid);
@@ -747,15 +829,16 @@
 
        kfree(ctp);
 }
+EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
 
-static irqreturn_t
+static void
 dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
-       u32     intstat;
+       u32                                     intstat, flags;
        u32     chan_index;
        chan_tab_t              *ctp;
        au1x_ddma_desc_t        *dp;
-       volatile au1x_dma_chan_t *cp;
+       au1x_dma_chan_t *cp;
 
        intstat = dbdma_gptr->ddma_intstat;
        au_sync();
@@ -774,19 +857,26 @@
                (ctp->chan_callback)(irq, ctp->chan_callparam, regs);
 
        ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
-
-       return IRQ_HANDLED;
 }
 
-static void
-au1xxx_dbdma_init(void)
+static void au1xxx_dbdma_init(void)
 {
+       int irq_nr;
+
        dbdma_gptr->ddma_config = 0;
        dbdma_gptr->ddma_throttle = 0;
        dbdma_gptr->ddma_inten = 0xffff;
        au_sync();
 
-       if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT,
+#if defined(CONFIG_SOC_AU1550)
+       irq_nr = AU1550_DDMA_INT;
+#elif defined(CONFIG_SOC_AU1200)
+       irq_nr = AU1200_DDMA_INT;
+#else
+       #error Unknown Au1x00 SOC
+#endif
+
+       if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT,
                        "Au1xxx dbdma", (void *)dbdma_gptr))
                printk("Can't get 1550 dbdma irq");
 }
@@ -797,7 +887,8 @@
        chan_tab_t              *ctp;
        au1x_ddma_desc_t        *dp;
        dbdev_tab_t             *stp, *dtp;
-       volatile au1x_dma_chan_t *cp;
+       au1x_dma_chan_t *cp;
+               u32                     i = 0;
 
        ctp = *((chan_tab_t **)chanid);
        stp = ctp->chan_src;
@@ -822,15 +913,64 @@
        dp = ctp->chan_desc_base;
 
        do {
-               printk("dp %08x, cmd0 %08x, cmd1 %08x\n",
-                       (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
-               printk("src0 %08x, src1 %08x, dest0 %08x\n",
-                       dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0);
-               printk("dest1 %08x, stat %08x, nxtptr %08x\n",
-                       dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr);
+                printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
+                        i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
+                printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
+                        dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, 
dp->dscr_dest1);
+                printk("stat %08x, nxtptr %08x\n",
+                        dp->dscr_stat, dp->dscr_nxtptr);
                dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
        } while (dp != ctp->chan_desc_base);
 }
 
+/* Put a descriptor into the DMA ring.
+ * This updates the source/destination pointers and byte count.
+ */
+u32
+au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
+{
+       chan_tab_t *ctp;
+       au1x_ddma_desc_t *dp;
+       u32 nbytes=0;
+
+       /* I guess we could check this to be within the
+       * range of the table......
+       */
+       ctp = *((chan_tab_t **)chanid);
+
+       /* We should have multiple callers for a particular channel,
+       * an interrupt doesn't affect this pointer nor the descriptor,
+       * so no locking should be needed.
+       */
+       dp = ctp->put_ptr;
+
+       /* If the descriptor is valid, we are way ahead of the DMA
+       * engine, so just return an error condition.
+       */
+       if (dp->dscr_cmd0 & DSCR_CMD0_V)
+               return 0;
+
+       /* Load up buffer addresses and byte count.
+       */
+       dp->dscr_dest0 = dscr->dscr_dest0;
+       dp->dscr_source0 = dscr->dscr_source0;
+       dp->dscr_dest1 = dscr->dscr_dest1;
+       dp->dscr_source1 = dscr->dscr_source1;
+       dp->dscr_cmd1 = dscr->dscr_cmd1;
+       nbytes = dscr->dscr_cmd1;
+       /* Allow the caller to specifiy if an interrupt is generated */
+       dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
+       dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
+       ctp->chan_ptr->ddma_dbell = 0;
+
+       /* Get next descriptor pointer.
+       */
+       ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
+
+       /* return something not zero.
+       */
+       return nbytes;
+}
+
 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
 
diff -urN linux/arch/mips/au1000/common/irq.c 
linux/arch/mips/au1000/common/irq.c
--- linux/arch/mips/au1000/common/irq.c 2005/02/28 13:39:57     1.37
+++ linux/arch/mips/au1000/common/irq.c 2005/03/01 06:33:16     1.38
@@ -488,7 +488,7 @@
        intc0_req0 |= au_readl(IC0_REQ0INT);
 
        if (!intc0_req0) return;
-
+#ifdef AU1000_USB_DEV_REQ_INT
        /*
         * Because of the tight timing of SETUP token to reply
         * transactions, the USB devices-side packet complete
@@ -499,7 +499,7 @@
                do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
                return;
        }
-
+#endif
        irq = au_ffs(intc0_req0) - 1;
        intc0_req0 &= ~(1<<irq);
        do_IRQ(irq, regs);
diff -urN linux/arch/mips/au1000/pb1200/Makefile 
linux/arch/mips/au1000/pb1200/Makefile
--- linux/arch/mips/au1000/pb1200/Makefile      2005/01/30 08:01:27     1.1
+++ linux/arch/mips/au1000/pb1200/Makefile      2005/03/01 06:33:16     1.2
@@ -0,0 +1,5 @@
+#
+# Makefile for the Alchemy Semiconductor PB1200 board.
+#
+
+lib-y := init.o board_setup.o irqmap.o
diff -urN linux/arch/mips/au1000/pb1200/board_setup.c 
linux/arch/mips/au1000/pb1200/board_setup.c
--- linux/arch/mips/au1000/pb1200/board_setup.c 2005/01/30 08:01:28     1.1
+++ linux/arch/mips/au1000/pb1200/board_setup.c 2005/03/01 06:33:16     1.2
@@ -0,0 +1,187 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *     Alchemy Pb1200/Db1200 board setup.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/mc146818rtc.h>
+#include <linux/delay.h>
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
+#include <linux/ide.h>
+#endif
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/pgtable.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
+
+#ifdef CONFIG_MIPS_PB1200
+#include <asm/mach-pb1x00/pb1200.h>
+#endif
+
+#ifdef CONFIG_MIPS_DB1200
+#include <asm/mach-db1x00/db1200.h>
+#define PB1200_ETH_INT DB1200_ETH_INT
+#define PB1200_IDE_INT DB1200_IDE_INT
+#endif
+
+extern void _board_init_irq(void);
+extern void    (*board_init_irq)(void);
+
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX
+extern struct ide_ops *ide_ops;
+extern struct ide_ops au1xxx_ide_ops;
+extern u32 au1xxx_ide_virtbase;
+extern u64 au1xxx_ide_physbase;
+extern int au1xxx_ide_irq;
+
+u32 led_base_addr;
+/* Ddma */
+chan_tab_t *ide_read_ch, *ide_write_ch;
+u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma
+
+dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 
0, 0x00000000, 0, 0 };
+#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */
+
+void board_reset (void)
+{
+       bcsr->resets = 0;
+}
+
+void __init board_setup(void)
+{
+       char *argptr = NULL;
+       u32 pin_func;
+
+#if 0
+       /* Enable PSC1 SYNC for AC97.  Normaly done in audio driver,
+        * but it is board specific code, so put it here.
+        */
+       pin_func = au_readl(SYS_PINFUNC);
+       au_sync();
+       pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
+       au_writel(pin_func, SYS_PINFUNC);
+
+       au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
+       au_sync();
+#endif
+
+#if defined( CONFIG_I2C_ALGO_AU1550 )
+       {
+       u32 freq0, clksrc;
+
+       /* Select SMBUS in CPLD */
+       bcsr->resets &= ~(BCSR_RESETS_PCS0MUX);
+
+       pin_func = au_readl(SYS_PINFUNC);
+       au_sync();
+       pin_func &= ~(3<<17 | 1<<4);
+       /* Set GPIOs correctly */
+       pin_func |= 2<<17;
+       au_writel(pin_func, SYS_PINFUNC);
+       au_sync();
+
+       /* The i2c driver depends on 50Mhz clock */
+       freq0 = au_readl(SYS_FREQCTRL0);
+       au_sync();
+       freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
+       freq0 |= (3<<SYS_FC_FRDIV1_BIT);
+       /* 396Mhz / (3+1)*2 == 49.5Mhz */
+       au_writel(freq0, SYS_FREQCTRL0);
+       au_sync();
+       freq0 |= SYS_FC_FE1;
+       au_writel(freq0, SYS_FREQCTRL0);
+       au_sync();
+
+       clksrc = au_readl(SYS_CLKSRC);
+       au_sync();
+       clksrc &= ~0x01f00000;
+       /* bit 22 is EXTCLK0 for PSC0 */
+       clksrc |= (0x3 << 22);
+       au_writel(clksrc, SYS_CLKSRC);
+       au_sync();
+       }
+#endif
+
+#ifdef CONFIG_FB_AU1200
+       argptr = prom_getcmdline();
+#ifdef CONFIG_MIPS_PB1200
+       strcat(argptr, " video=au1200fb:panel:s11");
+#endif
+#ifdef CONFIG_MIPS_DB1200
+       strcat(argptr, " video=au1200fb:panel:s7");
+#endif
+#endif
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
+       /*
+        * Iniz IDE parameters
+        */
+       ide_ops = &au1xxx_ide_ops;
+       au1xxx_ide_irq = PB1200_IDE_INT;
+       au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR;
+       au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR);
+       /*
+        * change PIO or PIO+Ddma
+        * check the GPIO-5 pin condition. pb1200:s18_dot */
+       switch4ddma = (au_readl(SYS_PINSTATERD) & (1 << 5)) ? 1 : 0; 
+#endif
+
+       /* The Pb1200 development board uses external MUX for PSC0 to
+       support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
+       */
+#if defined(CONFIG_AU1550_PSC_SPI) && defined(CONFIG_I2C_ALGO_AU1550)
+       #error I2C and SPI are mutually exclusive. Both are physically 
connected to PSC0.\
+                       Refer to Pb1200/Db1200 documentation.
+#elif defined( CONFIG_AU1550_PSC_SPI )
+       bcsr->resets |= BCSR_RESETS_PCS0MUX;
+#elif defined( CONFIG_I2C_ALGO_AU1550 )
+       bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
+#endif
+       au_sync();
+
+#ifdef CONFIG_MIPS_PB1200
+       printk("AMD Alchemy Pb1200 Board\n");
+#endif
+#ifdef CONFIG_MIPS_DB1200
+       printk("AMD Alchemy Db1200 Board\n");
+#endif
+#if 0
+       /* Setup Pb1200 External Interrupt Controller */
+       {
+               extern void (*board_init_irq)(void);
+               extern void _board_init_irq(void);
+               board_init_irq = _board_init_irq;
+       }
+#endif
+}
diff -urN linux/arch/mips/au1000/pb1200/init.c 
linux/arch/mips/au1000/pb1200/init.c
--- linux/arch/mips/au1000/pb1200/init.c        2005/01/30 08:01:28     1.1
+++ linux/arch/mips/au1000/pb1200/init.c        2005/03/01 06:33:16     1.2
@@ -0,0 +1,69 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *     PB1200 board setup
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *             ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/bootmem.h>
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+extern void  __init prom_init_cmdline(void);
+extern char *prom_getenv(char *envname);
+
+const char *get_system_type(void)
+{
+       return "Alchemy Pb1200";
+}
+
+void __init prom_init(void)
+{
+       unsigned char *memsize_str;
+       unsigned long memsize;
+
+       prom_argc = (int) fw_arg0;
+       prom_argv = (char **) fw_arg1;
+       prom_envp = (char **) fw_arg2;
+
+       mips_machgroup = MACH_GROUP_ALCHEMY;
+       mips_machtype = MACH_PB1200;
+
+       prom_init_cmdline();
+       memsize_str = prom_getenv("memsize");
+       if (!memsize_str) {
+               memsize = 0x08000000;
+       } else {
+               memsize = simple_strtol(memsize_str, NULL, 0);
+       }
+       add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
diff -urN linux/arch/mips/au1000/pb1200/irqmap.c 
linux/arch/mips/au1000/pb1200/irqmap.c
--- linux/arch/mips/au1000/pb1200/irqmap.c      2005/01/30 08:01:28     1.1
+++ linux/arch/mips/au1000/pb1200/irqmap.c      2005/03/01 06:33:16     1.2
@@ -0,0 +1,180 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *     Au1xxx irq map table
+ *
+ *  This program is free software; you can redistribute         it and/or 
modify it
+ *  under  the terms of         the GNU General  Public License as published 
by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED          ``AS  IS'' AND   ANY  EXPRESS OR 
IMPLIED
+ *  WARRANTIES,          INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED 
WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED          TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; 
LOSS OF
+ *  USE, DATA, OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN         CONTRACT, STRICT LIABILITY, OR 
TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#ifdef CONFIG_MIPS_PB1200
+#include <asm/mach-pb1x00/pb1200.h>
+#endif
+
+#ifdef CONFIG_MIPS_DB1200
+#include <asm/mach-db1x00/db1200.h>
+#define PB1200_INT_BEGIN DB1200_INT_BEGIN
+#define PB1200_INT_END DB1200_INT_END
+#endif
+
+au1xxx_irq_map_t au1xxx_irq_map[] = {
+       { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt 
cascade
+};
+
+int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+
+/*
+ *     Support for External interrupts on the PbAu1200 Development platform.
+ */
+static volatile int pb1200_cascade_en=0;
+
+void pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs)
+{
+       unsigned short bisr = bcsr->int_status;
+       int extirq_nr = 0;
+
+       /* Clear all the edge interrupts. This has no effect on level */
+       bcsr->int_status = bisr;
+       for( ; bisr; bisr &= (bisr-1) )
+       {
+               extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr);
+               /* Ack and dispatch IRQ */
+               do_IRQ(extirq_nr,regs);
+       }
+}
+
+inline void pb1200_enable_irq(unsigned int irq_nr)
+{
+       bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
+       bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN);
+}
+
+inline void pb1200_disable_irq(unsigned int irq_nr)
+{
+       bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
+       bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN);
+}
+
+static unsigned int pb1200_startup_irq( unsigned int irq_nr )
+{
+       if (++pb1200_cascade_en == 1)
+       {
+               request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
+                       0, "Pb1200 Cascade", &pb1200_cascade_handler );
+#ifdef CONFIG_MIPS_PB1200
+    /* We have a problem with CPLD rev3. Enable a workaround */
+       if( ((bcsr->whoami & BCSR_WHOAMI_CPLD)>>4) <= 3)
+       {
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n");
+               printk("updated to latest revision. This software will not\n");
+               printk("work on anything less than CPLD rev4\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               while(1);
+       }
+#endif
+       }
+       pb1200_enable_irq(irq_nr);
+       return 0;
+}
+
+static void pb1200_shutdown_irq( unsigned int irq_nr )
+{
+       pb1200_disable_irq(irq_nr);
+       if (--pb1200_cascade_en == 0)
+       {
+               free_irq(AU1000_GPIO_7,&pb1200_cascade_handler );
+       }
+       return;
+}
+
+static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr)
+{
+       pb1200_disable_irq( irq_nr );
+}
+
+static void pb1200_end_irq(unsigned int irq_nr)
+{
+       if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+               pb1200_enable_irq(irq_nr);
+       }
+}
+
+static struct hw_interrupt_type external_irq_type =
+{
+#ifdef CONFIG_MIPS_PB1200
+       "Pb1200 Ext",
+#endif
+#ifdef CONFIG_MIPS_DB1200
+       "Db1200 Ext",
+#endif
+       pb1200_startup_irq,
+       pb1200_shutdown_irq,
+       pb1200_enable_irq,
+       pb1200_disable_irq,
+       pb1200_mask_and_ack_irq,
+       pb1200_end_irq,
+       NULL
+};
+
+void _board_init_irq(void)
+{
+       int irq_nr;
+
+       for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++)
+       {
+               irq_desc[irq_nr].handler = &external_irq_type;
+               pb1200_disable_irq(irq_nr);
+       }
+
+       /* GPIO_7 can not be hooked here, so it is hooked upon first
+       request of any source attached to the cascade */
+}
+
diff -urN linux/arch/mips/kernel/cpu-probe.c linux/arch/mips/kernel/cpu-probe.c
--- linux/arch/mips/kernel/cpu-probe.c  2004/10/27 14:42:39     1.39
+++ linux/arch/mips/kernel/cpu-probe.c  2005/03/01 06:33:16     1.40
@@ -116,6 +116,8 @@
        case CPU_AU1000:
        case CPU_AU1100:
        case CPU_AU1500:
+       case CPU_AU1550:
+       case CPU_AU1200:
                if (au1k_wait_ptr != NULL) {
                        cpu_wait = au1k_wait_ptr;
                        printk(" available.\n");
@@ -511,6 +513,9 @@
                case 3:
                        c->cputype = CPU_AU1550;
                        break;
+               case 4:
+                       c->cputype = CPU_AU1200;
+                       break;
                default:
                        panic("Unknown Au Core!");
                        break;
diff -urN linux/arch/mips/kernel/proc.c linux/arch/mips/kernel/proc.c
--- linux/arch/mips/kernel/proc.c       2005/02/21 21:34:24     1.54
+++ linux/arch/mips/kernel/proc.c       2005/03/01 06:33:17     1.55
@@ -60,6 +60,9 @@
        [CPU_TX3927]    "TX3927",
        [CPU_AU1000]    "Au1000",
        [CPU_AU1500]    "Au1500",
+       [CPU_AU1100]    "Au1100",
+       [CPU_AU1550]    "Au1550",
+       [CPU_AU1200]    "Au1200",
        [CPU_4KEC]      "MIPS 4KEc",
        [CPU_4KSC]      "MIPS 4KSc",
        [CPU_VR41XX]    "NEC Vr41xx",
diff -urN linux/arch/mips/mm/c-r4k.c linux/arch/mips/mm/c-r4k.c
--- linux/arch/mips/mm/c-r4k.c  2005/02/19 13:32:02     1.104
+++ linux/arch/mips/mm/c-r4k.c  2005/03/01 06:33:17     1.105
@@ -1037,7 +1037,11 @@
                c->icache.flags |= MIPS_CACHE_VTAG;
                break;
 
+       case CPU_AU1000:
        case CPU_AU1500:
+       case CPU_AU1100:
+       case CPU_AU1550:
+       case CPU_AU1200:
                c->icache.flags |= MIPS_CACHE_IC_F_DC;
                break;
        }
diff -urN linux/arch/mips/mm/tlbex.c linux/arch/mips/mm/tlbex.c
--- linux/arch/mips/mm/tlbex.c  2005/01/12 16:38:50     1.16
+++ linux/arch/mips/mm/tlbex.c  2005/03/01 06:33:17     1.17
@@ -840,6 +840,7 @@
        case CPU_AU1100:
        case CPU_AU1500:
        case CPU_AU1550:
+       case CPU_AU1200:
                i_nop(p);
                tlbw(p);
                break;
diff -urN linux/include/asm-mips/bootinfo.h linux/include/asm-mips/bootinfo.h
--- linux/include/asm-mips/bootinfo.h   2004/12/15 14:08:18     1.79
+++ linux/include/asm-mips/bootinfo.h   2005/03/01 06:33:17     1.80
@@ -177,6 +177,8 @@
 #define  MACH_MTX1             7       /* 4G MTX-1 Au1500-based board */
 #define  MACH_PB1550           8       /* Au1550-based eval board */
 #define  MACH_DB1550           9       /* Au1550-based eval board */
+#define  MACH_PB1200           10       /* Au1200-based eval board */
+#define  MACH_DB1200           11       /* Au1200-based eval board */
 
 /*
  * Valid machtype for group NEC_VR41XX
diff -urN linux/include/asm-mips/cpu.h linux/include/asm-mips/cpu.h
--- linux/include/asm-mips/cpu.h        2005/02/07 21:52:35     1.53
+++ linux/include/asm-mips/cpu.h        2005/03/01 06:33:17     1.54
@@ -182,7 +182,8 @@
 #define CPU_VR4133             56
 #define CPU_AU1550             57
 #define CPU_24K                        58
-#define CPU_LAST               58
+#define CPU_AU1200             59
+#define CPU_LAST               59
 
 /*
  * ISA Level encodings
diff -urN linux/include/asm-mips/mach-au1x00/au1000.h 
linux/include/asm-mips/mach-au1x00/au1000.h
--- linux/include/asm-mips/mach-au1x00/au1000.h 2005/01/15 01:31:03     1.13
+++ linux/include/asm-mips/mach-au1x00/au1000.h 2005/03/01 06:33:19     1.14
@@ -162,28 +162,356 @@
 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
 #endif
 
-/* SDRAM Controller */
+/*
+ * SDRAM Register Offsets
+ */
 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || 
defined(CONFIG_SOC_AU1100)
-#define MEM_SDMODE0                0xB4000000
-#define MEM_SDMODE1                0xB4000004
-#define MEM_SDMODE2                0xB4000008
-
-#define MEM_SDADDR0                0xB400000C
-#define MEM_SDADDR1                0xB4000010
-#define MEM_SDADDR2                0xB4000014
-
-#define MEM_SDREFCFG               0xB4000018
-#define MEM_SDPRECMD               0xB400001C
-#define MEM_SDAUTOREF              0xB4000020
-
-#define MEM_SDWRMD0                0xB4000024
-#define MEM_SDWRMD1                0xB4000028
-#define MEM_SDWRMD2                0xB400002C
+#define MEM_SDMODE0            (0x0000)
+#define MEM_SDMODE1            (0x0004)
+#define MEM_SDMODE2            (0x0008)
+#define MEM_SDADDR0            (0x000C)
+#define MEM_SDADDR1            (0x0010)
+#define MEM_SDADDR2            (0x0014)
+#define MEM_SDREFCFG   (0x0018)
+#define MEM_SDPRECMD   (0x001C)
+#define MEM_SDAUTOREF  (0x0020)
+#define MEM_SDWRMD0            (0x0024)
+#define MEM_SDWRMD1            (0x0028)
+#define MEM_SDWRMD2            (0x002C)
+#define MEM_SDSLEEP            (0x0030)
+#define MEM_SDSMCKE            (0x0034)
+
+#ifndef ASSEMBLER
+/*typedef volatile struct
+{
+       uint32 sdmode0;
+       uint32 sdmode1;
+       uint32 sdmode2;
+       uint32 sdaddr0;
+       uint32 sdaddr1;
+       uint32 sdaddr2;
+       uint32 sdrefcfg;
+       uint32 sdautoref;
+       uint32 sdwrmd0;
+       uint32 sdwrmd1;
+       uint32 sdwrmd2;
+       uint32 sdsleep;
+       uint32 sdsmcke;
+
+} AU1X00_SDRAM;*/
+#endif
+
+/*
+ * MEM_SDMODE register content definitions
+ */
+#define MEM_SDMODE_F           (1<<22)
+#define MEM_SDMODE_SR          (1<<21)
+#define MEM_SDMODE_BS          (1<<20)
+#define MEM_SDMODE_RS          (3<<18)
+#define MEM_SDMODE_CS          (7<<15)
+#define MEM_SDMODE_TRAS                (15<<11)
+#define MEM_SDMODE_TMRD                (3<<9)
+#define MEM_SDMODE_TWR         (3<<7)
+#define MEM_SDMODE_TRP         (3<<5)
+#define MEM_SDMODE_TRCD                (3<<3)
+#define MEM_SDMODE_TCL         (7<<0)
+
+#define MEM_SDMODE_BS_2Bank    (0<<20)
+#define MEM_SDMODE_BS_4Bank    (1<<20)
+#define MEM_SDMODE_RS_11Row    (0<<18)
+#define MEM_SDMODE_RS_12Row    (1<<18)
+#define MEM_SDMODE_RS_13Row    (2<<18)
+#define MEM_SDMODE_RS_N(N)     ((N)<<18)
+#define MEM_SDMODE_CS_7Col     (0<<15)
+#define MEM_SDMODE_CS_8Col     (1<<15)
+#define MEM_SDMODE_CS_9Col     (2<<15)
+#define MEM_SDMODE_CS_10Col    (3<<15)
+#define MEM_SDMODE_CS_11Col    (4<<15)
+#define MEM_SDMODE_CS_N(N)             ((N)<<15)
+#define MEM_SDMODE_TRAS_N(N)   ((N)<<11)
+#define MEM_SDMODE_TMRD_N(N)   ((N)<<9)
+#define MEM_SDMODE_TWR_N(N)            ((N)<<7)
+#define MEM_SDMODE_TRP_N(N)            ((N)<<5)
+#define MEM_SDMODE_TRCD_N(N)   ((N)<<3)
+#define MEM_SDMODE_TCL_N(N)            ((N)<<0)
+
+/*
+ * MEM_SDADDR register contents definitions
+ */
+#define MEM_SDADDR_E                   (1<<20)
+#define MEM_SDADDR_CSBA                        (0x03FF<<10)
+#define MEM_SDADDR_CSMASK              (0x03FF<<0)
+#define MEM_SDADDR_CSBA_N(N)   ((N)&(0x03FF<<22)>>12)
+#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22)
+
+/*
+ * MEM_SDREFCFG register content definitions
+ */
+#define MEM_SDREFCFG_TRC               (15<<28)
+#define MEM_SDREFCFG_TRPM              (3<<26)
+#define MEM_SDREFCFG_E                 (1<<25)
+#define MEM_SDREFCFG_RE                        (0x1ffffff<<0)
+#define MEM_SDREFCFG_TRC_N(N)  ((N)<<MEM_SDREFCFG_TRC)
+#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM)
+#define MEM_SDREFCFG_REF_N(N)  (N)
+#endif
+
+/***********************************************************************/
+
+/*
+ * Au1550 SDRAM Register Offsets
+ */
 
-#define MEM_SDSLEEP                0xB4000030
-#define MEM_SDSMCKE                0xB4000034
+/***********************************************************************/
+
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+#define MEM_SDMODE0            (0x0800)
+#define MEM_SDMODE1            (0x0808)
+#define MEM_SDMODE2            (0x0810)
+#define MEM_SDADDR0            (0x0820)
+#define MEM_SDADDR1            (0x0828)
+#define MEM_SDADDR2            (0x0830)
+#define MEM_SDCONFIGA  (0x0840)
+#define MEM_SDCONFIGB  (0x0848)
+#define MEM_SDSTAT             (0x0850)
+#define MEM_SDERRADDR  (0x0858)
+#define MEM_SDSTRIDE0  (0x0860)
+#define MEM_SDSTRIDE1  (0x0868)
+#define MEM_SDSTRIDE2  (0x0870)
+#define MEM_SDWRMD0            (0x0880)
+#define MEM_SDWRMD1            (0x0888)
+#define MEM_SDWRMD2            (0x0890)
+#define MEM_SDPRECMD   (0x08C0)
+#define MEM_SDAUTOREF  (0x08C8)
+#define MEM_SDSREF             (0x08D0)
+#define MEM_SDSLEEP            MEM_SDSREF
+
+#ifndef ASSEMBLER
+/*typedef volatile struct
+{
+       uint32 sdmode0;
+       uint32 reserved0;
+       uint32 sdmode1;
+       uint32 reserved1;
+       uint32 sdmode2;
+       uint32 reserved2[3];
+       uint32 sdaddr0;
+       uint32 reserved3;
+       uint32 sdaddr1;
+       uint32 reserved4;
+       uint32 sdaddr2;
+       uint32 reserved5[3];
+       uint32 sdconfiga;
+       uint32 reserved6;
+       uint32 sdconfigb;
+       uint32 reserved7;
+       uint32 sdstat;
+       uint32 reserved8;
+       uint32 sderraddr;
+       uint32 reserved9;
+       uint32 sdstride0;
+       uint32 reserved10;
+       uint32 sdstride1;
+       uint32 reserved11;
+       uint32 sdstride2;
+       uint32 reserved12[3];
+       uint32 sdwrmd0;
+       uint32 reserved13;
+       uint32 sdwrmd1;
+       uint32 reserved14;
+       uint32 sdwrmd2;
+       uint32 reserved15[11];
+       uint32 sdprecmd;
+       uint32 reserved16;
+       uint32 sdautoref;
+       uint32 reserved17;
+       uint32 sdsref;
+
+} AU1550_SDRAM;*/
+#endif
 #endif
 
+/*
+ * Physical base addresses for integrated peripherals
+ */
+
+#ifdef CONFIG_SOC_AU1000
+#define        MEM_PHYS_ADDR           0x14000000
+#define        STATIC_MEM_PHYS_ADDR    0x14001000
+#define        DMA0_PHYS_ADDR          0x14002000
+#define        DMA1_PHYS_ADDR          0x14002100
+#define        DMA2_PHYS_ADDR          0x14002200
+#define        DMA3_PHYS_ADDR          0x14002300
+#define        DMA4_PHYS_ADDR          0x14002400
+#define        DMA5_PHYS_ADDR          0x14002500
+#define        DMA6_PHYS_ADDR          0x14002600
+#define        DMA7_PHYS_ADDR          0x14002700
+#define        IC0_PHYS_ADDR           0x10400000
+#define        IC1_PHYS_ADDR           0x11800000
+#define        AC97_PHYS_ADDR          0x10000000
+#define        USBH_PHYS_ADDR          0x10100000
+#define        USBD_PHYS_ADDR          0x10200000
+#define        IRDA_PHYS_ADDR          0x10300000
+#define        MAC0_PHYS_ADDR          0x10500000
+#define        MAC1_PHYS_ADDR          0x10510000
+#define        MACEN_PHYS_ADDR         0x10520000
+#define        MACDMA0_PHYS_ADDR       0x14004000
+#define        MACDMA1_PHYS_ADDR       0x14004200
+#define        I2S_PHYS_ADDR           0x11000000
+#define        UART0_PHYS_ADDR         0x11100000
+#define        UART1_PHYS_ADDR         0x11200000
+#define        UART2_PHYS_ADDR         0x11300000
+#define        UART3_PHYS_ADDR         0x11400000
+#define        SSI0_PHYS_ADDR          0x11600000
+#define        SSI1_PHYS_ADDR          0x11680000
+#define        SYS_PHYS_ADDR           0x11900000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#endif
+
+/********************************************************************/
+
+#ifdef CONFIG_SOC_AU1500
+#define        MEM_PHYS_ADDR           0x14000000
+#define        STATIC_MEM_PHYS_ADDR    0x14001000
+#define        DMA0_PHYS_ADDR          0x14002000
+#define        DMA1_PHYS_ADDR          0x14002100
+#define        DMA2_PHYS_ADDR          0x14002200
+#define        DMA3_PHYS_ADDR          0x14002300
+#define        DMA4_PHYS_ADDR          0x14002400
+#define        DMA5_PHYS_ADDR          0x14002500
+#define        DMA6_PHYS_ADDR          0x14002600
+#define        DMA7_PHYS_ADDR          0x14002700
+#define        IC0_PHYS_ADDR           0x10400000
+#define        IC1_PHYS_ADDR           0x11800000
+#define        AC97_PHYS_ADDR          0x10000000
+#define        USBH_PHYS_ADDR          0x10100000
+#define        USBD_PHYS_ADDR          0x10200000
+#define PCI_PHYS_ADDR          0x14005000
+#define        MAC0_PHYS_ADDR          0x11500000
+#define        MAC1_PHYS_ADDR          0x11510000
+#define        MACEN_PHYS_ADDR         0x11520000
+#define        MACDMA0_PHYS_ADDR       0x14004000
+#define        MACDMA1_PHYS_ADDR       0x14004200
+#define        I2S_PHYS_ADDR           0x11000000
+#define        UART0_PHYS_ADDR         0x11100000
+#define        UART3_PHYS_ADDR         0x11400000
+#define GPIO2_PHYS_ADDR                0x11700000
+#define        SYS_PHYS_ADDR           0x11900000
+#define PCI_MEM_PHYS_ADDR     0x400000000
+#define PCI_IO_PHYS_ADDR      0x500000000
+#define PCI_CONFIG0_PHYS_ADDR 0x600000000
+#define PCI_CONFIG1_PHYS_ADDR 0x680000000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#endif
+
+/********************************************************************/
+
+#ifdef CONFIG_SOC_AU1100
+#define        MEM_PHYS_ADDR           0x14000000
+#define        STATIC_MEM_PHYS_ADDR    0x14001000
+#define        DMA0_PHYS_ADDR          0x14002000
+#define        DMA1_PHYS_ADDR          0x14002100
+#define        DMA2_PHYS_ADDR          0x14002200
+#define        DMA3_PHYS_ADDR          0x14002300
+#define        DMA4_PHYS_ADDR          0x14002400
+#define        DMA5_PHYS_ADDR          0x14002500
+#define        DMA6_PHYS_ADDR          0x14002600
+#define        DMA7_PHYS_ADDR          0x14002700
+#define        IC0_PHYS_ADDR           0x10400000
+#define SD0_PHYS_ADDR          0x10600000
+#define SD1_PHYS_ADDR          0x10680000
+#define        IC1_PHYS_ADDR           0x11800000
+#define        AC97_PHYS_ADDR          0x10000000
+#define        USBH_PHYS_ADDR          0x10100000
+#define        USBD_PHYS_ADDR          0x10200000
+#define        IRDA_PHYS_ADDR          0x10300000
+#define        MAC0_PHYS_ADDR          0x10500000
+#define        MACEN_PHYS_ADDR         0x10520000
+#define        MACDMA0_PHYS_ADDR       0x14004000
+#define        MACDMA1_PHYS_ADDR       0x14004200
+#define        I2S_PHYS_ADDR           0x11000000
+#define        UART0_PHYS_ADDR         0x11100000
+#define        UART1_PHYS_ADDR         0x11200000
+#define        UART3_PHYS_ADDR         0x11400000
+#define        SSI0_PHYS_ADDR          0x11600000
+#define        SSI1_PHYS_ADDR          0x11680000
+#define GPIO2_PHYS_ADDR                0x11700000
+#define        SYS_PHYS_ADDR           0x11900000
+#define LCD_PHYS_ADDR          0x15000000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#endif
+
+/***********************************************************************/
+
+#ifdef CONFIG_SOC_AU1550
+#define        MEM_PHYS_ADDR           0x14000000
+#define        STATIC_MEM_PHYS_ADDR    0x14001000
+#define        IC0_PHYS_ADDR           0x10400000
+#define        IC1_PHYS_ADDR           0x11800000
+#define        USBH_PHYS_ADDR          0x14020000
+#define        USBD_PHYS_ADDR          0x10200000
+#define PCI_PHYS_ADDR          0x14005000
+#define        MAC0_PHYS_ADDR          0x10500000
+#define        MAC1_PHYS_ADDR          0x10510000
+#define        MACEN_PHYS_ADDR         0x10520000
+#define        MACDMA0_PHYS_ADDR       0x14004000
+#define        MACDMA1_PHYS_ADDR       0x14004200
+#define        UART0_PHYS_ADDR         0x11100000
+#define        UART1_PHYS_ADDR         0x11200000
+#define        UART3_PHYS_ADDR         0x11400000
+#define GPIO2_PHYS_ADDR                0x11700000
+#define        SYS_PHYS_ADDR           0x11900000
+#define        DDMA_PHYS_ADDR          0x14002000
+#define PE_PHYS_ADDR           0x14008000
+#define PSC0_PHYS_ADDR         0x11A00000
+#define PSC1_PHYS_ADDR         0x11B00000
+#define PSC2_PHYS_ADDR         0x10A00000
+#define PSC3_PHYS_ADDR         0x10B00000
+#define PCI_MEM_PHYS_ADDR     0x400000000
+#define PCI_IO_PHYS_ADDR      0x500000000
+#define PCI_CONFIG0_PHYS_ADDR 0x600000000
+#define PCI_CONFIG1_PHYS_ADDR 0x680000000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#endif
+
+/***********************************************************************/
+
+#ifdef CONFIG_SOC_AU1200
+#define        MEM_PHYS_ADDR           0x14000000
+#define        STATIC_MEM_PHYS_ADDR    0x14001000
+#define AES_PHYS_ADDR          0x10300000
+#define CIM_PHYS_ADDR          0x14004000
+#define        IC0_PHYS_ADDR           0x10400000
+#define        IC1_PHYS_ADDR           0x11800000
+#define USBM_PHYS_ADDR         0x14020000
+#define        USBH_PHYS_ADDR          0x14020100
+#define        UART0_PHYS_ADDR         0x11100000
+#define        UART1_PHYS_ADDR         0x11200000
+#define GPIO2_PHYS_ADDR                0x11700000
+#define        SYS_PHYS_ADDR           0x11900000
+#define        DDMA_PHYS_ADDR          0x14002000
+#define PSC0_PHYS_ADDR         0x11A00000
+#define PSC1_PHYS_ADDR         0x11B00000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#define SD0_PHYS_ADDR          0x10600000
+#define SD1_PHYS_ADDR          0x10680000
+#define LCD_PHYS_ADDR          0x15000000
+#define SWCNT_PHYS_ADDR                0x1110010C
+#define MAEFE_PHYS_ADDR                0x14012000
+#define MAEBE_PHYS_ADDR                0x14010000
+#endif
+
+
 /* Static Bus Controller */
 #define MEM_STCFG0                 0xB4001000
 #define MEM_STTIME0                0xB4001004
@@ -369,7 +697,7 @@
 #define AU1000_MAC0_ENABLE       0xB0520000
 #define AU1000_MAC1_ENABLE       0xB0520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1000
+#endif /* CONFIG_SOC_AU1000 */
 
 /* Au1500 */
 #ifdef CONFIG_SOC_AU1500
@@ -440,7 +768,7 @@
 #define AU1500_MAC0_ENABLE       0xB1520000
 #define AU1500_MAC1_ENABLE       0xB1520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1500
+#endif /* CONFIG_SOC_AU1500 */
 
 /* Au1100 */
 #ifdef CONFIG_SOC_AU1100
@@ -485,6 +813,22 @@
 #define AU1000_GPIO_13            45
 #define AU1000_GPIO_14            46
 #define AU1000_GPIO_15            47
+#define AU1000_GPIO_16            48
+#define AU1000_GPIO_17            49
+#define AU1000_GPIO_18            50
+#define AU1000_GPIO_19            51
+#define AU1000_GPIO_20            52
+#define AU1000_GPIO_21            53
+#define AU1000_GPIO_22            54
+#define AU1000_GPIO_23            55
+#define AU1000_GPIO_24            56
+#define AU1000_GPIO_25            57
+#define AU1000_GPIO_26            58
+#define AU1000_GPIO_27            59
+#define AU1000_GPIO_28            60
+#define AU1000_GPIO_29            61
+#define AU1000_GPIO_30            62
+#define AU1000_GPIO_31            63
 
 #define UART0_ADDR                0xB1100000
 #define UART1_ADDR                0xB1200000
@@ -496,7 +840,7 @@
 #define AU1100_ETH0_BASE         0xB0500000
 #define AU1100_MAC0_ENABLE       0xB0520000
 #define NUM_ETH_INTERFACES 1
-#endif // CONFIG_SOC_AU1100
+#endif /* CONFIG_SOC_AU1100 */
 
 #ifdef CONFIG_SOC_AU1550
 #define AU1550_UART0_INT          0
@@ -513,14 +857,14 @@
 #define AU1550_PSC1_INT           11
 #define AU1550_PSC2_INT           12
 #define AU1550_PSC3_INT           13
-#define AU1550_TOY_INT                   14
-#define AU1550_TOY_MATCH0_INT     15
-#define AU1550_TOY_MATCH1_INT     16
-#define AU1550_TOY_MATCH2_INT     17
-#define AU1550_RTC_INT            18
-#define AU1550_RTC_MATCH0_INT     19
-#define AU1550_RTC_MATCH1_INT     20
-#define AU1550_RTC_MATCH2_INT     21
+#define AU1000_TOY_INT                   14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
 #define AU1550_NAND_INT           23
 #define AU1550_USB_DEV_REQ_INT    24
 #define AU1550_USB_DEV_SUS_INT    25
@@ -575,7 +919,7 @@
 #define AU1550_MAC0_ENABLE       0xB0520000
 #define AU1550_MAC1_ENABLE       0xB0520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1550
+#endif /* CONFIG_SOC_AU1550 */
 
 #ifdef CONFIG_SOC_AU1200
 #define AU1200_UART0_INT          0
@@ -592,14 +936,14 @@
 #define AU1200_PSC1_INT           11
 #define AU1200_AES_INT            12
 #define AU1200_CAMERA_INT         13
-#define AU1200_TOY_INT                   14
-#define AU1200_TOY_MATCH0_INT     15
-#define AU1200_TOY_MATCH1_INT     16
-#define AU1200_TOY_MATCH2_INT     17
-#define AU1200_RTC_INT            18
-#define AU1200_RTC_MATCH0_INT     19
-#define AU1200_RTC_MATCH1_INT     20
-#define AU1200_RTC_MATCH2_INT     21
+#define AU1000_TOY_INT                   14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
 #define AU1200_NAND_INT           23
 #define AU1200_GPIO_204           24
 #define AU1200_GPIO_205           25
@@ -607,6 +951,7 @@
 #define AU1200_GPIO_207           27
 #define AU1200_GPIO_208_215       28 // Logical OR of 208:215
 #define AU1200_USB_INT            29
+#define AU1000_USB_HOST_INT              AU1200_USB_INT
 #define AU1200_LCD_INT            30
 #define AU1200_MAE_BOTH_INT       31
 #define AU1000_GPIO_0             32
@@ -645,21 +990,36 @@
 #define UART0_ADDR                0xB1100000
 #define UART1_ADDR                0xB1200000
 
-#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap
-#define USB_HOST_CONFIG           0xB4027ffc
+#define USB_UOC_BASE              0x14020020
+#define USB_UOC_LEN               0x20
+#define USB_OHCI_BASE             0x14020100
+#define USB_OHCI_LEN              0x100
+#define USB_EHCI_BASE             0x14020200
+#define USB_EHCI_LEN              0x100
+#define USB_UDC_BASE              0x14022000
+#define USB_UDC_LEN               0x2000
+#define USB_MSR_BASE                     0xB4020000
+#define USB_MSR_MCFG              4
+#define USBMSRMCFG_OMEMEN         0
+#define USBMSRMCFG_OBMEN          1
+#define USBMSRMCFG_EMEMEN         2
+#define USBMSRMCFG_EBMEN          3
+#define USBMSRMCFG_DMEMEN         4
+#define USBMSRMCFG_DBMEN          5
+#define USBMSRMCFG_GMEMEN         6
+#define USBMSRMCFG_OHCCLKEN       16
+#define USBMSRMCFG_EHCCLKEN       17
+#define USBMSRMCFG_UDCCLKEN       18
+#define USBMSRMCFG_PHYPLLEN       19
+#define USBMSRMCFG_RDCOMB         30
+#define USBMSRMCFG_PFEN           31
 
-// these are here for prototyping on au1550 (do not exist on au1200)
-#define AU1200_ETH0_BASE      0xB0500000
-#define AU1200_ETH1_BASE      0xB0510000
-#define AU1200_MAC0_ENABLE       0xB0520000
-#define AU1200_MAC1_ENABLE       0xB0520004
-#define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1200
+#endif /* CONFIG_SOC_AU1200 */
 
 #define AU1000_LAST_INTC0_INT     31
+#define AU1000_LAST_INTC1_INT     63
 #define AU1000_MAX_INTR           63
 
-
 /* Programmable Counters 0 and 1 */
 #define SYS_BASE                   0xB1900000
 #define SYS_COUNTER_CNTRL          (SYS_BASE + 0x14)
@@ -730,6 +1090,8 @@
   #define I2S_CONTROL_D         (1<<1)
   #define I2S_CONTROL_CE        (1<<0)
 
+#ifndef CONFIG_SOC_AU1200
+
 /* USB Host Controller */
 #define USB_OHCI_LEN              0x00100000
 
@@ -775,6 +1137,8 @@
   #define USBDEV_ENABLE (1<<1)
   #define USBDEV_CE     (1<<0)
 
+#endif /* !CONFIG_SOC_AU1200 */
+
 /* Ethernet Controllers  */
 
 /* 4 byte offsets from AU1000_ETH_BASE */
@@ -1173,6 +1537,37 @@
   #define SYS_PF_PSC1_S1               (1 << 1)
   #define SYS_PF_MUST_BE_SET           ((1 << 5) | (1 << 2))
 
+/* Au1200 Only */
+#ifdef CONFIG_SOC_AU1200
+#define SYS_PINFUNC_DMA                (1<<31)
+#define SYS_PINFUNC_S0A                (1<<30)
+#define SYS_PINFUNC_S1A                (1<<29)
+#define SYS_PINFUNC_LP0                (1<<28)
+#define SYS_PINFUNC_LP1                (1<<27)
+#define SYS_PINFUNC_LD16       (1<<26)
+#define SYS_PINFUNC_LD8                (1<<25)
+#define SYS_PINFUNC_LD1                (1<<24)
+#define SYS_PINFUNC_LD0                (1<<23)
+#define SYS_PINFUNC_P1A                (3<<21)
+#define SYS_PINFUNC_P1B                (1<<20)
+#define SYS_PINFUNC_FS3                (1<<19)
+#define SYS_PINFUNC_P0A                (3<<17)
+#define SYS_PINFUNC_CS         (1<<16)
+#define SYS_PINFUNC_CIM                (1<<15)
+#define SYS_PINFUNC_P1C                (1<<14)
+#define SYS_PINFUNC_U1T                (1<<12)
+#define SYS_PINFUNC_U1R                (1<<11)
+#define SYS_PINFUNC_EX1                (1<<10)
+#define SYS_PINFUNC_EX0                (1<<9)
+#define SYS_PINFUNC_U0R                (1<<8)
+#define SYS_PINFUNC_MC         (1<<7)
+#define SYS_PINFUNC_S0B                (1<<6)
+#define SYS_PINFUNC_S0C                (1<<5)
+#define SYS_PINFUNC_P0B                (1<<4)
+#define SYS_PINFUNC_U0T                (1<<3)
+#define SYS_PINFUNC_S1B                (1<<2)
+#endif
+
 #define SYS_TRIOUTRD              0xB1900100
 #define SYS_TRIOUTCLR             0xB1900100
 #define SYS_OUTPUTRD              0xB1900108
@@ -1300,7 +1695,6 @@
 #define SD1_XMIT_FIFO  0xB0680000
 #define SD1_RECV_FIFO  0xB0680004
 
-
 #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
 /* Au1500 PCI Controller */
 #define Au1500_CFG_BASE           0xB4005000 // virtual, kseg0 addr
@@ -1363,36 +1757,77 @@
                      _ctl_; })
 
 
-#else /* Au1000 and Au1100 */
+#else /* Au1000 and Au1100 and Au1200 */
 
 /* don't allow any legacy ports probing */
-#define IOPORT_RESOURCE_START 0x10000000;
+#define IOPORT_RESOURCE_START 0x10000000
 #define IOPORT_RESOURCE_END   0xffffffff
 #define IOMEM_RESOURCE_START  0x10000000
 #define IOMEM_RESOURCE_END    0xffffffff
 
-#ifdef CONFIG_MIPS_PB1000
-#define PCI_IO_START      0x10000000
-#define PCI_IO_END        0x1000ffff
-#define PCI_MEM_START     0x18000000
-#define PCI_MEM_END       0x18ffffff
-#define PCI_FIRST_DEVFN   0
-#define PCI_LAST_DEVFN    1
-#else
-/* no PCI bus controller */
 #define PCI_IO_START    0
 #define PCI_IO_END      0
 #define PCI_MEM_START   0
 #define PCI_MEM_END     0 
 #define PCI_FIRST_DEVFN 0
 #define PCI_LAST_DEVFN  0
-#endif
 
 #endif
 
+#ifndef _LANGUAGE_ASSEMBLY
+typedef volatile struct
+{
+       /* 0x0000 */ u32 toytrim;
+       /* 0x0004 */ u32 toywrite;
+       /* 0x0008 */ u32 toymatch0;
+       /* 0x000C */ u32 toymatch1;
+       /* 0x0010 */ u32 toymatch2;
+       /* 0x0014 */ u32 cntrctrl;
+       /* 0x0018 */ u32 scratch0;
+       /* 0x001C */ u32 scratch1;
+       /* 0x0020 */ u32 freqctrl0;
+       /* 0x0024 */ u32 freqctrl1;
+       /* 0x0028 */ u32 clksrc;
+       /* 0x002C */ u32 pinfunc;
+       /* 0x0030 */ u32 reserved0;
+       /* 0x0034 */ u32 wakemsk;
+       /* 0x0038 */ u32 endian;
+       /* 0x003C */ u32 powerctrl;
+       /* 0x0040 */ u32 toyread;
+       /* 0x0044 */ u32 rtctrim;
+       /* 0x0048 */ u32 rtcwrite;
+       /* 0x004C */ u32 rtcmatch0;
+       /* 0x0050 */ u32 rtcmatch1;
+       /* 0x0054 */ u32 rtcmatch2;
+       /* 0x0058 */ u32 rtcread;
+       /* 0x005C */ u32 wakesrc;
+       /* 0x0060 */ u32 cpupll;
+       /* 0x0064 */ u32 auxpll;
+       /* 0x0068 */ u32 reserved1;
+       /* 0x006C */ u32 reserved2;
+       /* 0x0070 */ u32 reserved3;
+       /* 0x0074 */ u32 reserved4;
+       /* 0x0078 */ u32 slppwr;
+       /* 0x007C */ u32 sleep;
+       /* 0x0080 */ u32 reserved5[32];
+       /* 0x0100 */ u32 trioutrd;
+#define trioutclr trioutrd
+       /* 0x0104 */ u32 reserved6;
+       /* 0x0108 */ u32 outputrd;
+#define outputset outputrd
+       /* 0x010C */ u32 outputclr;
+       /* 0x0110 */ u32 pinstaterd;
+#define pininputen pinstaterd
+
+} AU1X00_SYS;
+
+static AU1X00_SYS* const sys  = (AU1X00_SYS *)SYS_BASE;
+
+#endif
 /* Processor information base on prid.
  * Copied from PowerPC.
  */
+#ifndef _LANGUAGE_ASSEMBLY
 struct cpu_spec {
        /* CPU is matched via (PRID & prid_mask) == prid_value */
        unsigned int    prid_mask;
@@ -1406,3 +1841,6 @@
 extern struct cpu_spec         cpu_specs[];
 extern struct cpu_spec         *cur_cpu_spec[];
 #endif
+
+#endif
+
diff -urN linux/include/asm-mips/mach-au1x00/au1xxx_dbdma.h 
linux/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
--- linux/include/asm-mips/mach-au1x00/au1xxx_dbdma.h   2005/01/15 01:31:03     
1.2
+++ linux/include/asm-mips/mach-au1x00/au1xxx_dbdma.h   2005/03/01 06:33:19     
1.3
@@ -45,7 +45,7 @@
 #define DDMA_GLOBAL_BASE       0xb4003000
 #define DDMA_CHANNEL_BASE      0xb4002000
 
-typedef struct dbdma_global {
+typedef volatile struct dbdma_global {
        u32     ddma_config;
        u32     ddma_intstat;
        u32     ddma_throttle;
@@ -62,7 +62,7 @@
 
 /* The structure of a DMA Channel.
 */
-typedef struct au1xxx_dma_channel {
+typedef volatile struct au1xxx_dma_channel {
        u32     ddma_cfg;       /* See below */
        u32     ddma_desptr;    /* 32-byte aligned pointer to descriptor */
        u32     ddma_statptr;   /* word aligned pointer to status word */
@@ -98,7 +98,7 @@
 /* "Standard" DDMA Descriptor.
  * Must be 32-byte aligned.
  */
-typedef struct au1xxx_ddma_desc {
+typedef volatile struct au1xxx_ddma_desc {
        u32     dscr_cmd0;              /* See below */
        u32     dscr_cmd1;              /* See below */
        u32     dscr_source0;           /* source phys address */
@@ -107,6 +107,12 @@
        u32     dscr_dest1;             /* See below */
        u32     dscr_stat;              /* completion status */
        u32     dscr_nxtptr;            /* Next descriptor pointer (mostly) */
+       /* First 32bytes are HW specific!!!
+          Lets have some SW data following.. make sure its 32bytes
+        */
+       u32     sw_status;
+       u32     sw_context;
+       u32     sw_reserved[6];
 } au1x_ddma_desc_t;
 
 #define DSCR_CMD0_V            (1 << 31)       /* Descriptor valid */
@@ -125,8 +131,11 @@
 #define DSCR_CMD0_CV           (0x1 << 2)      /* Clear Valid when done */
 #define DSCR_CMD0_ST_MASK      (0x3 << 0)      /* Status instruction */
 
+#define SW_STATUS_INUSE                (1<<0)
+
 /* Command 0 device IDs.
 */
+#ifdef CONFIG_SOC_AU1550
 #define DSCR_CMD0_UART0_TX     0
 #define DSCR_CMD0_UART0_RX     1
 #define DSCR_CMD0_UART3_TX     2
@@ -155,9 +164,45 @@
 #define DSCR_CMD0_MAC0_TX      25
 #define DSCR_CMD0_MAC1_RX      26
 #define DSCR_CMD0_MAC1_TX      27
+#endif /* CONFIG_SOC_AU1550 */
+
+#ifdef CONFIG_SOC_AU1200
+#define DSCR_CMD0_UART0_TX     0
+#define DSCR_CMD0_UART0_RX     1
+#define DSCR_CMD0_UART1_TX     2
+#define DSCR_CMD0_UART1_RX     3
+#define DSCR_CMD0_DMA_REQ0     4
+#define DSCR_CMD0_DMA_REQ1     5
+#define DSCR_CMD0_MAE_BE       6
+#define DSCR_CMD0_MAE_FE       7
+#define DSCR_CMD0_SDMS_TX0     8
+#define DSCR_CMD0_SDMS_RX0     9
+#define DSCR_CMD0_SDMS_TX1     10
+#define DSCR_CMD0_SDMS_RX1     11
+#define DSCR_CMD0_AES_TX       13
+#define DSCR_CMD0_AES_RX       12
+#define DSCR_CMD0_PSC0_TX      14
+#define DSCR_CMD0_PSC0_RX      15
+#define DSCR_CMD0_PSC1_TX      16
+#define DSCR_CMD0_PSC1_RX      17
+#define DSCR_CMD0_CIM_RXA      18
+#define DSCR_CMD0_CIM_RXB      19
+#define DSCR_CMD0_CIM_RXC      20
+#define DSCR_CMD0_MAE_BOTH     21
+#define DSCR_CMD0_LCD          22
+#define DSCR_CMD0_NAND_FLASH   23
+#define DSCR_CMD0_PSC0_SYNC    24
+#define DSCR_CMD0_PSC1_SYNC    25
+#define DSCR_CMD0_CIM_SYNC     26
+#endif /* CONFIG_SOC_AU1200 */
+
 #define DSCR_CMD0_THROTTLE     30
 #define DSCR_CMD0_ALWAYS       31
 #define DSCR_NDEV_IDS          32
+/* THis macro is used to find/create custom device types */
+#define DSCR_DEV2CUSTOM_ID(x,d)        
(((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
+#define DSCR_CUSTOM2DEV_ID(x)  ((x)&0xFF)
+
 
 #define DSCR_CMD0_SID(x)       (((x) & 0x1f) << 25)
 #define DSCR_CMD0_DID(x)       (((x) & 0x1f) << 20)
@@ -246,6 +291,43 @@
 */
 #define NUM_DBDMA_CHANS        16
 
+/*
+ * Ddma API definitions
+ * FIXME: may not fit to this header file
+ */
+typedef struct dbdma_device_table {
+       u32             dev_id;
+       u32             dev_flags;
+       u32             dev_tsize;
+       u32             dev_devwidth;
+       u32             dev_physaddr;           /* If FIFO */
+       u32             dev_intlevel;
+       u32             dev_intpolarity;
+} dbdev_tab_t;
+
+
+typedef struct dbdma_chan_config {
+       spinlock_t      lock;
+
+       u32                     chan_flags;
+       u32                     chan_index;
+       dbdev_tab_t             *chan_src;
+       dbdev_tab_t             *chan_dest;
+       au1x_dma_chan_t         *chan_ptr;
+       au1x_ddma_desc_t        *chan_desc_base;
+       au1x_ddma_desc_t        *get_ptr, *put_ptr, *cur_ptr;
+       void                    *chan_callparam;
+       void (*chan_callback)(int, void *, struct pt_regs *);
+} chan_tab_t;
+
+#define DEV_FLAGS_INUSE                (1 << 0)
+#define DEV_FLAGS_ANYUSE       (1 << 1)
+#define DEV_FLAGS_OUT          (1 << 2)
+#define DEV_FLAGS_IN           (1 << 3)
+#define DEV_FLAGS_BURSTABLE (1 << 4)
+#define DEV_FLAGS_SYNC         (1 << 5)
+/* end Ddma API definitions */
+
 /* External functions for drivers to use.
 */
 /* Use this to allocate a dbdma channel.  The device ids are one of the
@@ -258,18 +340,6 @@
 
 #define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
 
-/* ACK!  These should be in a board specific description file.
-*/
-#ifdef CONFIG_MIPS_PB1550
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#endif
-#ifdef CONFIG_MIPS_DB1550
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#endif
-
-
 /* Set the device width of a in/out fifo.
 */
 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
@@ -280,8 +350,8 @@
 
 /* Put buffers on source/destination descriptors.
 */
-u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes);
-u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes);
+u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
+u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
 
 /* Get a buffer from the destination descriptor.
 */
@@ -295,5 +365,25 @@
 void au1xxx_dbdma_chan_free(u32 chanid);
 void au1xxx_dbdma_dump(u32 chanid);
 
+u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
+
+u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
+
+/*
+       Some compatibilty macros --
+               Needed to make changes to API without breaking existing drivers
+*/
+#define        
au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, 
nbytes, DDMA_FLAGS_IE)
+#define        au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) 
_au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
+
+#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) 
_au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
+#define        au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) 
_au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
+
+/*
+ *     Flags for the put_source/put_dest functions.
+ */
+#define DDMA_FLAGS_IE  (1<<0)
+#define DDMA_FLAGS_NOIE (1<<1)
+
 #endif /* _LANGUAGE_ASSEMBLY */
 #endif /* _AU1000_DBDMA_H_ */
diff -urN linux/include/asm-mips/mach-db1x00/db1200.h 
linux/include/asm-mips/mach-db1x00/db1200.h
--- linux/include/asm-mips/mach-db1x00/db1200.h 1970/01/01 00:00:00
+++ linux/include/asm-mips/mach-db1x00/db1200.h Tue Mar  1 06:33:19 2005        
1.1
@@ -0,0 +1,215 @@
+/*
+ * AMD Alchemy DB1200 Referrence Board
+ * Board Registers defines.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_DB1200_H
+#define __ASM_DB1200_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+// This is defined in au1000.h with bogus value
+#undef AU1X00_EXTERNAL_INT
+
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
+
+/* SPI and SMB are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define SPI_PSC_BASE        PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE      PSC0_BASE_ADDR
+/* AC97 and I2S are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define AC97_PSC_BASE       PSC1_BASE_ADDR
+#define I2S_PSC_BASE           PSC1_BASE_ADDR
+
+#define BCSR_KSEG1_ADDR 0xB9800000
+
+typedef volatile struct
+{
+       /*00*/  u16 whoami;
+               u16 reserved0;
+       /*04*/  u16 status;
+               u16 reserved1;
+       /*08*/  u16 switches;
+               u16 reserved2;
+       /*0C*/  u16 resets;
+               u16 reserved3;
+
+       /*10*/  u16 pcmcia;
+               u16 reserved4;
+       /*14*/  u16 board;
+               u16 reserved5;
+       /*18*/  u16 disk_leds;
+               u16 reserved6;
+       /*1C*/  u16 system;
+               u16 reserved7;
+
+       /*20*/  u16 intclr;
+               u16 reserved8;
+       /*24*/  u16 intset;
+               u16 reserved9;
+       /*28*/  u16 intclr_mask;
+               u16 reserved10;
+       /*2C*/  u16 intset_mask;
+               u16 reserved11;
+
+       /*30*/  u16 sig_status;
+               u16 reserved12;
+       /*34*/  u16 int_status;
+               u16 reserved13;
+       /*38*/  u16 reserved14;
+               u16 reserved15;
+       /*3C*/  u16 reserved16;
+               u16 reserved17;
+
+} BCSR;
+
+static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+
+/*
+ * Register bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID       0x000F
+#define BCSR_WHOAMI_CPLD       0x00F0
+#define BCSR_WHOAMI_BOARD      0x0F00
+
+#define BCSR_STATUS_PCMCIA0VS  0x0003
+#define BCSR_STATUS_PCMCIA1VS  0x000C
+#define BCSR_STATUS_SWAPBOOT   0x0040
+#define BCSR_STATUS_FLASHBUSY  0x0100
+#define BCSR_STATUS_IDECBLID   0x0200
+#define BCSR_STATUS_SD0WP              0x0400
+#define BCSR_STATUS_U0RXD              0x1000
+#define BCSR_STATUS_U1RXD              0x2000
+
+#define BCSR_SWITCHES_OCTAL    0x00FF
+#define BCSR_SWITCHES_DIP_1    0x0080
+#define BCSR_SWITCHES_DIP_2    0x0040
+#define BCSR_SWITCHES_DIP_3    0x0020
+#define BCSR_SWITCHES_DIP_4    0x0010
+#define BCSR_SWITCHES_DIP_5    0x0008
+#define BCSR_SWITCHES_DIP_6    0x0004
+#define BCSR_SWITCHES_DIP_7    0x0002
+#define BCSR_SWITCHES_DIP_8    0x0001
+#define BCSR_SWITCHES_ROTARY   0x0F00
+
+#define BCSR_RESETS_ETH                0x0001
+#define BCSR_RESETS_CAMERA     0x0002
+#define BCSR_RESETS_DC         0x0004
+#define BCSR_RESETS_IDE                0x0008
+#define BCSR_RESETS_TV         0x0010
+/* not resets but in the same register */
+#define BCSR_RESETS_PWMR1mUX 0x0800
+#define BCSR_RESETS_PCS0MUX    0x1000
+#define BCSR_RESETS_PCS1MUX    0x2000
+#define BCSR_RESETS_SPISEL     0x4000
+
+#define BCSR_PCMCIA_PC0VPP     0x0003
+#define BCSR_PCMCIA_PC0VCC     0x000C
+#define BCSR_PCMCIA_PC0DRVEN   0x0010
+#define BCSR_PCMCIA_PC0RST     0x0080
+#define BCSR_PCMCIA_PC1VPP     0x0300
+#define BCSR_PCMCIA_PC1VCC     0x0C00
+#define BCSR_PCMCIA_PC1DRVEN   0x1000
+#define BCSR_PCMCIA_PC1RST     0x8000
+
+#define BCSR_BOARD_LCDVEE      0x0001
+#define BCSR_BOARD_LCDVDD      0x0002
+#define BCSR_BOARD_LCDBL       0x0004
+#define BCSR_BOARD_CAMSNAP     0x0010
+#define BCSR_BOARD_CAMPWR      0x0020
+#define BCSR_BOARD_SD0PWR      0x0040
+
+#define BCSR_LEDS_DECIMALS     0x0003
+#define BCSR_LEDS_LED0         0x0100
+#define BCSR_LEDS_LED1         0x0200
+#define BCSR_LEDS_LED2         0x0400
+#define BCSR_LEDS_LED3         0x0800
+
+#define BCSR_SYSTEM_POWEROFF   0x4000
+#define BCSR_SYSTEM_RESET      0x8000
+
+/* Bit positions for the different interrupt sources */
+#define BCSR_INT_IDE           0x0001
+#define BCSR_INT_ETH           0x0002
+#define BCSR_INT_PC0           0x0004
+#define BCSR_INT_PC0STSCHG     0x0008
+#define BCSR_INT_PC1           0x0010
+#define BCSR_INT_PC1STSCHG     0x0020
+#define BCSR_INT_DC                    0x0040
+#define BCSR_INT_FLASHBUSY     0x0080
+#define BCSR_INT_PC0INSERT     0x0100
+#define BCSR_INT_PC0EJECT      0x0200
+#define BCSR_INT_PC1INSERT     0x0400
+#define BCSR_INT_PC1EJECT      0x0800
+#define BCSR_INT_SD0INSERT     0x1000
+#define BCSR_INT_SD0EJECT      0x2000
+
+#define AU1XXX_SMC91111_PHYS_ADDR      (0x19000300)
+#define AU1XXX_SMC91111_IRQ                    DB1200_ETH_INT
+
+#define AU1XXX_ATA_PHYS_ADDR           (0x18800000)
+#define AU1XXX_ATA_PHYS_LEN                    (0x100)
+#define AU1XXX_ATA_REG_OFFSET  (5)
+#define AU1XXX_ATA_INT                 DB1200_IDE_INT
+#define AU1XXX_ATA_DDMA_REQ            DSCR_CMD0_DMA_REQ1;
+#define AU1XXX_ATA_RQSIZE              128
+
+#define NAND_PHYS_ADDR   0x20000000
+
+/*
+ *     External Interrupts for Pb1200 as of 8/6/2004.
+ *   Bit positions in the CPLD registers can be calculated by taking
+ *   the interrupt define and subtracting the DB1200_INT_BEGIN value.
+ *    *example: IDE bis pos is  = 64 - 64
+                ETH bit pos is  = 65 - 64
+ */
+#define DB1200_INT_BEGIN               (AU1000_LAST_INTC1_INT + 1)
+#define DB1200_IDE_INT                 (DB1200_INT_BEGIN + 0)
+#define DB1200_ETH_INT                 (DB1200_INT_BEGIN + 1)
+#define DB1200_PC0_INT                 (DB1200_INT_BEGIN + 2)
+#define DB1200_PC0_STSCHG_INT  (DB1200_INT_BEGIN + 3)
+#define DB1200_PC1_INT                 (DB1200_INT_BEGIN + 4)
+#define DB1200_PC1_STSCHG_INT  (DB1200_INT_BEGIN + 5)
+#define DB1200_DC_INT                  (DB1200_INT_BEGIN + 6)
+#define DB1200_FLASHBUSY_INT   (DB1200_INT_BEGIN + 7)
+#define DB1200_PC0_INSERT_INT  (DB1200_INT_BEGIN + 8)
+#define DB1200_PC0_EJECT_INT   (DB1200_INT_BEGIN + 9)
+#define DB1200_PC1_INSERT_INT  (DB1200_INT_BEGIN + 10)
+#define DB1200_PC1_EJECT_INT   (DB1200_INT_BEGIN + 11)
+#define DB1200_SD0_INSERT_INT  (DB1200_INT_BEGIN + 12)
+#define DB1200_SD0_EJECT_INT   (DB1200_INT_BEGIN + 13)
+
+#define DB1200_INT_END                 (DB1200_INT_BEGIN + 15)
+
+/* For drivers/pcmcia/au1000_db1x00.c */
+#define BOARD_PC0_INT DB1200_PC0_INT
+#define BOARD_PC1_INT DB1200_PC1_INT
+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
+
+#endif /* __ASM_DB1200_H */
+
diff -urN linux/include/asm-mips/mach-pb1x00/pb1200.h 
linux/include/asm-mips/mach-pb1x00/pb1200.h
--- linux/include/asm-mips/mach-pb1x00/pb1200.h 1970/01/01 00:00:00
+++ linux/include/asm-mips/mach-pb1x00/pb1200.h Tue Mar  1 06:33:19 2005        
1.1
@@ -0,0 +1,245 @@
+/*
+ * AMD Alchemy PB1200 Referrence Board
+ * Board Registers defines.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1200_H
+#define __ASM_PB1200_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+// This is defined in au1000.h with bogus value
+#undef AU1X00_EXTERNAL_INT
+
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
+
+/* SPI and SMB are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define SPI_PSC_BASE        PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE      PSC0_BASE_ADDR
+/* AC97 and I2S are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define AC97_PSC_BASE       PSC1_BASE_ADDR
+#define I2S_PSC_BASE           PSC1_BASE_ADDR
+
+#define BCSR_KSEG1_ADDR 0xAD800000
+
+typedef volatile struct
+{
+       /*00*/  u16 whoami;
+               u16 reserved0;
+       /*04*/  u16 status;
+               u16 reserved1;
+       /*08*/  u16 switches;
+               u16 reserved2;
+       /*0C*/  u16 resets;
+               u16 reserved3;
+
+       /*10*/  u16 pcmcia;
+               u16 reserved4;
+       /*14*/  u16 board;
+               u16 reserved5;
+       /*18*/  u16 disk_leds;
+               u16 reserved6;
+       /*1C*/  u16 system;
+               u16 reserved7;
+
+       /*20*/  u16 intclr;
+               u16 reserved8;
+       /*24*/  u16 intset;
+               u16 reserved9;
+       /*28*/  u16 intclr_mask;
+               u16 reserved10;
+       /*2C*/  u16 intset_mask;
+               u16 reserved11;
+
+       /*30*/  u16 sig_status;
+               u16 reserved12;
+       /*34*/  u16 int_status;
+               u16 reserved13;
+       /*38*/  u16 reserved14;
+               u16 reserved15;
+       /*3C*/  u16 reserved16;
+               u16 reserved17;
+
+} BCSR;
+
+static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+
+/*
+ * Register bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID       0x000F
+#define BCSR_WHOAMI_CPLD       0x00F0
+#define BCSR_WHOAMI_BOARD      0x0F00
+
+#define BCSR_STATUS_PCMCIA0VS  0x0003
+#define BCSR_STATUS_PCMCIA1VS  0x000C
+#define BCSR_STATUS_SWAPBOOT   0x0040
+#define BCSR_STATUS_FLASHBUSY  0x0100
+#define BCSR_STATUS_IDECBLID   0x0200
+#define BCSR_STATUS_SD0WP              0x0400
+#define BCSR_STATUS_SD1WP              0x0800
+#define BCSR_STATUS_U0RXD              0x1000
+#define BCSR_STATUS_U1RXD              0x2000
+
+#define BCSR_SWITCHES_OCTAL    0x00FF
+#define BCSR_SWITCHES_DIP_1    0x0080
+#define BCSR_SWITCHES_DIP_2    0x0040
+#define BCSR_SWITCHES_DIP_3    0x0020
+#define BCSR_SWITCHES_DIP_4    0x0010
+#define BCSR_SWITCHES_DIP_5    0x0008
+#define BCSR_SWITCHES_DIP_6    0x0004
+#define BCSR_SWITCHES_DIP_7    0x0002
+#define BCSR_SWITCHES_DIP_8    0x0001
+#define BCSR_SWITCHES_ROTARY   0x0F00
+
+#define BCSR_RESETS_ETH                0x0001
+#define BCSR_RESETS_CAMERA     0x0002
+#define BCSR_RESETS_DC         0x0004
+#define BCSR_RESETS_IDE                0x0008
+/* not resets but in the same register */
+#define BCSR_RESETS_WSCFSM  0x0800
+#define BCSR_RESETS_PCS0MUX    0x1000
+#define BCSR_RESETS_PCS1MUX    0x2000
+#define BCSR_RESETS_SPISEL     0x4000
+#define BCSR_RESETS_SD1MUX  0x8000
+
+#define BCSR_PCMCIA_PC0VPP     0x0003
+#define BCSR_PCMCIA_PC0VCC     0x000C
+#define BCSR_PCMCIA_PC0DRVEN   0x0010
+#define BCSR_PCMCIA_PC0RST     0x0080
+#define BCSR_PCMCIA_PC1VPP     0x0300
+#define BCSR_PCMCIA_PC1VCC     0x0C00
+#define BCSR_PCMCIA_PC1DRVEN   0x1000
+#define BCSR_PCMCIA_PC1RST     0x8000
+
+#define BCSR_BOARD_LCDVEE      0x0001
+#define BCSR_BOARD_LCDVDD      0x0002
+#define BCSR_BOARD_LCDBL       0x0004
+#define BCSR_BOARD_CAMSNAP     0x0010
+#define BCSR_BOARD_CAMPWR      0x0020
+#define BCSR_BOARD_SD0PWR      0x0040
+#define BCSR_BOARD_SD1PWR      0x0080
+
+#define BCSR_LEDS_DECIMALS     0x00FF
+#define BCSR_LEDS_LED0         0x0100
+#define BCSR_LEDS_LED1         0x0200
+#define BCSR_LEDS_LED2         0x0400
+#define BCSR_LEDS_LED3         0x0800
+
+#define BCSR_SYSTEM_VDDI       0x001F
+#define BCSR_SYSTEM_POWEROFF   0x4000
+#define BCSR_SYSTEM_RESET      0x8000
+
+/* Bit positions for the different interrupt sources */
+#define BCSR_INT_IDE           0x0001
+#define BCSR_INT_ETH           0x0002
+#define BCSR_INT_PC0           0x0004
+#define BCSR_INT_PC0STSCHG     0x0008
+#define BCSR_INT_PC1           0x0010
+#define BCSR_INT_PC1STSCHG     0x0020
+#define BCSR_INT_DC                    0x0040
+#define BCSR_INT_FLASHBUSY     0x0080
+#define BCSR_INT_PC0INSERT     0x0100
+#define BCSR_INT_PC0EJECT      0x0200
+#define BCSR_INT_PC1INSERT     0x0400
+#define BCSR_INT_PC1EJECT      0x0800
+#define BCSR_INT_SD0INSERT     0x1000
+#define BCSR_INT_SD0EJECT      0x2000
+#define BCSR_INT_SD1INSERT     0x4000
+#define BCSR_INT_SD1EJECT      0x8000
+
+#define AU1XXX_SMC91111_PHYS_ADDR      (0x0D000300)
+#define AU1XXX_SMC91111_IRQ                    PB1200_ETH_INT
+
+#define AU1XXX_ATA_PHYS_ADDR           (0x0C800000)
+#define AU1XXX_ATA_PHYS_LEN                    (0x100)
+#define AU1XXX_ATA_REG_OFFSET  (5)
+#define AU1XXX_ATA_INT                 PB1200_IDE_INT
+#define AU1XXX_ATA_DDMA_REQ            DSCR_CMD0_DMA_REQ1;
+#define AU1XXX_ATA_RQSIZE              128
+
+#define NAND_PHYS_ADDR   0x1C000000
+
+/* Timing values as described in databook, * ns value stripped of
+ * lower 2 bits.
+ * These defines are here rather than an SOC1200 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H                       (18 >> 2)
+#define NAND_T_PUL                     (30 >> 2)
+#define NAND_T_SU                      (30 >> 2)
+#define NAND_T_WH                      (30 >> 2)
+
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT         0
+#define NAND_T_PUL_SHIFT       4
+#define NAND_T_SU_SHIFT                8
+#define NAND_T_WH_SHIFT                12
+
+#define NAND_TIMING    ((NAND_T_H   & 0xF)     << NAND_T_H_SHIFT)   | \
+                       ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
+                       ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
+                       ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
+
+
+/*
+ *     External Interrupts for Pb1200 as of 8/6/2004.
+ *   Bit positions in the CPLD registers can be calculated by taking
+ *   the interrupt define and subtracting the PB1200_INT_BEGIN value.
+ *    *example: IDE bis pos is  = 64 - 64
+                ETH bit pos is  = 65 - 64
+ */
+#define PB1200_INT_BEGIN               (AU1000_LAST_INTC1_INT + 1)
+#define PB1200_IDE_INT                 (PB1200_INT_BEGIN + 0)
+#define PB1200_ETH_INT                 (PB1200_INT_BEGIN + 1)
+#define PB1200_PC0_INT                 (PB1200_INT_BEGIN + 2)
+#define PB1200_PC0_STSCHG_INT  (PB1200_INT_BEGIN + 3)
+#define PB1200_PC1_INT                 (PB1200_INT_BEGIN + 4)
+#define PB1200_PC1_STSCHG_INT  (PB1200_INT_BEGIN + 5)
+#define PB1200_DC_INT                  (PB1200_INT_BEGIN + 6)
+#define PB1200_FLASHBUSY_INT   (PB1200_INT_BEGIN + 7)
+#define PB1200_PC0_INSERT_INT  (PB1200_INT_BEGIN + 8)
+#define PB1200_PC0_EJECT_INT   (PB1200_INT_BEGIN + 9)
+#define PB1200_PC1_INSERT_INT  (PB1200_INT_BEGIN + 10)
+#define PB1200_PC1_EJECT_INT   (PB1200_INT_BEGIN + 11)
+#define PB1200_SD0_INSERT_INT  (PB1200_INT_BEGIN + 12)
+#define PB1200_SD0_EJECT_INT   (PB1200_INT_BEGIN + 13)
+#define PB1200_SD1_INSERT_INT  (PB1200_INT_BEGIN + 14)
+#define PB1200_SD1_EJECT_INT   (PB1200_INT_BEGIN + 15)
+
+#define PB1200_INT_END                 (PB1200_INT_BEGIN + 15)
+
+/* For drivers/pcmcia/au1000_db1x00.c */
+#define BOARD_PC0_INT PB1200_PC0_INT
+#define BOARD_PC1_INT PB1200_PC1_INT
+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
+
+#endif /* __ASM_PB1200_H */
+

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