| To: | linux-cvs-patches@linux-mips.org |
|---|---|
| Subject: | CVS Update@linux-mips.org: linux |
| From: | ths@linux-mips.org |
| Date: | Sat, 19 Feb 2005 13:32:08 +0000 |
| Reply-to: | linux-mips@linux-mips.org |
| Sender: | linux-cvs-patches-bounce@linux-mips.org |
CVSROOT: /home/cvs
Module name: linux
Changes by: ths@ftp.linux-mips.org 05/02/19 13:32:02
Modified files:
arch/mips/mm : c-r4k.c
Log message:
Use intermediate variable.
diff -urN linux/arch/mips/mm/c-r4k.c linux/arch/mips/mm/c-r4k.c
--- linux/arch/mips/mm/c-r4k.c 2005/02/10 13:54:37 1.103
+++ linux/arch/mips/mm/c-r4k.c 2005/02/19 13:32:02 1.104
@@ -380,7 +380,7 @@
* If ownes no valid ASID yet, cannot possibly have gotten
* this page into the cache.
*/
- if (cpu_context(smp_processor_id(), vma->vm_mm) == 0)
+ if (cpu_context(smp_processor_id(), mm) == 0)
return;
page &= PAGE_MASK;
@@ -428,8 +428,8 @@
if (cpu_has_vtag_icache) {
int cpu = smp_processor_id();
- if (cpu_context(cpu, vma->vm_mm) != 0)
- drop_mmu_context(vma->vm_mm, cpu);
+ if (cpu_context(cpu, mm) != 0)
+ drop_mmu_context(mm, cpu);
} else
r4k_blast_icache_page_indexed(page);
}
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