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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: macro@linux-mips.org
Date: Thu, 03 Feb 2005 23:06:35 +0000
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     macro@ftp.linux-mips.org        05/02/03 23:06:29

Modified files:
        arch/mips/kernel: irq_cpu.c 

Log message:
        Mask and ack CPU interrupts upon initialization.  Keep the state
        of software interrupts when unmasking.

diff -urN linux/arch/mips/kernel/irq_cpu.c linux/arch/mips/kernel/irq_cpu.c
--- linux/arch/mips/kernel/irq_cpu.c    2004/02/11 15:09:05     1.8
+++ linux/arch/mips/kernel/irq_cpu.c    2005/02/03 23:06:29     1.9
@@ -3,6 +3,8 @@
  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  *
  * Copyright (C) 2001 Ralf Baechle
+ * Copyright (C) 2005  MIPS Technologies, Inc.  All rights reserved.
+ *      Author: Maciej W. Rozycki <macro@mips.com>
  *
  * This file define the irq handler for MIPS CPU interrupts.
  *
@@ -37,7 +39,6 @@
 
 static inline void unmask_mips_irq(unsigned int irq)
 {
-       clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
        set_c0_status(0x100 << (irq - mips_cpu_irq_base));
 }
 
@@ -107,6 +108,10 @@
 {
        int i;
 
+       /* Mask interrupts. */
+       clear_c0_status(ST0_IM);
+       clear_c0_cause(CAUSEF_IP);
+
        for (i = irq_base; i < irq_base + 8; i++) {
                irq_desc[i].status = IRQ_DISABLED;
                irq_desc[i].action = NULL;

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