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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: macro@linux-mips.org
Date: Tue, 01 Feb 2005 20:19:09 +0000
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     macro@ftp.linux-mips.org        05/02/01 20:19:03

Modified files:
        arch/mips/mips-boards/generic: init.c pci.c 
        arch/mips/pci  : ops-bonito64.c ops-gt64120.c ops-msc.c 
        include/asm-mips/mips-boards: msc01_pci.h 

Log message:
        Fixes for system controllers for Atlas/Malta core cards.

diff -urN linux/arch/mips/mips-boards/generic/init.c 
linux/arch/mips/mips-boards/generic/init.c
--- linux/arch/mips/mips-boards/generic/init.c  2004/08/20 10:03:22     1.18
+++ linux/arch/mips/mips-boards/generic/init.c  2005/02/01 20:18:59     1.19
@@ -1,6 +1,8 @@
 /*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
+ *     All rights reserved.
+ *     Authors: Carsten Langgaard <carstenl@mips.com>
+ *              Maciej W. Rozycki <macro@mips.com>
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
@@ -22,18 +24,17 @@
 #include <linux/string.h>
 #include <linux/kernel.h>
 
-#include <asm/io.h>
 #include <asm/bootinfo.h>
+#include <asm/gt64120.h>
+#include <asm/io.h>
+#include <asm/system.h>
+
 #include <asm/mips-boards/prom.h>
 #include <asm/mips-boards/generic.h>
-#ifdef CONFIG_MIPS_GT64120
-#include <asm/gt64120.h>
-#endif
-#include <asm/mips-boards/msc01_pci.h>
 #include <asm/mips-boards/bonito64.h>
-#ifdef CONFIG_MIPS_MALTA
+#include <asm/mips-boards/msc01_pci.h>
+
 #include <asm/mips-boards/malta.h>
-#endif
 
 #ifdef CONFIG_KGDB
 extern int rs_kgdb_hook(int, int);
@@ -225,6 +226,8 @@
 
 void __init prom_init(void)
 {
+       u32 start, map, mask, data;
+
        prom_argc = fw_arg0;
        _prom_argv = (int *) fw_arg1;
        _prom_envp = (int *) fw_arg2;
@@ -266,12 +269,15 @@
 #else
                GT_WRITE(GT_PCI0_CMD_OFS, 0);
 #endif
+               /* Fix up PCI I/O mapping if necessary (for Atlas).  */
+               start = GT_READ(GT_PCI0IOLD_OFS);
+               map = GT_READ(GT_PCI0IOREMAP_OFS);
+               if ((start & map) != 0) {
+                       map &= ~start;
+                       GT_WRITE(GT_PCI0IOREMAP_OFS, map);
+               }
 
-#ifdef CONFIG_MIPS_MALTA
                set_io_port_base(MALTA_GT_PORT_BASE);
-#else
-               set_io_port_base((unsigned long)ioremap(0, 0x20000000));
-#endif
                break;
 
        case MIPS_REVISION_CORID_CORE_EMUL_BON:
@@ -300,11 +306,7 @@
                        BONITO_BONGENCFG_BYTESWAP;
 #endif
 
-#ifdef CONFIG_MIPS_MALTA
                set_io_port_base(MALTA_BONITO_PORT_BASE);
-#else
-               set_io_port_base((unsigned long)ioremap(0, 0x20000000));
-#endif
                break;
 
        case MIPS_REVISION_CORID_CORE_MSC:
@@ -312,6 +314,12 @@
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 
0x2000); 
 
+               mb();
+               MSC_READ(MSC01_PCI_CFG, data);
+               MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
+               wmb();
+
+               /* Fix up lane swapping.  */
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
                MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
 #else
@@ -320,12 +328,23 @@
                          MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
                          MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
 #endif
+               /* Fix up target memory mapping.  */
+               MSC_READ(MSC01_PCI_BAR0, mask);
+               MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
+
+               /* Don't handle target retries indefinitely.  */
+               if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
+                   MSC01_PCI_CFG_MAXRTRY_MSK)
+                       data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
+                                        MSC01_PCI_CFG_MAXRTRY_SHF)) |
+                              ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
+                               MSC01_PCI_CFG_MAXRTRY_SHF);
+
+               wmb();
+               MSC_WRITE(MSC01_PCI_CFG, data);
+               mb();
 
-#ifdef CONFIG_MIPS_MALTA
                set_io_port_base(MALTA_MSC_PORT_BASE);
-#else
-               set_io_port_base((unsigned long)ioremap(0, 0x20000000));
-#endif
                break;
 
        default:
diff -urN linux/arch/mips/mips-boards/generic/pci.c 
linux/arch/mips/mips-boards/generic/pci.c
--- linux/arch/mips/mips-boards/generic/pci.c   2004/08/26 20:18:00     1.27
+++ linux/arch/mips/mips-boards/generic/pci.c   2005/02/01 20:18:59     1.28
@@ -1,6 +1,8 @@
 /*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
+ *     All rights reserved.
+ *     Authors: Carsten Langgaard <carstenl@mips.com>
+ *              Maciej W. Rozycki <macro@mips.com>
  *
  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
  *
@@ -25,59 +27,41 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include <asm/mips-boards/generic.h>
 #include <asm/gt64120.h>
+
+#include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/bonito64.h>
 #include <asm/mips-boards/msc01_pci.h>
-#ifdef CONFIG_MIPS_MALTA
-#include <asm/mips-boards/malta.h>
-#endif
 
 static struct resource bonito64_mem_resource = {
        .name   = "Bonito PCI MEM",
-       .start  = 0x10000000UL,
-       .end    = 0x1bffffffUL,
        .flags  = IORESOURCE_MEM,
 };
 
 static struct resource bonito64_io_resource = {
-       .name   = "Bonito IO MEM",
-       .start  = 0x00002000UL, /* avoid conflicts with YAMON allocated I/O 
addresses */
+       .name   = "Bonito PCI I/O",
+       .start  = 0x00000000UL,
        .end    = 0x000fffffUL,
        .flags  = IORESOURCE_IO,
 };
 
 static struct resource gt64120_mem_resource = {
-       .name   = "GT64120 PCI MEM",
-       .start  = 0x10000000UL,
-       .end    = 0x1bdfffffUL,
+       .name   = "GT-64120 PCI MEM",
        .flags  = IORESOURCE_MEM,
 };
 
 static struct resource gt64120_io_resource = {
-       .name   = "GT64120 IO MEM",
-#ifdef CONFIG_MIPS_ATLAS
-       .start  = 0x18000000UL,
-       .end    = 0x181fffffUL,
-#endif
-#ifdef CONFIG_MIPS_MALTA
-       .start  = 0x00002000UL,
-       .end    = 0x001fffffUL,
-#endif
+       .name   = "GT-64120 PCI I/O",
        .flags  = IORESOURCE_IO,
 };
 
 static struct resource msc_mem_resource = {
        .name   = "MSC PCI MEM",
-       .start  = 0x10000000UL,
-       .end    = 0x1fffffffUL,
        .flags  = IORESOURCE_MEM,
 };
 
 static struct resource msc_io_resource = {
-       .name   = "MSC IO MEM",
-       .start  = 0x00002000UL,
-       .end    = 0x007fffffUL,
+       .name   = "MSC PCI I/O",
        .flags  = IORESOURCE_IO,
 };
 
@@ -89,7 +73,6 @@
        .pci_ops        = &bonito64_pci_ops,
        .io_resource    = &bonito64_io_resource,
        .mem_resource   = &bonito64_mem_resource,
-       .mem_offset     = 0x10000000UL,
        .io_offset      = 0x00000000UL,
 };
 
@@ -97,21 +80,18 @@
        .pci_ops        = &gt64120_pci_ops,
        .io_resource    = &gt64120_io_resource,
        .mem_resource   = &gt64120_mem_resource,
-       .mem_offset     = 0x00000000UL,
-       .io_offset      = 0x00000000UL,
 };
 
-static struct pci_controller  msc_controller = {
+static struct pci_controller msc_controller = {
        .pci_ops        = &msc_pci_ops,
        .io_resource    = &msc_io_resource,
        .mem_resource   = &msc_mem_resource,
-       .mem_offset     = 0x10000000UL,
-       .io_offset      = 0x00000000UL,
 };
 
 static int __init pcibios_init(void)
 {
        struct pci_controller *controller;
+       unsigned long start, end, map, start1, end1, map1, map2, map3, mask;
 
        switch (mips_revision_corid) {
        case MIPS_REVISION_CORID_QED_RM5261:
@@ -130,29 +110,138 @@
                         (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
                         (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
                         ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
-                        GT_PCI0_CFGADDR_CONFIGEN_BIT );
+                        GT_PCI0_CFGADDR_CONFIGEN_BIT);
 
                /* Perform the write */
                GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
 
+               /* Set up resource ranges from the controller's registers.  */
+               start = GT_READ(GT_PCI0M0LD_OFS);
+               end = GT_READ(GT_PCI0M0HD_OFS);
+               map = GT_READ(GT_PCI0M0REMAP_OFS);
+               end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
+               start1 = GT_READ(GT_PCI0M1LD_OFS);
+               end1 = GT_READ(GT_PCI0M1HD_OFS);
+               map1 = GT_READ(GT_PCI0M1REMAP_OFS);
+               end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);
+               /* Cannot support multiple windows, use the wider.  */
+               if (end1 - start1 > end - start) {
+                       start = start1;
+                       end = end1;
+                       map = map1;
+               }
+               mask = ~(start ^ end);
+                /* We don't support remapping with a discontiguous mask.  */
+               BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
+                      mask != ~((mask & -mask) - 1));
+               gt64120_mem_resource.start = start;
+               gt64120_mem_resource.end = end;
+               gt64120_controller.mem_offset = (start & mask) - (map & mask);
+               /* Addresses are 36-bit, so do shifts in the destinations.  */
+               gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
+               gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
+               gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
+               gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;
+
+               start = GT_READ(GT_PCI0IOLD_OFS);
+               end = GT_READ(GT_PCI0IOHD_OFS);
+               map = GT_READ(GT_PCI0IOREMAP_OFS);
+               end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
+               mask = ~(start ^ end);
+                /* We don't support remapping with a discontiguous mask.  */
+               BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
+                      mask != ~((mask & -mask) - 1));
+               gt64120_io_resource.start = map & mask;
+               gt64120_io_resource.end = (map & mask) | ~mask;
+               gt64120_controller.io_offset = 0;
+               /* Addresses are 36-bit, so do shifts in the destinations.  */
+               gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
+               gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
+               gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
+
                controller = &gt64120_controller;
                break;
 
        case MIPS_REVISION_CORID_BONITO64:
        case MIPS_REVISION_CORID_CORE_20K:
        case MIPS_REVISION_CORID_CORE_EMUL_BON:
+               /* Set up resource ranges from the controller's registers.  */
+               map = BONITO_PCIMAP;
+               map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
+                      BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
+               map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
+                      BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
+               map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
+                      BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
+               /* Combine as many adjacent windows as possible.  */
+               map = map1;
+               start = BONITO_PCILO0_BASE;
+               end = 1;
+               if (map3 == map2 + 1) {
+                       map = map2;
+                       start = BONITO_PCILO1_BASE;
+                       end++;
+               }
+               if (map2 == map1 + 1) {
+                       map = map1;
+                       start = BONITO_PCILO0_BASE;
+                       end++;
+               }
+               bonito64_mem_resource.start = start;
+               bonito64_mem_resource.end = start +
+                                           BONITO_PCIMAP_WINBASE(end) - 1;
+               bonito64_controller.mem_offset = start -
+                                                BONITO_PCIMAP_WINBASE(map);
+
                controller = &bonito64_controller;
                break;
 
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
+               /* Set up resource ranges from the controller's registers.  */
+               MSC_READ(MSC01_PCI_SC2PMBASL, start);
+               MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
+               MSC_READ(MSC01_PCI_SC2PMMAPL, map);
+               msc_mem_resource.start = start & mask;
+               msc_mem_resource.end = (start & mask) | ~mask;
+               msc_controller.mem_offset = (start & mask) - (map & mask);
+
+               MSC_READ(MSC01_PCI_SC2PIOBASL, start);
+               MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
+               MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
+               msc_io_resource.start = map & mask;
+               msc_io_resource.end = (map & mask) | ~mask;
+               msc_controller.io_offset = 0;
+               ioport_resource.end = ~mask;
+
+               /* If ranges overlap I/O takes precedence.  */
+               start = start & mask;
+               end = start | ~mask;
+               if ((start >= msc_mem_resource.start &&
+                    start <= msc_mem_resource.end) ||
+                   (end >= msc_mem_resource.start &&
+                    end <= msc_mem_resource.end)) {
+                       /* Use the larger space.  */
+                       start = max(start, msc_mem_resource.start);
+                       end = min(end, msc_mem_resource.end);
+                       if (start - msc_mem_resource.start >=
+                           msc_mem_resource.end - end)
+                               msc_mem_resource.end = start - 1;
+                       else
+                               msc_mem_resource.start = end + 1;
+               }
+
                controller = &msc_controller;
                break;
        default:
                return 1;
        }
 
+       if (controller->io_resource->start < 0x00001000UL)      /* FIXME */
+               controller->io_resource->start = 0x00001000UL;
+
+       iomem_resource.end &= 0xfffffffffULL;                   /* 64 GB */
        ioport_resource.end = controller->io_resource->end;
 
        register_pci_controller (controller);
diff -urN linux/arch/mips/pci/ops-bonito64.c linux/arch/mips/pci/ops-bonito64.c
--- linux/arch/mips/pci/ops-bonito64.c  2004/01/20 12:53:38     1.5
+++ linux/arch/mips/pci/ops-bonito64.c  2005/02/01 20:19:01     1.6
@@ -1,6 +1,8 @@
 /*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
+ *     All rights reserved.
+ *     Authors: Carsten Langgaard <carstenl@mips.com>
+ *              Maciej W. Rozycki <macro@mips.com>
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
@@ -57,13 +59,6 @@
                return -1;
        }
 
-#ifdef CONFIG_MIPS_BOARDS_GEN
-       if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
-               /* MIPS Core boards have Bonito connected as device 17 */
-               return -1;
-       }
-#endif
-
        /* Clear cause register bits */
        BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
                          BONITO_PCICMD_MTABORT_CLR);
diff -urN linux/arch/mips/pci/ops-gt64120.c linux/arch/mips/pci/ops-gt64120.c
--- linux/arch/mips/pci/ops-gt64120.c   2004/01/22 03:06:31     1.8
+++ linux/arch/mips/pci/ops-gt64120.c   2005/02/01 20:19:01     1.9
@@ -1,6 +1,8 @@
 /*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
+ *     All rights reserved.
+ *     Authors: Carsten Langgaard <carstenl@mips.com>
+ *              Maciej W. Rozycki <macro@mips.com>
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
@@ -43,10 +45,6 @@
        unsigned char busnum = bus->number;
        u32 intr;
 
-       if ((busnum == 0) && (PCI_SLOT(devfn) == 0))
-               /* Galileo itself is devfn 0, don't move it around */
-               return -1;
-
        if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
                return -1;      /* Because of a bug in the galileo (for slot 
31). */
 
diff -urN linux/arch/mips/pci/ops-msc.c linux/arch/mips/pci/ops-msc.c
--- linux/arch/mips/pci/ops-msc.c       2005/01/15 01:31:05     1.5
+++ linux/arch/mips/pci/ops-msc.c       2005/02/01 20:19:01     1.6
@@ -1,6 +1,8 @@
 /*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
+ *     All rights reserved.
+ *     Authors: Carsten Langgaard <carstenl@mips.com>
+ *              Maciej W. Rozycki <macro@mips.com>
  * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  *
  *  This program is free software; you can distribute it and/or modify it
@@ -47,34 +49,17 @@
        struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
 {
        unsigned char busnum = bus->number;
-       unsigned char type;
        u32 intr;
 
-#ifdef CONFIG_MIPS_BOARDS_GEN
-       if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
-               /* MIPS Core boards have SOCit connected as device 17 */
-               return -1;
-       }
-#endif
-
        /* Clear status register bits. */
        MSC_WRITE(MSC01_PCI_INTSTAT,
                  (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
 
-       /* Setup address */
-       if (busnum == 0)
-               type = 0;       /* Type 0 */
-       else
-               type = 1;       /* Type 1 */
-
        MSC_WRITE(MSC01_PCI_CFGADDR,
                  ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
-                  (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF)
-                  | (PCI_FUNC(devfn) <<
-                     MSC01_PCI_CFGADDR_FNUM_SHF) | ((where /
-                                                     4) <<
-                                                    MSC01_PCI_CFGADDR_RNUM_SHF)
-                  | (type)));
+                  (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) |
+                  (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) |
+                  ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF)));
 
        /* Perform access */
        if (access_type == PCI_ACCESS_WRITE)
@@ -84,15 +69,12 @@
 
        /* Detect Master/Target abort */
        MSC_READ(MSC01_PCI_INTSTAT, intr);
-       if (intr & (MSC01_PCI_INTCFG_MA_BIT |
-                   MSC01_PCI_INTCFG_TA_BIT)) {
+       if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) {
                /* Error occurred */
 
                /* Clear bits */
-               MSC_READ(MSC01_PCI_INTSTAT, intr);
                MSC_WRITE(MSC01_PCI_INTSTAT,
-                         (MSC01_PCI_INTCFG_MA_BIT |
-                          MSC01_PCI_INTCFG_TA_BIT));
+                         (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
 
                return -1;
        }
diff -urN linux/include/asm-mips/mips-boards/msc01_pci.h 
linux/include/asm-mips/mips-boards/msc01_pci.h
--- linux/include/asm-mips/mips-boards/msc01_pci.h      2003/11/15 16:13:36     
1.4
+++ linux/include/asm-mips/mips-boards/msc01_pci.h      2005/02/01 20:19:03     
1.5
@@ -1,8 +1,9 @@
 /*
  * PCI Register definitions for the MIPS System Controller.
  *
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2002, 2005  MIPS Technologies, Inc.  All rights reserved.
+ *     Authors: Carsten Langgaard <carstenl@mips.com>
+ *              Maciej W. Rozycki <macro@mips.com>
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -29,22 +30,22 @@
 #define MSC01_PCI_CFGADDR_OFS          0x0610
 #define MSC01_PCI_CFGDATA_OFS          0x0618
 #define MSC01_PCI_IACK_OFS             0x0620
-#define MSC01_PCI_HEAD0_OFS            0x2000  /* DevID, VendorID */
-#define MSC01_PCI_HEAD1_OFS            0x2008  /* Status, Command */
-#define MSC01_PCI_HEAD2_OFS            0x2010  /* Class code, RevID */
-#define MSC01_PCI_HEAD3_OFS            0x2018  /* bist, header, latency */
-#define MSC01_PCI_HEAD4_OFS            0x2020  /* BAR 0 */
-#define MSC01_PCI_HEAD5_OFS            0x2028  /* BAR 1 */
-#define MSC01_PCI_HEAD6_OFS            0x2030  /* BAR 2 */
-#define MSC01_PCI_HEAD7_OFS            0x2038  /* BAR 3 */
-#define MSC01_PCI_HEAD8_OFS            0x2040  /* BAR 4 */
-#define MSC01_PCI_HEAD9_OFS            0x2048  /* BAR 5 */
-#define MSC01_PCI_HEAD10_OFS           0x2050  /* CardBus CIS Ptr */
-#define MSC01_PCI_HEAD11_OFS           0x2058  /* SubSystem ID, -VendorID */
-#define MSC01_PCI_HEAD12_OFS           0x2060  /* ROM BAR */
-#define MSC01_PCI_HEAD13_OFS           0x2068  /* Capabilities ptr */
-#define MSC01_PCI_HEAD14_OFS           0x2070  /* reserved */
-#define MSC01_PCI_HEAD15_OFS           0x2078  /* Maxl, ming, intpin, int */
+#define MSC01_PCI_HEAD0_OFS            0x2000  /* DevID, VendorID */
+#define MSC01_PCI_HEAD1_OFS            0x2008  /* Status, Command */
+#define MSC01_PCI_HEAD2_OFS            0x2010  /* Class code, RevID */
+#define MSC01_PCI_HEAD3_OFS            0x2018  /* bist, header, latency */
+#define MSC01_PCI_HEAD4_OFS            0x2020  /* BAR 0 */
+#define MSC01_PCI_HEAD5_OFS            0x2028  /* BAR 1 */
+#define MSC01_PCI_HEAD6_OFS            0x2030  /* BAR 2 */
+#define MSC01_PCI_HEAD7_OFS            0x2038  /* BAR 3 */
+#define MSC01_PCI_HEAD8_OFS            0x2040  /* BAR 4 */
+#define MSC01_PCI_HEAD9_OFS            0x2048  /* BAR 5 */
+#define MSC01_PCI_HEAD10_OFS           0x2050  /* CardBus CIS Ptr */
+#define MSC01_PCI_HEAD11_OFS           0x2058  /* SubSystem ID, -VendorID */
+#define MSC01_PCI_HEAD12_OFS           0x2060  /* ROM BAR */
+#define MSC01_PCI_HEAD13_OFS           0x2068  /* Capabilities ptr */
+#define MSC01_PCI_HEAD14_OFS           0x2070  /* reserved */
+#define MSC01_PCI_HEAD15_OFS           0x2078  /* Maxl, ming, intpin, int */
 #define MSC01_PCI_BAR0_OFS             0x2220
 #define MSC01_PCI_CFG_OFS              0x2380
 #define MSC01_PCI_SWAP_OFS             0x2388
@@ -86,73 +87,73 @@
 #define MSC01_PCI_P2SCMAPL_MAP_SHF     24
 #define MSC01_PCI_P2SCMAPL_MAP_MSK     0xff000000
 
-#define MSC01_PCI_INTCFG_RST_SHF        10
-#define MSC01_PCI_INTCFG_RST_MSK        0x00000400
-#define MSC01_PCI_INTCFG_RST_BIT        0x00000400
-#define MSC01_PCI_INTCFG_MWE_SHF        9
-#define MSC01_PCI_INTCFG_MWE_MSK        0x00000200
-#define MSC01_PCI_INTCFG_MWE_BIT        0x00000200
-#define MSC01_PCI_INTCFG_DTO_SHF        8
-#define MSC01_PCI_INTCFG_DTO_MSK        0x00000100
-#define MSC01_PCI_INTCFG_DTO_BIT        0x00000100
-#define MSC01_PCI_INTCFG_MA_SHF         7
-#define MSC01_PCI_INTCFG_MA_MSK         0x00000080
-#define MSC01_PCI_INTCFG_MA_BIT         0x00000080
-#define MSC01_PCI_INTCFG_TA_SHF         6
-#define MSC01_PCI_INTCFG_TA_MSK         0x00000040
-#define MSC01_PCI_INTCFG_TA_BIT         0x00000040
-#define MSC01_PCI_INTCFG_RTY_SHF        5
-#define MSC01_PCI_INTCFG_RTY_MSK        0x00000020
-#define MSC01_PCI_INTCFG_RTY_BIT        0x00000020
-#define MSC01_PCI_INTCFG_MWP_SHF        4
-#define MSC01_PCI_INTCFG_MWP_MSK        0x00000010
-#define MSC01_PCI_INTCFG_MWP_BIT        0x00000010
-#define MSC01_PCI_INTCFG_MRP_SHF        3
-#define MSC01_PCI_INTCFG_MRP_MSK        0x00000008
-#define MSC01_PCI_INTCFG_MRP_BIT        0x00000008
-#define MSC01_PCI_INTCFG_SWP_SHF        2
-#define MSC01_PCI_INTCFG_SWP_MSK        0x00000004
-#define MSC01_PCI_INTCFG_SWP_BIT        0x00000004
-#define MSC01_PCI_INTCFG_SRP_SHF        1
-#define MSC01_PCI_INTCFG_SRP_MSK        0x00000002
-#define MSC01_PCI_INTCFG_SRP_BIT        0x00000002
-#define MSC01_PCI_INTCFG_SE_SHF         0
-#define MSC01_PCI_INTCFG_SE_MSK         0x00000001
-#define MSC01_PCI_INTCFG_SE_BIT         0x00000001
-
-#define MSC01_PCI_INTSTAT_RST_SHF       10
-#define MSC01_PCI_INTSTAT_RST_MSK       0x00000400
-#define MSC01_PCI_INTSTAT_RST_BIT       0x00000400
-#define MSC01_PCI_INTSTAT_MWE_SHF       9
-#define MSC01_PCI_INTSTAT_MWE_MSK       0x00000200
-#define MSC01_PCI_INTSTAT_MWE_BIT       0x00000200
-#define MSC01_PCI_INTSTAT_DTO_SHF       8
-#define MSC01_PCI_INTSTAT_DTO_MSK       0x00000100
-#define MSC01_PCI_INTSTAT_DTO_BIT       0x00000100
-#define MSC01_PCI_INTSTAT_MA_SHF        7
-#define MSC01_PCI_INTSTAT_MA_MSK        0x00000080
-#define MSC01_PCI_INTSTAT_MA_BIT        0x00000080
-#define MSC01_PCI_INTSTAT_TA_SHF        6
-#define MSC01_PCI_INTSTAT_TA_MSK        0x00000040
-#define MSC01_PCI_INTSTAT_TA_BIT        0x00000040
-#define MSC01_PCI_INTSTAT_RTY_SHF       5
-#define MSC01_PCI_INTSTAT_RTY_MSK       0x00000020
-#define MSC01_PCI_INTSTAT_RTY_BIT       0x00000020
-#define MSC01_PCI_INTSTAT_MWP_SHF       4
-#define MSC01_PCI_INTSTAT_MWP_MSK       0x00000010
-#define MSC01_PCI_INTSTAT_MWP_BIT       0x00000010
-#define MSC01_PCI_INTSTAT_MRP_SHF       3
-#define MSC01_PCI_INTSTAT_MRP_MSK       0x00000008
-#define MSC01_PCI_INTSTAT_MRP_BIT       0x00000008
-#define MSC01_PCI_INTSTAT_SWP_SHF       2
-#define MSC01_PCI_INTSTAT_SWP_MSK       0x00000004
-#define MSC01_PCI_INTSTAT_SWP_BIT       0x00000004
-#define MSC01_PCI_INTSTAT_SRP_SHF       1
-#define MSC01_PCI_INTSTAT_SRP_MSK       0x00000002
-#define MSC01_PCI_INTSTAT_SRP_BIT       0x00000002
-#define MSC01_PCI_INTSTAT_SE_SHF        0
-#define MSC01_PCI_INTSTAT_SE_MSK        0x00000001
-#define MSC01_PCI_INTSTAT_SE_BIT        0x00000001
+#define MSC01_PCI_INTCFG_RST_SHF       10
+#define MSC01_PCI_INTCFG_RST_MSK       0x00000400
+#define MSC01_PCI_INTCFG_RST_BIT       0x00000400
+#define MSC01_PCI_INTCFG_MWE_SHF       9
+#define MSC01_PCI_INTCFG_MWE_MSK       0x00000200
+#define MSC01_PCI_INTCFG_MWE_BIT       0x00000200
+#define MSC01_PCI_INTCFG_DTO_SHF       8
+#define MSC01_PCI_INTCFG_DTO_MSK       0x00000100
+#define MSC01_PCI_INTCFG_DTO_BIT       0x00000100
+#define MSC01_PCI_INTCFG_MA_SHF                7
+#define MSC01_PCI_INTCFG_MA_MSK                0x00000080
+#define MSC01_PCI_INTCFG_MA_BIT                0x00000080
+#define MSC01_PCI_INTCFG_TA_SHF                6
+#define MSC01_PCI_INTCFG_TA_MSK                0x00000040
+#define MSC01_PCI_INTCFG_TA_BIT                0x00000040
+#define MSC01_PCI_INTCFG_RTY_SHF       5
+#define MSC01_PCI_INTCFG_RTY_MSK       0x00000020
+#define MSC01_PCI_INTCFG_RTY_BIT       0x00000020
+#define MSC01_PCI_INTCFG_MWP_SHF       4
+#define MSC01_PCI_INTCFG_MWP_MSK       0x00000010
+#define MSC01_PCI_INTCFG_MWP_BIT       0x00000010
+#define MSC01_PCI_INTCFG_MRP_SHF       3
+#define MSC01_PCI_INTCFG_MRP_MSK       0x00000008
+#define MSC01_PCI_INTCFG_MRP_BIT       0x00000008
+#define MSC01_PCI_INTCFG_SWP_SHF       2
+#define MSC01_PCI_INTCFG_SWP_MSK       0x00000004
+#define MSC01_PCI_INTCFG_SWP_BIT       0x00000004
+#define MSC01_PCI_INTCFG_SRP_SHF       1
+#define MSC01_PCI_INTCFG_SRP_MSK       0x00000002
+#define MSC01_PCI_INTCFG_SRP_BIT       0x00000002
+#define MSC01_PCI_INTCFG_SE_SHF                0
+#define MSC01_PCI_INTCFG_SE_MSK                0x00000001
+#define MSC01_PCI_INTCFG_SE_BIT                0x00000001
+
+#define MSC01_PCI_INTSTAT_RST_SHF      10
+#define MSC01_PCI_INTSTAT_RST_MSK      0x00000400
+#define MSC01_PCI_INTSTAT_RST_BIT      0x00000400
+#define MSC01_PCI_INTSTAT_MWE_SHF      9
+#define MSC01_PCI_INTSTAT_MWE_MSK      0x00000200
+#define MSC01_PCI_INTSTAT_MWE_BIT      0x00000200
+#define MSC01_PCI_INTSTAT_DTO_SHF      8
+#define MSC01_PCI_INTSTAT_DTO_MSK      0x00000100
+#define MSC01_PCI_INTSTAT_DTO_BIT      0x00000100
+#define MSC01_PCI_INTSTAT_MA_SHF       7
+#define MSC01_PCI_INTSTAT_MA_MSK       0x00000080
+#define MSC01_PCI_INTSTAT_MA_BIT       0x00000080
+#define MSC01_PCI_INTSTAT_TA_SHF       6
+#define MSC01_PCI_INTSTAT_TA_MSK       0x00000040
+#define MSC01_PCI_INTSTAT_TA_BIT       0x00000040
+#define MSC01_PCI_INTSTAT_RTY_SHF      5
+#define MSC01_PCI_INTSTAT_RTY_MSK      0x00000020
+#define MSC01_PCI_INTSTAT_RTY_BIT      0x00000020
+#define MSC01_PCI_INTSTAT_MWP_SHF      4
+#define MSC01_PCI_INTSTAT_MWP_MSK      0x00000010
+#define MSC01_PCI_INTSTAT_MWP_BIT      0x00000010
+#define MSC01_PCI_INTSTAT_MRP_SHF      3
+#define MSC01_PCI_INTSTAT_MRP_MSK      0x00000008
+#define MSC01_PCI_INTSTAT_MRP_BIT      0x00000008
+#define MSC01_PCI_INTSTAT_SWP_SHF      2
+#define MSC01_PCI_INTSTAT_SWP_MSK      0x00000004
+#define MSC01_PCI_INTSTAT_SWP_BIT      0x00000004
+#define MSC01_PCI_INTSTAT_SRP_SHF      1
+#define MSC01_PCI_INTSTAT_SRP_MSK      0x00000002
+#define MSC01_PCI_INTSTAT_SRP_BIT      0x00000002
+#define MSC01_PCI_INTSTAT_SE_SHF       0
+#define MSC01_PCI_INTSTAT_SE_MSK       0x00000001
+#define MSC01_PCI_INTSTAT_SE_BIT       0x00000001
 
 #define MSC01_PCI_CFGADDR_BNUM_SHF     16
 #define MSC01_PCI_CFGADDR_BNUM_MSK     0x00ff0000
@@ -167,29 +168,29 @@
 #define MSC01_PCI_CFGDATA_DATA_MSK     0xffffffff
 
 /* The defines below are ONLY valid for a MEM bar! */
-#define MSC01_PCI_BAR0_SIZE_SHF                4
-#define MSC01_PCI_BAR0_SIZE_MSK                0xfffffff0
-#define MSC01_PCI_BAR0_P_SHF           3
-#define MSC01_PCI_BAR0_P_MSK           0x00000008
-#define MSC01_PCI_BAR0_P_BIT           MSC01_PCI_BAR0_P_MSK
-#define MSC01_PCI_BAR0_D_SHF           1
-#define MSC01_PCI_BAR0_D_MSK           0x00000006
-#define MSC01_PCI_BAR0_T_SHF           0
-#define MSC01_PCI_BAR0_T_MSK           0x00000001
-#define MSC01_PCI_BAR0_T_BIT           MSC01_PCI_BAR0_T_MSK
-
-
-#define MSC01_PCI_CFG_RA_SHF           17
-#define MSC01_PCI_CFG_RA_MSK           0x00020000
-#define MSC01_PCI_CFG_RA_BIT           MSC01_PCI_CFG_RA_MSK
-#define MSC01_PCI_CFG_G_SHF            16
-#define MSC01_PCI_CFG_G_MSK            0x00010000
-#define MSC01_PCI_CFG_G_BIT            MSC01_PCI_CFG_G_MSK
-#define MSC01_PCI_CFG_EN_SHF           15
-#define MSC01_PCI_CFG_EN_MSK           0x00008000
-#define MSC01_PCI_CFG_EN_BIT           MSC01_PCI_CFG_EN_MSK
-#define MSC01_PCI_CFG_MAXRTRY_SHF       0
-#define MSC01_PCI_CFG_MAXRTRY_MSK       0x000000ff
+#define MSC01_PCI_BAR0_SIZE_SHF                4
+#define MSC01_PCI_BAR0_SIZE_MSK                0xfffffff0
+#define MSC01_PCI_BAR0_P_SHF           3
+#define MSC01_PCI_BAR0_P_MSK           0x00000008
+#define MSC01_PCI_BAR0_P_BIT           MSC01_PCI_BAR0_P_MSK
+#define MSC01_PCI_BAR0_D_SHF           1
+#define MSC01_PCI_BAR0_D_MSK           0x00000006
+#define MSC01_PCI_BAR0_T_SHF           0
+#define MSC01_PCI_BAR0_T_MSK           0x00000001
+#define MSC01_PCI_BAR0_T_BIT           MSC01_PCI_BAR0_T_MSK
+
+
+#define MSC01_PCI_CFG_RA_SHF           17
+#define MSC01_PCI_CFG_RA_MSK           0x00020000
+#define MSC01_PCI_CFG_RA_BIT           MSC01_PCI_CFG_RA_MSK
+#define MSC01_PCI_CFG_G_SHF            16
+#define MSC01_PCI_CFG_G_MSK            0x00010000
+#define MSC01_PCI_CFG_G_BIT            MSC01_PCI_CFG_G_MSK
+#define MSC01_PCI_CFG_EN_SHF           15
+#define MSC01_PCI_CFG_EN_MSK           0x00008000
+#define MSC01_PCI_CFG_EN_BIT           MSC01_PCI_CFG_EN_MSK
+#define MSC01_PCI_CFG_MAXRTRY_SHF      0
+#define MSC01_PCI_CFG_MAXRTRY_MSK      0x00000fff
 
 #define MSC01_PCI_SWAP_IO_SHF          18
 #define MSC01_PCI_SWAP_IO_MSK          0x000c0000
@@ -219,19 +220,19 @@
  * Registers absolute addresses
  */
 
-#define MSC01_PCI_ID            (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
-#define MSC01_PCI_SC2PMBASL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
-#define MSC01_PCI_SC2PMMSKL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
-#define MSC01_PCI_SC2PMMAPL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
-#define MSC01_PCI_SC2PIOBASL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
-#define MSC01_PCI_SC2PIOMSKL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
-#define MSC01_PCI_SC2PIOMAPL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
-#define MSC01_PCI_P2SCMSKL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
-#define MSC01_PCI_P2SCMAPL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
-#define MSC01_PCI_INTCFG        (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
-#define MSC01_PCI_INTSTAT       (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
-#define MSC01_PCI_CFGADDR       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
-#define MSC01_PCI_CFGDATA       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
+#define MSC01_PCI_ID           (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
+#define MSC01_PCI_SC2PMBASL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
+#define MSC01_PCI_SC2PMMSKL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
+#define MSC01_PCI_SC2PMMAPL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
+#define MSC01_PCI_SC2PIOBASL   (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
+#define MSC01_PCI_SC2PIOMSKL   (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
+#define MSC01_PCI_SC2PIOMAPL   (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
+#define MSC01_PCI_P2SCMSKL     (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
+#define MSC01_PCI_P2SCMAPL     (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
+#define MSC01_PCI_INTCFG       (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
+#define MSC01_PCI_INTSTAT      (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
+#define MSC01_PCI_CFGADDR      (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
+#define MSC01_PCI_CFGDATA      (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
 #define MSC01_PCI_IACK         (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
 #define MSC01_PCI_HEAD0                (MSC01_PCI_REG_BASE + 
MSC01_PCI_HEAD0_OFS)
 #define MSC01_PCI_HEAD1                (MSC01_PCI_REG_BASE + 
MSC01_PCI_HEAD1_OFS)
@@ -248,7 +249,7 @@
 #define MSC01_PCI_HEAD12       (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
 #define MSC01_PCI_HEAD13       (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
 #define MSC01_PCI_HEAD14       (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_HEAD15        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD15       (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
 #define MSC01_PCI_BAR0         (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
 #define MSC01_PCI_CFG          (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
 #define MSC01_PCI_SWAP         (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)

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