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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: ppopov@linux-mips.org
Date: Sun, 30 Jan 2005 08:01:34 +0000
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ppopov@ftp.linux-mips.org       05/01/30 08:01:28

Modified files:
        arch/mips      : Tag: linux_2_4 Makefile config-shared.in 
                         defconfig-bosporus defconfig-db1000 
                         defconfig-db1100 defconfig-db1500 
                         defconfig-db1550 defconfig-hydrogen3 
                         defconfig-mirage defconfig-pb1000 
                         defconfig-pb1100 defconfig-pb1500 
                         defconfig-pb1550 
        arch/mips/au1000/common: Tag: linux_2_4 Makefile au1xxx_irqmap.c 
                                 cputable.c dbdma.c irq.c pci_ops.c 
                                 power.c setup.c sleeper.S time.c 
        arch/mips/au1000/pb1550: Tag: linux_2_4 board_setup.c irqmap.c 
        arch/mips/kernel: Tag: linux_2_4 cpu-probe.c 
        drivers/sound  : Tag: linux_2_4 au1550_psc.c 
        include/asm-mips: Tag: linux_2_4 au1000.h au1000_gpio.h 
                          au1000_pcmcia.h au1100_mmc.h au1xxx_dbdma.h 
                          au1xxx_psc.h bootinfo.h pb1550.h 
Added files:
        arch/mips      : Tag: linux_2_4 defconfig-db1200 
                         defconfig-ficmmp defconfig-pb1200 
        arch/mips/au1000/common: Tag: linux_2_4 gpio.c 
        arch/mips/au1000/ficmmp: Tag: linux_2_4 Makefile 
                                 au1200_ibutton.c au1xxx_dock.c 
                                 board_setup.c init.c irqmap.c 
        arch/mips/au1000/pb1200: Tag: linux_2_4 Makefile board_setup.c 
                                 init.c irqmap.c mmc_support.c 
        include/asm-mips: Tag: linux_2_4 au1xxx_gpio.h ficmmp.h pb1200.h 

Log message:
        Added Au1200 SOC support and three boards based on this new
        SOC from AMD.

diff -urN linux/arch/mips/defconfig-db1200 linux/arch/mips/defconfig-db1200
--- linux/arch/mips/Attic/defconfig-db1200      1970/01/01 00:00:00
+++ linux/arch/mips/Attic/defconfig-db1200      Sun Jan 30 08:01:27 2005        
1.1.2.1
@@ -0,0 +1,1051 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+# CONFIG_MIPS64 is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_FICMMP is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+CONFIG_MIPS_DB1200=y
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_HYDROGEN3 is not set
+# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_COGENT_CSB250 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_CASIO_E55 is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_IBM_WORKPAD is not set
+# CONFIG_LASAT is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_MOMENCO_OCELOT_G is not set
+# CONFIG_MOMENCO_OCELOT_C is not set
+# CONFIG_MOMENCO_JAGUAR_ATX is not set
+# CONFIG_PMC_BIG_SUR is not set
+# CONFIG_PMC_STRETCH is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_NEC_EAGLE is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SIBYTE_SB1xxx_SOC is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TANBAC_TB0226 is not set
+# CONFIG_TANBAC_TB0229 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_VICTOR_MPC30X is not set
+# CONFIG_ZAO_CAPCELLA is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_SOC_AU1X00=y
+CONFIG_SOC_AU1200=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_PC_KEYB=y
+# CONFIG_MIPS_AU1000 is not set
+
+#
+# CPU selection
+#
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS64 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_VTAG_ICACHE is not set
+CONFIG_64BIT_PHYS_ADDR=y
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+# CONFIG_CPU_HAS_LLDSCD is not set
+# CONFIG_CPU_HAS_WB is not set
+CONFIG_CPU_HAS_SYNC=y
+
+#
+# General setup
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_BUILD_ELF64 is not set
+CONFIG_NET=y
+CONFIG_PCI=y
+CONFIG_PCI_NEW=y
+CONFIG_PCI_AUTO=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_ISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=m
+# CONFIG_CARDBUS is not set
+# CONFIG_TCIC is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+CONFIG_PCMCIA_AU1X00=m
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_HOTPLUG_PCI_COMPAQ is not set
+# CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+# CONFIG_HOTPLUG_PCI_SHPC_POLL_EVENT_MODE is not set
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_HOTPLUG_PCI_PCIE_POLL_EVENT_MODE is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_MIPS32_COMPAT is not set
+# CONFIG_MIPS32_O32 is not set
+# CONFIG_MIPS32_N32 is not set
+# CONFIG_BINFMT_ELF32 is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_OOM_KILLER is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="mem=96M"
+# CONFIG_PM is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
+# CONFIG_CISS_MONITOR_THREAD is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_BLK_STATS is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+
+#
+#   IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+
+#
+#    SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+CONFIG_IDEDISK_MULTI_MODE=y
+CONFIG_IDEDISK_STROKE=y
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+# CONFIG_BLK_DEV_ATARAID_MEDLEY is not set
+# CONFIG_BLK_DEV_ATARAID_SII is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+CONFIG_CHR_DEV_ST=y
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_SR_EXTRA_DEVS=2
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_MEGARAID2 is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_SATA_AHCI is not set
+# CONFIG_SCSI_SATA_SVW is not set
+# CONFIG_SCSI_ATA_PIIX is not set
+# CONFIG_SCSI_SATA_NV is not set
+# CONFIG_SCSI_SATA_PROMISE is not set
+# CONFIG_SCSI_SATA_SX4 is not set
+# CONFIG_SCSI_SATA_SIL is not set
+# CONFIG_SCSI_SATA_SIS is not set
+# CONFIG_SCSI_SATA_ULI is not set
+# CONFIG_SCSI_SATA_VIA is not set
+# CONFIG_SCSI_SATA_VITESSE is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# PCMCIA SCSI adapter support
+#
+# CONFIG_SCSI_PCMCIA is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_BOOT is not set
+# CONFIG_FUSION_ISENSE is not set
+# CONFIG_FUSION_CTL is not set
+# CONFIG_FUSION_LAN is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_MIPS_AU1X00_ENET is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# PCMCIA network device support
+#
+# CONFIG_NET_PCMCIA is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBDEV=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_UINPUT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_COMPUTONE is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_DIGI is not set
+# CONFIG_ESPSERIAL is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
+# CONFIG_SYNCLINK is not set
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_SX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+# CONFIG_SERIAL_TX3912 is not set
+# CONFIG_SERIAL_TX3912_CONSOLE is not set
+# CONFIG_SERIAL_TXX9 is not set
+# CONFIG_SERIAL_TXX9_CONSOLE is not set
+CONFIG_AU1X00_UART=y
+CONFIG_AU1X00_SERIAL_CONSOLE=y
+# CONFIG_AU1X00_USB_TTY is not set
+# CONFIG_AU1X00_USB_RAW is not set
+# CONFIG_TXX927_SERIAL is not set
+# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_INPUT_NS558 is not set
+# CONFIG_INPUT_LIGHTNING is not set
+# CONFIG_INPUT_PCIGAME is not set
+# CONFIG_INPUT_CS461X is not set
+# CONFIG_INPUT_EMU10K1 is not set
+# CONFIG_INPUT_SERIO is not set
+# CONFIG_INPUT_SERPORT is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_ANALOG is not set
+# CONFIG_INPUT_A3D is not set
+# CONFIG_INPUT_ADI is not set
+# CONFIG_INPUT_COBRA is not set
+# CONFIG_INPUT_GF2K is not set
+# CONFIG_INPUT_GRIP is not set
+# CONFIG_INPUT_INTERACT is not set
+# CONFIG_INPUT_TMDC is not set
+# CONFIG_INPUT_SIDEWINDER is not set
+# CONFIG_INPUT_IFORCE_USB is not set
+# CONFIG_INPUT_IFORCE_232 is not set
+# CONFIG_INPUT_WARRIOR is not set
+# CONFIG_INPUT_MAGELLAN is not set
+# CONFIG_INPUT_SPACEORB is not set
+# CONFIG_INPUT_SPACEBALL is not set
+# CONFIG_INPUT_STINGER is not set
+# CONFIG_INPUT_DB9 is not set
+# CONFIG_INPUT_GAMECON is not set
+# CONFIG_INPUT_TURBOGRAFX is not set
+# CONFIG_QIC02_TAPE is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_IPMI_PANIC_EVENT is not set
+# CONFIG_IPMI_DEVICE_INTERFACE is not set
+# CONFIG_IPMI_KCS is not set
+# CONFIG_IPMI_WATCHDOG is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_SCx200 is not set
+# CONFIG_SCx200_GPIO is not set
+# CONFIG_AMD_PM768 is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+
+#
+# Direct Rendering Manager (XFree86 DRI support)
+#
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_PCMCIA_SERIAL_CS is not set
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_AU1X00_GPIO is not set
+# CONFIG_TS_AU1X00_ADS7846 is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_AUTOFS_FS=y
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BEFS_DEBUG is not set
+# CONFIG_BFS_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_TRACE is not set
+# CONFIG_XFS_DEBUG is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_DIRECTIO is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+# CONFIG_NFSD_TCP is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Console drivers
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_CLGEN is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_INTEL is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_E1356 is not set
+# CONFIG_FB_IT8181 is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_FBCON_ADVANCED=y
+# CONFIG_FBCON_MFB is not set
+# CONFIG_FBCON_CFB2 is not set
+# CONFIG_FBCON_CFB4 is not set
+# CONFIG_FBCON_CFB8 is not set
+CONFIG_FBCON_CFB16=y
+# CONFIG_FBCON_CFB24 is not set
+CONFIG_FBCON_CFB32=y
+# CONFIG_FBCON_AFB is not set
+# CONFIG_FBCON_ILBM is not set
+# CONFIG_FBCON_IPLAN2P2 is not set
+# CONFIG_FBCON_IPLAN2P4 is not set
+# CONFIG_FBCON_IPLAN2P8 is not set
+# CONFIG_FBCON_MAC is not set
+# CONFIG_FBCON_VGA_PLANES is not set
+# CONFIG_FBCON_VGA is not set
+# CONFIG_FBCON_HGA is not set
+# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
+CONFIG_FBCON_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+# CONFIG_SOUND_ALI5455 is not set
+# CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_CMPCI is not set
+# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
+# CONFIG_SOUND_FUSION is not set
+# CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ES1370 is not set
+# CONFIG_SOUND_ES1371 is not set
+# CONFIG_SOUND_ESSSOLO1 is not set
+# CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_FORTE is not set
+# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
+# CONFIG_SOUND_SONICVIBES is not set
+# CONFIG_SOUND_AU1X00 is not set
+CONFIG_SOUND_AU1550_PSC=y
+# CONFIG_SOUND_AU1550_I2S is not set
+# CONFIG_SOUND_TRIDENT is not set
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_TVMIXER is not set
+# CONFIG_SOUND_AD1980 is not set
+# CONFIG_SOUND_WM97XX is not set
+
+#
+# USB support
+#
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+CONFIG_USB_OHCI=y
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_MIDI is not set
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT=y
+CONFIG_USB_HIDDEV=y
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_TIGL is not set
+# CONFIG_USB_BRLVGER is not set
+# CONFIG_USB_LCD is not set
+
+#
+# Support for USB gadgets
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_RUNTIME_DEBUG is not set
+# CONFIG_KGDB is not set
+# CONFIG_GDB_CONSOLE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_MIPS_UNCACHED is not set
+CONFIG_LOG_BUF_SHIFT=0
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC32 is not set
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+# CONFIG_FW_LOADER is not set
diff -urN linux/arch/mips/defconfig-ficmmp linux/arch/mips/defconfig-ficmmp
--- linux/arch/mips/Attic/defconfig-ficmmp      1970/01/01 00:00:00
+++ linux/arch/mips/Attic/defconfig-ficmmp      Sun Jan 30 08:01:27 2005        
1.1.2.1
@@ -0,0 +1,862 @@
+#
+# Automatically generated by make menuconfig: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+# CONFIG_MIPS64 is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+CONFIG_MIPS_FICMMP=y
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_HYDROGEN3 is not set
+# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_MIPS_EP1000 is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_COGENT_CSB250 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_CASIO_E55 is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_IBM_WORKPAD is not set
+# CONFIG_LASAT is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_MOMENCO_OCELOT_G is not set
+# CONFIG_MOMENCO_OCELOT_C is not set
+# CONFIG_MOMENCO_JAGUAR_ATX is not set
+# CONFIG_PMC_BIG_SUR is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_NEC_EAGLE is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SIBYTE_SB1xxx_SOC is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TANBAC_TB0226 is not set
+# CONFIG_TANBAC_TB0229 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_VICTOR_MPC30X is not set
+# CONFIG_ZAO_CAPCELLA is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_SOC_AU1X00=y
+CONFIG_SOC_AU1200=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_PC_KEYB=y
+# CONFIG_MIPS_AU1000 is not set
+
+#
+# CPU selection
+#
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS64 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_VTAG_ICACHE is not set
+CONFIG_64BIT_PHYS_ADDR=y
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+# CONFIG_CPU_HAS_LLDSCD is not set
+# CONFIG_CPU_HAS_WB is not set
+CONFIG_CPU_HAS_SYNC=y
+
+#
+# General setup
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NET=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_NEW is not set
+CONFIG_PCI_AUTO=y
+# CONFIG_ISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_MIPS32_COMPAT is not set
+# CONFIG_MIPS32_O32 is not set
+# CONFIG_MIPS32_N32 is not set
+# CONFIG_BINFMT_ELF32 is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_OOM_KILLER is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="ide3=dma mem=96M root=/dev/hda2 rootflags=data=journal"
+# CONFIG_PM is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
+# CONFIG_CISS_MONITOR_THREAD is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_BLK_STATS is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+
+#
+#   IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+
+#
+#    SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+
+#
+# Appletalk devices
+#
+# CONFIG_DEV_APPLETALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+CONFIG_BLK_DEV_HD_IDE=y
+CONFIG_BLK_DEV_HD=y
+CONFIG_BLK_DEV_IDEDISK=y
+CONFIG_IDEDISK_MULTI_MODE=y
+CONFIG_IDEDISK_STROKE=y
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_BLK_DEV_IDE_AU1XXX=y
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+# CONFIG_BLK_DEV_ATARAID_MEDLEY is not set
+# CONFIG_BLK_DEV_ATARAID_SII is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+CONFIG_CHR_DEV_ST=y
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_SR_EXTRA_DEVS=2
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_MEGARAID2 is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_BOOT is not set
+# CONFIG_FUSION_ISENSE is not set
+# CONFIG_FUSION_CTL is not set
+# CONFIG_FUSION_LAN is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_MIPS_AU1X00_ENET is not set
+CONFIG_AU1XXX_SMC91111=m
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBDEV=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_UINPUT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_COMPUTONE is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_DIGI is not set
+# CONFIG_ESPSERIAL is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
+# CONFIG_SYNCLINK is not set
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_SX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+# CONFIG_SERIAL_TX3912 is not set
+# CONFIG_SERIAL_TX3912_CONSOLE is not set
+# CONFIG_SERIAL_TXX9 is not set
+# CONFIG_SERIAL_TXX9_CONSOLE is not set
+CONFIG_AU1X00_UART=y
+CONFIG_AU1X00_SERIAL_CONSOLE=y
+# CONFIG_AU1X00_USB_TTY is not set
+# CONFIG_AU1X00_USB_RAW is not set
+# CONFIG_TXX927_SERIAL is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_ALGOPCF is not set
+CONFIG_I2C_ALGO_AU1550=y
+# CONFIG_I2C_CHARDEV is not set
+# CONFIG_I2C_PROC is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_INPUT_NS558 is not set
+# CONFIG_INPUT_LIGHTNING is not set
+# CONFIG_INPUT_PCIGAME is not set
+# CONFIG_INPUT_CS461X is not set
+# CONFIG_INPUT_EMU10K1 is not set
+# CONFIG_INPUT_SERIO is not set
+# CONFIG_INPUT_SERPORT is not set
+# CONFIG_INPUT_ANALOG is not set
+# CONFIG_INPUT_A3D is not set
+# CONFIG_INPUT_ADI is not set
+# CONFIG_INPUT_COBRA is not set
+# CONFIG_INPUT_GF2K is not set
+# CONFIG_INPUT_GRIP is not set
+# CONFIG_INPUT_INTERACT is not set
+# CONFIG_INPUT_TMDC is not set
+# CONFIG_INPUT_SIDEWINDER is not set
+# CONFIG_INPUT_IFORCE_USB is not set
+# CONFIG_INPUT_IFORCE_232 is not set
+# CONFIG_INPUT_WARRIOR is not set
+# CONFIG_INPUT_MAGELLAN is not set
+# CONFIG_INPUT_SPACEORB is not set
+# CONFIG_INPUT_SPACEBALL is not set
+# CONFIG_INPUT_STINGER is not set
+# CONFIG_INPUT_DB9 is not set
+# CONFIG_INPUT_GAMECON is not set
+# CONFIG_INPUT_TURBOGRAFX is not set
+# CONFIG_QIC02_TAPE is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_IPMI_PANIC_EVENT is not set
+# CONFIG_IPMI_DEVICE_INTERFACE is not set
+# CONFIG_IPMI_KCS is not set
+# CONFIG_IPMI_WATCHDOG is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_SCx200 is not set
+# CONFIG_SCx200_GPIO is not set
+# CONFIG_AMD_PM768 is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+
+#
+# Direct Rendering Manager (XFree86 DRI support)
+#
+# CONFIG_DRM is not set
+# CONFIG_AU1X00_GPIO is not set
+# CONFIG_TS_AU1X00_ADS7846 is not set
+# CONFIG_AU1550_PSC_SPI is not set
+# CONFIG_AU1XXX_MAE is not set
+# CONFIG_AU1XXX_AES is not set
+# CONFIG_AU1XXX_CIM is not set
+# CONFIG_AU1XXX_AES_TEST is not set
+# CONFIG_AU1XXX_BUTTONS is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_AUTOFS_FS=y
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BEFS_DEBUG is not set
+# CONFIG_BFS_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_TRACE is not set
+# CONFIG_XFS_DEBUG is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+# CONFIG_NFS_FS is not set
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+# CONFIG_NFSD_TCP is not set
+# CONFIG_SUNRPC is not set
+# CONFIG_LOCKD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Console drivers
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_CYBER2000 is not set
+CONFIG_FB_AU1200=y
+CONFIG_FB_AU1200_DEVS=4
+CONFIG_FOCUS_ENHANCEMENTS=y
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_FBCON_ADVANCED=y
+# CONFIG_FBCON_MFB is not set
+# CONFIG_FBCON_CFB2 is not set
+# CONFIG_FBCON_CFB4 is not set
+# CONFIG_FBCON_CFB8 is not set
+CONFIG_FBCON_CFB16=y
+# CONFIG_FBCON_CFB24 is not set
+# CONFIG_FBCON_CFB32 is not set
+# CONFIG_FBCON_AFB is not set
+# CONFIG_FBCON_ILBM is not set
+# CONFIG_FBCON_IPLAN2P2 is not set
+# CONFIG_FBCON_IPLAN2P4 is not set
+# CONFIG_FBCON_IPLAN2P8 is not set
+# CONFIG_FBCON_MAC is not set
+# CONFIG_FBCON_VGA_PLANES is not set
+# CONFIG_FBCON_VGA is not set
+# CONFIG_FBCON_HGA is not set
+# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
+CONFIG_FBCON_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+# CONFIG_SOUND_ALI5455 is not set
+# CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_CMPCI is not set
+# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
+# CONFIG_SOUND_FUSION is not set
+# CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ES1370 is not set
+# CONFIG_SOUND_ES1371 is not set
+# CONFIG_SOUND_ESSSOLO1 is not set
+# CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_FORTE is not set
+# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
+# CONFIG_SOUND_SONICVIBES is not set
+# CONFIG_SOUND_AU1X00 is not set
+# CONFIG_SOUND_AU1550_PSC is not set
+CONFIG_SOUND_AU1550_I2S=y
+# CONFIG_SOUND_TRIDENT is not set
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_TVMIXER is not set
+# CONFIG_SOUND_AD1980 is not set
+# CONFIG_SOUND_WM97XX is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# Support for USB gadgets
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+# CONFIG_MMC_AU1100 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_RUNTIME_DEBUG is not set
+# CONFIG_KGDB is not set
+# CONFIG_GDB_CONSOLE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_MIPS_UNCACHED is not set
+CONFIG_LOG_BUF_SHIFT=0
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC32 is not set
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
diff -urN linux/arch/mips/defconfig-pb1200 linux/arch/mips/defconfig-pb1200
--- linux/arch/mips/Attic/defconfig-pb1200      1970/01/01 00:00:00
+++ linux/arch/mips/Attic/defconfig-pb1200      Sun Jan 30 08:01:27 2005        
1.1.2.1
@@ -0,0 +1,1063 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+# CONFIG_MIPS64 is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_FICMMP is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+CONFIG_MIPS_PB1200=y
+# CONFIG_MIPS_HYDROGEN3 is not set
+# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_COGENT_CSB250 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_CASIO_E55 is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_IBM_WORKPAD is not set
+# CONFIG_LASAT is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_MOMENCO_OCELOT_G is not set
+# CONFIG_MOMENCO_OCELOT_C is not set
+# CONFIG_MOMENCO_JAGUAR_ATX is not set
+# CONFIG_PMC_BIG_SUR is not set
+# CONFIG_PMC_STRETCH is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_NEC_EAGLE is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_NINO is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SIBYTE_SB1xxx_SOC is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TANBAC_TB0226 is not set
+# CONFIG_TANBAC_TB0229 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_VICTOR_MPC30X is not set
+# CONFIG_ZAO_CAPCELLA is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_SOC_AU1X00=y
+CONFIG_SOC_AU1200=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_PC_KEYB=y
+# CONFIG_MIPS_AU1000 is not set
+
+#
+# CPU selection
+#
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS64 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_VTAG_ICACHE is not set
+CONFIG_64BIT_PHYS_ADDR=y
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+# CONFIG_CPU_HAS_LLDSCD is not set
+# CONFIG_CPU_HAS_WB is not set
+CONFIG_CPU_HAS_SYNC=y
+
+#
+# General setup
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_BUILD_ELF64 is not set
+CONFIG_NET=y
+CONFIG_PCI=y
+CONFIG_PCI_NEW=y
+CONFIG_PCI_AUTO=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_ISA is not set
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_HOTPLUG=y
+
+#
+# PCMCIA/CardBus support
+#
+CONFIG_PCMCIA=m
+# CONFIG_CARDBUS is not set
+# CONFIG_TCIC is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+CONFIG_PCMCIA_AU1X00=m
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_HOTPLUG_PCI_COMPAQ is not set
+# CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+# CONFIG_HOTPLUG_PCI_SHPC_POLL_EVENT_MODE is not set
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_HOTPLUG_PCI_PCIE_POLL_EVENT_MODE is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_MIPS32_COMPAT is not set
+# CONFIG_MIPS32_O32 is not set
+# CONFIG_MIPS32_N32 is not set
+# CONFIG_BINFMT_ELF32 is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_OOM_KILLER is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="mem=96M"
+# CONFIG_PM is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
+# CONFIG_CISS_MONITOR_THREAD is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_BLK_STATS is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+
+#
+#   IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+
+#
+#    SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+# CONFIG_PHONE_IXJ is not set
+# CONFIG_PHONE_IXJ_PCMCIA is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+CONFIG_IDEDISK_MULTI_MODE=y
+CONFIG_IDEDISK_STROKE=y
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+# CONFIG_BLK_DEV_ATARAID_MEDLEY is not set
+# CONFIG_BLK_DEV_ATARAID_SII is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+CONFIG_CHR_DEV_ST=y
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_SR_EXTRA_DEVS=2
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_MEGARAID2 is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_SATA_AHCI is not set
+# CONFIG_SCSI_SATA_SVW is not set
+# CONFIG_SCSI_ATA_PIIX is not set
+# CONFIG_SCSI_SATA_NV is not set
+# CONFIG_SCSI_SATA_PROMISE is not set
+# CONFIG_SCSI_SATA_SX4 is not set
+# CONFIG_SCSI_SATA_SIL is not set
+# CONFIG_SCSI_SATA_SIS is not set
+# CONFIG_SCSI_SATA_ULI is not set
+# CONFIG_SCSI_SATA_VIA is not set
+# CONFIG_SCSI_SATA_VITESSE is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# PCMCIA SCSI adapter support
+#
+# CONFIG_SCSI_PCMCIA is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_BOOT is not set
+# CONFIG_FUSION_ISENSE is not set
+# CONFIG_FUSION_CTL is not set
+# CONFIG_FUSION_LAN is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_MIPS_AU1X00_ENET is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+# CONFIG_PPP_BSDCOMP is not set
+CONFIG_PPPOE=m
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# PCMCIA network device support
+#
+# CONFIG_NET_PCMCIA is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input core support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBDEV=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_UINPUT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_COMPUTONE is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_DIGI is not set
+# CONFIG_ESPSERIAL is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
+# CONFIG_SYNCLINK is not set
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_SX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+# CONFIG_SERIAL_TX3912 is not set
+# CONFIG_SERIAL_TX3912_CONSOLE is not set
+# CONFIG_SERIAL_TXX9 is not set
+# CONFIG_SERIAL_TXX9_CONSOLE is not set
+CONFIG_AU1X00_UART=y
+CONFIG_AU1X00_SERIAL_CONSOLE=y
+# CONFIG_AU1X00_USB_TTY is not set
+# CONFIG_AU1X00_USB_RAW is not set
+# CONFIG_TXX927_SERIAL is not set
+# CONFIG_MIPS_HYDROGEN3_BUTTONS is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_PROC=y
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_INPUT_NS558 is not set
+# CONFIG_INPUT_LIGHTNING is not set
+# CONFIG_INPUT_PCIGAME is not set
+# CONFIG_INPUT_CS461X is not set
+# CONFIG_INPUT_EMU10K1 is not set
+# CONFIG_INPUT_SERIO is not set
+# CONFIG_INPUT_SERPORT is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_ANALOG is not set
+# CONFIG_INPUT_A3D is not set
+# CONFIG_INPUT_ADI is not set
+# CONFIG_INPUT_COBRA is not set
+# CONFIG_INPUT_GF2K is not set
+# CONFIG_INPUT_GRIP is not set
+# CONFIG_INPUT_INTERACT is not set
+# CONFIG_INPUT_TMDC is not set
+# CONFIG_INPUT_SIDEWINDER is not set
+# CONFIG_INPUT_IFORCE_USB is not set
+# CONFIG_INPUT_IFORCE_232 is not set
+# CONFIG_INPUT_WARRIOR is not set
+# CONFIG_INPUT_MAGELLAN is not set
+# CONFIG_INPUT_SPACEORB is not set
+# CONFIG_INPUT_SPACEBALL is not set
+# CONFIG_INPUT_STINGER is not set
+# CONFIG_INPUT_DB9 is not set
+# CONFIG_INPUT_GAMECON is not set
+# CONFIG_INPUT_TURBOGRAFX is not set
+# CONFIG_QIC02_TAPE is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_IPMI_PANIC_EVENT is not set
+# CONFIG_IPMI_DEVICE_INTERFACE is not set
+# CONFIG_IPMI_KCS is not set
+# CONFIG_IPMI_WATCHDOG is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_SCx200 is not set
+# CONFIG_SCx200_GPIO is not set
+# CONFIG_AMD_PM768 is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+
+#
+# Direct Rendering Manager (XFree86 DRI support)
+#
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_PCMCIA_SERIAL_CS is not set
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_AU1X00_GPIO is not set
+# CONFIG_TS_AU1X00_ADS7846 is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_AUTOFS_FS=y
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BEFS_DEBUG is not set
+# CONFIG_BFS_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+CONFIG_RAMFS=y
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_TRACE is not set
+# CONFIG_XFS_DEBUG is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_DIRECTIO is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+# CONFIG_NFSD_TCP is not set
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Console drivers
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+
+#
+# Frame-buffer support
+#
+CONFIG_FB=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_CLGEN is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_INTEL is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_E1356 is not set
+# CONFIG_FB_IT8181 is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_FBCON_ADVANCED=y
+# CONFIG_FBCON_MFB is not set
+# CONFIG_FBCON_CFB2 is not set
+# CONFIG_FBCON_CFB4 is not set
+# CONFIG_FBCON_CFB8 is not set
+CONFIG_FBCON_CFB16=y
+# CONFIG_FBCON_CFB24 is not set
+CONFIG_FBCON_CFB32=y
+# CONFIG_FBCON_AFB is not set
+# CONFIG_FBCON_ILBM is not set
+# CONFIG_FBCON_IPLAN2P2 is not set
+# CONFIG_FBCON_IPLAN2P4 is not set
+# CONFIG_FBCON_IPLAN2P8 is not set
+# CONFIG_FBCON_MAC is not set
+# CONFIG_FBCON_VGA_PLANES is not set
+# CONFIG_FBCON_VGA is not set
+# CONFIG_FBCON_HGA is not set
+# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
+CONFIG_FBCON_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+# CONFIG_SOUND_ALI5455 is not set
+# CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_CMPCI is not set
+# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
+# CONFIG_SOUND_FUSION is not set
+# CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ES1370 is not set
+# CONFIG_SOUND_ES1371 is not set
+# CONFIG_SOUND_ESSSOLO1 is not set
+# CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_FORTE is not set
+# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
+# CONFIG_SOUND_SONICVIBES is not set
+# CONFIG_SOUND_AU1X00 is not set
+CONFIG_SOUND_AU1550_PSC=y
+# CONFIG_SOUND_AU1550_I2S is not set
+# CONFIG_SOUND_TRIDENT is not set
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+# CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_TVMIXER is not set
+# CONFIG_SOUND_AD1980 is not set
+# CONFIG_SOUND_WM97XX is not set
+
+#
+# USB support
+#
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+CONFIG_USB_OHCI=y
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_MIDI is not set
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+CONFIG_USB_HID=y
+CONFIG_USB_HIDINPUT=y
+CONFIG_USB_HIDDEV=y
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_TIGL is not set
+# CONFIG_USB_BRLVGER is not set
+# CONFIG_USB_LCD is not set
+
+#
+# Support for USB gadgets
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_RUNTIME_DEBUG is not set
+# CONFIG_KGDB is not set
+# CONFIG_GDB_CONSOLE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_MIPS_UNCACHED is not set
+CONFIG_LOG_BUF_SHIFT=0
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC32 is not set
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+# CONFIG_FW_LOADER is not set
diff -urN linux/arch/mips/Makefile linux/arch/mips/Makefile
--- linux/arch/mips/Makefile    2004/11/18 04:16:52     1.78.2.59
+++ linux/arch/mips/Makefile    2005/01/30 08:01:26     1.78.2.60
@@ -211,7 +211,7 @@
 endif
 
 #
-# Au1000 (Alchemy Semi PB1000) eval board
+# Au1x AMD Alchemy eval boards
 #
 ifdef CONFIG_MIPS_PB1000
 LIBS           += arch/mips/au1000/pb1000/pb1000.o \
@@ -220,9 +220,6 @@
 LOADADDR       := 0x80100000
 endif
 
-#
-# Au1100 (Alchemy Semi PB1100) eval board
-#
 ifdef CONFIG_MIPS_PB1100
 LIBS          += arch/mips/au1000/pb1100/pb1100.o \
                  arch/mips/au1000/common/au1000.o
@@ -230,9 +227,6 @@
 LOADADDR      += 0x80100000
 endif
 
-#
-# Au1500 (Alchemy Semi PB1500) eval board
-#
 ifdef CONFIG_MIPS_PB1500
 LIBS           += arch/mips/au1000/pb1500/pb1500.o \
                   arch/mips/au1000/common/au1000.o
@@ -240,9 +234,6 @@
 LOADADDR       := 0x80100000
 endif
 
-#
-# Au1x00 (AMD/Alchemy) eval boards
-#
 ifdef CONFIG_MIPS_DB1000
 LIBS          += arch/mips/au1000/db1x00/db1x00.o \
                  arch/mips/au1000/common/au1000.o
@@ -313,6 +304,27 @@
 LOADADDR      += 0x80100000
 endif
 
+ifdef CONFIG_MIPS_PB1200
+LIBS          += arch/mips/au1000/pb1200/pb1200.o \
+                 arch/mips/au1000/common/au1000.o
+SUBDIRS       += arch/mips/au1000/pb1200 arch/mips/au1000/common
+LOADADDR      += 0x80100000
+endif
+
+ifdef CONFIG_MIPS_DB1200
+LIBS          += arch/mips/au1000/pb1200/pb1200.o \
+                 arch/mips/au1000/common/au1000.o
+SUBDIRS       += arch/mips/au1000/pb1200 arch/mips/au1000/common
+LOADADDR      += 0x80100000
+endif
+
+ifdef CONFIG_MIPS_FICMMP
+LIBS          += arch/mips/au1000/ficmmp/ficmmp.o \
+                 arch/mips/au1000/common/au1000.o
+SUBDIRS       += arch/mips/au1000/ficmmp arch/mips/au1000/common
+LOADADDR      += 0x80100000
+endif
+
 
 #
 # Cogent CSB250
diff -urN linux/arch/mips/config-shared.in linux/arch/mips/config-shared.in
--- linux/arch/mips/Attic/config-shared.in      2004/11/19 00:28:32     
1.1.2.126
+++ linux/arch/mips/Attic/config-shared.in      2005/01/30 08:01:26     
1.1.2.127
@@ -21,16 +21,19 @@
 comment 'Machine selection'
 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 
$CONFIG_EXPERIMENTAL
 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS 
$CONFIG_MIPS32
+dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP 
$CONFIG_MIPS32
 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
 dep_bool 'Support for Alchemy Db1000 board' CONFIG_MIPS_DB1000 $CONFIG_MIPS32
 dep_bool 'Support for Alchemy Db1100 board' CONFIG_MIPS_DB1100 $CONFIG_MIPS32
 dep_bool 'Support for Alchemy Db1500 board' CONFIG_MIPS_DB1500 $CONFIG_MIPS32
 dep_bool 'Support for Alchemy Db1550 board' CONFIG_MIPS_DB1550 $CONFIG_MIPS32
+dep_bool 'Support for Alchemy Db1200 board' CONFIG_MIPS_DB1200 $CONFIG_MIPS32
 dep_bool 'Support for Alchemy PB1000 board' CONFIG_MIPS_PB1000 $CONFIG_MIPS32
 dep_bool 'Support for Alchemy PB1100 board' CONFIG_MIPS_PB1100 $CONFIG_MIPS32
 dep_bool 'Support for Alchemy PB1500 board' CONFIG_MIPS_PB1500 $CONFIG_MIPS32
-dep_bool 'Support for Alchemy Hydrogen3 board' CONFIG_MIPS_HYDROGEN3 
$CONFIG_MIPS32
 dep_bool 'Support for Alchemy PB1550 board' CONFIG_MIPS_PB1550 $CONFIG_MIPS32
+dep_bool 'Support for Alchemy PB1200 board' CONFIG_MIPS_PB1200 $CONFIG_MIPS32
+dep_bool 'Support for Alchemy Hydrogen3 board' CONFIG_MIPS_HYDROGEN3 
$CONFIG_MIPS32
 dep_bool 'Support for MyCable XXS1500 board' CONFIG_MIPS_XXS1500 $CONFIG_MIPS32
 dep_bool 'Support for 4G Systems MTX-1 board' CONFIG_MIPS_MTX1 $CONFIG_MIPS32
 dep_bool 'Support for Cogent CSB250 board' CONFIG_COGENT_CSB250 $CONFIG_MIPS32
@@ -249,6 +252,12 @@
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_NONCOHERENT_IO y
 fi
+if [ "$CONFIG_MIPS_FICMMP" = "y" ]; then
+   define_bool CONFIG_SOC_AU1X00 y
+   define_bool CONFIG_SOC_AU1200 y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_PC_KEYB y
+fi
 if [ "$CONFIG_MIPS_BOSPORUS" = "y" ]; then
    define_bool CONFIG_SOC_AU1X00 y
    define_bool CONFIG_SOC_AU1500 y
@@ -263,6 +272,12 @@
    define_bool CONFIG_SWAP_IO_SPACE_W y
    define_bool CONFIG_SWAP_IO_SPACE_L y
 fi
+if [ "$CONFIG_MIPS_PB1500" = "y" ]; then
+   define_bool CONFIG_SOC_AU1X00 y
+   define_bool CONFIG_SOC_AU1500 y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_PC_KEYB y
+fi
 if [ "$CONFIG_MIPS_PB1100" = "y" ]; then
    define_bool CONFIG_SOC_AU1X00 y
    define_bool CONFIG_SOC_AU1100 y
@@ -271,9 +286,15 @@
    define_bool CONFIG_SWAP_IO_SPACE_W y
    define_bool CONFIG_SWAP_IO_SPACE_L y
 fi
-if [ "$CONFIG_MIPS_PB1500" = "y" ]; then
+if [ "$CONFIG_MIPS_PB1550" = "y" ]; then
    define_bool CONFIG_SOC_AU1X00 y
-   define_bool CONFIG_SOC_AU1500 y
+   define_bool CONFIG_SOC_AU1550 y
+   define_bool CONFIG_NONCOHERENT_IO n
+   define_bool CONFIG_PC_KEYB y
+fi
+if [ "$CONFIG_MIPS_PB1200" = "y" ]; then
+   define_bool CONFIG_SOC_AU1X00 y
+   define_bool CONFIG_SOC_AU1200 y
    define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
 fi
@@ -290,18 +311,24 @@
    define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
 fi
+if [ "$CONFIG_MIPS_DB1100" = "y" ]; then
+   define_bool CONFIG_SOC_AU1X00 y
+   define_bool CONFIG_SOC_AU1100 y
+   define_bool CONFIG_NONCOHERENT_IO y
+   define_bool CONFIG_PC_KEYB y
+   define_bool CONFIG_SWAP_IO_SPACE y
+fi
 if [ "$CONFIG_MIPS_DB1550" = "y" ]; then
    define_bool CONFIG_SOC_AU1X00 y
    define_bool CONFIG_SOC_AU1550 y
    define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
 fi
-if [ "$CONFIG_MIPS_DB1100" = "y" ]; then
+if [ "$CONFIG_MIPS_DB1200" = "y" ]; then
    define_bool CONFIG_SOC_AU1X00 y
-   define_bool CONFIG_SOC_AU1100 y
+   define_bool CONFIG_SOC_AU1200 y
    define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
-   define_bool CONFIG_SWAP_IO_SPACE y
 fi
 if [ "$CONFIG_MIPS_HYDROGEN3" = "y" ]; then
    define_bool CONFIG_SOC_AU1X00 y
@@ -327,12 +354,6 @@
    define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PC_KEYB y
 fi
-if [ "$CONFIG_MIPS_PB1550" = "y" ]; then
-   define_bool CONFIG_SOC_AU1X00 y
-   define_bool CONFIG_SOC_AU1550 y
-   define_bool CONFIG_NONCOHERENT_IO n
-   define_bool CONFIG_PC_KEYB y
-fi
 if [ "$CONFIG_MIPS_COBALT" = "y" ]; then
    define_bool CONFIG_BOOT_ELF32 y
    define_bool CONFIG_COBALT_LCD y
@@ -729,6 +750,13 @@
      "$CONFIG_MIPS_PB1000" = "y" -o \
      "$CONFIG_MIPS_PB1100" = "y" -o \
      "$CONFIG_MIPS_PB1500" = "y" -o \
+     "$CONFIG_MIPS_PB1550" = "y" -o \
+     "$CONFIG_MIPS_PB1200" = "y" -o \
+     "$CONFIG_MIPS_DB1000" = "y" -o \
+     "$CONFIG_MIPS_DB1100" = "y" -o \
+     "$CONFIG_MIPS_DB1500" = "y" -o \
+     "$CONFIG_MIPS_DB1550" = "y" -o \
+     "$CONFIG_MIPS_DB1200" = "y" -o \
      "$CONFIG_NEC_OSPREY" = "y" -o \
      "$CONFIG_NEC_EAGLE" = "y" -o \
      "$CONFIG_NINO" = "y" -o \
diff -urN linux/arch/mips/defconfig-bosporus linux/arch/mips/defconfig-bosporus
--- linux/arch/mips/Attic/defconfig-bosporus    2005/01/20 02:19:22     1.1.2.41
+++ linux/arch/mips/Attic/defconfig-bosporus    2005/01/30 08:01:26     1.1.2.42
@@ -895,7 +895,7 @@
 # CONFIG_USB_UHCI is not set
 # CONFIG_USB_UHCI_ALT is not set
 CONFIG_USB_OHCI=y
-
+CONFIG_USB_NON_PCI_OHCI=y
 #
 # USB Device Class drivers
 #
diff -urN linux/arch/mips/defconfig-db1000 linux/arch/mips/defconfig-db1000
--- linux/arch/mips/Attic/defconfig-db1000      2005/01/09 19:33:59     1.1.2.54
+++ linux/arch/mips/Attic/defconfig-db1000      2005/01/30 08:01:26     1.1.2.55
@@ -926,7 +926,7 @@
 # CONFIG_USB_UHCI is not set
 # CONFIG_USB_UHCI_ALT is not set
 CONFIG_USB_OHCI=y
-
+CONFIG_USB_NON_PCI_OHCI=y
 #
 # USB Device Class drivers
 #
diff -urN linux/arch/mips/defconfig-db1100 linux/arch/mips/defconfig-db1100
--- linux/arch/mips/Attic/defconfig-db1100      2005/01/09 19:33:59     1.1.2.45
+++ linux/arch/mips/Attic/defconfig-db1100      2005/01/30 08:01:26     1.1.2.46
@@ -967,7 +967,7 @@
 # CONFIG_USB_UHCI is not set
 # CONFIG_USB_UHCI_ALT is not set
 CONFIG_USB_OHCI=y
-
+CONFIG_USB_NON_PCI_OHCI=y
 #
 # USB Device Class drivers
 #
diff -urN linux/arch/mips/defconfig-db1500 linux/arch/mips/defconfig-db1500
--- linux/arch/mips/Attic/defconfig-db1500      2005/01/09 19:33:59     1.1.2.58
+++ linux/arch/mips/Attic/defconfig-db1500      2005/01/30 08:01:26     1.1.2.59
@@ -802,7 +802,7 @@
 # CONFIG_USB_UHCI is not set
 # CONFIG_USB_UHCI_ALT is not set
 CONFIG_USB_OHCI=y
-
+CONFIG_USB_NON_PCI_OHCI=y
 #
 # USB Device Class drivers
 #
diff -urN linux/arch/mips/defconfig-db1550 linux/arch/mips/defconfig-db1550
--- linux/arch/mips/Attic/defconfig-db1550      2005/01/09 19:33:59     1.1.2.12
+++ linux/arch/mips/Attic/defconfig-db1550      2005/01/30 08:01:26     1.1.2.13
@@ -883,6 +883,7 @@
 # CONFIG_FB_ATY128 is not set
 # CONFIG_FB_INTEL is not set
 # CONFIG_FB_SIS is not set
+CONFIG_FB_SMI501=y
 # CONFIG_FB_NEOMAGIC is not set
 # CONFIG_FB_3DFX is not set
 # CONFIG_FB_VOODOO1 is not set
@@ -964,7 +965,7 @@
 # CONFIG_USB_UHCI is not set
 # CONFIG_USB_UHCI_ALT is not set
 CONFIG_USB_OHCI=y
-
+CONFIG_USB_NON_PCI_OHCI=y
 #
 # USB Device Class drivers
 #
diff -urN linux/arch/mips/defconfig-hydrogen3 
linux/arch/mips/defconfig-hydrogen3
--- linux/arch/mips/Attic/defconfig-hydrogen3   2005/01/09 19:33:59     1.1.2.24
+++ linux/arch/mips/Attic/defconfig-hydrogen3   2005/01/30 08:01:26     1.1.2.25
@@ -22,6 +22,7 @@
 #
 # CONFIG_ACER_PICA_61 is not set
 # CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_FICMMP is not set
 # CONFIG_MIPS_MIRAGE is not set
 # CONFIG_MIPS_DB1000 is not set
 # CONFIG_MIPS_DB1100 is not set
@@ -30,9 +31,11 @@
 # CONFIG_MIPS_PB1000 is not set
 # CONFIG_MIPS_PB1100 is not set
 # CONFIG_MIPS_PB1500 is not set
-CONFIG_MIPS_HYDROGEN3=y
 # CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_PB1200 is not set
+CONFIG_MIPS_HYDROGEN3=y
 # CONFIG_MIPS_XXS1500 is not set
+# CONFIG_MIPS_EP1000 is not set
 # CONFIG_MIPS_MTX1 is not set
 # CONFIG_COGENT_CSB250 is not set
 # CONFIG_BAGET_MIPS is not set
@@ -185,6 +188,7 @@
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -196,6 +200,7 @@
 # CONFIG_MTD_CFI_INTELEXT is not set
 CONFIG_MTD_CFI_AMDSTD=y
 # CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
@@ -207,17 +212,12 @@
 #
 # Mapping drivers for chip access
 #
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
 # CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_PB1000 is not set
-# CONFIG_MTD_PB1500 is not set
-# CONFIG_MTD_PB1100 is not set
-# CONFIG_MTD_BOSPORUS is not set
-# CONFIG_MTD_XXS1500 is not set
-# CONFIG_MTD_MTX1 is not set
-# CONFIG_MTD_DB1X00 is not set
 # CONFIG_MTD_PB1550 is not set
-CONFIG_MTD_HYDROGEN3=y
-# CONFIG_MTD_MIRAGE is not set
+# CONFIG_MTD_DB1550 is not set
+# CONFIG_MTD_PB1200 is not set
+# CONFIG_MTD_XXS1500 is not set
 # CONFIG_MTD_CSTM_MIPS_IXX is not set
 # CONFIG_MTD_OCELOT is not set
 # CONFIG_MTD_LASAT is not set
@@ -235,9 +235,9 @@
 #
 # Disk-On-Chip Device Drivers
 #
-# CONFIG_MTD_DOC1000 is not set
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
 # CONFIG_MTD_DOCPROBE is not set
 
 #
@@ -381,6 +381,7 @@
 #
 # Please see Documentation/ide.txt for help/info on IDE drives
 #
+# CONFIG_BLK_DEV_IDE_AU1XXX is not set
 # CONFIG_BLK_DEV_HD_IDE is not set
 # CONFIG_BLK_DEV_HD is not set
 # CONFIG_BLK_DEV_IDE_SATA is not set
@@ -398,6 +399,7 @@
 #
 # IDE chipset support/bugfixes
 #
+# CONFIG_BLK_DEV_IDE_AU1XXX is not set
 # CONFIG_BLK_DEV_CMD640 is not set
 # CONFIG_BLK_DEV_CMD640_ENHANCED is not set
 # CONFIG_BLK_DEV_ISAPNP is not set
@@ -585,7 +587,6 @@
 # CONFIG_AU1X00_USB_TTY is not set
 # CONFIG_AU1X00_USB_RAW is not set
 # CONFIG_TXX927_SERIAL is not set
-CONFIG_MIPS_HYDROGEN3_BUTTONS=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_UNIX98_PTY_COUNT=256
 
@@ -672,6 +673,12 @@
 # CONFIG_SYNCLINK_CS is not set
 # CONFIG_AU1X00_GPIO is not set
 # CONFIG_TS_AU1X00_ADS7846 is not set
+# CONFIG_AU1550_PSC_SPI is not set
+# CONFIG_AU1XXX_MAE is not set
+# CONFIG_AU1XXX_AES is not set
+# CONFIG_AU1XXX_CIM is not set
+# CONFIG_AU1XXX_AES_TEST is not set
+CONFIG_AU1XXX_BUTTONS=y
 
 #
 # File systems
@@ -833,18 +840,20 @@
 # CONFIG_FB_PM2 is not set
 # CONFIG_FB_PM3 is not set
 # CONFIG_FB_CYBER2000 is not set
+CONFIG_FB_AU1100=y
+# CONFIG_FOCUS_ENHANCEMENTS is not set
 # CONFIG_FB_MATROX is not set
 # CONFIG_FB_ATY is not set
 # CONFIG_FB_RADEON is not set
 # CONFIG_FB_ATY128 is not set
 # CONFIG_FB_INTEL is not set
 # CONFIG_FB_SIS is not set
+# CONFIG_FB_SMI501 is not set
 # CONFIG_FB_NEOMAGIC is not set
 # CONFIG_FB_3DFX is not set
 # CONFIG_FB_VOODOO1 is not set
 # CONFIG_FB_TRIDENT is not set
 # CONFIG_FB_E1356 is not set
-CONFIG_FB_AU1100=y
 # CONFIG_FB_IT8181 is not set
 # CONFIG_FB_VIRTUAL is not set
 CONFIG_FBCON_ADVANCED=y
@@ -918,9 +927,11 @@
 # USB Host Controller Drivers
 #
 # CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_NON_PCI_EHCI is not set
 # CONFIG_USB_UHCI is not set
 # CONFIG_USB_UHCI_ALT is not set
 CONFIG_USB_OHCI=y
+CONFIG_USB_NON_PCI_OHCI=y
 
 #
 # USB Device Class drivers
diff -urN linux/arch/mips/defconfig-mirage linux/arch/mips/defconfig-mirage
--- linux/arch/mips/Attic/defconfig-mirage      2005/01/09 19:33:59     1.1.2.36
+++ linux/arch/mips/Attic/defconfig-mirage      2005/01/30 08:01:26     1.1.2.37
@@ -858,7 +858,7 @@
 # CONFIG_USB_UHCI is not set
 # CONFIG_USB_UHCI_ALT is not set
 CONFIG_USB_OHCI=y
-
+CONFIG_USB_NON_PCI_OHCI=y
 #
 # USB Device Class drivers
 #
diff -urN linux/arch/mips/defconfig-pb1000 linux/arch/mips/defconfig-pb1000
--- linux/arch/mips/Attic/defconfig-pb1000      2005/01/09 19:33:59     
1.29.2.87
+++ linux/arch/mips/Attic/defconfig-pb1000      2005/01/30 08:01:26     
1.29.2.88
@@ -22,16 +22,19 @@
 #
 # CONFIG_ACER_PICA_61 is not set
 # CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_FICMMP is not set
 # CONFIG_MIPS_MIRAGE is not set
 # CONFIG_MIPS_DB1000 is not set
 # CONFIG_MIPS_DB1100 is not set
 # CONFIG_MIPS_DB1500 is not set
 # CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_DB1200 is not set
 CONFIG_MIPS_PB1000=y
 # CONFIG_MIPS_PB1100 is not set
 # CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_HYDROGEN3 is not set
 # CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_HYDROGEN3 is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_MIPS_MTX1 is not set
 # CONFIG_COGENT_CSB250 is not set
diff -urN linux/arch/mips/defconfig-pb1100 linux/arch/mips/defconfig-pb1100
--- linux/arch/mips/Attic/defconfig-pb1100      2005/01/09 19:33:59     1.1.2.67
+++ linux/arch/mips/Attic/defconfig-pb1100      2005/01/30 08:01:26     1.1.2.68
@@ -942,7 +942,7 @@
 # CONFIG_USB_UHCI is not set
 # CONFIG_USB_UHCI_ALT is not set
 CONFIG_USB_OHCI=y
-
+CONFIG_USB_NON_PCI_OHCI=y
 #
 # USB Device Class drivers
 #
diff -urN linux/arch/mips/defconfig-pb1500 linux/arch/mips/defconfig-pb1500
--- linux/arch/mips/Attic/defconfig-pb1500      2005/01/09 19:33:59     1.1.2.77
+++ linux/arch/mips/Attic/defconfig-pb1500      2005/01/30 08:01:27     1.1.2.78
@@ -928,6 +928,7 @@
 # CONFIG_FB_ATY128 is not set
 # CONFIG_FB_INTEL is not set
 # CONFIG_FB_SIS is not set
+CONFIG_FB_SMI501=y
 # CONFIG_FB_NEOMAGIC is not set
 # CONFIG_FB_3DFX is not set
 # CONFIG_FB_VOODOO1 is not set
@@ -1011,7 +1012,7 @@
 # CONFIG_USB_UHCI is not set
 # CONFIG_USB_UHCI_ALT is not set
 CONFIG_USB_OHCI=y
-
+CONFIG_USB_NON_PCI_OHCI=y
 #
 # USB Device Class drivers
 #
diff -urN linux/arch/mips/defconfig-pb1550 linux/arch/mips/defconfig-pb1550
--- linux/arch/mips/Attic/defconfig-pb1550      2005/01/09 19:33:59     1.1.2.18
+++ linux/arch/mips/Attic/defconfig-pb1550      2005/01/30 08:01:27     1.1.2.19
@@ -883,6 +883,7 @@
 # CONFIG_FB_ATY128 is not set
 # CONFIG_FB_INTEL is not set
 # CONFIG_FB_SIS is not set
+CONFIG_FB_SMI501=y
 # CONFIG_FB_NEOMAGIC is not set
 # CONFIG_FB_3DFX is not set
 # CONFIG_FB_VOODOO1 is not set
@@ -964,7 +965,7 @@
 # CONFIG_USB_UHCI is not set
 # CONFIG_USB_UHCI_ALT is not set
 CONFIG_USB_OHCI=y
-
+CONFIG_USB_NON_PCI_OHCI=y
 #
 # USB Device Class drivers
 #
diff -urN linux/arch/mips/au1000/common/gpio.c 
linux/arch/mips/au1000/common/gpio.c
--- linux/arch/mips/au1000/common/Attic/gpio.c  1970/01/01 00:00:00
+++ linux/arch/mips/au1000/common/Attic/gpio.c  Sun Jan 30 08:01:27 2005        
1.1.2.1
@@ -0,0 +1,118 @@
+/*
+ *  This program is free software; you can redistribute         it and/or 
modify it
+ *  under  the terms of         the GNU General  Public License as published 
by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED          ``AS  IS'' AND   ANY  EXPRESS OR 
IMPLIED
+ *  WARRANTIES,          INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED 
WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED          TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; 
LOSS OF
+ *  USE, DATA, OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN         CONTRACT, STRICT LIABILITY, OR 
TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/au1000.h>
+#include <asm/au1xxx_gpio.h>
+
+#define gpio1 sys
+#if !defined(CONFIG_SOC_AU1000)
+static AU1X00_GPIO2 * const gpio2 = (AU1X00_GPIO2 *)GPIO2_BASE;
+
+#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
+
+int au1xxx_gpio2_read(int signal)
+{
+       signal -= 200;
+/*     gpio2->dir &= ~(0x01 << signal);                                        
        //Set GPIO to input */
+       return ((gpio2->pinstate >> signal) & 0x01);
+}
+
+void au1xxx_gpio2_write(int signal, int value)
+{
+       signal -= 200;
+
+       gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << signal) | 
+               (value << signal);
+}
+
+void au1xxx_gpio2_tristate(int signal)
+{
+       signal -= 200;
+       gpio2->dir &= ~(0x01 << signal);        /* Set GPIO to input */
+}
+#endif
+
+int au1xxx_gpio1_read(int signal)
+{
+/*     gpio1->trioutclr |= (0x01 << signal); */
+       return ((gpio1->pinstaterd >> signal) & 0x01);
+}
+
+void au1xxx_gpio1_write(int signal, int value)
+{
+       if(value)
+               gpio1->outputset = (0x01 << signal);
+       else
+               gpio1->outputclr = (0x01 << signal);    /* Output a Zero */
+}
+
+void au1xxx_gpio1_tristate(int signal)
+{
+       gpio1->trioutclr = (0x01 << signal);            /* Tristate signal */
+}
+
+
+int au1xxx_gpio_read(int signal)
+{
+       if(signal >= 200)
+#if defined(CONFIG_SOC_AU1000)
+               return 0;
+#else
+               return au1xxx_gpio2_read(signal);
+#endif
+       else
+               return au1xxx_gpio1_read(signal);
+}
+
+void au1xxx_gpio_write(int signal, int value)
+{
+       if(signal >= 200)
+#if defined(CONFIG_SOC_AU1000)
+               ;
+#else
+               au1xxx_gpio2_write(signal, value);
+#endif
+       else
+               au1xxx_gpio1_write(signal, value);
+}
+
+void au1xxx_gpio_tristate(int signal)
+{
+       if(signal >= 200)
+#if defined(CONFIG_SOC_AU1000)
+               ;
+#else
+               au1xxx_gpio2_tristate(signal);
+#endif
+       else
+               au1xxx_gpio1_tristate(signal);
+}
+
+void au1xxx_gpio1_set_inputs(void)
+{
+       gpio1->pininputen = 0;
+}
+
+EXPORT_SYMBOL(au1xxx_gpio1_set_inputs);
+EXPORT_SYMBOL(au1xxx_gpio_tristate);
+EXPORT_SYMBOL(au1xxx_gpio_write);
+EXPORT_SYMBOL(au1xxx_gpio_read);
diff -urN linux/arch/mips/au1000/common/Makefile 
linux/arch/mips/au1000/common/Makefile
--- linux/arch/mips/au1000/common/Makefile      2004/07/07 18:19:37     1.5.2.18
+++ linux/arch/mips/au1000/common/Makefile      2005/01/30 08:01:27     1.5.2.19
@@ -19,9 +19,9 @@
 export-objs            = prom.o clocks.o power.o usbdev.o
 
 obj-y := prom.o int-handler.o irq.o puts.o time.o reset.o cputable.o \
-       au1xxx_irqmap.o clocks.o power.o setup.o sleeper.o dma.o dbdma.o
+       au1xxx_irqmap.o clocks.o power.o setup.o sleeper.o dma.o dbdma.o gpio.o
   
-export-objs += dma.o dbdma.o
+export-objs += dma.o dbdma.o gpio.o
 
 obj-$(CONFIG_AU1X00_USB_DEVICE) += usbdev.o
 obj-$(CONFIG_KGDB) += dbg_io.o
diff -urN linux/arch/mips/au1000/common/au1xxx_irqmap.c 
linux/arch/mips/au1000/common/au1xxx_irqmap.c
--- linux/arch/mips/au1000/common/au1xxx_irqmap.c       2004/07/07 18:19:37     
1.1.2.2
+++ linux/arch/mips/au1000/common/au1xxx_irqmap.c       2005/01/30 08:01:27     
1.1.2.3
@@ -172,14 +172,14 @@
        { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
        { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0},
        { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_TOY_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
-       { AU1550_RTC_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
+       { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0},
        { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
@@ -200,14 +200,14 @@
        { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
        { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0},
        { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1200_TOY_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
-       { AU1200_RTC_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
+       { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+       { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0},
        { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
diff -urN linux/arch/mips/au1000/common/cputable.c 
linux/arch/mips/au1000/common/cputable.c
--- linux/arch/mips/au1000/common/cputable.c    2004/07/07 18:19:37     1.1.2.2
+++ linux/arch/mips/au1000/common/cputable.c    2005/01/30 08:01:27     1.1.2.3
@@ -39,7 +39,8 @@
     { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 },
     { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 },
     { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 },
-    { 0xffffffff, 0x04030200, "Au1200 AA", 0, 1 },
+    { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 },
+    { 0xffffffff, 0x04030201, "Au1200 AC", 0, 0 },
     { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 },
 };
 
diff -urN linux/arch/mips/au1000/common/dbdma.c 
linux/arch/mips/au1000/common/dbdma.c
--- linux/arch/mips/au1000/common/dbdma.c       2004/07/14 06:27:07     1.1.2.4
+++ linux/arch/mips/au1000/common/dbdma.c       2005/01/30 08:01:27     1.1.2.5
@@ -41,6 +41,8 @@
 #include <asm/au1xxx_dbdma.h>
 #include <asm/system.h>
 
+#include <linux/module.h>
+
 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
 
 /*
@@ -60,37 +62,10 @@
 */
 #define ALIGN_ADDR(x, a)       ((((u32)(x)) + (a-1)) & ~(a-1))
 
-static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t 
*)DDMA_GLOBAL_BASE;
-static int dbdma_initialized;
+static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
+static int dbdma_initialized=0;
 static void au1xxx_dbdma_init(void);
 
-typedef struct dbdma_device_table {
-       u32             dev_id;
-       u32             dev_flags;
-       u32             dev_tsize;
-       u32             dev_devwidth;
-       u32             dev_physaddr;           /* If FIFO */
-       u32             dev_intlevel;
-       u32             dev_intpolarity;
-} dbdev_tab_t;
-
-typedef struct dbdma_chan_config {
-       u32                     chan_flags;
-       u32                     chan_index;
-       dbdev_tab_t             *chan_src;
-       dbdev_tab_t             *chan_dest;
-       au1x_dma_chan_t         *chan_ptr;
-       au1x_ddma_desc_t        *chan_desc_base;
-       au1x_ddma_desc_t        *get_ptr, *put_ptr, *cur_ptr;
-       void                    *chan_callparam;
-       void (*chan_callback)(int, void *, struct pt_regs *);
-} chan_tab_t;
-
-#define        DEV_FLAGS_INUSE         (1 << 0)
-#define        DEV_FLAGS_ANYUSE        (1 << 1)
-#define DEV_FLAGS_OUT          (1 << 2)
-#define DEV_FLAGS_IN           (1 << 3)
-
 static dbdev_tab_t dbdev_tab[] = {
 #ifdef CONFIG_SOC_AU1550
        /* UARTS */
@@ -156,13 +131,13 @@
        { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
        { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
 
-       { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-       { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-       { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-       { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+       { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
+       { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
+       { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
+       { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
 
-       { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-       { DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+       { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
+       { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
 
        { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
        { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
@@ -172,9 +147,9 @@
        { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
        { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
 
-       { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-       { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
-       { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+       { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
+       { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
+       { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
        { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
 
        { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
@@ -183,6 +158,24 @@
 
        { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
        { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+
+       /* Provide 16 user definable device types */
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
+       { 0, 0, 0, 0, 0, 0, 0 },
 };
 
 #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
@@ -202,6 +195,30 @@
        return NULL;
 }
 
+u32
+au1xxx_ddma_add_device(dbdev_tab_t *dev)
+{
+       u32 ret = 0;
+       dbdev_tab_t *p=NULL;
+       static u16 new_id=0x1000;
+
+       p = find_dbdev_id(0);
+       if ( NULL != p )
+       {
+               memcpy(p, dev, sizeof(dbdev_tab_t));
+               p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
+               ret = p->dev_id;
+               new_id++;
+#if 0
+               printk("add_device: id:%x flags:%x padd:%x\n", 
+                               p->dev_id, p->dev_flags, p->dev_physaddr );
+#endif
+       }
+
+       return ret;
+}
+EXPORT_SYMBOL(au1xxx_ddma_add_device);
+
 /* Allocate a channel and return a non-zero descriptor if successful.
 */
 u32
@@ -214,7 +231,7 @@
        int             i;
        dbdev_tab_t     *stp, *dtp;
        chan_tab_t      *ctp;
-       volatile au1x_dma_chan_t *cp;
+       au1x_dma_chan_t *cp;
 
        /* We do the intialization on the first channel allocation.
         * We have to wait because of the interrupt handler initialization
@@ -224,9 +241,6 @@
                au1xxx_dbdma_init();
        dbdma_initialized = 1;
 
-       if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS))
-               return 0;
-       
        if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
        if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
 
@@ -268,9 +282,9 @@
                                /* If kmalloc fails, it is caught below same
                                 * as a channel not available.
                                 */
-                               ctp = (chan_tab_t *)kmalloc(sizeof(chan_tab_t), 
GFP_KERNEL);
+                               ctp = (chan_tab_t *)
+                                       kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
                                chan_tab_ptr[i] = ctp;
-                               ctp->chan_index = chan = i;
                                break;
                        }
                }
@@ -278,10 +292,11 @@
 
                if (ctp != NULL) {
                        memset(ctp, 0, sizeof(chan_tab_t));
+                       ctp->chan_index = chan = i;
                        dcp = DDMA_CHANNEL_BASE;
                        dcp += (0x0100 * chan);
                        ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
-                       cp = (volatile au1x_dma_chan_t *)dcp;
+                       cp = (au1x_dma_chan_t *)dcp;
                        ctp->chan_src = stp;
                        ctp->chan_dest = dtp;
                        ctp->chan_callback = callback;
@@ -298,6 +313,9 @@
                                i |= DDMA_CFG_DED;
                        if (dtp->dev_intpolarity)
                                i |= DDMA_CFG_DP;
+                       if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
+                               (dtp->dev_flags & DEV_FLAGS_SYNC))
+                                       i |= DDMA_CFG_SYNC;
                        cp->ddma_cfg = i;
                        au_sync();
 
@@ -308,14 +326,14 @@
                        rv = (u32)(&chan_tab_ptr[chan]);
                }
                else {
-                       /* Release devices.
-                       */
+                       /* Release devices */
                        stp->dev_flags &= ~DEV_FLAGS_INUSE;
                        dtp->dev_flags &= ~DEV_FLAGS_INUSE;
                }
        }
        return rv;
 }
+EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
 
 /* Set the device width if source or destination is a FIFO.
  * Should be 8, 16, or 32 bits.
@@ -343,6 +361,7 @@
 
        return rv;
 }
+EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
 
 /* Allocate a descriptor ring, initializing as much as possible.
 */
@@ -369,7 +388,8 @@
         * and if we try that first we are likely to not waste larger
         * slabs of memory.
         */
-       desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), 
GFP_KERNEL);
+       desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), 
+                       GFP_KERNEL|GFP_DMA);
        if (desc_base == 0)
                return 0;
        
@@ -380,7 +400,7 @@
                kfree((const void *)desc_base);
                i = entries * sizeof(au1x_ddma_desc_t);
                i += (sizeof(au1x_ddma_desc_t) - 1);
-               if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0)
+               if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
                        return 0;
 
                desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
@@ -460,9 +480,14 @@
        /* If source input is fifo, set static address.
        */
        if (stp->dev_flags & DEV_FLAGS_IN) {
-               src0 = stp->dev_physaddr;
-               src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
+               if ( stp->dev_flags & DEV_FLAGS_BURSTABLE ) 
+                       src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
+               else 
+                       src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
+
        }
+       if (stp->dev_physaddr) 
+               src0 = stp->dev_physaddr;
 
        /* Set up dest1.  For now, assume no stride and increment.
         * A channel attribute update can change this later.
@@ -486,10 +511,18 @@
        /* If destination output is fifo, set static address.
        */
        if (dtp->dev_flags & DEV_FLAGS_OUT) {
-               dest0 = dtp->dev_physaddr;
+               if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
+                       dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
+                               else
                dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
        }
+       if (dtp->dev_physaddr) 
+               dest0 = dtp->dev_physaddr;
        
+#if 0
+               printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x 
dest0:%x dest1:%x\n",
+                       dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, 
dest0, dest1 );
+#endif
        for (i=0; i<entries; i++) {
                dp->dscr_cmd0 = cmd0;
                dp->dscr_cmd1 = cmd1;
@@ -498,6 +531,7 @@
                dp->dscr_dest0 = dest0;
                dp->dscr_dest1 = dest1;
                dp->dscr_stat = 0;
+                               dp->sw_context = dp->sw_status = 0;
                dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
                dp++;
        }
@@ -510,13 +544,14 @@
 
        return (u32)(ctp->chan_desc_base);
 }
+EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
 
 /* Put a source buffer into the DMA ring.
  * This updates the source pointer and byte count.  Normally used
  * for memory to fifo transfers.
  */
 u32
-au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
+_au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
 {
        chan_tab_t              *ctp;
        au1x_ddma_desc_t        *dp;
@@ -543,24 +578,41 @@
        */
        dp->dscr_source0 = virt_to_phys(buf);
        dp->dscr_cmd1 = nbytes;
-       dp->dscr_cmd0 |= DSCR_CMD0_V;   /* Let it rip */
-       ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */
-       
+       /* Check flags  */
+       if (flags & DDMA_FLAGS_IE) 
+               dp->dscr_cmd0 |= DSCR_CMD0_IE;
+       if (flags & DDMA_FLAGS_NOIE)
+               dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
        /* Get next descriptor pointer.
        */
        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
+       /*
+        * There is an errata on the Au1200/Au1550 parts that could result 
+        * in "stale" data being DMA'd. It has to do with the snoop logic on 
+        * the dache eviction buffer.  NONCOHERENT_IO is on by default for 
+        * these parts. If it is fixedin the future, these dma_cache_inv will 
+        * just be nothing more than empty macros. See io.h.
+        * */
+       dma_cache_wback_inv(buf,nbytes);
+        dp->dscr_cmd0 |= DSCR_CMD0_V;        /* Let it rip */
+       dma_cache_wback_inv(dp, sizeof(dp));
+
+        ctp->chan_ptr->ddma_dbell = 0;
+               au_sync();
+
        /* return something not zero.
        */
        return nbytes;
 }
+EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
 
 /* Put a destination buffer into the DMA ring.
  * This updates the destination pointer and byte count.  Normally used
  * to place an empty buffer into the ring for fifo to memory transfers.
  */
 u32
-au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
+_au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
 {
        chan_tab_t              *ctp;
        au1x_ddma_desc_t        *dp;
@@ -582,11 +634,34 @@
        if (dp->dscr_cmd0 & DSCR_CMD0_V)
                return 0;
        
-       /* Load up buffer address and byte count.
-       */
+       /* Load up buffer address and byte count */
+
+       /* Check flags  */
+       if (flags & DDMA_FLAGS_IE) 
+               dp->dscr_cmd0 |= DSCR_CMD0_IE;
+       if (flags & DDMA_FLAGS_NOIE)
+               dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
+
        dp->dscr_dest0 = virt_to_phys(buf);
        dp->dscr_cmd1 = nbytes;
+#if 0
+       printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", 
+                       dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0, 
+                       dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
+#endif
+       /*
+        * There is an errata on the Au1200/Au1550 parts that could result in 
+        * "stale" data being DMA'd. It has to do with the snoop logic on the 
+        * dache eviction buffer. NONCOHERENT_IO is on by default for these 
+        * parts. If it is fixedin the future, these dma_cache_inv will just 
+        * be nothing more than empty macros. See io.h. 
+        * */
+       dma_cache_inv(buf,nbytes);
        dp->dscr_cmd0 |= DSCR_CMD0_V;   /* Let it rip */
+       dma_cache_wback_inv(dp, sizeof(dp));
+
+        ctp->chan_ptr->ddma_dbell = 0;
+       au_sync();
        
        /* Get next descriptor pointer.
        */
@@ -596,6 +671,7 @@
        */
        return nbytes;
 }
+EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
 
 /* Get a destination buffer into the DMA ring.
  * Normally used to get a full buffer from the ring during fifo
@@ -645,7 +721,7 @@
 au1xxx_dbdma_stop(u32 chanid)
 {
        chan_tab_t      *ctp;
-       volatile au1x_dma_chan_t *cp;
+       au1x_dma_chan_t *cp;
        int halt_timeout = 0;
 
        ctp = *((chan_tab_t **)chanid);
@@ -665,6 +741,7 @@
        cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
        au_sync();
 }
+EXPORT_SYMBOL(au1xxx_dbdma_stop);
 
 /* Start using the current descriptor pointer.  If the dbdma encounters
  * a not valid descriptor, it will stop.  In this case, we can just
@@ -674,17 +751,17 @@
 au1xxx_dbdma_start(u32 chanid)
 {
        chan_tab_t      *ctp;
-       volatile au1x_dma_chan_t *cp;
+       au1x_dma_chan_t *cp;
 
        ctp = *((chan_tab_t **)chanid);
-
        cp = ctp->chan_ptr;
        cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
        cp->ddma_cfg |= DDMA_CFG_EN;    /* Enable channel */
        au_sync();
-       cp->ddma_dbell = 0xffffffff;    /* Make it go */
+       cp->ddma_dbell = 0;
        au_sync();
 }
+EXPORT_SYMBOL(au1xxx_dbdma_start);
 
 void
 au1xxx_dbdma_reset(u32 chanid)
@@ -703,15 +780,21 @@
 
        do {
                dp->dscr_cmd0 &= ~DSCR_CMD0_V;
+               /* reset our SW status -- this is used to determine 
+                * if a descriptor is in use by upper level SW. Since 
+                * posting can reset 'V' bit. 
+                */
+               dp->sw_status = 0;
                dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
        } while (dp != ctp->chan_desc_base);
 }
+EXPORT_SYMBOL(au1xxx_dbdma_reset);
 
 u32
 au1xxx_get_dma_residue(u32 chanid)
 {
        chan_tab_t      *ctp;
-       volatile au1x_dma_chan_t *cp;
+       au1x_dma_chan_t *cp;
        u32             rv;
 
        ctp = *((chan_tab_t **)chanid);
@@ -746,15 +829,16 @@
 
        kfree(ctp);
 }
+EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
 
 static void
 dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
-       u32     intstat;
+       u32                                     intstat, flags;
        u32     chan_index;
        chan_tab_t              *ctp;
        au1x_ddma_desc_t        *dp;
-       volatile au1x_dma_chan_t *cp;
+       au1x_dma_chan_t *cp;
 
        intstat = dbdma_gptr->ddma_intstat;
        au_sync();
@@ -773,18 +857,26 @@
                (ctp->chan_callback)(irq, ctp->chan_callparam, regs);
 
        ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
-       
 }
 
-static void
-au1xxx_dbdma_init(void)
+static void au1xxx_dbdma_init(void)
 {
+       int irq_nr;
+
        dbdma_gptr->ddma_config = 0;
        dbdma_gptr->ddma_throttle = 0;
        dbdma_gptr->ddma_inten = 0xffff;
        au_sync();
 
-       if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT,
+#if defined(CONFIG_SOC_AU1550)
+       irq_nr = AU1550_DDMA_INT;
+#elif defined(CONFIG_SOC_AU1200)
+       irq_nr = AU1200_DDMA_INT;
+#else
+       #error Unknown Au1x00 SOC
+#endif
+
+       if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT,
                        "Au1xxx dbdma", (void *)dbdma_gptr))
                printk("Can't get 1550 dbdma irq");
 }
@@ -795,7 +887,8 @@
        chan_tab_t              *ctp;
        au1x_ddma_desc_t        *dp;
        dbdev_tab_t             *stp, *dtp;
-       volatile au1x_dma_chan_t *cp;
+       au1x_dma_chan_t *cp;
+               u32                     i = 0;
 
        ctp = *((chan_tab_t **)chanid);
        stp = ctp->chan_src;
@@ -820,15 +913,64 @@
        dp = ctp->chan_desc_base;
 
        do {
-               printk("dp %08x, cmd0 %08x, cmd1 %08x\n",
-                       (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
-               printk("src0 %08x, src1 %08x, dest0 %08x\n",
-                       dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0);
-               printk("dest1 %08x, stat %08x, nxtptr %08x\n",
-                       dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr);
+                printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
+                        i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
+                printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
+                        dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, 
dp->dscr_dest1);
+                printk("stat %08x, nxtptr %08x\n",
+                        dp->dscr_stat, dp->dscr_nxtptr);
                dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
        } while (dp != ctp->chan_desc_base);
 }
 
+/* Put a descriptor into the DMA ring.
+ * This updates the source/destination pointers and byte count.
+ */
+u32
+au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
+{
+       chan_tab_t *ctp;
+       au1x_ddma_desc_t *dp;
+       u32 nbytes=0;
+
+       /* I guess we could check this to be within the
+       * range of the table......
+       */
+       ctp = *((chan_tab_t **)chanid);
+
+       /* We should have multiple callers for a particular channel,
+       * an interrupt doesn't affect this pointer nor the descriptor,
+       * so no locking should be needed.
+       */
+       dp = ctp->put_ptr;
+
+       /* If the descriptor is valid, we are way ahead of the DMA
+       * engine, so just return an error condition.
+       */
+       if (dp->dscr_cmd0 & DSCR_CMD0_V)
+               return 0;
+
+       /* Load up buffer addresses and byte count.
+       */
+       dp->dscr_dest0 = dscr->dscr_dest0;
+       dp->dscr_source0 = dscr->dscr_source0;
+       dp->dscr_dest1 = dscr->dscr_dest1;
+       dp->dscr_source1 = dscr->dscr_source1;
+       dp->dscr_cmd1 = dscr->dscr_cmd1;
+       nbytes = dscr->dscr_cmd1;
+       /* Allow the caller to specifiy if an interrupt is generated */
+       dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
+       dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
+       ctp->chan_ptr->ddma_dbell = 0;
+
+       /* Get next descriptor pointer.
+       */
+       ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
+
+       /* return something not zero.
+       */
+       return nbytes;
+}
+
 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
 
diff -urN linux/arch/mips/au1000/common/irq.c 
linux/arch/mips/au1000/common/irq.c
--- linux/arch/mips/au1000/common/irq.c 2004/03/05 05:23:49     1.11.2.27
+++ linux/arch/mips/au1000/common/irq.c 2005/01/30 08:01:27     1.11.2.28
@@ -508,6 +508,7 @@
 
        if (!intc0_req0) return;
 
+#ifdef AU1000_USB_DEV_REQ_INT
        /*
         * Because of the tight timing of SETUP token to reply
         * transactions, the USB devices-side packet complete
@@ -518,6 +519,7 @@
                do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
                return;
        }
+#endif
 
        irq = au_ffs(intc0_req0) - 1;
        intc0_req0 &= ~(1<<irq);
diff -urN linux/arch/mips/au1000/common/pci_ops.c 
linux/arch/mips/au1000/common/pci_ops.c
--- linux/arch/mips/au1000/common/Attic/pci_ops.c       2004/01/11 00:11:35     
1.1.2.6
+++ linux/arch/mips/au1000/common/Attic/pci_ops.c       2005/01/30 08:01:27     
1.1.2.7
@@ -162,6 +162,7 @@
 static int config_access(unsigned char access_type, struct pci_dev *dev, 
                         unsigned char where, u32 * data)
 {
+       int error = PCIBIOS_SUCCESSFUL;
 #if defined( CONFIG_SOC_AU1500 ) || defined( CONFIG_SOC_AU1550 )
        unsigned char bus = dev->bus->number;
        unsigned int dev_fn = dev->devfn;
@@ -170,7 +171,6 @@
        unsigned long offset, status;
        unsigned long cfg_base;
        unsigned long flags;
-       int error = PCIBIOS_SUCCESSFUL;
        unsigned long entryLo0, entryLo1;
 
        if (device > 19) {
@@ -271,8 +271,11 @@
        }
 
        local_irq_restore(flags);
-       return error;
+#else
+       /* Fake out Config space access with no responder */
+       *data = 0xFFFFFFFF;
 #endif
+       return error;
 }
 #endif
 
diff -urN linux/arch/mips/au1000/common/power.c 
linux/arch/mips/au1000/common/power.c
--- linux/arch/mips/au1000/common/power.c       2004/04/20 15:52:43     1.2.2.12
+++ linux/arch/mips/au1000/common/power.c       2005/01/30 08:01:27     1.2.2.13
@@ -50,7 +50,6 @@
 
 static void calibrate_delay(void);
 
-extern void set_au1x00_speed(unsigned int new_freq);
 extern unsigned int get_au1x00_speed(void);
 extern unsigned long get_au1x00_uart_baud_base(void);
 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
@@ -116,6 +115,7 @@
        sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
        sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
 
+#ifndef CONFIG_SOC_AU1200
        /* Shutdown USB host/device.
        */
        sleep_usbhost_enable = au_readl(USB_HOST_CONFIG);
@@ -127,6 +127,7 @@
 
        sleep_usbdev_enable = au_readl(USBD_ENABLE);
        au_writel(0, USBD_ENABLE); au_sync();
+#endif
 
        /* Save interrupt controller state.
        */
@@ -212,14 +213,12 @@
 int au_sleep(void)
 {
        unsigned long wakeup, flags;
-       extern  void    save_and_sleep(void);
+       extern unsigned int save_and_sleep(void);
 
        spin_lock_irqsave(&pm_lock,flags);
 
        save_core_regs();
 
-       flush_cache_all();
-
        /** The code below is all system dependent and we should probably
         ** have a function call out of here to set this up.  You need
         ** to configure the GPIO or timer interrupts that will bring
@@ -227,27 +226,26 @@
         ** For testing, the TOY counter wakeup is useful.
         **/
 
-#if 0
+#if 1
        au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
 
        /* gpio 6 can cause a wake up event */
        wakeup = au_readl(SYS_WAKEMSK);
        wakeup &= ~(1 << 8);    /* turn off match20 wakeup */
-       wakeup |= 1 << 6;       /* turn on gpio 6 wakeup   */
+       wakeup = 1 << 5;        /* turn on gpio 6 wakeup   */
 #else
-       /* For testing, allow match20 to wake us up.
-       */
+       /* For testing, allow match20 to wake us up.  */
 #ifdef SLEEP_TEST_TIMEOUT
        wakeup_counter0_set(sleep_ticks);
 #endif
        wakeup = 1 << 8;        /* turn on match20 wakeup   */
        wakeup = 0;
 #endif
-       au_writel(1, SYS_WAKESRC);      /* clear cause */
+       au_writel(0, SYS_WAKESRC);      /* clear cause */
        au_sync();
        au_writel(wakeup, SYS_WAKEMSK);
        au_sync();
-
+       DPRINTK("Entering sleep!\n");
        save_and_sleep();
 
        /* after a wakeup, the cpu vectors back to 0x1fc00000 so
@@ -255,6 +253,7 @@
         */
        restore_core_regs();
        spin_unlock_irqrestore(&pm_lock, flags);
+       DPRINTK("Leaving sleep!\n");
        return 0;
 }
 
@@ -285,7 +284,6 @@
 
                if (retval)
                        return retval;
-
                au_sleep();
                retval = pm_send_all(PM_RESUME, (void *) 0);
        }
@@ -312,120 +310,9 @@
 }
 
 
-static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
-                     void *buffer, size_t * len)
-{
-       int retval = 0, i;
-       unsigned long val, pll;
-#define TMPBUFLEN 64
-#define MAX_CPU_FREQ 396
-       char buf[TMPBUFLEN], *p;
-       unsigned long flags, intc0_mask, intc1_mask;
-       unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk,
-           old_refresh;
-       unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
-
-       spin_lock_irqsave(&pm_lock, flags);
-       if (!write) {
-               *len = 0;
-       } else {
-               /* Parse the new frequency */
-               if (*len > TMPBUFLEN - 1) {
-                       spin_unlock_irqrestore(&pm_lock, flags);
-                       return -EFAULT;
-               }
-               if (copy_from_user(buf, buffer, *len)) {
-                       spin_unlock_irqrestore(&pm_lock, flags);
-                       return -EFAULT;
-               }
-               buf[*len] = 0;
-               p = buf;
-               val = simple_strtoul(p, &p, 0);
-               if (val > MAX_CPU_FREQ) {
-                       spin_unlock_irqrestore(&pm_lock, flags);
-                       return -EFAULT;
-               }
-
-               pll = val / 12;
-               if ((pll > 33) || (pll < 7)) {  /* 396 MHz max, 84 MHz min */
-                       /* revisit this for higher speed cpus */
-                       spin_unlock_irqrestore(&pm_lock, flags);
-                       return -EFAULT;
-               }
-
-               old_baud_base = get_au1x00_uart_baud_base();
-               old_cpu_freq = get_au1x00_speed();
-
-               new_cpu_freq = pll * 12 * 1000000;
-               new_baud_base =  (new_cpu_freq / (2 * 
((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
-               set_au1x00_speed(new_cpu_freq);
-               set_au1x00_uart_baud_base(new_baud_base);
-
-               old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
-               new_refresh =
-                   ((old_refresh * new_cpu_freq) /
-                    old_cpu_freq) | (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
-
-               au_writel(pll, SYS_CPUPLL);
-               au_sync_delay(1);
-               au_writel(new_refresh, MEM_SDREFCFG);
-               au_sync_delay(1);
-
-               for (i = 0; i < 4; i++) {
-                       if (au_readl
-                           (UART_BASE + UART_MOD_CNTRL +
-                            i * 0x00100000) == 3) {
-                               old_clk =
-                                   au_readl(UART_BASE + UART_CLK +
-                                         i * 0x00100000);
-                               // baud_rate = baud_base/clk
-                               baud_rate = old_baud_base / old_clk;
-                               /* we won't get an exact baud rate and the error
-                                * could be significant enough that our new
-                                * calculation will result in a clock that will
-                                * give us a baud rate that's too far off from
-                                * what we really want.
-                                */
-                               if (baud_rate > 100000)
-                                       baud_rate = 115200;
-                               else if (baud_rate > 50000)
-                                       baud_rate = 57600;
-                               else if (baud_rate > 30000)
-                                       baud_rate = 38400;
-                               else if (baud_rate > 17000)
-                                       baud_rate = 19200;
-                               else
-                                       (baud_rate = 9600);
-                               // new_clk = new_baud_base/baud_rate
-                               new_clk = new_baud_base / baud_rate;
-                               au_writel(new_clk,
-                                      UART_BASE + UART_CLK +
-                                      i * 0x00100000);
-                               au_sync_delay(10);
-                       }
-               }
-       }
-
-
-       /* We don't want _any_ interrupts other than
-        * match20. Otherwise our calibrate_delay()
-        * calculation will be off, potentially a lot.
-        */
-       intc0_mask = save_local_and_disable(0);
-       intc1_mask = save_local_and_disable(1);
-       local_enable_irq(AU1000_TOY_MATCH2_INT);
-       spin_unlock_irqrestore(&pm_lock, flags);
-       calibrate_delay();
-       restore_local_and_enable(0, intc0_mask);
-       restore_local_and_enable(1, intc1_mask);
-       return retval;
-}
-
-
 static struct ctl_table pm_table[] = {
        {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, &pm_do_suspend},
        {ACPI_SLEEP, "sleep", NULL, 0, 0600, NULL, &pm_do_sleep},
-       {CTL_ACPI, "freq", NULL, 0, 0600, NULL, &pm_do_freq},
        {0}
 };
 
diff -urN linux/arch/mips/au1000/common/setup.c 
linux/arch/mips/au1000/common/setup.c
--- linux/arch/mips/au1000/common/setup.c       2004/04/12 06:32:08     1.1.2.14
+++ linux/arch/mips/au1000/common/setup.c       2005/01/30 08:01:27     1.1.2.15
@@ -174,6 +174,40 @@
        initrd_end = (unsigned long)&__rd_end;
 #endif
 
+#if defined(CONFIG_SOC_AU1200)
+#ifdef CONFIG_USB_EHCI_HCD
+       if ((argptr = strstr(argptr, "usb_ehci=")) == NULL) {
+               char usb_args[80];
+               argptr = prom_getcmdline();
+               memset(usb_args, 0, sizeof(usb_args));
+               sprintf(usb_args, " usb_ehci=base:0x%x,len:0x%x,irq:%d",
+                       USB_EHCI_BASE, USB_EHCI_LEN, AU1000_USB_HOST_INT);
+               strcat(argptr, usb_args);
+       }
+#ifdef CONFIG_USB_AMD5536UDC
+       /* enable EHC + OHC + UDC clocks, memory and bus mastering */
+/*     au_writel( 0x00DF207F, USB_MSR_BASE + 4); */
+       au_writel( 0xC0DF207F, USB_MSR_BASE + 4);  // incl. prefetch
+#else
+       /* enable EHC + OHC clocks, memory and bus mastering */
+/*     au_writel( 0x00DB200F, USB_MSR_BASE + 4); */
+       au_writel( 0xC0DB200F, USB_MSR_BASE + 4);  /* incl. prefetch */
+#endif
+       udelay(1000);
+
+#else /* CONFIG_USB_EHCI_HCD */
+
+#ifdef CONFIG_USB_AMD5536UDC
+#ifndef CONFIG_USB_OHCI
+       /* enable UDC clocks, memory and bus mastering */
+/*     au_writel( 0x00DC2070, USB_MSR_BASE + 4); */
+       au_writel( 0xC0DC2070, USB_MSR_BASE + 4);  // incl. prefetch
+       udelay(1000);
+#endif
+#endif
+#endif /* CONFIG_USB_EHCI_HCD */
+#endif /* CONFIG_SOC_AU1200 */
+
 #if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
 #ifdef CONFIG_USB_OHCI
        if ((argptr = strstr(argptr, "usb_ohci=")) == NULL) {
@@ -187,19 +221,38 @@
 #endif
 
 #ifdef CONFIG_USB_OHCI
-       // enable host controller and wait for reset done
+#if defined(CONFIG_SOC_AU1200)
+#ifndef CONFIG_USB_EHCI_HCD
+#ifdef CONFIG_USB_AMD5536UDC
+       /* enable OHC + UDC clocks, memory and bus mastering */
+/*     au_writel( 0x00DD2073, USB_MSR_BASE + 4); */
+       au_writel( 0xC0DD2073, USB_MSR_BASE + 4);  // incl. prefetch
+#else
+       /* enable OHC clocks, memory and bus mastering */
+       au_writel( 0x00D12003, USB_MSR_BASE + 4);
+#endif
+       udelay(1000);
+printk("DEBUG: Reading Au1200 USB2 reg 0x%x\n", au_readl(USB_MSR_BASE + 4));
+#endif
+#else
+       /* Au1000, Au1500, Au1100, Au1550 */
+       /* enable host controller and wait for reset done */
        au_writel(0x08, USB_HOST_CONFIG);
        udelay(1000);
        au_writel(0x0E, USB_HOST_CONFIG);
        udelay(1000);
-       au_readl(USB_HOST_CONFIG); // throw away first read
+       au_readl(USB_HOST_CONFIG); /* throw away first read */
        while (!(au_readl(USB_HOST_CONFIG) & 0x10))
                au_readl(USB_HOST_CONFIG);
+#endif /* CONFIG_SOC_AU1200 */
 #endif
-#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
+#else
+
+#endif /* defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) */
+
 
 #ifdef CONFIG_FB
-       // Needed if PCI video card in use
+       /* Needed if PCI video card in use */
        conswitchp = &dummy_con;
 #endif
 
@@ -209,8 +262,7 @@
 #endif
 
 #ifdef CONFIG_BLK_DEV_IDE
-       /* Board setup takes precedence for unique devices.
-       */
+       /* Board setup takes precedence for unique devices.  */
        if ((ide_ops == NULL) || (ide_ops == &no_ide_ops))
                ide_ops = &std_ide_ops;
 #endif
diff -urN linux/arch/mips/au1000/common/sleeper.S 
linux/arch/mips/au1000/common/sleeper.S
--- linux/arch/mips/au1000/common/sleeper.S     2003/10/10 04:42:36     1.1.2.1
+++ linux/arch/mips/au1000/common/sleeper.S     2005/01/30 08:01:27     1.1.2.2
@@ -15,17 +15,48 @@
 #include <asm/addrspace.h>
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
+#include <asm/au1000.h>
+
+/*
+ * Note: This file is *not* conditional on CONFIG_PM since Alchemy sleep 
+ * need not be tied to any particular power management scheme.
+ */
+
+       .extern ___flush_cache_all
 
        .text
-       .set    macro
-       .set    noat
        .align  5
 
-/* Save all of the processor general registers and go to sleep.
- * A wakeup condition will get us back here to restore the registers.
+/*
+ * Save the processor general registers and go to sleep. A wakeup
+ * condition will get us back here to restore the registers.
  */
-LEAF(save_and_sleep)
 
+/* still need to fix alignment issues here */
+save_and_sleep_frmsz = 48
+NESTED(save_and_sleep, save_and_sleep_frmsz, ra)
+       .set noreorder
+       .set nomacro
+       .set noat
+       subu sp, save_and_sleep_frmsz
+       sw ra, save_and_sleep_frmsz-4(sp)
+       sw s0, save_and_sleep_frmsz-8(sp)
+       sw s1, save_and_sleep_frmsz-12(sp)
+       sw s2, save_and_sleep_frmsz-16(sp)
+       sw s3, save_and_sleep_frmsz-20(sp)
+       sw s4, save_and_sleep_frmsz-24(sp)
+       sw s5, save_and_sleep_frmsz-28(sp)
+       sw s6, save_and_sleep_frmsz-32(sp)
+       sw s7, save_and_sleep_frmsz-36(sp)
+       sw s8, save_and_sleep_frmsz-40(sp)
+       sw gp, save_and_sleep_frmsz-44(sp)
+
+       /* We only need to save the registers that the calling function 
+        * hasn't saved for us.  0 is always zero.  8 - 15, 24 and 25 are 
+        * temporaries and can be used without saving. 26 and 27 are reserved 
+        * for interrupt/trap handling and expected to change.  29 is the 
+        * stack pointer which is handled as a special case here.
+        */
        subu    sp, PT_SIZE
        sw      $1, PT_R1(sp)
        sw      $2, PT_R2(sp)
@@ -34,14 +65,6 @@
        sw      $5, PT_R5(sp)
        sw      $6, PT_R6(sp)
        sw      $7, PT_R7(sp)
-       sw      $8, PT_R8(sp)
-       sw      $9, PT_R9(sp)
-       sw      $10, PT_R10(sp)
-       sw      $11, PT_R11(sp)
-       sw      $12, PT_R12(sp)
-       sw      $13, PT_R13(sp)
-       sw      $14, PT_R14(sp)
-       sw      $15, PT_R15(sp)
        sw      $16, PT_R16(sp)
        sw      $17, PT_R17(sp)
        sw      $18, PT_R18(sp)
@@ -50,32 +73,47 @@
        sw      $21, PT_R21(sp)
        sw      $22, PT_R22(sp)
        sw      $23, PT_R23(sp)
-       sw      $24, PT_R24(sp)
-       sw      $25, PT_R25(sp)
-       sw      $26, PT_R26(sp)
-       sw      $27, PT_R27(sp)
        sw      $28, PT_R28(sp)
-       sw      $29, PT_R29(sp)
        sw      $30, PT_R30(sp)
        sw      $31, PT_R31(sp)
+#define PT_C0STATUS PT_LO
+#define PT_CONTEXT PT_HI
+#define PT_PAGEMASK PT_EPC
+#define PT_CONFIG PT_BVADDR
        mfc0    k0, CP0_STATUS
-       sw      k0, 0x20(sp)
+       sw      k0, PT_C0STATUS(sp) // 0x20
        mfc0    k0, CP0_CONTEXT
-       sw      k0, 0x1c(sp)
+       sw      k0, PT_CONTEXT(sp) // 0x1c
        mfc0    k0, CP0_PAGEMASK
-       sw      k0, 0x18(sp)
+       sw      k0, PT_PAGEMASK(sp) // 0x18
        mfc0    k0, CP0_CONFIG
-       sw      k0, 0x14(sp)
+       sw      k0, PT_CONFIG(sp) // 0x14
+
+       .set macro
+       .set at
+
+       li t0, SYS_SLPPWR
+       sw      zero, 0(t0)     /* Get the processor ready to sleep */
+       sync
 
        /* Now set up the scratch registers so the boot rom will
         * return to this point upon wakeup.
+        * sys_scratch0 : SP
+        * sys_scratch1 : RA
+        */
+       li      t0, SYS_SCRATCH0
+       li      t1, SYS_SCRATCH1
+       sw      sp, 0(t0)
+       la      k0, resume_from_sleep
+       sw      k0, 0(t1)
+
+/*
+ * Flush DCACHE to make sure context is in memory
         */
-       la      k0, 1f
-       lui     k1, 0xb190
-       ori     k1, 0x18
-       sw      sp, 0(k1)
-       ori     k1, 0x1c
-       sw      k0, 0(k1)
+       la      t1,___flush_cache_all   /* _flush_cache_all is a function 
pointer */
+       lw      t0,0(t1)
+       jal t0
+       nop
 
 /* Put SDRAM into self refresh.  Preload instructions into cache,
  * issue a precharge, then auto refresh, then sleep commands to it.
@@ -88,30 +126,65 @@
        cache   0x14, 96(t0)
        .set    mips0
 
+       /* Put SDRAM to sleep */
 sdsleep:
-       lui     k0, 0xb400
-       sw      zero, 0x001c(k0)        /* Precharge */
-       sw      zero, 0x0020(k0)        /* Auto refresh */
-       sw      zero, 0x0030(k0)        /* SDRAM sleep */
+       li      a0, MEM_PHYS_ADDR
+       or      a0, a0, 0xA0000000
+#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100) || 
defined(CONFIG_SOC_AU1500)
+       lw      k0, MEM_SDMODE0(a0)
+       sw      zero, MEM_SDPRECMD(a0)  /* Precharge */
+       sw      zero, MEM_SDAUTOREF(a0) /* Auto Refresh */
+       sw      zero, MEM_SDSLEEP(a0)   /* Sleep */
        sync
-
-       lui     k1, 0xb190
-       sw      zero, 0x0078(k1)        /* get ready  to sleep */
+#endif
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+       sw      zero, MEM_SDPRECMD(a0)  /* Precharge */
+       sw      zero, MEM_SDSREF(a0)
+       
+       #lw     t0, MEM_SDSTAT(a0)
+       #and t0, t0, 0x01000000
+       li      t0, 0x01000000
+refresh_not_set:
+       lw      t1, MEM_SDSTAT(a0)
+       and     t2, t1, t0
+       beq     zero, t2, refresh_not_set
+       nop
+
+       li      t0, ~0x30000000
+       lw      t1, MEM_SDCONFIGA(a0)
+       and t1, t0, t1
+       sw      t1, MEM_SDCONFIGA(a0)
        sync
-       sw      zero, 0x007c(k1)        /* Put processor to sleep */
+#endif
+
+       li      t0, SYS_SLEEP
+       sw      zero, 0(t0)     /* Put processor to sleep */
        sync
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+
 
        /* This is where we return upon wakeup.
         * Reload all of the registers and return.
         */
-1:     nop
-       lw      k0, 0x20(sp)
+resume_from_sleep:
+       nop
+       .set nomacro
+       .set noat
+
+       lw      k0, PT_C0STATUS(sp) // 0x20
        mtc0    k0, CP0_STATUS
-       lw      k0, 0x1c(sp)
+       lw      k0, PT_CONTEXT(sp) // 0x1c
        mtc0    k0, CP0_CONTEXT
-       lw      k0, 0x18(sp)
+       lw      k0, PT_PAGEMASK(sp) // 0x18
        mtc0    k0, CP0_PAGEMASK
-       lw      k0, 0x14(sp)
+       lw      k0, PT_CONFIG(sp) // 0x14
        mtc0    k0, CP0_CONFIG
        lw      $1, PT_R1(sp)
        lw      $2, PT_R2(sp)
@@ -120,14 +193,6 @@
        lw      $5, PT_R5(sp)
        lw      $6, PT_R6(sp)
        lw      $7, PT_R7(sp)
-       lw      $8, PT_R8(sp)
-       lw      $9, PT_R9(sp)
-       lw      $10, PT_R10(sp)
-       lw      $11, PT_R11(sp)
-       lw      $12, PT_R12(sp)
-       lw      $13, PT_R13(sp)
-       lw      $14, PT_R14(sp)
-       lw      $15, PT_R15(sp)
        lw      $16, PT_R16(sp)
        lw      $17, PT_R17(sp)
        lw      $18, PT_R18(sp)
@@ -136,15 +201,36 @@
        lw      $21, PT_R21(sp)
        lw      $22, PT_R22(sp)
        lw      $23, PT_R23(sp)
-       lw      $24, PT_R24(sp)
-       lw      $25, PT_R25(sp)
-       lw      $26, PT_R26(sp)
-       lw      $27, PT_R27(sp)
        lw      $28, PT_R28(sp)
-       lw      $29, PT_R29(sp)
        lw      $30, PT_R30(sp)
        lw      $31, PT_R31(sp)
+
+       .set macro
+       .set at
+
+       /* clear the wake source, but save it as the return value of the 
function */
+       li      t0, SYS_WAKESRC
+       lw v0, 0(t0)
+       sw v0, PT_R2(sp)
+       sw zero, 0(t0)
+
        addiu   sp, PT_SIZE
 
+       lw gp, save_and_sleep_frmsz-44(sp)
+       lw s8, save_and_sleep_frmsz-40(sp)
+       lw s7, save_and_sleep_frmsz-36(sp)
+       lw s6, save_and_sleep_frmsz-32(sp)
+       lw s5, save_and_sleep_frmsz-28(sp)
+       lw s4, save_and_sleep_frmsz-24(sp)
+       lw s3, save_and_sleep_frmsz-20(sp)
+       lw s2, save_and_sleep_frmsz-16(sp)
+       lw s1, save_and_sleep_frmsz-12(sp)
+       lw s0, save_and_sleep_frmsz-8(sp)
+       lw ra, save_and_sleep_frmsz-4(sp)
+
+       addu sp, save_and_sleep_frmsz
        jr      ra
+       nop
+       .set reorder
 END(save_and_sleep)
+
diff -urN linux/arch/mips/au1000/common/time.c 
linux/arch/mips/au1000/common/time.c
--- linux/arch/mips/au1000/common/time.c        2004/10/08 02:42:32     1.5.2.18
+++ linux/arch/mips/au1000/common/time.c        2005/01/30 08:01:27     1.5.2.19
@@ -437,9 +437,6 @@
                au_writel(0, SYS_TOYWRITE);
                while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
 
-               au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
-               au_writel(~0, SYS_WAKESRC);
-               au_sync();
                while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
 
                /* setup match20 to interrupt once every 10ms */
diff -urN linux/arch/mips/au1000/ficmmp/Makefile 
linux/arch/mips/au1000/ficmmp/Makefile
--- linux/arch/mips/au1000/ficmmp/Attic/Makefile        1970/01/01 00:00:00
+++ linux/arch/mips/au1000/ficmmp/Attic/Makefile        Sun Jan 30 08:01:27 
2005        1.1.2.1
@@ -0,0 +1,25 @@
+#
+#  Copyright 2000 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc.
+#      ppopov@mvista.com or source@mvista.com
+#
+# Makefile for the Alchemy Semiconductor FIC board.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+
+USE_STANDARD_AS_RULE := true
+
+O_TARGET := ficmmp.o
+
+obj-y := init.o board_setup.o irqmap.o au1200_ibutton.o au1xxx_dock.o
+
+ifdef CONFIG_MMC
+obj-y += mmc_support.o
+export-objs +=mmc_support.o
+endif
+
+
+include $(TOPDIR)/Rules.make
diff -urN linux/arch/mips/au1000/ficmmp/au1200_ibutton.c 
linux/arch/mips/au1000/ficmmp/au1200_ibutton.c
--- linux/arch/mips/au1000/ficmmp/Attic/au1200_ibutton.c        1970/01/01 
00:00:00
+++ linux/arch/mips/au1000/ficmmp/Attic/au1200_ibutton.c        Sun Jan 30 
08:01:27 2005        1.1.2.1
@@ -0,0 +1,270 @@
+/* ---------------------------------------------------------------------- 
+ *  mtwilson_keys.c
+ *
+ *  Copyright (C) 2003 Intrinsyc Software Inc.
+ *
+ *  Intel Personal Media Player buttons
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  May 02, 2003 : Initial version [FB]
+ *
+ ------------------------------------------------------------------------*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/sched.h>
+#include <linux/miscdevice.h>
+#include <linux/errno.h>
+#include <linux/poll.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+
+#include <asm/au1000.h>
+#include <asm/uaccess.h>
+#include <asm/au1xxx_gpio.h>
+#include <asm/irq.h>
+#include <asm/keyboard.h>
+#include <linux/time.h>
+
+#define DRIVER_VERSION "V1.0"
+#define DRIVER_AUTHOR  "FIC"
+#define DRIVER_DESC            "FIC Travis Media Player Button Driver"
+#define DRIVER_NAME            "Au1200Button"
+
+#define BUTTON_MAIN            (1<<1)
+#define BUTTON_SELECT  (1<<6)
+#define BUTTON_GUIDE   (1<<12)
+#define BUTTON_DOWN            (1<<17)
+#define BUTTON_LEFT            (1<<19)
+#define BUTTON_RIGHT   (1<<26)
+#define BUTTON_UP              (1<<28)
+
+#define BUTTON_MASK (\
+    BUTTON_MAIN   \
+    | BUTTON_SELECT    \
+    | BUTTON_GUIDE     \
+    | BUTTON_DOWN      \
+    | BUTTON_LEFT      \
+    | BUTTON_RIGHT     \
+    | BUTTON_UP                \
+    )
+
+#define BUTTON_INVERT (\
+    BUTTON_MAIN   \
+    | 0                                \
+    | BUTTON_GUIDE     \
+    | 0                                \
+    | 0                                \
+    | 0                                \
+    | 0                                \
+    )
+
+char 
button_map[32]={0,KEY_S,0,0,0,0,KEY_ENTER,0,0,0,0,0,KEY_G,0,0,0,0,KEY_DOWN,0,KEY_LEFT,0,0,0,0,0,0,KEY_RIGHT,0,KEY_UP,0,0,0};
+//char 
button_map[32]={0,0,0,0,0,0,KEY_ENTER,0,0,0,0,0,KEY_G,0,0,0,0,KEY_DOWN,0,KEY_LEFT,0,0,0,0,0,0,KEY_RIGHT,0,KEY_UP,0,0,0};
+
+//char 
button_map[32]={0,KEY_TAB,0,0,0,0,KEY_M,0,0,0,0,0,KEY_S,0,0,0,0,KEY_DOWN,0,KEY_LEFT,0,0,0,0,0,0,KEY_RIGHT,0,KEY_UP,0,0,0};
+//char 
button_map[32]={0,0,0,0,0,0,KEY_M,0,0,0,0,0,KEY_S,0,0,0,0,KEY_DOWN,0,KEY_LEFT,0,0,0,0,0,0,KEY_RIGHT,0,KEY_UP,0,0,0};
+
+#define BUTTON_COUNT (sizeof (button_map) / sizeof (button_map[0]))
+
+struct input_dev dev;
+struct timeval cur_tv;
+
+static unsigned int old_tv_usec = 0;
+
+static unsigned int read_button_state(void)
+{
+       unsigned int state;
+
+       state = au_readl(SYS_PINSTATERD) & BUTTON_MASK; /* get gpio status */
+
+       state ^= BUTTON_INVERT;         /* invert main & guide button */
+
+       /* printk("au1200_ibutton.c: button state [0x%X]\r\n",state); */
+       return state;
+}
+
+//This function returns 0 if the allowed microseconds have elapsed since the 
last call to ths function, otherwise it returns 1 to indicate a bounce condition
+static unsigned int bounce() 
+{
+
+       unsigned int elapsed_time;
+
+       do_gettimeofday (&cur_tv);    
+
+       if (!old_tv_usec) {
+               old_tv_usec = cur_tv.tv_usec;
+               return 0;
+       }
+
+       if(cur_tv.tv_usec > old_tv_usec) {
+               /* If there hasn't been rollover */
+               elapsed_time =  ((cur_tv.tv_usec - old_tv_usec));
+       }
+       else {
+               /* Accounting for rollover */
+               elapsed_time =  ((1000000 - old_tv_usec + cur_tv.tv_usec));
+       }
+
+       if (elapsed_time > 250000) {
+               old_tv_usec = 0;        /* reset the bounce time */
+               return 0;
+       }
+
+       return 1;
+}
+
+/* button interrupt handler */
+static void button_interrupt(int irq, void *dev, struct pt_regs *regs)
+{
+
+       unsigned int i,bit_mask, key_choice;
+       u32 button_state;
+       
+       /* Report state to upper level */
+       
+       button_state = read_button_state() & BUTTON_MASK; /* get new gpio 
status */
+
+       /* Return if this is a repeated (bouncing) event */
+       if(bounce())
+               return;
+
+       /* we want to make keystrokes */
+       for( i=0; i< BUTTON_COUNT; i++) {
+               bit_mask = 1<<i;
+               if (button_state & bit_mask) {
+                       key_choice = button_map[i];
+                       /* toggle key down */
+                       input_report_key(dev, key_choice, 1);
+                       /* toggle key up */
+                       input_report_key(dev, key_choice, 0);
+                       printk("ibutton gpio %d stat %x scan code %d\r\n", 
+                                       i, button_state, key_choice);
+                       /* Only report the first key event; it doesn't make 
+                        * sense for two keys to be pressed at the same time, 
+                        * and causes problems with the directional keys 
+                        * return;      
+                        */
+               }
+       }
+}
+
+static int 
+button_translate(unsigned char scancode, unsigned char *keycode, char 
raw_mode) 
+{
+       static int prev_scancode;
+       
+       printk( "ibutton.c: translate: scancode=%x raw_mode=%x\n", 
+                       scancode, raw_mode);
+
+       if (scancode == 0xe0 || scancode == 0xe1) {
+               prev_scancode = scancode;
+               return 0;
+       }
+
+       if (scancode == 0x00 || scancode == 0xff) {
+               prev_scancode = 0;
+               return 0;
+       }
+
+       *keycode = scancode;
+
+       return 1;
+}
+
+/* init button hardware */
+static int button_hw_init(void)
+{
+       unsigned int    ipinfunc=0;     
+
+       printk("au1200_ibutton.c: Initializing buttons hardware\n");
+
+       // initialize GPIO pin function assignments     
+
+       ipinfunc = au_readl(SYS_PINFUNC);
+
+       ipinfunc &= ~(SYS_PINFUNC_DMA | SYS_PINFUNC_S0A | SYS_PINFUNC_S0B);     
+       au_writel( ipinfunc ,SYS_PINFUNC);
+       
+       ipinfunc |=  (SYS_PINFUNC_S0C);
+       au_writel( ipinfunc ,SYS_PINFUNC);
+       
+       return 0;
+}
+
+/* button driver init */
+static int __init button_init(void)
+{
+       int ret, i;
+       unsigned int flag=0;
+
+       printk("au1200_ibutton.c: button_init()\r\n");
+       
+       button_hw_init();
+       
+       /* register all button irq handler */
+       
+       for(i=0; i< izeof(button_map)/sizeof(button_map[0]); i++)
+       {
+               /* register irq <-- gpio 1 ,6 ,12 , 17 ,19 , 26 ,28 */
+               if(button_map[i] != 0)  
+               {
+                       ret = request_irq(AU1000_GPIO_0 + i , 
+                                       &button_interrupt , SA_INTERRUPT , 
+                                       DRIVER_NAME , &dev);
+                       if(ret) flag |= 1<<i;
+               }
+       }
+
+       printk("au1200_ibutton.c: request_irq,ret:0x%x\r\n",ret);
+       
+       if (ret) {
+               printk("au1200_ibutton.c: request_irq:%X failed\r\n",flag);
+               return ret;
+       }
+               
+       dev.name = DRIVER_NAME;
+       dev.evbit[0] = BIT(EV_KEY) | BIT(EV_REP);
+
+       for (i=0;i<sizeof(button_map)/sizeof(button_map[0]);i++)
+       {
+               dev.keybit[LONG(button_map[i])] |= BIT(button_map[i]);
+       }
+       
+       input_register_device(&dev);
+
+       /* ready to receive interrupts */
+
+       return 0;
+}
+
+/* button driver exit */
+static void __exit button_exit(void)
+{
+       int i;
+       
+       for(i=0;i<sizeof(button_map)/sizeof(button_map[0]);i++)
+       {
+               if(button_map[i] != 0)
+               {
+                       free_irq( AU1000_GPIO_0 + i, &dev);
+               }
+       }
+       
+       input_unregister_device(&dev);
+       
+       printk("au1200_ibutton.c: button_exit()\r\n");
+}
+
+module_init(button_init);
+module_exit(button_exit);
+
+MODULE_AUTHOR( DRIVER_AUTHOR );
+MODULE_DESCRIPTION( DRIVER_DESC );
+MODULE_LICENSE("GPL");
diff -urN linux/arch/mips/au1000/ficmmp/au1xxx_dock.c 
linux/arch/mips/au1000/ficmmp/au1xxx_dock.c
--- linux/arch/mips/au1000/ficmmp/Attic/au1xxx_dock.c   1970/01/01 00:00:00
+++ linux/arch/mips/au1000/ficmmp/Attic/au1xxx_dock.c   Sun Jan 30 08:01:27 
2005        1.1.2.1
@@ -0,0 +1,261 @@
+/*
+ *  Copyright (C) 2003 Metrowerks, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/sched.h>
+#include <linux/miscdevice.h>
+#include <linux/errno.h>
+#include <linux/poll.h>
+#include <asm/au1000.h>
+#include <asm/uaccess.h>
+#include <asm/au1xxx_gpio.h>
+
+
+#if defined(CONFIG_MIPS_FICMMP)
+       #define DOCK_GPIO       215
+#else
+       #error Unsupported Au1xxx Platform
+#endif
+
+#define MAKE_FLAG 0x20
+
+#undef DEBUG
+
+#define DEBUG 0
+//#define DEBUG 1
+
+#if DEBUG
+#define DPRINTK(format, args...) printk(__FUNCTION__ ": "  format, ## args)
+#else
+#define DPRINTK(format, args...) do { } while (0)
+#endif
+
+/* Please note that this driver is based on a timer and is not interrupt
+ * driven.  If you are going to make use of this driver, you will need to have
+ * your application open the dock listing from the /dev directory first.
+ */
+
+struct au1xxx_dock {
+       struct fasync_struct *fasync;
+       wait_queue_head_t     read_wait;
+       int open_count;
+       unsigned int debounce;
+       unsigned int current;
+       unsigned int last;
+};
+
+static struct au1xxx_dock dock_info;
+
+
+static void dock_timer_periodic(void *data);
+
+static struct tq_struct dock_task = {
+       routine:        dock_timer_periodic,
+       data:           NULL
+};
+
+static int cleanup_flag = 0;
+static DECLARE_WAIT_QUEUE_HEAD(cleanup_wait_queue);
+
+
+static unsigned int read_dock_state(void)
+{
+       u32 state;
+
+       state = au1xxx_gpio_read(DOCK_GPIO);
+       
+       /* printk( "Current Dock State: %d\n", state ); */
+
+       return state;
+}
+
+
+static void dock_timer_periodic(void *data)
+{
+       struct au1xxx_dock *dock = (struct au1xxx_dock *)data;
+       unsigned long dock_state;
+       
+       /* If cleanup wants us to die */
+       if (cleanup_flag) {
+               /* now cleanup_module can return */
+               wake_up(&cleanup_wait_queue); 
+       } else {
+               /* put ourselves back in the task queue */
+               queue_task(&dock_task, &tq_timer);      
+       }
+
+       /* read current dock */
+       dock_state = read_dock_state();
+
+       /* if dock states hasn't changed */
+       /* save time and be done. */
+       if (dock_state == dock->current) {
+               return;
+       }
+       
+       if (dock_state == dock->debounce) {
+               dock->current = dock_state;
+       } else {
+               dock->debounce = dock_state;
+       }
+       if (dock->current != dock->last) {
+               if (waitqueue_active(&dock->read_wait)) {
+                   wake_up_interruptible(&dock->read_wait);
+               }
+       }
+}
+
+
+static ssize_t au1xxx_dock_read(struct file *filp, char *buffer, size_t count, 
loff_t *ppos)
+{
+       struct au1xxx_dock *dock = filp->private_data;
+       char event[3];
+       int last;
+       int cur;
+       int err;
+       
+try_again:
+
+       while (dock->current == dock->last) {
+               if (filp->f_flags & O_NONBLOCK) {
+                       return -EAGAIN;
+               }
+               interruptible_sleep_on(&dock->read_wait);
+               if (signal_pending(current)) {
+                       return -ERESTARTSYS;
+               }
+       }
+       
+       cur  = dock->current;
+       last = dock->last;
+
+       if(cur != last)
+       {
+               event[0] = cur ? 'D' : 'U';
+               event[1] = '\r';
+               event[2] = '\n';
+       }
+       else
+               goto try_again;
+       
+       dock->last = cur;
+       err = copy_to_user(buffer, &event, 3);
+       if (err) {
+               return err;
+       }
+       
+       return 3;
+}
+
+
+static int au1xxx_dock_open(struct inode *inode, struct file *filp)
+{
+       struct au1xxx_dock *dock = &dock_info;
+
+       MOD_INC_USE_COUNT;
+
+       filp->private_data = dock;
+
+       if (dock->open_count++ == 0) {
+               dock_task.data = dock;
+               cleanup_flag = 0;
+               queue_task(&dock_task, &tq_timer);
+       }
+
+       return 0;
+}
+
+
+static unsigned int au1xxx_dock_poll(struct file *filp, poll_table *wait)
+{
+       struct au1xxx_dock *dock = filp->private_data;
+       int ret = 0;
+
+       DPRINTK("start\n");
+       poll_wait(filp, &dock->read_wait, wait);
+       if (dock->current != dock->last) {
+               ret = POLLIN | POLLRDNORM;
+       }
+       return ret;
+}
+
+
+static int au1xxx_dock_release(struct inode *inode, struct file *filp)
+{
+       struct au1xxx_dock *dock = filp->private_data;
+
+       DPRINTK("start\n");
+
+       if (--dock->open_count == 0) {
+               cleanup_flag = 1;
+               sleep_on(&cleanup_wait_queue);
+       }
+       MOD_DEC_USE_COUNT;
+       
+       return 0;
+}
+
+
+
+static struct file_operations au1xxx_dock_fops = {
+       owner:          THIS_MODULE,
+       read:           au1xxx_dock_read,
+       poll:           au1xxx_dock_poll,
+       open:           au1xxx_dock_open,
+       release:        au1xxx_dock_release,
+};
+
+/*
+ * The au1xxx dock is a misc device:
+ * Major 10 char
+ * Minor 22        /dev/dock
+ * 
+ * This is /dev/misc/dock if devfs is used.
+ */
+
+static struct miscdevice au1xxx_dock_dev = {
+       minor:  23,
+       name:   "dock",
+       fops:   &au1xxx_dock_fops,
+};
+
+static int __init au1xxx_dock_init(void)
+{
+       struct au1xxx_dock *dock = &dock_info;
+       int ret;
+
+       DPRINTK("Initializing dock driver\n");
+       dock->open_count = 0;
+       cleanup_flag        = 0;
+       init_waitqueue_head(&dock->read_wait);
+
+
+       /* yamon configures GPIO pins for the dock
+        * no initialization needed
+        */
+
+       ret = misc_register(&au1xxx_dock_dev);
+
+       DPRINTK("dock driver fully initialized.\n");
+
+       return ret;
+}
+
+
+static void __exit au1xxx_dock_exit(void)
+{
+       DPRINTK("unloading dock driver\n");
+       misc_deregister(&au1xxx_dock_dev);
+}
+
+
+module_init(au1xxx_dock_init);
+module_exit(au1xxx_dock_exit);
diff -urN linux/arch/mips/au1000/ficmmp/board_setup.c 
linux/arch/mips/au1000/ficmmp/board_setup.c
--- linux/arch/mips/au1000/ficmmp/Attic/board_setup.c   1970/01/01 00:00:00
+++ linux/arch/mips/au1000/ficmmp/Attic/board_setup.c   Sun Jan 30 08:01:27 
2005        1.1.2.1
@@ -0,0 +1,191 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *     Alchemy Pb1200 board setup.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/mc146818rtc.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
+#include <linux/ide.h>
+#endif
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/keyboard.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/pgtable.h>
+#include <asm/au1000.h>
+#include <asm/ficmmp.h>
+#include <asm/au1xxx_dbdma.h>
+#include <asm/au1xxx_gpio.h>
+
+extern struct rtc_ops no_rtc_ops;
+
+/* value currently in the board configuration register */
+u16 ficmmp_config = 0;
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
+extern struct ide_ops *ide_ops;
+extern struct ide_ops au1xxx_ide_ops;
+extern u32 au1xxx_ide_virtbase;
+extern u64 au1xxx_ide_physbase;
+extern int au1xxx_ide_irq;
+
+u32 led_base_addr;
+/* Ddma */
+chan_tab_t *ide_read_ch, *ide_write_ch;
+u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma
+
+dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 
0, 0x00000000, 0, 0 };
+#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */
+
+void board_reset (void)
+{
+       au_writel(0, 0xAD80001C);
+}
+
+void __init board_setup(void)
+{
+       char *argptr = NULL;
+       u32 pin_func;
+       rtc_ops = &no_rtc_ops;
+
+       ficmmp_config_init();   //Initialize FIC control register
+       
+#if 0
+       /* Enable PSC1 SYNC for AC97.  Normaly done in audio driver,
+        * but it is board specific code, so put it here.
+        */
+       pin_func = au_readl(SYS_PINFUNC);
+       au_sync();
+       pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
+       au_writel(pin_func, SYS_PINFUNC);
+
+       au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
+       au_sync();
+#endif
+
+#if defined( CONFIG_I2C_ALGO_AU1550 )
+       {
+       u32 freq0, clksrc;
+
+       /* Select SMBUS in CPLD */
+       /* bcsr->resets &= ~(BCSR_RESETS_PCS0MUX); */
+
+       pin_func = au_readl(SYS_PINFUNC);
+       au_sync();
+       pin_func &= ~(3<<17 | 1<<4);
+       /* Set GPIOs correctly */
+       pin_func |= 2<<17;
+       au_writel(pin_func, SYS_PINFUNC);
+       au_sync();
+
+       /* The i2c driver depends on 50Mhz clock */
+       freq0 = au_readl(SYS_FREQCTRL0);
+       au_sync();
+       freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
+       freq0 |= (3<<SYS_FC_FRDIV1_BIT);
+       /* 396Mhz / (3+1)*2 == 49.5Mhz */
+       au_writel(freq0, SYS_FREQCTRL0);
+       au_sync();
+       freq0 |= SYS_FC_FE1;
+       au_writel(freq0, SYS_FREQCTRL0);
+       au_sync();
+
+       clksrc = au_readl(SYS_CLKSRC);
+       au_sync();
+       clksrc &= ~0x01f00000;
+       /* bit 22 is EXTCLK0 for PSC0 */
+       clksrc |= (0x3 << 22);
+       au_writel(clksrc, SYS_CLKSRC);
+       au_sync();
+       }
+#endif
+
+#ifdef CONFIG_FB_AU1200
+       argptr = prom_getcmdline();
+       strcat(argptr, " video=au1200fb:panel:s11");
+#endif
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
+       /*
+        * Iniz IDE parameters
+        */
+       ide_ops = &au1xxx_ide_ops;
+       au1xxx_ide_irq = FICMMP_IDE_INT;
+       au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR;
+       au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR);
+       switch4ddma = 0;
+       /*
+       ide_ops = &au1xxx_ide_ops;
+       au1xxx_ide_irq = FICMMP_IDE_INT;
+       au1xxx_ide_base = KSEG1ADDR(AU1XXX_ATA_BASE);
+       */
+       au1xxx_gpio_write(9, 1);
+       printk("B4001010: %X\n", *((u32*)0xB4001010));
+       printk("B4001014: %X\n", *((u32*)0xB4001014));
+       printk("B4001018: %X\n", *((u32*)0xB4001018));
+       printk("B1900100: %X\n", *((u32*)0xB1900100));
+       
+#if 0
+       ficmmp_config_clear(FICMMP_CONFIG_IDERST);
+       mdelay(100);
+       ficmmp_config_set(FICMMP_CONFIG_IDERST);
+       mdelay(100);
+#endif
+       /*
+        * change PIO or PIO+Ddma
+        * check the GPIO-5 pin condition. pb1200:s18_dot
+        */
+/*     switch4ddma = 0; //(au_readl(SYS_PINSTATERD) & (1 << 5)) ? 1 : 0; */
+#endif
+
+       /* The Pb1200 development board uses external MUX for PSC0 to
+       support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
+       */
+#if defined(CONFIG_AU1550_PSC_SPI) && defined(CONFIG_I2C_ALGO_AU1550)
+       #error I2C and SPI are mutually exclusive. Both are physically 
connected to PSC0.\
+                       Refer to Pb1200 documentation.
+#elif defined( CONFIG_AU1550_PSC_SPI )
+       //bcsr->resets |= BCSR_RESETS_PCS0MUX;
+#elif defined( CONFIG_I2C_ALGO_AU1550 )
+       //bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
+#endif
+       au_sync();
+
+       printk("FIC Multimedia Player Board\n");
+       au1xxx_gpio_tristate(5);
+       printk("B1900100: %X\n", *((volatile u32*)0xB1900100));
+       printk("B190002C: %X\n", *((volatile u32*)0xB190002C));
+}
+
diff -urN linux/arch/mips/au1000/ficmmp/init.c 
linux/arch/mips/au1000/ficmmp/init.c
--- linux/arch/mips/au1000/ficmmp/Attic/init.c  1970/01/01 00:00:00
+++ linux/arch/mips/au1000/ficmmp/Attic/init.c  Sun Jan 30 08:01:27 2005        
1.1.2.1
@@ -0,0 +1,76 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *     PB1200 board setup
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/bootmem.h>
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+#include <linux/config.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+extern void  __init prom_init_cmdline(void);
+extern char *prom_getenv(char *envname);
+
+const char *get_system_type(void)
+{
+       return "FIC Multimedia Player (Au1200)";
+}
+
+u32 mae_memsize = 0;
+
+int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
+{
+       unsigned char *memsize_str;
+       unsigned long memsize;
+
+       prom_argc = argc;
+       prom_argv = argv;
+       prom_envp = envp;
+
+       mips_machgroup = MACH_GROUP_ALCHEMY;
+       mips_machtype = MACH_PB1000;    /* set the platform # */   
+       prom_init_cmdline();
+
+       memsize_str = prom_getenv("memsize");
+       if (!memsize_str) {
+               memsize = 0x08000000;
+       } else {
+               memsize = simple_strtol(memsize_str, NULL, 0);
+       }
+
+       /* reserved 32MB for MAE driver */
+       memsize -= (32 * 1024 * 1024);
+       add_memory_region(0, memsize, BOOT_MEM_RAM);
+       mae_memsize = memsize; /* for drivers/char/au1xxx_mae.c */
+       return 0;
+}
+
diff -urN linux/arch/mips/au1000/ficmmp/irqmap.c 
linux/arch/mips/au1000/ficmmp/irqmap.c
--- linux/arch/mips/au1000/ficmmp/Attic/irqmap.c        1970/01/01 00:00:00
+++ linux/arch/mips/au1000/ficmmp/Attic/irqmap.c        Sun Jan 30 08:01:27 
2005        1.1.2.1
@@ -0,0 +1,61 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *     Au1xxx irq map table
+ *
+ *  This program is free software; you can redistribute         it and/or 
modify it
+ *  under  the terms of         the GNU General  Public License as published 
by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED          ``AS  IS'' AND   ANY  EXPRESS OR 
IMPLIED
+ *  WARRANTIES,          INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED 
WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED          TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; 
LOSS OF
+ *  USE, DATA, OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN         CONTRACT, STRICT LIABILITY, OR 
TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/au1000.h>
+#include <asm/ficmmp.h>
+
+au1xxx_irq_map_t au1xxx_irq_map[] = {
+       { FICMMP_IDE_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1XXX_SMC91111_IRQ, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_GPIO_1 , INTC_INT_FALL_EDGE, 0 },              // main button
+       { AU1000_GPIO_6 , INTC_INT_RISE_EDGE, 0 },              // select button
+       { AU1000_GPIO_12, INTC_INT_FALL_EDGE, 0 },              // guide button
+       { AU1000_GPIO_17, INTC_INT_RISE_EDGE, 0 },              // down button
+       { AU1000_GPIO_19, INTC_INT_RISE_EDGE, 0 },              // left button
+       { AU1000_GPIO_26, INTC_INT_RISE_EDGE, 0 },              // right button
+       { AU1000_GPIO_28, INTC_INT_RISE_EDGE, 0 },              // up button
+};
+
+int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+
diff -urN linux/arch/mips/au1000/pb1200/Makefile 
linux/arch/mips/au1000/pb1200/Makefile
--- linux/arch/mips/au1000/pb1200/Attic/Makefile        1970/01/01 00:00:00
+++ linux/arch/mips/au1000/pb1200/Attic/Makefile        Sun Jan 30 08:01:28 
2005        1.1.2.1
@@ -0,0 +1,25 @@
+#
+#  Copyright 2000 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc.
+#      ppopov@mvista.com or source@mvista.com
+#
+# Makefile for the Alchemy Semiconductor PB1000 board.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+
+USE_STANDARD_AS_RULE := true
+
+O_TARGET := pb1200.o
+
+obj-y := init.o board_setup.o irqmap.o
+
+ifdef CONFIG_MMC
+obj-y += mmc_support.o
+export-objs +=mmc_support.o
+endif
+
+
+include $(TOPDIR)/Rules.make
diff -urN linux/arch/mips/au1000/pb1200/board_setup.c 
linux/arch/mips/au1000/pb1200/board_setup.c
--- linux/arch/mips/au1000/pb1200/Attic/board_setup.c   1970/01/01 00:00:00
+++ linux/arch/mips/au1000/pb1200/Attic/board_setup.c   Sun Jan 30 08:01:28 
2005        1.1.2.1
@@ -0,0 +1,190 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *     Alchemy Pb1200 board setup.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/mc146818rtc.h>
+#include <linux/delay.h>
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
+#include <linux/ide.h>
+#endif
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/keyboard.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/pgtable.h>
+#include <asm/au1000.h>
+#include <asm/au1xxx_dbdma.h>
+
+#ifdef CONFIG_MIPS_PB1200
+#include <asm/pb1200.h>
+#endif
+
+#ifdef CONFIG_MIPS_DB1200
+#include <asm/db1200.h>
+#define PB1200_ETH_INT DB1200_ETH_INT
+#define PB1200_IDE_INT DB1200_IDE_INT
+#endif
+
+extern struct rtc_ops no_rtc_ops;
+
+extern void _board_init_irq(void);
+extern void    (*board_init_irq)(void);
+
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX
+extern struct ide_ops *ide_ops;
+extern struct ide_ops au1xxx_ide_ops;
+extern u32 au1xxx_ide_virtbase;
+extern u64 au1xxx_ide_physbase;
+extern int au1xxx_ide_irq;
+
+u32 led_base_addr;
+/* Ddma */
+chan_tab_t *ide_read_ch, *ide_write_ch;
+u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma
+
+dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 
0, 0x00000000, 0, 0 };
+#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */
+
+void board_reset (void)
+{
+       bcsr->resets = 0;
+}
+
+void __init board_setup(void)
+{
+       char *argptr = NULL;
+       u32 pin_func;
+       rtc_ops = &no_rtc_ops;
+
+#if 0
+       /* Enable PSC1 SYNC for AC97.  Normaly done in audio driver,
+        * but it is board specific code, so put it here.
+        */
+       pin_func = au_readl(SYS_PINFUNC);
+       au_sync();
+       pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
+       au_writel(pin_func, SYS_PINFUNC);
+
+       au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
+       au_sync();
+#endif
+
+#if defined( CONFIG_I2C_ALGO_AU1550 )
+       {
+       u32 freq0, clksrc;
+
+       /* Select SMBUS in CPLD */
+       bcsr->resets &= ~(BCSR_RESETS_PCS0MUX);
+
+       pin_func = au_readl(SYS_PINFUNC);
+       au_sync();
+       pin_func &= ~(3<<17 | 1<<4);
+       /* Set GPIOs correctly */
+       pin_func |= 2<<17;
+       au_writel(pin_func, SYS_PINFUNC);
+       au_sync();
+
+       /* The i2c driver depends on 50Mhz clock */
+       freq0 = au_readl(SYS_FREQCTRL0);
+       au_sync();
+       freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
+       freq0 |= (3<<SYS_FC_FRDIV1_BIT);
+       /* 396Mhz / (3+1)*2 == 49.5Mhz */
+       au_writel(freq0, SYS_FREQCTRL0);
+       au_sync();
+       freq0 |= SYS_FC_FE1;
+       au_writel(freq0, SYS_FREQCTRL0);
+       au_sync();
+
+       clksrc = au_readl(SYS_CLKSRC);
+       au_sync();
+       clksrc &= ~0x01f00000;
+       /* bit 22 is EXTCLK0 for PSC0 */
+       clksrc |= (0x3 << 22);
+       au_writel(clksrc, SYS_CLKSRC);
+       au_sync();
+       }
+#endif
+
+#ifdef CONFIG_FB_AU1200
+       argptr = prom_getcmdline();
+#ifdef CONFIG_MIPS_PB1200
+       strcat(argptr, " video=au1200fb:panel:s11");
+#endif
+#ifdef CONFIG_MIPS_DB1200
+       strcat(argptr, " video=au1200fb:panel:s7");
+#endif
+#endif
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
+       /*
+        * Iniz IDE parameters
+        */
+       ide_ops = &au1xxx_ide_ops;
+       au1xxx_ide_irq = PB1200_IDE_INT;
+       au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR;
+       au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR);
+       /*
+        * change PIO or PIO+Ddma
+        * check the GPIO-5 pin condition. pb1200:s18_dot */
+       switch4ddma = (au_readl(SYS_PINSTATERD) & (1 << 5)) ? 1 : 0; 
+#endif
+
+       /* The Pb1200 development board uses external MUX for PSC0 to
+       support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
+       */
+#if defined(CONFIG_AU1550_PSC_SPI) && defined(CONFIG_I2C_ALGO_AU1550)
+       #error I2C and SPI are mutually exclusive. Both are physically 
connected to PSC0.\
+                       Refer to Pb1200/Db1200 documentation.
+#elif defined( CONFIG_AU1550_PSC_SPI )
+       bcsr->resets |= BCSR_RESETS_PCS0MUX;
+#elif defined( CONFIG_I2C_ALGO_AU1550 )
+       bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
+#endif
+       au_sync();
+
+#ifdef CONFIG_MIPS_PB1200
+       printk("AMD Alchemy Pb1200 Board\n");
+#endif
+#ifdef CONFIG_MIPS_DB1200
+       printk("AMD Alchemy Db1200 Board\n");
+#endif
+
+       /* Setup Pb1200 External Interrupt Controller */
+       {
+               extern void (*board_init_irq)(void);
+               extern void _board_init_irq(void);
+               board_init_irq = _board_init_irq;
+       }
+}
diff -urN linux/arch/mips/au1000/pb1200/init.c 
linux/arch/mips/au1000/pb1200/init.c
--- linux/arch/mips/au1000/pb1200/Attic/init.c  1970/01/01 00:00:00
+++ linux/arch/mips/au1000/pb1200/Attic/init.c  Sun Jan 30 08:01:28 2005        
1.1.2.1
@@ -0,0 +1,72 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *     PB1200 board setup
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/bootmem.h>
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+#include <linux/config.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+extern void  __init prom_init_cmdline(void);
+extern char *prom_getenv(char *envname);
+
+const char *get_system_type(void)
+{
+       return "AMD Alchemy Au1200/Pb1200";
+}
+
+u32 mae_memsize = 0;
+
+int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
+{
+       unsigned char *memsize_str;
+       unsigned long memsize;
+
+       prom_argc = argc;
+       prom_argv = argv;
+       prom_envp = envp;
+
+       mips_machgroup = MACH_GROUP_ALCHEMY;
+       mips_machtype = MACH_PB1000;    /* set the platform # */   
+       prom_init_cmdline();
+
+       memsize_str = prom_getenv("memsize");
+       if (!memsize_str) {
+               memsize = 0x08000000;
+       } else {
+               memsize = simple_strtol(memsize_str, NULL, 0);
+       }
+       add_memory_region(0, memsize, BOOT_MEM_RAM);
+       return 0;
+}
+
diff -urN linux/arch/mips/au1000/pb1200/irqmap.c 
linux/arch/mips/au1000/pb1200/irqmap.c
--- linux/arch/mips/au1000/pb1200/Attic/irqmap.c        1970/01/01 00:00:00
+++ linux/arch/mips/au1000/pb1200/Attic/irqmap.c        Sun Jan 30 08:01:28 
2005        1.1.2.1
@@ -0,0 +1,180 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *     Au1xxx irq map table
+ *
+ *  This program is free software; you can redistribute         it and/or 
modify it
+ *  under  the terms of         the GNU General  Public License as published 
by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED          ``AS  IS'' AND   ANY  EXPRESS OR 
IMPLIED
+ *  WARRANTIES,          INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED 
WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED          TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; 
LOSS OF
+ *  USE, DATA, OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN         CONTRACT, STRICT LIABILITY, OR 
TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/au1000.h>
+
+#ifdef CONFIG_MIPS_PB1200
+#include <asm/pb1200.h>
+#endif
+
+#ifdef CONFIG_MIPS_DB1200
+#include <asm/db1200.h>
+#define PB1200_INT_BEGIN DB1200_INT_BEGIN
+#define PB1200_INT_END DB1200_INT_END
+#endif
+
+au1xxx_irq_map_t au1xxx_irq_map[] = {
+       { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt 
cascade
+};
+
+int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+
+/*
+ *     Support for External interrupts on the PbAu1200 Development platform.
+ */
+static volatile int pb1200_cascade_en=0;
+
+void pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs)
+{
+       unsigned short bisr = bcsr->int_status;
+       int extirq_nr = 0;
+
+       /* Clear all the edge interrupts. This has no effect on level */
+       bcsr->int_status = bisr;
+       for( ; bisr; bisr &= (bisr-1) )
+       {
+               extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr);
+               /* Ack and dispatch IRQ */
+               do_IRQ(extirq_nr,regs);
+       }
+}
+
+inline void pb1200_enable_irq(unsigned int irq_nr)
+{
+       bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
+       bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN);
+}
+
+inline void pb1200_disable_irq(unsigned int irq_nr)
+{
+       bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
+       bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN);
+}
+
+static unsigned int pb1200_startup_irq( unsigned int irq_nr )
+{
+       if (++pb1200_cascade_en == 1)
+       {
+               request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
+                       0, "Pb1200 Cascade", &pb1200_cascade_handler );
+#ifdef CONFIG_MIPS_PB1200
+    /* We have a problem with CPLD rev3. Enable a workaround */
+       if( ((bcsr->whoami & BCSR_WHOAMI_CPLD)>>4) <= 3)
+       {
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n");
+               printk("updated to latest revision. This software will not\n");
+               printk("work on anything less than CPLD rev4\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               printk("\nWARNING!!!\n");
+               while(1);
+       }
+#endif
+       }
+       pb1200_enable_irq(irq_nr);
+       return 0;
+}
+
+static void pb1200_shutdown_irq( unsigned int irq_nr )
+{
+       pb1200_disable_irq(irq_nr);
+       if (--pb1200_cascade_en == 0)
+       {
+               free_irq(AU1000_GPIO_7,&pb1200_cascade_handler );
+       }
+       return;
+}
+
+static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr)
+{
+       pb1200_disable_irq( irq_nr );
+}
+
+static void pb1200_end_irq(unsigned int irq_nr)
+{
+       if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+               pb1200_enable_irq(irq_nr);
+       }
+}
+
+static struct hw_interrupt_type external_irq_type =
+{
+#ifdef CONFIG_MIPS_PB1200
+       "Pb1200 Ext",
+#endif
+#ifdef CONFIG_MIPS_DB1200
+       "Db1200 Ext",
+#endif
+       pb1200_startup_irq,
+       pb1200_shutdown_irq,
+       pb1200_enable_irq,
+       pb1200_disable_irq,
+       pb1200_mask_and_ack_irq,
+       pb1200_end_irq,
+       NULL
+};
+
+void _board_init_irq(void)
+{
+       int irq_nr;
+
+       for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++)
+       {
+               irq_desc[irq_nr].handler = &external_irq_type;
+               pb1200_disable_irq(irq_nr);
+       }
+
+       /* GPIO_7 can not be hooked here, so it is hooked upon first
+       request of any source attached to the cascade */
+}
+
diff -urN linux/arch/mips/au1000/pb1200/mmc_support.c 
linux/arch/mips/au1000/pb1200/mmc_support.c
--- linux/arch/mips/au1000/pb1200/Attic/mmc_support.c   1970/01/01 00:00:00
+++ linux/arch/mips/au1000/pb1200/Attic/mmc_support.c   Sun Jan 30 08:01:28 
2005        1.1.2.1
@@ -0,0 +1,141 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *
+ *     MMC support routines for PB1200.
+ *
+ *
+ * Copyright (c) 2003-2004 Embedded Edge, LLC.
+ * Author: Embedded Edge, LLC.
+ * Contact: dan@embeddededge.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <asm/irq.h>
+#include <asm/au1000.h>
+#include <asm/au1100_mmc.h>
+
+#ifdef CONFIG_MIPS_PB1200
+#include <asm/pb1200.h>
+#endif
+
+#ifdef CONFIG_MIPS_DB1200
+/* NOTE: DB1200 only has SD0 pinned out and usable */
+#include <asm/db1200.h>
+#endif
+
+/* SD/MMC controller support functions */
+
+/*
+ * Detect card.
+ */
+void mmc_card_inserted(int socket, int *result)
+{
+       u16 mask;
+
+       if (socket)
+#ifdef CONFIG_MIPS_DB1200
+               mask = 0;
+#else
+               mask = BCSR_INT_SD1INSERT; 
+#endif
+       else
+               mask = BCSR_INT_SD0INSERT;
+
+       *result = ((bcsr->sig_status & mask) != 0);
+}
+
+/*
+ * Check card write protection.
+ */
+void mmc_card_writable(int socket, int *result)
+{
+       u16 mask;
+
+       if (socket)
+#ifdef CONFIG_MIPS_DB1200
+               mask = 0;
+#else
+               mask = BCSR_STATUS_SD1WP; 
+#endif
+       else
+               mask = BCSR_STATUS_SD0WP;
+
+       /* low means card writable */
+       if (!(bcsr->status & mask)) {
+               *result = 1;
+       } else {
+               *result = 0;
+       }
+}
+
+/*
+ * Apply power to card slot.
+ */
+void mmc_power_on(int socket)
+{
+       u16 mask;
+
+       if (socket)
+#ifdef CONFIG_MIPS_DB1200
+               mask = 0;
+#else
+               mask = BCSR_BOARD_SD1PWR;
+#endif
+       else
+               mask = BCSR_BOARD_SD0PWR;
+
+       bcsr->board |= mask;
+       au_sync_delay(1);
+}
+
+/*
+ * Remove power from card slot.
+ */
+void mmc_power_off(int socket)
+{
+       u16 mask;
+
+       if (socket)
+#ifdef CONFIG_MIPS_DB1200
+               mask = 0;
+#else
+               mask = BCSR_BOARD_SD1PWR;
+#endif
+       else
+               mask = BCSR_BOARD_SD0PWR;
+
+       bcsr->board &= ~mask;
+       au_sync_delay(1);
+}
+
+EXPORT_SYMBOL(mmc_card_inserted);
+EXPORT_SYMBOL(mmc_card_writable);
+EXPORT_SYMBOL(mmc_power_on);
+EXPORT_SYMBOL(mmc_power_off);
+
diff -urN linux/arch/mips/au1000/pb1550/board_setup.c 
linux/arch/mips/au1000/pb1550/board_setup.c
--- linux/arch/mips/au1000/pb1550/board_setup.c 2004/09/18 22:07:37     1.1.2.6
+++ linux/arch/mips/au1000/pb1550/board_setup.c 2005/01/30 08:01:28     1.1.2.7
@@ -48,6 +48,16 @@
 
 extern struct rtc_ops no_rtc_ops;
 
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
+extern struct ide_ops *ide_ops;
+extern struct ide_ops au1xxx_ide_ops;
+extern u32 au1xxx_ide_virtbase;
+extern u64 au1xxx_ide_physbase;
+extern unsigned int au1xxx_ide_irq;
+
+u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma
+#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */
+
 void board_reset (void)
 {
     /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
@@ -78,5 +88,36 @@
        au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
        au_sync();
 
+#if defined(CONFIG_AU1XXX_SMC91111)
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
+#error "Resource conflict occured. Disable either Ethernet or IDE daughter 
card."
+#else
+#define CPLD_CONTROL (0xAF00000C)
+       {
+       /* set up the Static Bus timing */
+       /* only 396Mhz */
+       /* reset the DC */
+       au_writew(au_readw(CPLD_CONTROL) | 0x0f, CPLD_CONTROL);
+       au_writel(0x00010003, MEM_STCFG0);
+       au_writel(0x000c00c0, MEM_STCFG2);
+       au_writel(0x85E1900D, MEM_STTIME2);
+       }
+#endif
+#endif /* end CONFIG_SMC91111 */
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
+       /*
+        * Iniz IDE parameters
+        */
+       ide_ops = &au1xxx_ide_ops;
+       au1xxx_ide_irq = DAUGHTER_CARD_IRQ;;
+       au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR;
+       au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR);
+       /*
+        * change PIO or PIO+Ddma
+        * check the GPIO-6 pin condition. pb1550:s15_dot
+        */
+       switch4ddma = (au_readl(SYS_PINSTATERD) & (1 << 6)) ? 1 : 0;
+#endif
        printk("AMD Alchemy Pb1550 Board\n");
 }
diff -urN linux/arch/mips/au1000/pb1550/irqmap.c 
linux/arch/mips/au1000/pb1550/irqmap.c
--- linux/arch/mips/au1000/pb1550/irqmap.c      2004/04/02 09:04:01     1.1.2.4
+++ linux/arch/mips/au1000/pb1550/irqmap.c      2005/01/30 08:01:28     1.1.2.5
@@ -50,6 +50,9 @@
 au1xxx_irq_map_t au1xxx_irq_map[] = {
        { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
        { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
+#ifdef CONFIG_AU1XXX_SMC91111
+       { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 },
+#endif
 };
 
 int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
diff -urN linux/arch/mips/kernel/cpu-probe.c linux/arch/mips/kernel/cpu-probe.c
--- linux/arch/mips/kernel/cpu-probe.c  2004/09/20 15:55:30     1.1.2.37
+++ linux/arch/mips/kernel/cpu-probe.c  2005/01/30 08:01:28     1.1.2.38
@@ -105,6 +105,7 @@
        case CPU_AU1100:
        case CPU_AU1500:
        case CPU_AU1550:
+       case CPU_AU1200:
                if (au1k_wait_ptr != NULL) {
                        cpu_wait = au1k_wait_ptr;
                        printk(" available.\n");
diff -urN linux/drivers/sound/au1550_psc.c linux/drivers/sound/au1550_psc.c
--- linux/drivers/sound/Attic/au1550_psc.c      2004/09/18 22:07:37     1.1.2.4
+++ linux/drivers/sound/Attic/au1550_psc.c      2005/01/30 08:01:28     1.1.2.5
@@ -30,6 +30,7 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
  */
+
 #include <linux/version.h>
 #include <linux/module.h>
 #include <linux/string.h>
@@ -63,6 +64,14 @@
 #include <asm/db1x00.h>
 #endif
 
+#ifdef CONFIG_MIPS_PB1200
+#include <asm/pb1200.h>
+#endif
+
+#ifdef CONFIG_MIPS_DB1200
+#include <asm/db1200.h>
+#endif
+
 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
 
 #define AU1550_MODULE_NAME "Au1550 psc audio"
@@ -521,7 +530,14 @@
        spin_unlock_irqrestore(&s->lock, flags);
 }
 
-
+/* 
+   NOTE: The xmit slots cannot be changed on the fly when in full-duplex 
+   because the AC'97 block must be stopped/started.  When using this driver 
+   in full-duplex (in & out at the same time), the DMA engine will stop if 
+   you disable the block.
+   TODO: change implementation to properly restart adc/dac after setting 
+   xmit slots.
+*/
 static void
 set_xmit_slots(int num_channels)
 {
@@ -565,6 +581,14 @@
        } while ((stat & PSC_AC97STAT_DR) == 0);
 }
 
+/* 
+   NOTE: The recv slots cannot be changed on the fly when in full-duplex 
+   because the AC'97 block must be stopped/started.  When using this driver 
+   in full-duplex (in & out at the same time), the DMA engine will stop if 
+   you disable the block.
+   TODO: change implementation to properly restart adc/dac after setting 
+   recv slots.
+*/
 static void
 set_recv_slots(int num_channels)
 {
@@ -608,7 +632,6 @@
 
        spin_lock_irqsave(&s->lock, flags);
 
-       set_xmit_slots(db->num_channels);
        au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
        au_sync();
        au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
@@ -640,7 +663,6 @@
                        db->nextIn -= db->dmasize;
        }
 
-       set_recv_slots(db->num_channels);
        au1xxx_dbdma_start(db->dmanr);
        au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
        au_sync();
@@ -752,12 +774,16 @@
        if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
                dbg("AC97C status = 0x%08x", ac97c_stat);
 #endif
+       /* There is a possiblity that we are getting 1 interrupt for
+          multiple descriptors. Use ddma api to find out how many
+          completed.
+       */
        db->dma_qcount--;
 
        if (db->count >= db->fragsize) {
                if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
                                                        db->fragsize) == 0) {
-                       err("qcount < 2 and no ring room!");
+                       err("qcount < 2 and no ring room1!");
                }
                db->nextOut += db->fragsize;
                if (db->nextOut >= db->rawbuf + db->dmasize)
@@ -941,11 +967,12 @@
 
                /* duplicate every audio frame src_factor times
                */
-               for (i = 0; i < db->src_factor; i++)
+               for (i = 0; i < db->src_factor; i++) {
                        memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
+                       dmabuf += interp_bytes_per_sample;
+               }
 
                userbuf += db->user_bytes_per_sample;
-               dmabuf += interp_bytes_per_sample;
        }
 
        return num_samples * interp_bytes_per_sample;
@@ -1203,7 +1230,7 @@
                while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
                        if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
                                                        db->fragsize) == 0) {
-                               err("qcount < 2 and no ring room!");
+                               err("qcount < 2 and no ring room!0");
                        }
                        db->nextOut += db->fragsize;
                        if (db->nextOut >= db->rawbuf + db->dmasize)
@@ -1481,6 +1508,7 @@
                                        return -EINVAL;
                                stop_adc(s);
                                s->dma_adc.num_channels = val;
+                               set_recv_slots(val);
                                if ((ret = prog_dmabuf_adc(s)))
                                        return ret;
                        }
@@ -1538,6 +1566,7 @@
                                }
 
                                s->dma_dac.num_channels = val;
+                               set_xmit_slots(val);
                                if ((ret = prog_dmabuf_dac(s)))
                                        return ret;
                        }
@@ -1832,10 +1861,8 @@
                down(&s->open_sem);
        }
 
-       stop_dac(s);
-       stop_adc(s);
-
        if (file->f_mode & FMODE_READ) {
+               stop_adc(s);
                s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
                        s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
                s->dma_adc.num_channels = 1;
@@ -1846,6 +1873,7 @@
        }
 
        if (file->f_mode & FMODE_WRITE) {
+               stop_dac(s);
                s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
                        s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
                s->dma_dac.num_channels = 1;
@@ -2091,6 +2119,9 @@
                                             ac97_read_proc, &s->codec);
 #endif
 
+       set_xmit_slots(1);
+       set_recv_slots(1);
+
        return 0;
 
  err_dev3:
diff -urN linux/include/asm-mips/au1xxx_gpio.h 
linux/include/asm-mips/au1xxx_gpio.h
--- linux/include/asm-mips/Attic/au1xxx_gpio.h  1970/01/01 00:00:00
+++ linux/include/asm-mips/Attic/au1xxx_gpio.h  Sun Jan 30 08:01:28 2005        
1.1.2.1
@@ -0,0 +1,22 @@
+
+
+#ifndef __AU1XXX_GPIO_H
+#define __AU1XXX_GPIO_H
+
+void au1xxx_gpio1_set_inputs(void);
+void au1xxx_gpio_tristate(int signal);
+void au1xxx_gpio_write(int signal, int value);
+int  au1xxx_gpio_read(int signal);
+
+typedef volatile struct
+{
+       u32 dir;
+       u32 reserved;
+       u32 output;
+       u32 pinstate;
+       u32 inten;
+       u32 enable;
+
+} AU1X00_GPIO2;
+
+#endif //__AU1XXX_GPIO_H
diff -urN linux/include/asm-mips/ficmmp.h linux/include/asm-mips/ficmmp.h
--- linux/include/asm-mips/Attic/ficmmp.h       1970/01/01 00:00:00
+++ linux/include/asm-mips/Attic/ficmmp.h       Sun Jan 30 08:01:28 2005        
1.1.2.1
@@ -0,0 +1,156 @@
+/*
+ * FIC MMP
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_FICMMP_H
+#define __ASM_FICMMP_H
+
+#include <linux/types.h>
+#include <asm/au1000.h>
+#include <asm/au1xxx_gpio.h>
+
+// This is defined in au1000.h with bogus value
+#undef AU1X00_EXTERNAL_INT
+
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
+/* SPI and SMB are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define SPI_PSC_BASE        PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE      PSC0_BASE_ADDR
+/* AC97 and I2S are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define AC97_PSC_BASE       PSC1_BASE_ADDR
+#define I2S_PSC_BASE           PSC1_BASE_ADDR
+
+
+/*
+ * SMSC LAN91C111
+ */
+#define AU1XXX_SMC91111_PHYS_ADDR      (0xAC000300)
+#define AU1XXX_SMC91111_IRQ                    AU1000_GPIO_5
+
+/* DC_IDE and DC_ETHERNET */
+#define FICMMP_IDE_INT AU1000_GPIO_4
+
+#define AU1XXX_ATA_PHYS_ADDR   (0x0C800000)
+#define AU1XXX_ATA_REG_OFFSET  (5)
+/*
+#define AU1XXX_ATA_BASE                (0x0C800000)
+#define AU1XXX_ATA_END                 (0x0CFFFFFF)
+#define AU1XXX_ATA_MEM_SIZE            (AU1XXX_ATA_END - AU1XXX_ATA_BASE +1)
+
+#define AU1XXX_ATA_REG_OFFSET          (5)
+*/
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT)\
+       ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
+
+       
+#define FICMMP_CONFIG_BASE             0xAD000000
+#define FICMMP_CONFIG_ENABLE   13
+
+#define FICMMP_CONFIG_I2SFREQ(N)       (N<<0)
+#define FICMMP_CONFIG_I2SXTAL0         (1<<0)
+#define FICMMP_CONFIG_I2SXTAL1         (1<<1)
+#define FICMMP_CONFIG_I2SXTAL2         (1<<2)
+#define FICMMP_CONFIG_I2SXTAL3         (1<<3)
+#define FICMMP_CONFIG_ADV1                     (1<<4)
+#define FICMMP_CONFIG_IDERST           (1<<5)
+#define FICMMP_CONFIG_LCMEN                    (1<<6)
+#define FICMMP_CONFIG_CAMPWDN          (1<<7)
+#define FICMMP_CONFIG_USBPWREN         (1<<8)
+#define FICMMP_CONFIG_LCMPWREN         (1<<9)
+#define FICMMP_CONFIG_TVOUTPWREN       (1<<10)
+#define FICMMP_CONFIG_RS232PWREN       (1<<11)
+#define FICMMP_CONFIG_LCMDATAOUT       (1<<12)
+#define FICMMP_CONFIG_TVODATAOUT       (1<<13)
+#define FICMMP_CONFIG_ADV3                     (1<<14)
+#define FICMMP_CONFIG_ADV4                     (1<<15)
+
+#define I2S_FREQ_8_192                         (0x0)
+#define I2S_FREQ_11_2896                       (0x1)
+#define I2S_FREQ_12_288                                (0x2)
+#define I2S_FREQ_24_576                                (0x3)
+//#define I2S_FREQ_12_288                      (0x4)
+#define I2S_FREQ_16_9344                       (0x5)
+#define I2S_FREQ_18_432                                (0x6)
+#define I2S_FREQ_36_864                                (0x7)
+#define I2S_FREQ_16_384                                (0x8)
+#define I2S_FREQ_22_5792                       (0x9)
+//#define I2S_FREQ_24_576                      (0x10)
+#define I2S_FREQ_49_152                                (0x11)
+//#define I2S_FREQ_24_576                      (0x12)
+#define I2S_FREQ_33_8688                       (0x13)
+//#define I2S_FREQ_36_864                      (0x14)
+#define I2S_FREQ_73_728                                (0x15)
+
+#define FICMMP_IDE_PWR                         9
+#define FICMMP_FOCUS_RST                       2
+
+static __inline void ficmmp_config_set(u16 bits)
+{
+       extern u16 ficmmp_config;
+       //printk("set_config: %X, Old: %X, New: %X\n", bits, ficmmp_config, 
ficmmp_config | bits);
+       ficmmp_config |= bits;
+       *((u16*)FICMMP_CONFIG_BASE) = ficmmp_config;
+}
+
+static __inline void ficmmp_config_clear(u16 bits)
+{
+       extern u16 ficmmp_config;
+//     printk("clear_config: %X, Old: %X, New: %X\n", bits, ficmmp_config, 
ficmmp_config & ~bits);
+       ficmmp_config &= ~bits;
+       *((u16*)FICMMP_CONFIG_BASE) = ficmmp_config;
+}
+
+static __inline void ficmmp_config_init(void)
+{
+       au1xxx_gpio_write(FICMMP_CONFIG_ENABLE, 0);     //Enable configuration 
latch
+       ficmmp_config_set(FICMMP_CONFIG_LCMDATAOUT | FICMMP_CONFIG_TVODATAOUT | 
FICMMP_CONFIG_IDERST);  //Disable display data buffers
+       ficmmp_config_set(FICMMP_CONFIG_I2SFREQ(I2S_FREQ_36_864));
+}
+
+static __inline u32 ficmmp_set_i2s_sample_rate(u32 rate)
+{
+       u32 freq;
+       
+       switch(rate)
+       {
+       case 88200: 
+       case 44100:
+       case  8018: freq = I2S_FREQ_11_2896; break;
+       case 48000:
+       case 32000: //freq = I2S_FREQ_18_432; break;
+       case  8000: freq = I2S_FREQ_12_288; break;
+       default:    freq = I2S_FREQ_12_288; rate = 8000; 
+       }
+       ficmmp_config_clear(FICMMP_CONFIG_I2SFREQ(0xF));
+       ficmmp_config_set(FICMMP_CONFIG_I2SFREQ(freq));
+       return rate;
+}
+
+#endif /* __ASM_FICMMP_H */
+
diff -urN linux/include/asm-mips/pb1200.h linux/include/asm-mips/pb1200.h
--- linux/include/asm-mips/Attic/pb1200.h       1970/01/01 00:00:00
+++ linux/include/asm-mips/Attic/pb1200.h       Sun Jan 30 08:01:28 2005        
1.1.2.1
@@ -0,0 +1,244 @@
+/*
+ * AMD Alchemy PB1200 Referrence Board
+ * Board Registers defines.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1200_H
+#define __ASM_PB1200_H
+
+#include <linux/types.h>
+
+// This is defined in au1000.h with bogus value
+#undef AU1X00_EXTERNAL_INT
+
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
+
+/* SPI and SMB are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define SPI_PSC_BASE        PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE      PSC0_BASE_ADDR
+/* AC97 and I2S are muxed on the Pb1200 board.
+   Refer to board documentation.
+ */
+#define AC97_PSC_BASE       PSC1_BASE_ADDR
+#define I2S_PSC_BASE           PSC1_BASE_ADDR
+
+#define BCSR_KSEG1_ADDR 0xAD800000
+
+typedef volatile struct
+{
+       /*00*/  u16 whoami;
+               u16 reserved0;
+       /*04*/  u16 status;
+               u16 reserved1;
+       /*08*/  u16 switches;
+               u16 reserved2;
+       /*0C*/  u16 resets;
+               u16 reserved3;
+
+       /*10*/  u16 pcmcia;
+               u16 reserved4;
+       /*14*/  u16 board;
+               u16 reserved5;
+       /*18*/  u16 disk_leds;
+               u16 reserved6;
+       /*1C*/  u16 system;
+               u16 reserved7;
+
+       /*20*/  u16 intclr;
+               u16 reserved8;
+       /*24*/  u16 intset;
+               u16 reserved9;
+       /*28*/  u16 intclr_mask;
+               u16 reserved10;
+       /*2C*/  u16 intset_mask;
+               u16 reserved11;
+
+       /*30*/  u16 sig_status;
+               u16 reserved12;
+       /*34*/  u16 int_status;
+               u16 reserved13;
+       /*38*/  u16 reserved14;
+               u16 reserved15;
+       /*3C*/  u16 reserved16;
+               u16 reserved17;
+
+} BCSR;
+
+static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+
+/*
+ * Register bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID       0x000F
+#define BCSR_WHOAMI_CPLD       0x00F0
+#define BCSR_WHOAMI_BOARD      0x0F00
+
+#define BCSR_STATUS_PCMCIA0VS  0x0003
+#define BCSR_STATUS_PCMCIA1VS  0x000C
+#define BCSR_STATUS_SWAPBOOT   0x0040
+#define BCSR_STATUS_FLASHBUSY  0x0100
+#define BCSR_STATUS_IDECBLID   0x0200
+#define BCSR_STATUS_SD0WP              0x0400
+#define BCSR_STATUS_SD1WP              0x0800
+#define BCSR_STATUS_U0RXD              0x1000
+#define BCSR_STATUS_U1RXD              0x2000
+
+#define BCSR_SWITCHES_OCTAL    0x00FF
+#define BCSR_SWITCHES_DIP_1    0x0080
+#define BCSR_SWITCHES_DIP_2    0x0040
+#define BCSR_SWITCHES_DIP_3    0x0020
+#define BCSR_SWITCHES_DIP_4    0x0010
+#define BCSR_SWITCHES_DIP_5    0x0008
+#define BCSR_SWITCHES_DIP_6    0x0004
+#define BCSR_SWITCHES_DIP_7    0x0002
+#define BCSR_SWITCHES_DIP_8    0x0001
+#define BCSR_SWITCHES_ROTARY   0x0F00
+
+#define BCSR_RESETS_ETH                0x0001
+#define BCSR_RESETS_CAMERA     0x0002
+#define BCSR_RESETS_DC         0x0004
+#define BCSR_RESETS_IDE                0x0008
+/* not resets but in the same register */
+#define BCSR_RESETS_WSCFSM  0x0800
+#define BCSR_RESETS_PCS0MUX    0x1000
+#define BCSR_RESETS_PCS1MUX    0x2000
+#define BCSR_RESETS_SPISEL     0x4000
+#define BCSR_RESETS_SD1MUX  0x8000
+
+#define BCSR_PCMCIA_PC0VPP     0x0003
+#define BCSR_PCMCIA_PC0VCC     0x000C
+#define BCSR_PCMCIA_PC0DRVEN   0x0010
+#define BCSR_PCMCIA_PC0RST     0x0080
+#define BCSR_PCMCIA_PC1VPP     0x0300
+#define BCSR_PCMCIA_PC1VCC     0x0C00
+#define BCSR_PCMCIA_PC1DRVEN   0x1000
+#define BCSR_PCMCIA_PC1RST     0x8000
+
+#define BCSR_BOARD_LCDVEE      0x0001
+#define BCSR_BOARD_LCDVDD      0x0002
+#define BCSR_BOARD_LCDBL       0x0004
+#define BCSR_BOARD_CAMSNAP     0x0010
+#define BCSR_BOARD_CAMPWR      0x0020
+#define BCSR_BOARD_SD0PWR      0x0040
+#define BCSR_BOARD_SD1PWR      0x0080
+
+#define BCSR_LEDS_DECIMALS     0x00FF
+#define BCSR_LEDS_LED0         0x0100
+#define BCSR_LEDS_LED1         0x0200
+#define BCSR_LEDS_LED2         0x0400
+#define BCSR_LEDS_LED3         0x0800
+
+#define BCSR_SYSTEM_VDDI       0x001F
+#define BCSR_SYSTEM_POWEROFF   0x4000
+#define BCSR_SYSTEM_RESET      0x8000
+
+/* Bit positions for the different interrupt sources */
+#define BCSR_INT_IDE           0x0001
+#define BCSR_INT_ETH           0x0002
+#define BCSR_INT_PC0           0x0004
+#define BCSR_INT_PC0STSCHG     0x0008
+#define BCSR_INT_PC1           0x0010
+#define BCSR_INT_PC1STSCHG     0x0020
+#define BCSR_INT_DC                    0x0040
+#define BCSR_INT_FLASHBUSY     0x0080
+#define BCSR_INT_PC0INSERT     0x0100
+#define BCSR_INT_PC0EJECT      0x0200
+#define BCSR_INT_PC1INSERT     0x0400
+#define BCSR_INT_PC1EJECT      0x0800
+#define BCSR_INT_SD0INSERT     0x1000
+#define BCSR_INT_SD0EJECT      0x2000
+#define BCSR_INT_SD1INSERT     0x4000
+#define BCSR_INT_SD1EJECT      0x8000
+
+#define AU1XXX_SMC91111_PHYS_ADDR      (0x0D000300)
+#define AU1XXX_SMC91111_IRQ                    PB1200_ETH_INT
+
+#define AU1XXX_ATA_PHYS_ADDR           (0x0C800000)
+#define AU1XXX_ATA_PHYS_LEN                    (0x100)
+#define AU1XXX_ATA_REG_OFFSET  (5)
+#define AU1XXX_ATA_INT                 PB1200_IDE_INT
+#define AU1XXX_ATA_DDMA_REQ            DSCR_CMD0_DMA_REQ1;
+#define AU1XXX_ATA_RQSIZE              128
+
+#define NAND_PHYS_ADDR   0x1C000000
+
+/* Timing values as described in databook, * ns value stripped of
+ * lower 2 bits.
+ * These defines are here rather than an SOC1200 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H                       (18 >> 2)
+#define NAND_T_PUL                     (30 >> 2)
+#define NAND_T_SU                      (30 >> 2)
+#define NAND_T_WH                      (30 >> 2)
+
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT         0
+#define NAND_T_PUL_SHIFT       4
+#define NAND_T_SU_SHIFT                8
+#define NAND_T_WH_SHIFT                12
+
+#define NAND_TIMING    ((NAND_T_H   & 0xF)     << NAND_T_H_SHIFT)   | \
+                       ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
+                       ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
+                       ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
+
+
+/*
+ *     External Interrupts for Pb1200 as of 8/6/2004.
+ *   Bit positions in the CPLD registers can be calculated by taking
+ *   the interrupt define and subtracting the PB1200_INT_BEGIN value.
+ *    *example: IDE bis pos is  = 64 - 64
+                ETH bit pos is  = 65 - 64
+ */
+#define PB1200_INT_BEGIN               (AU1000_LAST_INTC1_INT + 1)
+#define PB1200_IDE_INT                 (PB1200_INT_BEGIN + 0)
+#define PB1200_ETH_INT                 (PB1200_INT_BEGIN + 1)
+#define PB1200_PC0_INT                 (PB1200_INT_BEGIN + 2)
+#define PB1200_PC0_STSCHG_INT  (PB1200_INT_BEGIN + 3)
+#define PB1200_PC1_INT                 (PB1200_INT_BEGIN + 4)
+#define PB1200_PC1_STSCHG_INT  (PB1200_INT_BEGIN + 5)
+#define PB1200_DC_INT                  (PB1200_INT_BEGIN + 6)
+#define PB1200_FLASHBUSY_INT   (PB1200_INT_BEGIN + 7)
+#define PB1200_PC0_INSERT_INT  (PB1200_INT_BEGIN + 8)
+#define PB1200_PC0_EJECT_INT   (PB1200_INT_BEGIN + 9)
+#define PB1200_PC1_INSERT_INT  (PB1200_INT_BEGIN + 10)
+#define PB1200_PC1_EJECT_INT   (PB1200_INT_BEGIN + 11)
+#define PB1200_SD0_INSERT_INT  (PB1200_INT_BEGIN + 12)
+#define PB1200_SD0_EJECT_INT   (PB1200_INT_BEGIN + 13)
+#define PB1200_SD1_INSERT_INT  (PB1200_INT_BEGIN + 14)
+#define PB1200_SD1_EJECT_INT   (PB1200_INT_BEGIN + 15)
+
+#define PB1200_INT_END                 (PB1200_INT_BEGIN + 15)
+
+/* For drivers/pcmcia/au1000_db1x00.c */
+#define BOARD_PC0_INT PB1200_PC0_INT
+#define BOARD_PC1_INT PB1200_PC1_INT
+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
+
+#endif /* __ASM_PB1200_H */
+
diff -urN linux/include/asm-mips/au1000.h linux/include/asm-mips/au1000.h
--- linux/include/asm-mips/Attic/au1000.h       2004/07/07 18:19:37     1.5.2.29
+++ linux/include/asm-mips/Attic/au1000.h       2005/01/30 08:01:28     1.5.2.30
@@ -160,28 +160,356 @@
 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
 #endif
 
-/* SDRAM Controller */
+/*
+ * SDRAM Register Offsets
+ */
 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || 
defined(CONFIG_SOC_AU1100)
-#define MEM_SDMODE0                0xB4000000
-#define MEM_SDMODE1                0xB4000004
-#define MEM_SDMODE2                0xB4000008
-
-#define MEM_SDADDR0                0xB400000C
-#define MEM_SDADDR1                0xB4000010
-#define MEM_SDADDR2                0xB4000014
-
-#define MEM_SDREFCFG               0xB4000018
-#define MEM_SDPRECMD               0xB400001C
-#define MEM_SDAUTOREF              0xB4000020
-
-#define MEM_SDWRMD0                0xB4000024
-#define MEM_SDWRMD1                0xB4000028
-#define MEM_SDWRMD2                0xB400002C
+#define MEM_SDMODE0            (0x0000)
+#define MEM_SDMODE1            (0x0004)
+#define MEM_SDMODE2            (0x0008)
+#define MEM_SDADDR0            (0x000C)
+#define MEM_SDADDR1            (0x0010)
+#define MEM_SDADDR2            (0x0014)
+#define MEM_SDREFCFG   (0x0018)
+#define MEM_SDPRECMD   (0x001C)
+#define MEM_SDAUTOREF  (0x0020)
+#define MEM_SDWRMD0            (0x0024)
+#define MEM_SDWRMD1            (0x0028)
+#define MEM_SDWRMD2            (0x002C)
+#define MEM_SDSLEEP            (0x0030)
+#define MEM_SDSMCKE            (0x0034)
+
+#ifndef ASSEMBLER
+/*typedef volatile struct
+{
+       uint32 sdmode0;
+       uint32 sdmode1;
+       uint32 sdmode2;
+       uint32 sdaddr0;
+       uint32 sdaddr1;
+       uint32 sdaddr2;
+       uint32 sdrefcfg;
+       uint32 sdautoref;
+       uint32 sdwrmd0;
+       uint32 sdwrmd1;
+       uint32 sdwrmd2;
+       uint32 sdsleep;
+       uint32 sdsmcke;
+
+} AU1X00_SDRAM;*/
+#endif
+
+/*
+ * MEM_SDMODE register content definitions
+ */
+#define MEM_SDMODE_F           (1<<22)
+#define MEM_SDMODE_SR          (1<<21)
+#define MEM_SDMODE_BS          (1<<20)
+#define MEM_SDMODE_RS          (3<<18)
+#define MEM_SDMODE_CS          (7<<15)
+#define MEM_SDMODE_TRAS                (15<<11)
+#define MEM_SDMODE_TMRD                (3<<9)
+#define MEM_SDMODE_TWR         (3<<7)
+#define MEM_SDMODE_TRP         (3<<5)
+#define MEM_SDMODE_TRCD                (3<<3)
+#define MEM_SDMODE_TCL         (7<<0)
+
+#define MEM_SDMODE_BS_2Bank    (0<<20)
+#define MEM_SDMODE_BS_4Bank    (1<<20)
+#define MEM_SDMODE_RS_11Row    (0<<18)
+#define MEM_SDMODE_RS_12Row    (1<<18)
+#define MEM_SDMODE_RS_13Row    (2<<18)
+#define MEM_SDMODE_RS_N(N)     ((N)<<18)
+#define MEM_SDMODE_CS_7Col     (0<<15)
+#define MEM_SDMODE_CS_8Col     (1<<15)
+#define MEM_SDMODE_CS_9Col     (2<<15)
+#define MEM_SDMODE_CS_10Col    (3<<15)
+#define MEM_SDMODE_CS_11Col    (4<<15)
+#define MEM_SDMODE_CS_N(N)             ((N)<<15)
+#define MEM_SDMODE_TRAS_N(N)   ((N)<<11)
+#define MEM_SDMODE_TMRD_N(N)   ((N)<<9)
+#define MEM_SDMODE_TWR_N(N)            ((N)<<7)
+#define MEM_SDMODE_TRP_N(N)            ((N)<<5)
+#define MEM_SDMODE_TRCD_N(N)   ((N)<<3)
+#define MEM_SDMODE_TCL_N(N)            ((N)<<0)
+
+/*
+ * MEM_SDADDR register contents definitions
+ */
+#define MEM_SDADDR_E                   (1<<20)
+#define MEM_SDADDR_CSBA                        (0x03FF<<10)
+#define MEM_SDADDR_CSMASK              (0x03FF<<0)
+#define MEM_SDADDR_CSBA_N(N)   ((N)&(0x03FF<<22)>>12)
+#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22)
+
+/*
+ * MEM_SDREFCFG register content definitions
+ */
+#define MEM_SDREFCFG_TRC               (15<<28)
+#define MEM_SDREFCFG_TRPM              (3<<26)
+#define MEM_SDREFCFG_E                 (1<<25)
+#define MEM_SDREFCFG_RE                        (0x1ffffff<<0)
+#define MEM_SDREFCFG_TRC_N(N)  ((N)<<MEM_SDREFCFG_TRC)
+#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM)
+#define MEM_SDREFCFG_REF_N(N)  (N)
+#endif
+
+/***********************************************************************/
+
+/*
+ * Au1550 SDRAM Register Offsets
+ */
+
+/***********************************************************************/
+
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+#define MEM_SDMODE0            (0x0800)
+#define MEM_SDMODE1            (0x0808)
+#define MEM_SDMODE2            (0x0810)
+#define MEM_SDADDR0            (0x0820)
+#define MEM_SDADDR1            (0x0828)
+#define MEM_SDADDR2            (0x0830)
+#define MEM_SDCONFIGA  (0x0840)
+#define MEM_SDCONFIGB  (0x0848)
+#define MEM_SDSTAT             (0x0850)
+#define MEM_SDERRADDR  (0x0858)
+#define MEM_SDSTRIDE0  (0x0860)
+#define MEM_SDSTRIDE1  (0x0868)
+#define MEM_SDSTRIDE2  (0x0870)
+#define MEM_SDWRMD0            (0x0880)
+#define MEM_SDWRMD1            (0x0888)
+#define MEM_SDWRMD2            (0x0890)
+#define MEM_SDPRECMD   (0x08C0)
+#define MEM_SDAUTOREF  (0x08C8)
+#define MEM_SDSREF             (0x08D0)
+#define MEM_SDSLEEP            MEM_SDSREF
+
+#ifndef ASSEMBLER
+/*typedef volatile struct
+{
+       uint32 sdmode0;
+       uint32 reserved0;
+       uint32 sdmode1;
+       uint32 reserved1;
+       uint32 sdmode2;
+       uint32 reserved2[3];
+       uint32 sdaddr0;
+       uint32 reserved3;
+       uint32 sdaddr1;
+       uint32 reserved4;
+       uint32 sdaddr2;
+       uint32 reserved5[3];
+       uint32 sdconfiga;
+       uint32 reserved6;
+       uint32 sdconfigb;
+       uint32 reserved7;
+       uint32 sdstat;
+       uint32 reserved8;
+       uint32 sderraddr;
+       uint32 reserved9;
+       uint32 sdstride0;
+       uint32 reserved10;
+       uint32 sdstride1;
+       uint32 reserved11;
+       uint32 sdstride2;
+       uint32 reserved12[3];
+       uint32 sdwrmd0;
+       uint32 reserved13;
+       uint32 sdwrmd1;
+       uint32 reserved14;
+       uint32 sdwrmd2;
+       uint32 reserved15[11];
+       uint32 sdprecmd;
+       uint32 reserved16;
+       uint32 sdautoref;
+       uint32 reserved17;
+       uint32 sdsref;
+
+} AU1550_SDRAM;*/
+#endif
+#endif
+
+/*
+ * Physical base addresses for integrated peripherals
+ */
+
+#ifdef CONFIG_SOC_AU1000
+#define        MEM_PHYS_ADDR           0x14000000
+#define        STATIC_MEM_PHYS_ADDR    0x14001000
+#define        DMA0_PHYS_ADDR          0x14002000
+#define        DMA1_PHYS_ADDR          0x14002100
+#define        DMA2_PHYS_ADDR          0x14002200
+#define        DMA3_PHYS_ADDR          0x14002300
+#define        DMA4_PHYS_ADDR          0x14002400
+#define        DMA5_PHYS_ADDR          0x14002500
+#define        DMA6_PHYS_ADDR          0x14002600
+#define        DMA7_PHYS_ADDR          0x14002700
+#define        IC0_PHYS_ADDR           0x10400000
+#define        IC1_PHYS_ADDR           0x11800000
+#define        AC97_PHYS_ADDR          0x10000000
+#define        USBH_PHYS_ADDR          0x10100000
+#define        USBD_PHYS_ADDR          0x10200000
+#define        IRDA_PHYS_ADDR          0x10300000
+#define        MAC0_PHYS_ADDR          0x10500000
+#define        MAC1_PHYS_ADDR          0x10510000
+#define        MACEN_PHYS_ADDR         0x10520000
+#define        MACDMA0_PHYS_ADDR       0x14004000
+#define        MACDMA1_PHYS_ADDR       0x14004200
+#define        I2S_PHYS_ADDR           0x11000000
+#define        UART0_PHYS_ADDR         0x11100000
+#define        UART1_PHYS_ADDR         0x11200000
+#define        UART2_PHYS_ADDR         0x11300000
+#define        UART3_PHYS_ADDR         0x11400000
+#define        SSI0_PHYS_ADDR          0x11600000
+#define        SSI1_PHYS_ADDR          0x11680000
+#define        SYS_PHYS_ADDR           0x11900000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#endif
+
+/********************************************************************/
 
-#define MEM_SDSLEEP                0xB4000030
-#define MEM_SDSMCKE                0xB4000034
+#ifdef CONFIG_SOC_AU1500
+#define        MEM_PHYS_ADDR           0x14000000
+#define        STATIC_MEM_PHYS_ADDR    0x14001000
+#define        DMA0_PHYS_ADDR          0x14002000
+#define        DMA1_PHYS_ADDR          0x14002100
+#define        DMA2_PHYS_ADDR          0x14002200
+#define        DMA3_PHYS_ADDR          0x14002300
+#define        DMA4_PHYS_ADDR          0x14002400
+#define        DMA5_PHYS_ADDR          0x14002500
+#define        DMA6_PHYS_ADDR          0x14002600
+#define        DMA7_PHYS_ADDR          0x14002700
+#define        IC0_PHYS_ADDR           0x10400000
+#define        IC1_PHYS_ADDR           0x11800000
+#define        AC97_PHYS_ADDR          0x10000000
+#define        USBH_PHYS_ADDR          0x10100000
+#define        USBD_PHYS_ADDR          0x10200000
+#define PCI_PHYS_ADDR          0x14005000
+#define        MAC0_PHYS_ADDR          0x11500000
+#define        MAC1_PHYS_ADDR          0x11510000
+#define        MACEN_PHYS_ADDR         0x11520000
+#define        MACDMA0_PHYS_ADDR       0x14004000
+#define        MACDMA1_PHYS_ADDR       0x14004200
+#define        I2S_PHYS_ADDR           0x11000000
+#define        UART0_PHYS_ADDR         0x11100000
+#define        UART3_PHYS_ADDR         0x11400000
+#define GPIO2_PHYS_ADDR                0x11700000
+#define        SYS_PHYS_ADDR           0x11900000
+#define PCI_MEM_PHYS_ADDR     0x400000000
+#define PCI_IO_PHYS_ADDR      0x500000000
+#define PCI_CONFIG0_PHYS_ADDR 0x600000000
+#define PCI_CONFIG1_PHYS_ADDR 0x680000000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
 #endif
 
+/********************************************************************/
+
+#ifdef CONFIG_SOC_AU1100
+#define        MEM_PHYS_ADDR           0x14000000
+#define        STATIC_MEM_PHYS_ADDR    0x14001000
+#define        DMA0_PHYS_ADDR          0x14002000
+#define        DMA1_PHYS_ADDR          0x14002100
+#define        DMA2_PHYS_ADDR          0x14002200
+#define        DMA3_PHYS_ADDR          0x14002300
+#define        DMA4_PHYS_ADDR          0x14002400
+#define        DMA5_PHYS_ADDR          0x14002500
+#define        DMA6_PHYS_ADDR          0x14002600
+#define        DMA7_PHYS_ADDR          0x14002700
+#define        IC0_PHYS_ADDR           0x10400000
+#define SD0_PHYS_ADDR          0x10600000
+#define SD1_PHYS_ADDR          0x10680000
+#define        IC1_PHYS_ADDR           0x11800000
+#define        AC97_PHYS_ADDR          0x10000000
+#define        USBH_PHYS_ADDR          0x10100000
+#define        USBD_PHYS_ADDR          0x10200000
+#define        IRDA_PHYS_ADDR          0x10300000
+#define        MAC0_PHYS_ADDR          0x10500000
+#define        MACEN_PHYS_ADDR         0x10520000
+#define        MACDMA0_PHYS_ADDR       0x14004000
+#define        MACDMA1_PHYS_ADDR       0x14004200
+#define        I2S_PHYS_ADDR           0x11000000
+#define        UART0_PHYS_ADDR         0x11100000
+#define        UART1_PHYS_ADDR         0x11200000
+#define        UART3_PHYS_ADDR         0x11400000
+#define        SSI0_PHYS_ADDR          0x11600000
+#define        SSI1_PHYS_ADDR          0x11680000
+#define GPIO2_PHYS_ADDR                0x11700000
+#define        SYS_PHYS_ADDR           0x11900000
+#define LCD_PHYS_ADDR          0x15000000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#endif
+
+/***********************************************************************/
+
+#ifdef CONFIG_SOC_AU1550
+#define        MEM_PHYS_ADDR           0x14000000
+#define        STATIC_MEM_PHYS_ADDR    0x14001000
+#define        IC0_PHYS_ADDR           0x10400000
+#define        IC1_PHYS_ADDR           0x11800000
+#define        USBH_PHYS_ADDR          0x14020000
+#define        USBD_PHYS_ADDR          0x10200000
+#define PCI_PHYS_ADDR          0x14005000
+#define        MAC0_PHYS_ADDR          0x10500000
+#define        MAC1_PHYS_ADDR          0x10510000
+#define        MACEN_PHYS_ADDR         0x10520000
+#define        MACDMA0_PHYS_ADDR       0x14004000
+#define        MACDMA1_PHYS_ADDR       0x14004200
+#define        UART0_PHYS_ADDR         0x11100000
+#define        UART1_PHYS_ADDR         0x11200000
+#define        UART3_PHYS_ADDR         0x11400000
+#define GPIO2_PHYS_ADDR                0x11700000
+#define        SYS_PHYS_ADDR           0x11900000
+#define        DDMA_PHYS_ADDR          0x14002000
+#define PE_PHYS_ADDR           0x14008000
+#define PSC0_PHYS_ADDR         0x11A00000
+#define PSC1_PHYS_ADDR         0x11B00000
+#define PSC2_PHYS_ADDR         0x10A00000
+#define PSC3_PHYS_ADDR         0x10B00000
+#define PCI_MEM_PHYS_ADDR     0x400000000
+#define PCI_IO_PHYS_ADDR      0x500000000
+#define PCI_CONFIG0_PHYS_ADDR 0x600000000
+#define PCI_CONFIG1_PHYS_ADDR 0x680000000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#endif
+
+/***********************************************************************/
+
+#ifdef CONFIG_SOC_AU1200
+#define        MEM_PHYS_ADDR           0x14000000
+#define        STATIC_MEM_PHYS_ADDR    0x14001000
+#define AES_PHYS_ADDR          0x10300000
+#define CIM_PHYS_ADDR          0x14004000
+#define        IC0_PHYS_ADDR           0x10400000
+#define        IC1_PHYS_ADDR           0x11800000
+#define USBM_PHYS_ADDR         0x14020000
+#define        USBH_PHYS_ADDR          0x14020100
+#define        UART0_PHYS_ADDR         0x11100000
+#define        UART1_PHYS_ADDR         0x11200000
+#define GPIO2_PHYS_ADDR                0x11700000
+#define        SYS_PHYS_ADDR           0x11900000
+#define        DDMA_PHYS_ADDR          0x14002000
+#define PSC0_PHYS_ADDR         0x11A00000
+#define PSC1_PHYS_ADDR         0x11B00000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#define SD0_PHYS_ADDR          0x10600000
+#define SD1_PHYS_ADDR          0x10680000
+#define LCD_PHYS_ADDR          0x15000000
+#define SWCNT_PHYS_ADDR                0x1110010C
+#define MAEFE_PHYS_ADDR                0x14012000
+#define MAEBE_PHYS_ADDR                0x14010000
+#endif
+
+
 /* Static Bus Controller */
 #define MEM_STCFG0                 0xB4001000
 #define MEM_STTIME0                0xB4001004
@@ -367,7 +695,7 @@
 #define AU1000_MAC0_ENABLE       0xB0520000
 #define AU1000_MAC1_ENABLE       0xB0520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1000
+#endif /* CONFIG_SOC_AU1000 */
 
 /* Au1500 */
 #ifdef CONFIG_SOC_AU1500
@@ -438,7 +766,7 @@
 #define AU1500_MAC0_ENABLE       0xB1520000
 #define AU1500_MAC1_ENABLE       0xB1520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1500
+#endif /* CONFIG_SOC_AU1500 */
 
 /* Au1100 */
 #ifdef CONFIG_SOC_AU1100
@@ -483,6 +811,22 @@
 #define AU1000_GPIO_13            45
 #define AU1000_GPIO_14            46
 #define AU1000_GPIO_15            47
+#define AU1000_GPIO_16            48
+#define AU1000_GPIO_17            49
+#define AU1000_GPIO_18            50
+#define AU1000_GPIO_19            51
+#define AU1000_GPIO_20            52
+#define AU1000_GPIO_21            53
+#define AU1000_GPIO_22            54
+#define AU1000_GPIO_23            55
+#define AU1000_GPIO_24            56
+#define AU1000_GPIO_25            57
+#define AU1000_GPIO_26            58
+#define AU1000_GPIO_27            59
+#define AU1000_GPIO_28            60
+#define AU1000_GPIO_29            61
+#define AU1000_GPIO_30            62
+#define AU1000_GPIO_31            63
 
 #define UART0_ADDR                0xB1100000
 #define UART1_ADDR                0xB1200000
@@ -494,7 +838,7 @@
 #define AU1100_ETH0_BASE         0xB0500000
 #define AU1100_MAC0_ENABLE       0xB0520000
 #define NUM_ETH_INTERFACES 1
-#endif // CONFIG_SOC_AU1100
+#endif /* CONFIG_SOC_AU1100 */
 
 #ifdef CONFIG_SOC_AU1550
 #define AU1550_UART0_INT          0
@@ -511,14 +855,14 @@
 #define AU1550_PSC1_INT           11
 #define AU1550_PSC2_INT           12
 #define AU1550_PSC3_INT           13
-#define AU1550_TOY_INT                   14
-#define AU1550_TOY_MATCH0_INT     15
-#define AU1550_TOY_MATCH1_INT     16
-#define AU1550_TOY_MATCH2_INT     17
-#define AU1550_RTC_INT            18
-#define AU1550_RTC_MATCH0_INT     19
-#define AU1550_RTC_MATCH1_INT     20
-#define AU1550_RTC_MATCH2_INT     21
+#define AU1000_TOY_INT                   14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
 #define AU1550_NAND_INT           23
 #define AU1550_USB_DEV_REQ_INT    24
 #define AU1550_USB_DEV_SUS_INT    25
@@ -573,7 +917,7 @@
 #define AU1550_MAC0_ENABLE       0xB0520000
 #define AU1550_MAC1_ENABLE       0xB0520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1550
+#endif /* CONFIG_SOC_AU1550 */
 
 #ifdef CONFIG_SOC_AU1200
 #define AU1200_UART0_INT          0
@@ -590,14 +934,14 @@
 #define AU1200_PSC1_INT           11
 #define AU1200_AES_INT            12
 #define AU1200_CAMERA_INT         13
-#define AU1200_TOY_INT                   14
-#define AU1200_TOY_MATCH0_INT     15
-#define AU1200_TOY_MATCH1_INT     16
-#define AU1200_TOY_MATCH2_INT     17
-#define AU1200_RTC_INT            18
-#define AU1200_RTC_MATCH0_INT     19
-#define AU1200_RTC_MATCH1_INT     20
-#define AU1200_RTC_MATCH2_INT     21
+#define AU1000_TOY_INT                   14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
 #define AU1200_NAND_INT           23
 #define AU1200_GPIO_204           24
 #define AU1200_GPIO_205           25
@@ -605,6 +949,7 @@
 #define AU1200_GPIO_207           27
 #define AU1200_GPIO_208_215       28 // Logical OR of 208:215
 #define AU1200_USB_INT            29
+#define AU1000_USB_HOST_INT              AU1200_USB_INT
 #define AU1200_LCD_INT            30
 #define AU1200_MAE_BOTH_INT       31
 #define AU1000_GPIO_0             32
@@ -643,21 +988,36 @@
 #define UART0_ADDR                0xB1100000
 #define UART1_ADDR                0xB1200000
 
-#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap
-#define USB_HOST_CONFIG           0xB4027ffc
+#define USB_UOC_BASE              0x14020020
+#define USB_UOC_LEN               0x20
+#define USB_OHCI_BASE             0x14020100
+#define USB_OHCI_LEN              0x100
+#define USB_EHCI_BASE             0x14020200
+#define USB_EHCI_LEN              0x100
+#define USB_UDC_BASE              0x14022000
+#define USB_UDC_LEN               0x2000
+#define USB_MSR_BASE                     0xB4020000
+#define USB_MSR_MCFG              4
+#define USBMSRMCFG_OMEMEN         0
+#define USBMSRMCFG_OBMEN          1
+#define USBMSRMCFG_EMEMEN         2
+#define USBMSRMCFG_EBMEN          3
+#define USBMSRMCFG_DMEMEN         4
+#define USBMSRMCFG_DBMEN          5
+#define USBMSRMCFG_GMEMEN         6
+#define USBMSRMCFG_OHCCLKEN       16
+#define USBMSRMCFG_EHCCLKEN       17
+#define USBMSRMCFG_UDCCLKEN       18
+#define USBMSRMCFG_PHYPLLEN       19
+#define USBMSRMCFG_RDCOMB         30
+#define USBMSRMCFG_PFEN           31
 
-// these are here for prototyping on au1550 (do not exist on au1200)
-#define AU1200_ETH0_BASE      0xB0500000
-#define AU1200_ETH1_BASE      0xB0510000
-#define AU1200_MAC0_ENABLE       0xB0520000
-#define AU1200_MAC1_ENABLE       0xB0520004
-#define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1200
+#endif /* CONFIG_SOC_AU1200 */
 
 #define AU1000_LAST_INTC0_INT     31
+#define AU1000_LAST_INTC1_INT     63
 #define AU1000_MAX_INTR           63
 
-
 /* Programmable Counters 0 and 1 */
 #define SYS_BASE                   0xB1900000
 #define SYS_COUNTER_CNTRL          (SYS_BASE + 0x14)
@@ -728,6 +1088,8 @@
   #define I2S_CONTROL_D         (1<<1)
   #define I2S_CONTROL_CE        (1<<0)
 
+#ifndef CONFIG_SOC_AU1200
+
 /* USB Host Controller */
 #define USB_OHCI_LEN              0x00100000
 
@@ -773,6 +1135,8 @@
   #define USBDEV_ENABLE (1<<1)
   #define USBDEV_CE     (1<<0)
 
+#endif /* !CONFIG_SOC_AU1200 */
+
 /* Ethernet Controllers  */
 
 /* 4 byte offsets from AU1000_ETH_BASE */
@@ -1171,6 +1535,37 @@
   #define SYS_PF_PSC1_S1               (1 << 1)
   #define SYS_PF_MUST_BE_SET           ((1 << 5) | (1 << 2))
 
+/* Au1200 Only */
+#ifdef CONFIG_SOC_AU1200
+#define SYS_PINFUNC_DMA                (1<<31)
+#define SYS_PINFUNC_S0A                (1<<30)
+#define SYS_PINFUNC_S1A                (1<<29)
+#define SYS_PINFUNC_LP0                (1<<28)
+#define SYS_PINFUNC_LP1                (1<<27)
+#define SYS_PINFUNC_LD16       (1<<26)
+#define SYS_PINFUNC_LD8                (1<<25)
+#define SYS_PINFUNC_LD1                (1<<24)
+#define SYS_PINFUNC_LD0                (1<<23)
+#define SYS_PINFUNC_P1A                (3<<21)
+#define SYS_PINFUNC_P1B                (1<<20)
+#define SYS_PINFUNC_FS3                (1<<19)
+#define SYS_PINFUNC_P0A                (3<<17)
+#define SYS_PINFUNC_CS         (1<<16)
+#define SYS_PINFUNC_CIM                (1<<15)
+#define SYS_PINFUNC_P1C                (1<<14)
+#define SYS_PINFUNC_U1T                (1<<12)
+#define SYS_PINFUNC_U1R                (1<<11)
+#define SYS_PINFUNC_EX1                (1<<10)
+#define SYS_PINFUNC_EX0                (1<<9)
+#define SYS_PINFUNC_U0R                (1<<8)
+#define SYS_PINFUNC_MC         (1<<7)
+#define SYS_PINFUNC_S0B                (1<<6)
+#define SYS_PINFUNC_S0C                (1<<5)
+#define SYS_PINFUNC_P0B                (1<<4)
+#define SYS_PINFUNC_U0T                (1<<3)
+#define SYS_PINFUNC_S1B                (1<<2)
+#endif
+
 #define SYS_TRIOUTRD              0xB1900100
 #define SYS_TRIOUTCLR             0xB1900100
 #define SYS_OUTPUTRD              0xB1900108
@@ -1298,7 +1693,6 @@
 #define SD1_XMIT_FIFO  0xB0680000
 #define SD1_RECV_FIFO  0xB0680004
 
-
 #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
 /* Au1500 PCI Controller */
 #define Au1500_CFG_BASE           0xB4005000 // virtual, kseg0 addr
@@ -1388,9 +1782,60 @@
 
 #endif
 
+#ifndef _LANGUAGE_ASSEMBLY
+typedef volatile struct
+{
+       /* 0x0000 */ u32 toytrim;
+       /* 0x0004 */ u32 toywrite;
+       /* 0x0008 */ u32 toymatch0;
+       /* 0x000C */ u32 toymatch1;
+       /* 0x0010 */ u32 toymatch2;
+       /* 0x0014 */ u32 cntrctrl;
+       /* 0x0018 */ u32 scratch0;
+       /* 0x001C */ u32 scratch1;
+       /* 0x0020 */ u32 freqctrl0;
+       /* 0x0024 */ u32 freqctrl1;
+       /* 0x0028 */ u32 clksrc;
+       /* 0x002C */ u32 pinfunc;
+       /* 0x0030 */ u32 reserved0;
+       /* 0x0034 */ u32 wakemsk;
+       /* 0x0038 */ u32 endian;
+       /* 0x003C */ u32 powerctrl;
+       /* 0x0040 */ u32 toyread;
+       /* 0x0044 */ u32 rtctrim;
+       /* 0x0048 */ u32 rtcwrite;
+       /* 0x004C */ u32 rtcmatch0;
+       /* 0x0050 */ u32 rtcmatch1;
+       /* 0x0054 */ u32 rtcmatch2;
+       /* 0x0058 */ u32 rtcread;
+       /* 0x005C */ u32 wakesrc;
+       /* 0x0060 */ u32 cpupll;
+       /* 0x0064 */ u32 auxpll;
+       /* 0x0068 */ u32 reserved1;
+       /* 0x006C */ u32 reserved2;
+       /* 0x0070 */ u32 reserved3;
+       /* 0x0074 */ u32 reserved4;
+       /* 0x0078 */ u32 slppwr;
+       /* 0x007C */ u32 sleep;
+       /* 0x0080 */ u32 reserved5[32];
+       /* 0x0100 */ u32 trioutrd;
+#define trioutclr trioutrd
+       /* 0x0104 */ u32 reserved6;
+       /* 0x0108 */ u32 outputrd;
+#define outputset outputrd
+       /* 0x010C */ u32 outputclr;
+       /* 0x0110 */ u32 pinstaterd;
+#define pininputen pinstaterd
+
+} AU1X00_SYS;
+
+static AU1X00_SYS* const sys  = (AU1X00_SYS *)SYS_BASE;
+
+#endif
 /* Processor information base on prid.
  * Copied from PowerPC.
  */
+#ifndef _LANGUAGE_ASSEMBLY
 struct cpu_spec {
        /* CPU is matched via (PRID & prid_mask) == prid_value */
        unsigned int    prid_mask;
@@ -1404,3 +1849,6 @@
 extern struct cpu_spec         cpu_specs[];
 extern struct cpu_spec         *cur_cpu_spec[];
 #endif
+
+#endif
+
diff -urN linux/include/asm-mips/au1000_gpio.h 
linux/include/asm-mips/au1000_gpio.h
--- linux/include/asm-mips/Attic/au1000_gpio.h  2002/08/05 23:53:37     1.1.2.1
+++ linux/include/asm-mips/Attic/au1000_gpio.h  2005/01/30 08:01:28     1.1.2.2
@@ -30,6 +30,13 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+/*
+ *  Revision history
+ *    01/31/02  0.01   Initial release. Steve Longerbeam, MontaVista
+ *    10/12/03  0.1    Added Au1100/Au1500, GPIO2, and bit operations. K.C. 
Nishio, AMD
+ *    08/05/04  0.11   Added Au1550 and Au1200. K.C. Nishio
+ */
+
 #ifndef __AU1000_GPIO_H
 #define __AU1000_GPIO_H
 
@@ -44,13 +51,94 @@
 #define AU1000GPIO_TRISTATE    _IOW (AU1000GPIO_IOC_MAGIC, 4, int)
 #define AU1000GPIO_AVAIL_MASK  _IOR (AU1000GPIO_IOC_MAGIC, 5, int)
 
+// bit operations
+#define AU1000GPIO_BIT_READ    _IOW (AU1000GPIO_IOC_MAGIC, 6, int)
+#define AU1000GPIO_BIT_SET     _IOW (AU1000GPIO_IOC_MAGIC, 7, int)
+#define AU1000GPIO_BIT_CLEAR   _IOW (AU1000GPIO_IOC_MAGIC, 8, int)
+#define AU1000GPIO_BIT_TRISTATE        _IOW (AU1000GPIO_IOC_MAGIC, 9, int)
+#define AU1000GPIO_BIT_INIT    _IOW (AU1000GPIO_IOC_MAGIC, 10, int)
+#define AU1000GPIO_BIT_TERM    _IOW (AU1000GPIO_IOC_MAGIC, 11, int)
+
+/* set this major numer same as the CRIS GPIO driver */
+#define AU1X00_GPIO_MAJOR      (120)
+
+#define ENABLED_ZERO           (0)
+#define ENABLED_ONE            (1)
+#define ENABLED_10             (0x2)
+#define ENABLED_11             (0x3)
+#define ENABLED_111            (0x7)
+#define NOT_AVAIL              (-1)
+#define AU1X00_MAX_PRIMARY_GPIO        (32) 
+
+#define AU1000_GPIO_MINOR_MAX  AU1X00_MAX_PRIMARY_GPIO
+/* Au1100, 1500, 1550 and 1200 have the secondary GPIO block */
+#define AU1XX0_GPIO_MINOR_MAX  (48)
+
+#define AU1X00_GPIO_NAME       "gpio"
+
+/* GPIO pins which are not multiplexed */
+#if defined(CONFIG_SOC_AU1000)
+  #define NATIVE_GPIOPIN       ((1 << 15) | (1 << 8) | (1 << 7) | (1 << 1) | 
(1 << 0))
+  #define NATIVE_GPIO2PIN      (0)
+#elif defined(CONFIG_SOC_AU1100)
+  #define NATIVE_GPIOPIN       ((1 << 23) | (1 << 22) | (1 << 21) | (1 << 20) 
| (1 << 19) | (1 << 18) | \
+                                (1 << 17) | (1 << 16) | (1 << 7) | (1 << 1) | 
(1 << 0))
+  #define NATIVE_GPIO2PIN      (0)
+#elif defined(CONFIG_SOC_AU1500)
+  #define NATIVE_GPIOPIN       ((1 << 15) | (1 << 8) | (1 << 7) | (1 << 1) | 
(1 << 0))
+  /* exclude the PCI reset output signal: GPIO[200], DMA_REQ2 and DMA_REQ3 */
+  #define NATIVE_GPIO2PIN      (0xfffe & ~((1 << 9) | (1 << 8))) 
+#elif defined(CONFIG_SOC_AU1550)
+  #define NATIVE_GPIOPIN       ((1 << 15) | (1 << 8) | (1 << 7) | (1 << 6) | 
(1 << 1) | (1 << 0))
+  /* please refere Au1550 Data Book, chapter 15 */
+  #define NATIVE_GPIO2PIN      (1 << 5) 
+#elif defined(CONFIG_SOC_AU1200)
+  #define NATIVE_GPIOPIN       ((1 << 7) | (1 << 5))
+  #define NATIVE_GPIO2PIN      (0) 
+#endif
+
+/* minor as u32 */
+#define MINOR_TO_GPIOPIN(minor)                ((minor < 
AU1X00_MAX_PRIMARY_GPIO) ? minor : (minor - AU1X00_MAX_PRIMARY_GPIO))
+#define IS_PRIMARY_GPIOPIN(minor)      ((minor < AU1X00_MAX_PRIMARY_GPIO) ? 1 
: 0)
+
+/*
+ * pin to minor mapping.
+ * GPIO0-GPIO31, minor=0-31.
+ * GPIO200-GPIO215, minor=32-47.
+ */
+typedef struct _au1x00_gpio_bit_ctl {
+       int direction;  // The direction of this GPIO pin. 0: IN, 1: OUT.
+       int data;       // Pin output when itized (0/1), or at the term. 0/1/-1 
(tristate).
+} au1x00_gpio_bit_ctl;
+
+typedef struct _au1x00_gpio_driver {
+       const char      *driver_name;
+       const char      *name;
+       int             name_base;      /* offset of printed name */
+       short           major;          /* major device number */
+       short           minor_start;    /* start of minor device number*/
+       short           num;            /* number of devices */
+} au1x00_gpio_driver;
+
 #ifdef __KERNEL__
-extern u32 get_au1000_avail_gpio_mask(void);
-extern int au1000gpio_tristate(u32 data);
-extern int au1000gpio_in(u32 *data);
-extern int au1000gpio_set(u32 data);
-extern int au1000gpio_clear(u32 data);
-extern int au1000gpio_out(u32 data);
+extern u32 get_au1000_avail_gpio_mask(u32 *avail_gpio2);
+extern int au1000gpio_tristate(u32 minor, u32 data);
+extern int au1000gpio_in(u32 minor, u32 *data);
+extern int au1000gpio_set(u32 minor, u32 data);
+extern int au1000gpio_clear(u32 minor, u32 data);
+extern int au1000gpio_out(u32 minor, u32 data);
+extern int au1000gpio_bit_read(u32 minor, u32 *read_data);
+extern int au1000gpio_bit_set(u32 minor);
+extern int au1000gpio_bit_clear(u32 minor);
+extern int au1000gpio_bit_tristate(u32 minor);
+extern int check_minor_to_gpio(u32 minor);
+extern int au1000gpio_bit_init(u32 minor, au1x00_gpio_bit_ctl *bit_opt);
+extern int au1000gpio_bit_term(u32 minor, au1x00_gpio_bit_ctl *bit_opt);
+
+extern void gpio_register_devfs (au1x00_gpio_driver *driver, unsigned int 
flags, unsigned minor);
+extern void gpio_unregister_devfs (au1x00_gpio_driver *driver, unsigned minor);
+extern int gpio_register_driver(au1x00_gpio_driver *driver);
+extern int gpio_unregister_driver(au1x00_gpio_driver *driver);
 #endif
 
 #endif
diff -urN linux/include/asm-mips/au1000_pcmcia.h 
linux/include/asm-mips/au1000_pcmcia.h
--- linux/include/asm-mips/Attic/au1000_pcmcia.h        2004/04/14 18:37:16     
1.2.2.16
+++ linux/include/asm-mips/Attic/au1000_pcmcia.h        2005/01/30 08:01:28     
1.2.2.17
@@ -38,16 +38,41 @@
 #define AU1X_SOCK0_PHYS_MEM  0xF80000000
 
 /* pcmcia socket 1 needs external glue logic so the memory map
- * differs from board to board.
+ * differs from board to board. the general rule is that
+ * static bus address bit 26 should be used to decode socket 0
+ * from socket 1. alas, some boards dont follow this...
+ * These really belong in a board-specific header file...
  */
-#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || 
defined(CONFIG_MIPS_PB1500)
-#define AU1X_SOCK1_IO        0xF08000000
-#define AU1X_SOCK1_PHYS_ATTR 0xF48000000
-#define AU1X_SOCK1_PHYS_MEM  0xF88000000
-#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || 
defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_PB1550) || 
defined(CONFIG_MIPS_DB1550)
-#define AU1X_SOCK1_IO        0xF04000000
-#define AU1X_SOCK1_PHYS_ATTR 0xF44000000
-#define AU1X_SOCK1_PHYS_MEM  0xF84000000
+#ifdef CONFIG_MIPS_PB1000
+#define SOCK1_DECODE (1<<27)
+#endif
+#ifdef CONFIG_MIPS_DB1000
+#define SOCK1_DECODE (1<<26)
+#endif
+#ifdef CONFIG_MIPS_DB1500
+#define SOCK1_DECODE (1<<26)
+#endif
+#ifdef CONFIG_MIPS_DB1100
+#define SOCK1_DECODE (1<<26)
+#endif
+#ifdef CONFIG_MIPS_DB1550
+#define SOCK1_DECODE (1<<26)
+#endif
+#ifdef CONFIG_MIPS_DB1200
+#define SOCK1_DECODE (1<<26)
+#endif
+#ifdef CONFIG_MIPS_PB1550
+#define SOCK1_DECODE (1<<26)
+#endif
+#ifdef CONFIG_MIPS_PB1200
+#define SOCK1_DECODE (1<<26)
+#endif
+
+/* The board has a second PCMCIA socket */
+#ifdef SOCK1_DECODE
+#define AU1X_SOCK1_IO        (0xF00000000|SOCK1_DECODE)
+#define AU1X_SOCK1_PHYS_ATTR (0xF40000000|SOCK1_DECODE)
+#define AU1X_SOCK1_PHYS_MEM  (0xF80000000|SOCK1_DECODE)
 #endif
 
 struct pcmcia_state {
diff -urN linux/include/asm-mips/au1100_mmc.h 
linux/include/asm-mips/au1100_mmc.h
--- linux/include/asm-mips/Attic/au1100_mmc.h   2004/03/31 08:24:24     1.1.2.1
+++ linux/include/asm-mips/Attic/au1100_mmc.h   2005/01/30 08:01:28     1.1.2.2
@@ -39,16 +39,22 @@
 #define __ASM_AU1100_MMC_H
 
 
-#define NUM_AU1100_MMC_CONTROLLERS     2
-
-
-#define AU1100_SD_IRQ  2
-
+#if defined(CONFIG_SOC_AU1100)
+#define NUM_MMC_CONTROLLERS    2
+#define AU1X_MMC_INT AU1100_SD_INT
+#endif
+
+#if defined(CONFIG_SOC_AU1200)
+#define NUM_MMC_CONTROLLERS    2
+#define AU1X_MMC_INT AU1200_SD_INT
+#endif
 
 #define SD0_BASE       0xB0600000
 #define SD1_BASE       0xB0680000
 
 
+
+
 /*
  *  Register offsets.
  */
@@ -201,5 +207,12 @@
 #define SD_CMD_RT_1B   (0x00810000)
 
 
+/* support routines required on a platform-specific basis */
+extern void mmc_card_inserted(int _n_, int *_res_);
+extern void mmc_card_writable(int _n_, int *_res_);
+extern void mmc_power_on(int _n_);
+extern void mmc_power_off(int _n_);
+
+
 #endif /* __ASM_AU1100_MMC_H */
 
diff -urN linux/include/asm-mips/au1xxx_dbdma.h 
linux/include/asm-mips/au1xxx_dbdma.h
--- linux/include/asm-mips/Attic/au1xxx_dbdma.h 2004/07/14 06:30:30     1.1.2.5
+++ linux/include/asm-mips/Attic/au1xxx_dbdma.h 2005/01/30 08:01:28     1.1.2.6
@@ -43,7 +43,7 @@
 #define DDMA_GLOBAL_BASE       0xb4003000
 #define DDMA_CHANNEL_BASE      0xb4002000
 
-typedef struct dbdma_global {
+typedef volatile struct dbdma_global {
        u32     ddma_config;
        u32     ddma_intstat;
        u32     ddma_throttle;
@@ -60,7 +60,7 @@
 
 /* The structure of a DMA Channel.
 */
-typedef struct au1xxx_dma_channel {
+typedef volatile struct au1xxx_dma_channel {
        u32     ddma_cfg;       /* See below */
        u32     ddma_desptr;    /* 32-byte aligned pointer to descriptor */
        u32     ddma_statptr;   /* word aligned pointer to status word */
@@ -96,7 +96,7 @@
 /* "Standard" DDMA Descriptor.
  * Must be 32-byte aligned.
  */
-typedef struct au1xxx_ddma_desc {
+typedef volatile struct au1xxx_ddma_desc {
        u32     dscr_cmd0;              /* See below */
        u32     dscr_cmd1;              /* See below */
        u32     dscr_source0;           /* source phys address */
@@ -105,6 +105,12 @@
        u32     dscr_dest1;             /* See below */
        u32     dscr_stat;              /* completion status */
        u32     dscr_nxtptr;            /* Next descriptor pointer (mostly) */
+       /* First 32bytes are HW specific!!!
+          Lets have some SW data following.. make sure its 32bytes
+        */
+       u32     sw_status;
+       u32     sw_context;
+       u32     sw_reserved[6];
 } au1x_ddma_desc_t;
 
 #define DSCR_CMD0_V            (1 << 31)       /* Descriptor valid */
@@ -123,6 +129,8 @@
 #define DSCR_CMD0_CV           (0x1 << 2)      /* Clear Valid when done */
 #define DSCR_CMD0_ST_MASK      (0x3 << 0)      /* Status instruction */
 
+#define SW_STATUS_INUSE                (1<<0)
+
 /* Command 0 device IDs.
 */
 #ifdef CONFIG_SOC_AU1550
@@ -169,8 +177,8 @@
 #define DSCR_CMD0_SDMS_RX0     9
 #define DSCR_CMD0_SDMS_TX1     10
 #define DSCR_CMD0_SDMS_RX1     11
-#define DSCR_CMD0_AES_TX       12
-#define DSCR_CMD0_AES_RX       13
+#define DSCR_CMD0_AES_TX       13
+#define DSCR_CMD0_AES_RX       12
 #define DSCR_CMD0_PSC0_TX      14
 #define DSCR_CMD0_PSC0_RX      15
 #define DSCR_CMD0_PSC1_TX      16
@@ -189,6 +197,10 @@
 #define DSCR_CMD0_THROTTLE     30
 #define DSCR_CMD0_ALWAYS       31
 #define DSCR_NDEV_IDS          32
+/* THis macro is used to find/create custom device types */
+#define DSCR_DEV2CUSTOM_ID(x,d)        
(((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
+#define DSCR_CUSTOM2DEV_ID(x)  ((x)&0xFF)
+
 
 #define DSCR_CMD0_SID(x)       (((x) & 0x1f) << 25)
 #define DSCR_CMD0_DID(x)       (((x) & 0x1f) << 20)
@@ -277,6 +289,43 @@
 */
 #define NUM_DBDMA_CHANS        16
 
+/*
+ * Ddma API definitions
+ * FIXME: may not fit to this header file
+ */
+typedef struct dbdma_device_table {
+       u32             dev_id;
+       u32             dev_flags;
+       u32             dev_tsize;
+       u32             dev_devwidth;
+       u32             dev_physaddr;           /* If FIFO */
+       u32             dev_intlevel;
+       u32             dev_intpolarity;
+} dbdev_tab_t;
+
+
+typedef struct dbdma_chan_config {
+       spinlock_t      lock;
+
+       u32                     chan_flags;
+       u32                     chan_index;
+       dbdev_tab_t             *chan_src;
+       dbdev_tab_t             *chan_dest;
+       au1x_dma_chan_t         *chan_ptr;
+       au1x_ddma_desc_t        *chan_desc_base;
+       au1x_ddma_desc_t        *get_ptr, *put_ptr, *cur_ptr;
+       void                    *chan_callparam;
+       void (*chan_callback)(int, void *, struct pt_regs *);
+} chan_tab_t;
+
+#define DEV_FLAGS_INUSE                (1 << 0)
+#define DEV_FLAGS_ANYUSE       (1 << 1)
+#define DEV_FLAGS_OUT          (1 << 2)
+#define DEV_FLAGS_IN           (1 << 3)
+#define DEV_FLAGS_BURSTABLE (1 << 4)
+#define DEV_FLAGS_SYNC         (1 << 5)
+/* end Ddma API definitions */
+
 /* External functions for drivers to use.
 */
 /* Use this to allocate a dbdma channel.  The device ids are one of the
@@ -299,8 +348,8 @@
 
 /* Put buffers on source/destination descriptors.
 */
-u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes);
-u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes);
+u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
+u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
 
 /* Get a buffer from the destination descriptor.
 */
@@ -314,5 +363,25 @@
 void au1xxx_dbdma_chan_free(u32 chanid);
 void au1xxx_dbdma_dump(u32 chanid);
 
+u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
+
+u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
+
+/*
+       Some compatibilty macros --
+               Needed to make changes to API without breaking existing drivers
+*/
+#define        
au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, 
nbytes, DDMA_FLAGS_IE)
+#define        au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) 
_au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
+
+#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) 
_au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
+#define        au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) 
_au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
+
+/*
+ *     Flags for the put_source/put_dest functions.
+ */
+#define DDMA_FLAGS_IE  (1<<0)
+#define DDMA_FLAGS_NOIE (1<<1)
+
 #endif /* _LANGUAGE_ASSEMBLY */
 #endif /* _AU1000_DBDMA_H_ */
diff -urN linux/include/asm-mips/au1xxx_psc.h 
linux/include/asm-mips/au1xxx_psc.h
--- linux/include/asm-mips/Attic/au1xxx_psc.h   2004/09/18 22:07:37     1.1.2.6
+++ linux/include/asm-mips/Attic/au1xxx_psc.h   2005/01/30 08:01:28     1.1.2.7
@@ -41,6 +41,11 @@
 #define PSC3_BASE_ADDR         0xb0d00000
 #endif
 
+#ifdef CONFIG_SOC_AU1200
+#define PSC0_BASE_ADDR         0xb1a00000
+#define PSC1_BASE_ADDR         0xb1b00000
+#endif
+
 /* The PSC select and control registers are common to
  * all protocols.
  */
@@ -226,6 +231,8 @@
 #define PSC_I2SCFG_DD_DISABLE  (1 << 27)
 #define PSC_I2SCFG_DE_ENABLE   (1 << 26)
 #define PSC_I2SCFG_SET_WS(x)   (((((x) / 2) - 1) & 0x7f) << 16)
+#define PSC_I2SCFG_WS(n)               ((n&0xFF)<<16)
+#define PSC_I2SCFG_WS_MASK     (PSC_I2SCFG_WS(0x3F))
 #define PSC_I2SCFG_WI          (1 << 15)
 
 #define PSC_I2SCFG_DIV_MASK    (3 << 13)
diff -urN linux/include/asm-mips/bootinfo.h linux/include/asm-mips/bootinfo.h
--- linux/include/asm-mips/bootinfo.h   2004/01/11 00:11:35     1.43.2.32
+++ linux/include/asm-mips/bootinfo.h   2005/01/30 08:01:28     1.43.2.33
@@ -180,6 +180,9 @@
 #define MACH_MTX1              7       /* 4G MTX-1 Au1500-based board */
 #define MACH_CSB250            8       /* Cogent Au1500 */
 #define MACH_PB1550            9       /* Au1550-based eval board */
+#define MACH_PB1200            10      /* Au1200-based eval board */
+#define MACH_DB1550            11      /* Au1550-based eval board */
+#define MACH_DB1200            12      /* Au1200-based eval board */
 
 /*
  * Valid machtype for group NEC_VR41XX
diff -urN linux/include/asm-mips/pb1550.h linux/include/asm-mips/pb1550.h
--- linux/include/asm-mips/Attic/pb1550.h       2004/09/18 22:07:37     1.1.2.5
+++ linux/include/asm-mips/Attic/pb1550.h       2005/01/30 08:01:28     1.1.2.6
@@ -30,13 +30,11 @@
 
 #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
 #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
-
 #define SPI_PSC_BASE        PSC0_BASE_ADDR
 #define AC97_PSC_BASE       PSC1_BASE_ADDR
 #define SMBUS_PSC_BASE      PSC2_BASE_ADDR
 #define I2S_PSC_BASE        PSC3_BASE_ADDR
+#define NAND_CS 1
 
 #define BCSR_PHYS_ADDR 0xAF000000
 
@@ -160,9 +158,23 @@
 #define NAND_T_SU_SHIFT                8
 #define NAND_T_WH_SHIFT                12
 
-#define NAND_TIMING    ((NAND_T_H   & 0xF)     << NAND_T_H_SHIFT)   | \
-                       ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
-                       ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
-                       ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
+#define NAND_TIMING    ((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
+                       ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
+                       ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
+                       ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT)
+
+/*
+ * Daughter card information.
+ */
+#define DAUGHTER_CARD_BASE             (0xAC000000)
+#define DAUGHTER_CARD_MEM_SIZE         (0xADFFFFFF - DAUGHTER_CARD_BASE + 1)
+#define DAUGHTER_CARD_IRQ              (AU1000_GPIO_3)
+
+/* DC_IDE and DC_ETHERNET */
+#define AU1XXX_ATA_PHYS_ADDR           (0x0C000000)
+#define AU1XXX_ATA_REG_OFFSET          (5)     
+
+#define AU1XXX_SMC91111_PHYS_ADDR      (0x0C000300)
+#define AU1XXX_SMC91111_IRQ            AU1000_GPIO_3
 
 #endif /* __ASM_PB1550_H */

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