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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: ppopov@linux-mips.org
Date: Tue, 18 Jan 2005 05:22:01 +0000
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ppopov@ftp.linux-mips.org       05/01/18 05:21:55

Modified files:
        include/asm-mips/mach-au1x00: au1xxx_psc.h 
        include/asm-mips/mach-pb1x00: pb1550.h 

Log message:
        Patch adds a number of definitions required for drivers using I2C
        and PSC on Au1550 and Pb1550 specifically.

diff -urN linux/include/asm-mips/mach-au1x00/au1xxx_psc.h 
linux/include/asm-mips/mach-au1x00/au1xxx_psc.h
--- linux/include/asm-mips/mach-au1x00/au1xxx_psc.h     2005/01/15 01:31:03     
1.2
+++ linux/include/asm-mips/mach-au1x00/au1xxx_psc.h     2005/01/18 05:21:55     
1.3
@@ -33,29 +33,14 @@
 #ifndef _AU1000_PSC_H_
 #define _AU1000_PSC_H_
 
-#include <linux/config.h>
-
-/* The PSC base addresses.
-*/
-#define PSC_BASE0              0xb1a00000
-#define PSC_BASE1              0xb1b00000
-#define PSC_BASE2              0xb0a00000
-#define PSC_BASE3              0xb0d00000
-
-/* These should be defined in a board specific file!
-*/
-#ifdef CONFIG_MIPS_PB1550
-#define SPI_PSC_BASE           PSC_BASE0
-#define AC97_PSC_BASE          PSC_BASE1
-#define SMBUS_PSC_BASE         PSC_BASE2
-#endif
-#ifdef CONFIG_MIPS_DB1550
-#define SPI_PSC_BASE           PSC_BASE0
-#define AC97_PSC_BASE          PSC_BASE1
-#define SMBUS_PSC_BASE         PSC_BASE2
+/* The PSC base addresses.  */
+#ifdef CONFIG_SOC_AU1550
+#define PSC0_BASE_ADDR         0xb1a00000
+#define PSC1_BASE_ADDR         0xb1b00000
+#define PSC2_BASE_ADDR         0xb0a00000
+#define PSC3_BASE_ADDR         0xb0d00000
 #endif
 
-
 /* The PSC select and control registers are common to
  * all protocols.
  */
@@ -210,4 +195,328 @@
 #define PSC_AC97RST_SNC                (1 << 0)
 
 
+/* PSC in I2S Mode.
+*/
+typedef struct psc_i2s {
+       u32     psc_sel;
+       u32     psc_ctrl;
+       u32     psc_i2scfg;
+       u32     psc_i2smsk;
+       u32     psc_i2spcr;
+       u32     psc_i2sstat;
+       u32     psc_i2sevent;
+       u32     psc_i2stxrx;
+       u32     psc_i2sudf;
+} psc_i2s_t;
+
+/* I2S Config Register.
+*/
+#define PSC_I2SCFG_RT_MASK     (3 << 30)
+#define PSC_I2SCFG_RT_FIFO1    (0 << 30)
+#define PSC_I2SCFG_RT_FIFO2    (1 << 30)
+#define PSC_I2SCFG_RT_FIFO4    (2 << 30)
+#define PSC_I2SCFG_RT_FIFO8    (3 << 30)
+
+#define PSC_I2SCFG_TT_MASK     (3 << 28)
+#define PSC_I2SCFG_TT_FIFO1    (0 << 28)
+#define PSC_I2SCFG_TT_FIFO2    (1 << 28)
+#define PSC_I2SCFG_TT_FIFO4    (2 << 28)
+#define PSC_I2SCFG_TT_FIFO8    (3 << 28)
+
+#define PSC_I2SCFG_DD_DISABLE  (1 << 27)
+#define PSC_I2SCFG_DE_ENABLE   (1 << 26)
+#define PSC_I2SCFG_SET_WS(x)   (((((x) / 2) - 1) & 0x7f) << 16)
+#define PSC_I2SCFG_WI          (1 << 15)
+
+#define PSC_I2SCFG_DIV_MASK    (3 << 13)
+#define PSC_I2SCFG_DIV2                (0 << 13)
+#define PSC_I2SCFG_DIV4                (1 << 13)
+#define PSC_I2SCFG_DIV8                (2 << 13)
+#define PSC_I2SCFG_DIV16       (3 << 13)
+
+#define PSC_I2SCFG_BI          (1 << 12)
+#define PSC_I2SCFG_BUF         (1 << 11)
+#define PSC_I2SCFG_MLJ         (1 << 10)
+#define PSC_I2SCFG_XM          (1 << 9)
+
+/* The word length equation is simply LEN+1.
+ */
+#define PSC_I2SCFG_SET_LEN(x)  ((((x) - 1) & 0x1f) << 4)
+#define PSC_I2SCFG_GET_LEN(x)  ((((x) >> 4) & 0x1f) + 1)
+
+#define PSC_I2SCFG_LB          (1 << 2)
+#define PSC_I2SCFG_MLF         (1 << 1)
+#define PSC_I2SCFG_MS          (1 << 0)
+
+/* I2S Mask Register.
+*/
+#define PSC_I2SMSK_RR          (1 << 13)
+#define PSC_I2SMSK_RO          (1 << 12)
+#define PSC_I2SMSK_RU          (1 << 11)
+#define PSC_I2SMSK_TR          (1 << 10)
+#define PSC_I2SMSK_TO          (1 << 9)
+#define PSC_I2SMSK_TU          (1 << 8)
+#define PSC_I2SMSK_RD          (1 << 5)
+#define PSC_I2SMSK_TD          (1 << 4)
+#define PSC_I2SMSK_ALLMASK     (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \
+                                PSC_I2SMSK_RU | PSC_I2SMSK_TR | \
+                                PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
+                                PSC_I2SMSK_RD | PSC_I2SMSK_TD)
+
+/* I2S Protocol Control Register.
+*/
+#define PSC_I2SPCR_RC          (1 << 6)
+#define PSC_I2SPCR_RP          (1 << 5)
+#define PSC_I2SPCR_RS          (1 << 4)
+#define PSC_I2SPCR_TC          (1 << 2)
+#define PSC_I2SPCR_TP          (1 << 1)
+#define PSC_I2SPCR_TS          (1 << 0)
+
+/* I2S Status register (read only).
+*/
+#define PSC_I2SSTAT_RF         (1 << 13)
+#define PSC_I2SSTAT_RE         (1 << 12)
+#define PSC_I2SSTAT_RR         (1 << 11)
+#define PSC_I2SSTAT_TF         (1 << 10)
+#define PSC_I2SSTAT_TE         (1 << 9)
+#define PSC_I2SSTAT_TR         (1 << 8)
+#define PSC_I2SSTAT_RB         (1 << 5)
+#define PSC_I2SSTAT_TB         (1 << 4)
+#define PSC_I2SSTAT_DI         (1 << 2)
+#define PSC_I2SSTAT_DR         (1 << 1)
+#define PSC_I2SSTAT_SR         (1 << 0)
+
+/* I2S Event Register.
+*/
+#define PSC_I2SEVNT_RR         (1 << 13)
+#define PSC_I2SEVNT_RO         (1 << 12)
+#define PSC_I2SEVNT_RU         (1 << 11)
+#define PSC_I2SEVNT_TR         (1 << 10)
+#define PSC_I2SEVNT_TO         (1 << 9)
+#define PSC_I2SEVNT_TU         (1 << 8)
+#define PSC_I2SEVNT_RD         (1 << 5)
+#define PSC_I2SEVNT_TD         (1 << 4)
+
+/* PSC in SPI Mode.
+*/
+typedef struct psc_spi {
+       u32     psc_sel;
+       u32     psc_ctrl;
+       u32     psc_spicfg;
+       u32     psc_spimsk;
+       u32     psc_spipcr;
+       u32     psc_spistat;
+       u32     psc_spievent;
+       u32     psc_spitxrx;
+} psc_spi_t;
+
+/* SPI Config Register.
+*/
+#define PSC_SPICFG_RT_MASK     (3 << 30)
+#define PSC_SPICFG_RT_FIFO1    (0 << 30)
+#define PSC_SPICFG_RT_FIFO2    (1 << 30)
+#define PSC_SPICFG_RT_FIFO4    (2 << 30)
+#define PSC_SPICFG_RT_FIFO8    (3 << 30)
+
+#define PSC_SPICFG_TT_MASK     (3 << 28)
+#define PSC_SPICFG_TT_FIFO1    (0 << 28)
+#define PSC_SPICFG_TT_FIFO2    (1 << 28)
+#define PSC_SPICFG_TT_FIFO4    (2 << 28)
+#define PSC_SPICFG_TT_FIFO8    (3 << 28)
+
+#define PSC_SPICFG_DD_DISABLE  (1 << 27)
+#define PSC_SPICFG_DE_ENABLE   (1 << 26)
+#define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15))
+#define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15)
+
+#define PSC_SPICFG_SET_DIV(x)  (((x) & 0x03) << 13)
+#define PSC_SPICFG_DIV2                0
+#define PSC_SPICFG_DIV4                1
+#define PSC_SPICFG_DIV8                2
+#define PSC_SPICFG_DIV16       3
+
+#define PSC_SPICFG_BI          (1 << 12)
+#define PSC_SPICFG_PSE         (1 << 11)
+#define PSC_SPICFG_CGE         (1 << 10)
+#define PSC_SPICFG_CDE         (1 << 9)
+
+#define PSC_SPICFG_CLR_LEN(x)  ((x) & ~((0x1f) << 4))
+#define PSC_SPICFG_SET_LEN(x)  (((x-1) & 0x1f) << 4)
+
+#define PSC_SPICFG_LB          (1 << 3)
+#define PSC_SPICFG_MLF         (1 << 1)
+#define PSC_SPICFG_MO          (1 << 0)
+
+/* SPI Mask Register.
+*/
+#define PSC_SPIMSK_MM          (1 << 16)
+#define PSC_SPIMSK_RR          (1 << 13)
+#define PSC_SPIMSK_RO          (1 << 12)
+#define PSC_SPIMSK_RU          (1 << 11)
+#define PSC_SPIMSK_TR          (1 << 10)
+#define PSC_SPIMSK_TO          (1 << 9)
+#define PSC_SPIMSK_TU          (1 << 8)
+#define PSC_SPIMSK_SD          (1 << 5)
+#define PSC_SPIMSK_MD          (1 << 4)
+#define PSC_SPIMSK_ALLMASK     (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \
+                                PSC_SPIMSK_RO | PSC_SPIMSK_TO | \
+                                PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
+                                PSC_SPIMSK_MD)
+
+/* SPI Protocol Control Register.
+*/
+#define PSC_SPIPCR_RC          (1 << 6)
+#define PSC_SPIPCR_SP          (1 << 5)
+#define PSC_SPIPCR_SS          (1 << 4)
+#define PSC_SPIPCR_TC          (1 << 2)
+#define PSC_SPIPCR_MS          (1 << 0)
+
+/* SPI Status register (read only).
+*/
+#define PSC_SPISTAT_RF         (1 << 13)
+#define PSC_SPISTAT_RE         (1 << 12)
+#define PSC_SPISTAT_RR         (1 << 11)
+#define PSC_SPISTAT_TF         (1 << 10)
+#define PSC_SPISTAT_TE         (1 << 9)
+#define PSC_SPISTAT_TR         (1 << 8)
+#define PSC_SPISTAT_SB         (1 << 5)
+#define PSC_SPISTAT_MB         (1 << 4)
+#define PSC_SPISTAT_DI         (1 << 2)
+#define PSC_SPISTAT_DR         (1 << 1)
+#define PSC_SPISTAT_SR         (1 << 0)
+
+/* SPI Event Register.
+*/
+#define PSC_SPIEVNT_MM         (1 << 16)
+#define PSC_SPIEVNT_RR         (1 << 13)
+#define PSC_SPIEVNT_RO         (1 << 12)
+#define PSC_SPIEVNT_RU         (1 << 11)
+#define PSC_SPIEVNT_TR         (1 << 10)
+#define PSC_SPIEVNT_TO         (1 << 9)
+#define PSC_SPIEVNT_TU         (1 << 8)
+#define PSC_SPIEVNT_SD         (1 << 5)
+#define PSC_SPIEVNT_MD         (1 << 4)
+
+/* Transmit register control.
+*/
+#define PSC_SPITXRX_LC         (1 << 29)
+#define PSC_SPITXRX_SR         (1 << 28)
+
+/* PSC in SMBus (I2C) Mode.
+*/
+typedef struct psc_smb {
+       u32     psc_sel;
+       u32     psc_ctrl;
+       u32     psc_smbcfg;
+       u32     psc_smbmsk;
+       u32     psc_smbpcr;
+       u32     psc_smbstat;
+       u32     psc_smbevnt;
+       u32     psc_smbtxrx;
+       u32     psc_smbtmr;
+} psc_smb_t;
+
+/* SMBus Config Register.
+*/
+#define PSC_SMBCFG_RT_MASK     (3 << 30)
+#define PSC_SMBCFG_RT_FIFO1    (0 << 30)
+#define PSC_SMBCFG_RT_FIFO2    (1 << 30)
+#define PSC_SMBCFG_RT_FIFO4    (2 << 30)
+#define PSC_SMBCFG_RT_FIFO8    (3 << 30)
+
+#define PSC_SMBCFG_TT_MASK     (3 << 28)
+#define PSC_SMBCFG_TT_FIFO1    (0 << 28)
+#define PSC_SMBCFG_TT_FIFO2    (1 << 28)
+#define PSC_SMBCFG_TT_FIFO4    (2 << 28)
+#define PSC_SMBCFG_TT_FIFO8    (3 << 28)
+
+#define PSC_SMBCFG_DD_DISABLE  (1 << 27)
+#define PSC_SMBCFG_DE_ENABLE   (1 << 26)
+
+#define PSC_SMBCFG_SET_DIV(x)  (((x) & 0x03) << 13)
+#define PSC_SMBCFG_DIV2                0
+#define PSC_SMBCFG_DIV4                1
+#define PSC_SMBCFG_DIV8                2
+#define PSC_SMBCFG_DIV16       3
+
+#define PSC_SMBCFG_GCE         (1 << 9)
+#define PSC_SMBCFG_SFM         (1 << 8)
+
+#define PSC_SMBCFG_SET_SLV(x)  (((x) & 0x7f) << 1)
+
+/* SMBus Mask Register.
+*/
+#define PSC_SMBMSK_DN          (1 << 30)
+#define PSC_SMBMSK_AN          (1 << 29)
+#define PSC_SMBMSK_AL          (1 << 28)
+#define PSC_SMBMSK_RR          (1 << 13)
+#define PSC_SMBMSK_RO          (1 << 12)
+#define PSC_SMBMSK_RU          (1 << 11)
+#define PSC_SMBMSK_TR          (1 << 10)
+#define PSC_SMBMSK_TO          (1 << 9)
+#define PSC_SMBMSK_TU          (1 << 8)
+#define PSC_SMBMSK_SD          (1 << 5)
+#define PSC_SMBMSK_MD          (1 << 4)
+#define PSC_SMBMSK_ALLMASK     (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \
+                                PSC_SMBMSK_AL | PSC_SMBMSK_RR | \
+                                PSC_SMBMSK_RO | PSC_SMBMSK_TO | \
+                                PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
+                                PSC_SMBMSK_MD)
+
+/* SMBus Protocol Control Register.
+*/
+#define PSC_SMBPCR_DC          (1 << 2)
+#define PSC_SMBPCR_MS          (1 << 0)
+
+/* SMBus Status register (read only).
+*/
+#define PSC_SMBSTAT_BB         (1 << 28)
+#define PSC_SMBSTAT_RF         (1 << 13)
+#define PSC_SMBSTAT_RE         (1 << 12)
+#define PSC_SMBSTAT_RR         (1 << 11)
+#define PSC_SMBSTAT_TF         (1 << 10)
+#define PSC_SMBSTAT_TE         (1 << 9)
+#define PSC_SMBSTAT_TR         (1 << 8)
+#define PSC_SMBSTAT_SB         (1 << 5)
+#define PSC_SMBSTAT_MB         (1 << 4)
+#define PSC_SMBSTAT_DI         (1 << 2)
+#define PSC_SMBSTAT_DR         (1 << 1)
+#define PSC_SMBSTAT_SR         (1 << 0)
+
+/* SMBus Event Register.
+*/
+#define PSC_SMBEVNT_DN         (1 << 30)
+#define PSC_SMBEVNT_AN         (1 << 29)
+#define PSC_SMBEVNT_AL         (1 << 28)
+#define PSC_SMBEVNT_RR         (1 << 13)
+#define PSC_SMBEVNT_RO         (1 << 12)
+#define PSC_SMBEVNT_RU         (1 << 11)
+#define PSC_SMBEVNT_TR         (1 << 10)
+#define PSC_SMBEVNT_TO         (1 << 9)
+#define PSC_SMBEVNT_TU         (1 << 8)
+#define PSC_SMBEVNT_SD         (1 << 5)
+#define PSC_SMBEVNT_MD         (1 << 4)
+#define PSC_SMBEVNT_ALLCLR     (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \
+                                PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \
+                                PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \
+                                PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
+                                PSC_SMBEVNT_MD)
+
+/* Transmit register control.
+*/
+#define PSC_SMBTXRX_RSR                (1 << 30)
+#define PSC_SMBTXRX_STP                (1 << 29)
+#define PSC_SMBTXRX_DATAMASK   (0xff)
+
+/* SMBus protocol timers register.
+*/
+#define PSC_SMBTMR_SET_TH(x)   (((x) & 0x3) << 30)
+#define PSC_SMBTMR_SET_PS(x)   (((x) & 0x1f) << 25)
+#define PSC_SMBTMR_SET_PU(x)   (((x) & 0x1f) << 20)
+#define PSC_SMBTMR_SET_SH(x)   (((x) & 0x1f) << 15)
+#define PSC_SMBTMR_SET_SU(x)   (((x) & 0x1f) << 10)
+#define PSC_SMBTMR_SET_CL(x)   (((x) & 0x1f) << 5)
+#define PSC_SMBTMR_SET_CH(x)   (((x) & 0x1f) << 0)
+
+
 #endif /* _AU1000_PSC_H_ */
diff -urN linux/include/asm-mips/mach-pb1x00/pb1550.h 
linux/include/asm-mips/mach-pb1x00/pb1550.h
--- linux/include/asm-mips/mach-pb1x00/pb1550.h 2005/01/15 01:31:04     1.3
+++ linux/include/asm-mips/mach-pb1x00/pb1550.h 2005/01/18 05:21:55     1.4
@@ -30,6 +30,16 @@
 #include <linux/config.h>
 #include <linux/types.h>
 
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
+
+#define SPI_PSC_BASE        PSC0_BASE_ADDR
+#define AC97_PSC_BASE       PSC1_BASE_ADDR
+#define SMBUS_PSC_BASE      PSC2_BASE_ADDR
+#define I2S_PSC_BASE        PSC3_BASE_ADDR
+
 #define BCSR_PHYS_ADDR 0xAF000000
 
 typedef volatile struct

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