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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: ralf@linux-mips.org
Date: Mon, 17 Jan 2005 17:46:52 +0000
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 05/01/17 17:46:45

Modified files:
        include/asm-mips: mipsregs.h 

Log message:
        More performance counter stuff.

diff -urN linux/include/asm-mips/mipsregs.h linux/include/asm-mips/mipsregs.h
--- linux/include/asm-mips/mipsregs.h   2004/12/19 22:39:46     1.68
+++ linux/include/asm-mips/mipsregs.h   2005/01/17 17:46:43     1.69
@@ -873,6 +873,26 @@
 #define read_c0_depc()         __read_ulong_c0_register($24, 0)
 #define write_c0_depc(val)     __write_ulong_c0_register($24, 0, val)
 
+/*
+ * MIPS32 / MIPS64 performance counters
+ */
+#define read_c0_perfctrl0()    __read_32bit_c0_register($25, 0)
+#define write_c0_perfctrl0(val)        __write_32bit_c0_register($25, 0, val)
+#define read_c0_perfcntr0()    __read_32bit_c0_register($25, 1)
+#define write_c0_perfcntr0(val)        __write_32bit_c0_register($25, 1, val)
+#define read_c0_perfctrl1()    __read_32bit_c0_register($25, 2)
+#define write_c0_perfctrl1(val)        __write_32bit_c0_register($25, 2, val)
+#define read_c0_perfcntr1()    __read_32bit_c0_register($25, 3)
+#define write_c0_perfcntr1(val)        __write_32bit_c0_register($25, 3, val)
+#define read_c0_perfctrl2()    __read_32bit_c0_register($25, 4)
+#define write_c0_perfctrl2(val)        __write_32bit_c0_register($25, 4, val)
+#define read_c0_perfcntr2()    __read_32bit_c0_register($25, 5)
+#define write_c0_perfcntr2(val)        __write_32bit_c0_register($25, 5, val)
+#define read_c0_perfctrl3()    __read_32bit_c0_register($25, 6)
+#define write_c0_perfctrl3(val)        __write_32bit_c0_register($25, 6, val)
+#define read_c0_perfcntr3()    __read_32bit_c0_register($25, 7)
+#define write_c0_perfcntr3(val)        __write_32bit_c0_register($25, 7, val)
+
 /* RM9000 PerfCount performance counter register */
 #define read_c0_perfcount()    __read_64bit_c0_register($25, 0)
 #define write_c0_perfcount(val)        __write_64bit_c0_register($25, 0, val)

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